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1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
5
6#include <linux/module.h>
7#include <linux/types.h>
8#include <linux/init.h>
9#include <linux/pci.h>
10#include <linux/vmalloc.h>
11#include <linux/pagemap.h>
12#include <linux/delay.h>
13#include <linux/netdevice.h>
14#include <linux/interrupt.h>
15#include <linux/tcp.h>
16#include <linux/ipv6.h>
17#include <linux/slab.h>
18#include <net/checksum.h>
19#include <net/ip6_checksum.h>
20#include <linux/ethtool.h>
21#include <linux/if_vlan.h>
22#include <linux/cpu.h>
23#include <linux/smp.h>
24#include <linux/pm_qos.h>
25#include <linux/pm_runtime.h>
26#include <linux/prefetch.h>
27#include <linux/suspend.h>
28#include <linux/dmi.h>
29
30#include "e1000.h"
31#define CREATE_TRACE_POINTS
32#include "e1000e_trace.h"
33
34char e1000e_driver_name[] = "e1000e";
35
36#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
37static int debug = -1;
38module_param(debug, int, 0);
39MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
40
41static const struct e1000_info *e1000_info_tbl[] = {
42 [board_82571] = &e1000_82571_info,
43 [board_82572] = &e1000_82572_info,
44 [board_82573] = &e1000_82573_info,
45 [board_82574] = &e1000_82574_info,
46 [board_82583] = &e1000_82583_info,
47 [board_80003es2lan] = &e1000_es2_info,
48 [board_ich8lan] = &e1000_ich8_info,
49 [board_ich9lan] = &e1000_ich9_info,
50 [board_ich10lan] = &e1000_ich10_info,
51 [board_pchlan] = &e1000_pch_info,
52 [board_pch2lan] = &e1000_pch2_info,
53 [board_pch_lpt] = &e1000_pch_lpt_info,
54 [board_pch_spt] = &e1000_pch_spt_info,
55 [board_pch_cnp] = &e1000_pch_cnp_info,
56 [board_pch_tgp] = &e1000_pch_tgp_info,
57 [board_pch_adp] = &e1000_pch_adp_info,
58 [board_pch_mtp] = &e1000_pch_mtp_info,
59 [board_pch_ptp] = &e1000_pch_ptp_info,
60};
61
62static const struct dmi_system_id disable_k1_list[] = {
63 {
64 .ident = "Dell Pro 16 Plus PB16250",
65 .matches = {
66 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
67 DMI_MATCH(DMI_PRODUCT_NAME, "Dell Pro 16 Plus PB16250"),
68 },
69 },
70 {
71 .ident = "Lenovo ThinkPad P14s Gen 5",
72 .matches = {
73 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
74 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad P14s Gen 5"),
75 },
76 },
77 {}
78};
79
80struct e1000_reg_info {
81 u32 ofs;
82 char *name;
83};
84
85static const struct e1000_reg_info e1000_reg_info_tbl[] = {
86 /* General Registers */
87 {E1000_CTRL, "CTRL"},
88 {E1000_STATUS, "STATUS"},
89 {E1000_CTRL_EXT, "CTRL_EXT"},
90
91 /* Interrupt Registers */
92 {E1000_ICR, "ICR"},
93
94 /* Rx Registers */
95 {E1000_RCTL, "RCTL"},
96 {E1000_RDLEN(0), "RDLEN"},
97 {E1000_RDH(0), "RDH"},
98 {E1000_RDT(0), "RDT"},
99 {E1000_RDTR, "RDTR"},
100 {E1000_RXDCTL(0), "RXDCTL"},
101 {E1000_ERT, "ERT"},
102 {E1000_RDBAL(0), "RDBAL"},
103 {E1000_RDBAH(0), "RDBAH"},
104 {E1000_RDFH, "RDFH"},
105 {E1000_RDFT, "RDFT"},
106 {E1000_RDFHS, "RDFHS"},
107 {E1000_RDFTS, "RDFTS"},
108 {E1000_RDFPC, "RDFPC"},
109
110 /* Tx Registers */
111 {E1000_TCTL, "TCTL"},
112 {E1000_TDBAL(0), "TDBAL"},
113 {E1000_TDBAH(0), "TDBAH"},
114 {E1000_TDLEN(0), "TDLEN"},
115 {E1000_TDH(0), "TDH"},
116 {E1000_TDT(0), "TDT"},
117 {E1000_TIDV, "TIDV"},
118 {E1000_TXDCTL(0), "TXDCTL"},
119 {E1000_TADV, "TADV"},
120 {E1000_TARC(0), "TARC"},
121 {E1000_TDFH, "TDFH"},
122 {E1000_TDFT, "TDFT"},
123 {E1000_TDFHS, "TDFHS"},
124 {E1000_TDFTS, "TDFTS"},
125 {E1000_TDFPC, "TDFPC"},
126
127 /* List Terminator */
128 {0, NULL}
129};
130
131/**
132 * __ew32_prepare - prepare to write to MAC CSR register on certain parts
133 * @hw: pointer to the HW structure
134 *
135 * When updating the MAC CSR registers, the Manageability Engine (ME) could
136 * be accessing the registers at the same time. Normally, this is handled in
137 * h/w by an arbiter but on some parts there is a bug that acknowledges Host
138 * accesses later than it should which could result in the register to have
139 * an incorrect value. Workaround this by checking the FWSM register which
140 * has bit 24 set while ME is accessing MAC CSR registers, wait if it is set
141 * and try again a number of times.
142 **/
143static void __ew32_prepare(struct e1000_hw *hw)
144{
145 s32 i = E1000_ICH_FWSM_PCIM2PCI_COUNT;
146
147 while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i)
148 udelay(50);
149}
150
151void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val)
152{
153 if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
154 __ew32_prepare(hw);
155
156 writel(val, hw->hw_addr + reg);
157}
158
159/**
160 * e1000_regdump - register printout routine
161 * @hw: pointer to the HW structure
162 * @reginfo: pointer to the register info table
163 **/
164static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo)
165{
166 int n = 0;
167 char rname[16];
168 u32 regs[8];
169
170 switch (reginfo->ofs) {
171 case E1000_RXDCTL(0):
172 for (n = 0; n < 2; n++)
173 regs[n] = __er32(hw, E1000_RXDCTL(n));
174 break;
175 case E1000_TXDCTL(0):
176 for (n = 0; n < 2; n++)
177 regs[n] = __er32(hw, E1000_TXDCTL(n));
178 break;
179 case E1000_TARC(0):
180 for (n = 0; n < 2; n++)
181 regs[n] = __er32(hw, E1000_TARC(n));
182 break;
183 default:
184 pr_info("%-15s %08x\n",
185 reginfo->name, __er32(hw, reginfo->ofs));
186 return;
187 }
188
189 snprintf(rname, 16, "%s%s", reginfo->name, "[0-1]");
190 pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]);
191}
192
193static void e1000e_dump_ps_pages(struct e1000_adapter *adapter,
194 struct e1000_buffer *bi)
195{
196 int i;
197 struct e1000_ps_page *ps_page;
198
199 for (i = 0; i < adapter->rx_ps_pages; i++) {
200 ps_page = &bi->ps_pages[i];
201
202 if (ps_page->page) {
203 pr_info("packet dump for ps_page %d:\n", i);
204 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
205 16, 1, page_address(ps_page->page),
206 PAGE_SIZE, true);
207 }
208 }
209}
210
211/**
212 * e1000e_dump - Print registers, Tx-ring and Rx-ring
213 * @adapter: board private structure
214 **/
215static void e1000e_dump(struct e1000_adapter *adapter)
216{
217 struct net_device *netdev = adapter->netdev;
218 struct e1000_hw *hw = &adapter->hw;
219 struct e1000_reg_info *reginfo;
220 struct e1000_ring *tx_ring = adapter->tx_ring;
221 struct e1000_tx_desc *tx_desc;
222 struct my_u0 {
223 __le64 a;
224 __le64 b;
225 } *u0;
226 struct e1000_buffer *buffer_info;
227 struct e1000_ring *rx_ring = adapter->rx_ring;
228 union e1000_rx_desc_packet_split *rx_desc_ps;
229 union e1000_rx_desc_extended *rx_desc;
230 struct my_u1 {
231 __le64 a;
232 __le64 b;
233 __le64 c;
234 __le64 d;
235 } *u1;
236 u32 staterr;
237 int i = 0;
238
239 if (!netif_msg_hw(adapter))
240 return;
241
242 /* Print netdevice Info */
243 if (netdev) {
244 dev_info(&adapter->pdev->dev, "Net device Info\n");
245 pr_info("Device Name state trans_start\n");
246 pr_info("%-15s %016lX %016lX\n", netdev->name,
247 netdev->state, dev_trans_start(netdev));
248 }
249
250 /* Print Registers */
251 dev_info(&adapter->pdev->dev, "Register Dump\n");
252 pr_info(" Register Name Value\n");
253 for (reginfo = (struct e1000_reg_info *)e1000_reg_info_tbl;
254 reginfo->name; reginfo++) {
255 e1000_regdump(hw, reginfo);
256 }
257
258 /* Print Tx Ring Summary */
259 if (!netdev || !netif_running(netdev))
260 return;
261
262 dev_info(&adapter->pdev->dev, "Tx Ring Summary\n");
263 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
264 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean];
265 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
266 0, tx_ring->next_to_use, tx_ring->next_to_clean,
267 (unsigned long long)buffer_info->dma,
268 buffer_info->length,
269 buffer_info->next_to_watch,
270 (unsigned long long)buffer_info->time_stamp);
271
272 /* Print Tx Ring */
273 if (!netif_msg_tx_done(adapter))
274 goto rx_ring_summary;
275
276 dev_info(&adapter->pdev->dev, "Tx Ring Dump\n");
277
278 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended)
279 *
280 * Legacy Transmit Descriptor
281 * +--------------------------------------------------------------+
282 * 0 | Buffer Address [63:0] (Reserved on Write Back) |
283 * +--------------------------------------------------------------+
284 * 8 | Special | CSS | Status | CMD | CSO | Length |
285 * +--------------------------------------------------------------+
286 * 63 48 47 36 35 32 31 24 23 16 15 0
287 *
288 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload
289 * 63 48 47 40 39 32 31 16 15 8 7 0
290 * +----------------------------------------------------------------+
291 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS |
292 * +----------------------------------------------------------------+
293 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN |
294 * +----------------------------------------------------------------+
295 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
296 *
297 * Extended Data Descriptor (DTYP=0x1)
298 * +----------------------------------------------------------------+
299 * 0 | Buffer Address [63:0] |
300 * +----------------------------------------------------------------+
301 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN |
302 * +----------------------------------------------------------------+
303 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
304 */
305 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n");
306 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n");
307 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n");
308 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
309 const char *next_desc;
310 tx_desc = E1000_TX_DESC(*tx_ring, i);
311 buffer_info = &tx_ring->buffer_info[i];
312 u0 = (struct my_u0 *)tx_desc;
313 if (i == tx_ring->next_to_use && i == tx_ring->next_to_clean)
314 next_desc = " NTC/U";
315 else if (i == tx_ring->next_to_use)
316 next_desc = " NTU";
317 else if (i == tx_ring->next_to_clean)
318 next_desc = " NTC";
319 else
320 next_desc = "";
321 pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n",
322 (!(le64_to_cpu(u0->b) & BIT(29)) ? 'l' :
323 ((le64_to_cpu(u0->b) & BIT(20)) ? 'd' : 'c')),
324 i,
325 (unsigned long long)le64_to_cpu(u0->a),
326 (unsigned long long)le64_to_cpu(u0->b),
327 (unsigned long long)buffer_info->dma,
328 buffer_info->length, buffer_info->next_to_watch,
329 (unsigned long long)buffer_info->time_stamp,
330 buffer_info->skb, next_desc);
331
332 if (netif_msg_pktdata(adapter) && buffer_info->skb)
333 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
334 16, 1, buffer_info->skb->data,
335 buffer_info->skb->len, true);
336 }
337
338 /* Print Rx Ring Summary */
339rx_ring_summary:
340 dev_info(&adapter->pdev->dev, "Rx Ring Summary\n");
341 pr_info("Queue [NTU] [NTC]\n");
342 pr_info(" %5d %5X %5X\n",
343 0, rx_ring->next_to_use, rx_ring->next_to_clean);
344
345 /* Print Rx Ring */
346 if (!netif_msg_rx_status(adapter))
347 return;
348
349 dev_info(&adapter->pdev->dev, "Rx Ring Dump\n");
350 switch (adapter->rx_ps_pages) {
351 case 1:
352 case 2:
353 case 3:
354 /* [Extended] Packet Split Receive Descriptor Format
355 *
356 * +-----------------------------------------------------+
357 * 0 | Buffer Address 0 [63:0] |
358 * +-----------------------------------------------------+
359 * 8 | Buffer Address 1 [63:0] |
360 * +-----------------------------------------------------+
361 * 16 | Buffer Address 2 [63:0] |
362 * +-----------------------------------------------------+
363 * 24 | Buffer Address 3 [63:0] |
364 * +-----------------------------------------------------+
365 */
366 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n");
367 /* [Extended] Receive Descriptor (Write-Back) Format
368 *
369 * 63 48 47 32 31 13 12 8 7 4 3 0
370 * +------------------------------------------------------+
371 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS |
372 * | Checksum | Ident | | Queue | | Type |
373 * +------------------------------------------------------+
374 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
375 * +------------------------------------------------------+
376 * 63 48 47 32 31 20 19 0
377 */
378 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n");
379 for (i = 0; i < rx_ring->count; i++) {
380 const char *next_desc;
381 buffer_info = &rx_ring->buffer_info[i];
382 rx_desc_ps = E1000_RX_DESC_PS(*rx_ring, i);
383 u1 = (struct my_u1 *)rx_desc_ps;
384 staterr =
385 le32_to_cpu(rx_desc_ps->wb.middle.status_error);
386
387 if (i == rx_ring->next_to_use)
388 next_desc = " NTU";
389 else if (i == rx_ring->next_to_clean)
390 next_desc = " NTC";
391 else
392 next_desc = "";
393
394 if (staterr & E1000_RXD_STAT_DD) {
395 /* Descriptor Done */
396 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX ---------------- %p%s\n",
397 "RWB", i,
398 (unsigned long long)le64_to_cpu(u1->a),
399 (unsigned long long)le64_to_cpu(u1->b),
400 (unsigned long long)le64_to_cpu(u1->c),
401 (unsigned long long)le64_to_cpu(u1->d),
402 buffer_info->skb, next_desc);
403 } else {
404 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX %016llX %p%s\n",
405 "R ", i,
406 (unsigned long long)le64_to_cpu(u1->a),
407 (unsigned long long)le64_to_cpu(u1->b),
408 (unsigned long long)le64_to_cpu(u1->c),
409 (unsigned long long)le64_to_cpu(u1->d),
410 (unsigned long long)buffer_info->dma,
411 buffer_info->skb, next_desc);
412
413 if (netif_msg_pktdata(adapter))
414 e1000e_dump_ps_pages(adapter,
415 buffer_info);
416 }
417 }
418 break;
419 default:
420 case 0:
421 /* Extended Receive Descriptor (Read) Format
422 *
423 * +-----------------------------------------------------+
424 * 0 | Buffer Address [63:0] |
425 * +-----------------------------------------------------+
426 * 8 | Reserved |
427 * +-----------------------------------------------------+
428 */
429 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n");
430 /* Extended Receive Descriptor (Write-Back) Format
431 *
432 * 63 48 47 32 31 24 23 4 3 0
433 * +------------------------------------------------------+
434 * | RSS Hash | | | |
435 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS |
436 * | Packet | IP | | | Type |
437 * | Checksum | Ident | | | |
438 * +------------------------------------------------------+
439 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
440 * +------------------------------------------------------+
441 * 63 48 47 32 31 20 19 0
442 */
443 pr_info("RWB[desc] [cs ipid mrq] [vt ln xe xs] [bi->skb] <-- Ext (Write-Back) format\n");
444
445 for (i = 0; i < rx_ring->count; i++) {
446 const char *next_desc;
447
448 buffer_info = &rx_ring->buffer_info[i];
449 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
450 u1 = (struct my_u1 *)rx_desc;
451 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
452
453 if (i == rx_ring->next_to_use)
454 next_desc = " NTU";
455 else if (i == rx_ring->next_to_clean)
456 next_desc = " NTC";
457 else
458 next_desc = "";
459
460 if (staterr & E1000_RXD_STAT_DD) {
461 /* Descriptor Done */
462 pr_info("%s[0x%03X] %016llX %016llX ---------------- %p%s\n",
463 "RWB", i,
464 (unsigned long long)le64_to_cpu(u1->a),
465 (unsigned long long)le64_to_cpu(u1->b),
466 buffer_info->skb, next_desc);
467 } else {
468 pr_info("%s[0x%03X] %016llX %016llX %016llX %p%s\n",
469 "R ", i,
470 (unsigned long long)le64_to_cpu(u1->a),
471 (unsigned long long)le64_to_cpu(u1->b),
472 (unsigned long long)buffer_info->dma,
473 buffer_info->skb, next_desc);
474
475 if (netif_msg_pktdata(adapter) &&
476 buffer_info->skb)
477 print_hex_dump(KERN_INFO, "",
478 DUMP_PREFIX_ADDRESS, 16,
479 1,
480 buffer_info->skb->data,
481 adapter->rx_buffer_len,
482 true);
483 }
484 }
485 }
486}
487
488/**
489 * e1000_desc_unused - calculate if we have unused descriptors
490 * @ring: pointer to ring struct to perform calculation on
491 **/
492static int e1000_desc_unused(struct e1000_ring *ring)
493{
494 if (ring->next_to_clean > ring->next_to_use)
495 return ring->next_to_clean - ring->next_to_use - 1;
496
497 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
498}
499
500/**
501 * e1000e_systim_to_hwtstamp - convert system time value to hw time stamp
502 * @adapter: board private structure
503 * @hwtstamps: time stamp structure to update
504 * @systim: unsigned 64bit system time value.
505 *
506 * Convert the system time value stored in the RX/TXSTMP registers into a
507 * hwtstamp which can be used by the upper level time stamping functions.
508 *
509 * The 'systim_lock' spinlock is used to protect the consistency of the
510 * system time value. This is needed because reading the 64 bit time
511 * value involves reading two 32 bit registers. The first read latches the
512 * value.
513 **/
514static void e1000e_systim_to_hwtstamp(struct e1000_adapter *adapter,
515 struct skb_shared_hwtstamps *hwtstamps,
516 u64 systim)
517{
518 u64 ns;
519 unsigned long flags;
520
521 spin_lock_irqsave(&adapter->systim_lock, flags);
522 ns = timecounter_cyc2time(&adapter->tc, systim);
523 spin_unlock_irqrestore(&adapter->systim_lock, flags);
524
525 memset(hwtstamps, 0, sizeof(*hwtstamps));
526 hwtstamps->hwtstamp = ns_to_ktime(ns);
527}
528
529/**
530 * e1000e_rx_hwtstamp - utility function which checks for Rx time stamp
531 * @adapter: board private structure
532 * @status: descriptor extended error and status field
533 * @skb: particular skb to include time stamp
534 *
535 * If the time stamp is valid, convert it into the timecounter ns value
536 * and store that result into the shhwtstamps structure which is passed
537 * up the network stack.
538 **/
539static void e1000e_rx_hwtstamp(struct e1000_adapter *adapter, u32 status,
540 struct sk_buff *skb)
541{
542 struct e1000_hw *hw = &adapter->hw;
543 u64 rxstmp;
544
545 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP) ||
546 !(status & E1000_RXDEXT_STATERR_TST) ||
547 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
548 return;
549
550 /* The Rx time stamp registers contain the time stamp. No other
551 * received packet will be time stamped until the Rx time stamp
552 * registers are read. Because only one packet can be time stamped
553 * at a time, the register values must belong to this packet and
554 * therefore none of the other additional attributes need to be
555 * compared.
556 */
557 rxstmp = (u64)er32(RXSTMPL);
558 rxstmp |= (u64)er32(RXSTMPH) << 32;
559 e1000e_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), rxstmp);
560
561 adapter->flags2 &= ~FLAG2_CHECK_RX_HWTSTAMP;
562}
563
564/**
565 * e1000_receive_skb - helper function to handle Rx indications
566 * @adapter: board private structure
567 * @netdev: pointer to netdev struct
568 * @staterr: descriptor extended error and status field as written by hardware
569 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
570 * @skb: pointer to sk_buff to be indicated to stack
571 **/
572static void e1000_receive_skb(struct e1000_adapter *adapter,
573 struct net_device *netdev, struct sk_buff *skb,
574 u32 staterr, __le16 vlan)
575{
576 u16 tag = le16_to_cpu(vlan);
577
578 e1000e_rx_hwtstamp(adapter, staterr, skb);
579
580 skb->protocol = eth_type_trans(skb, netdev);
581
582 if (staterr & E1000_RXD_STAT_VP)
583 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), tag);
584
585 napi_gro_receive(&adapter->napi, skb);
586}
587
588/**
589 * e1000_rx_checksum - Receive Checksum Offload
590 * @adapter: board private structure
591 * @status_err: receive descriptor status and error fields
592 * @skb: socket buffer with received data
593 **/
594static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err,
595 struct sk_buff *skb)
596{
597 u16 status = (u16)status_err;
598 u8 errors = (u8)(status_err >> 24);
599
600 skb_checksum_none_assert(skb);
601
602 /* Rx checksum disabled */
603 if (!(adapter->netdev->features & NETIF_F_RXCSUM))
604 return;
605
606 /* Ignore Checksum bit is set */
607 if (status & E1000_RXD_STAT_IXSM)
608 return;
609
610 /* TCP/UDP checksum error bit or IP checksum error bit is set */
611 if (errors & (E1000_RXD_ERR_TCPE | E1000_RXD_ERR_IPE)) {
612 /* let the stack verify checksum errors */
613 adapter->hw_csum_err++;
614 return;
615 }
616
617 /* TCP/UDP Checksum has not been calculated */
618 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
619 return;
620
621 /* It must be a TCP or UDP packet with a valid checksum */
622 skb->ip_summed = CHECKSUM_UNNECESSARY;
623 adapter->hw_csum_good++;
624}
625
626static void e1000e_update_rdt_wa(struct e1000_ring *rx_ring, unsigned int i)
627{
628 struct e1000_adapter *adapter = rx_ring->adapter;
629 struct e1000_hw *hw = &adapter->hw;
630
631 __ew32_prepare(hw);
632 writel(i, rx_ring->tail);
633
634 if (unlikely(i != readl(rx_ring->tail))) {
635 u32 rctl = er32(RCTL);
636
637 ew32(RCTL, rctl & ~E1000_RCTL_EN);
638 e_err("ME firmware caused invalid RDT - resetting\n");
639 schedule_work(&adapter->reset_task);
640 }
641}
642
643static void e1000e_update_tdt_wa(struct e1000_ring *tx_ring, unsigned int i)
644{
645 struct e1000_adapter *adapter = tx_ring->adapter;
646 struct e1000_hw *hw = &adapter->hw;
647
648 __ew32_prepare(hw);
649 writel(i, tx_ring->tail);
650
651 if (unlikely(i != readl(tx_ring->tail))) {
652 u32 tctl = er32(TCTL);
653
654 ew32(TCTL, tctl & ~E1000_TCTL_EN);
655 e_err("ME firmware caused invalid TDT - resetting\n");
656 schedule_work(&adapter->reset_task);
657 }
658}
659
660/**
661 * e1000_alloc_rx_buffers - Replace used receive buffers
662 * @rx_ring: Rx descriptor ring
663 * @cleaned_count: number to reallocate
664 * @gfp: flags for allocation
665 **/
666static void e1000_alloc_rx_buffers(struct e1000_ring *rx_ring,
667 int cleaned_count, gfp_t gfp)
668{
669 struct e1000_adapter *adapter = rx_ring->adapter;
670 struct net_device *netdev = adapter->netdev;
671 struct pci_dev *pdev = adapter->pdev;
672 union e1000_rx_desc_extended *rx_desc;
673 struct e1000_buffer *buffer_info;
674 struct sk_buff *skb;
675 unsigned int i;
676 unsigned int bufsz = adapter->rx_buffer_len;
677
678 i = rx_ring->next_to_use;
679 buffer_info = &rx_ring->buffer_info[i];
680
681 while (cleaned_count--) {
682 skb = buffer_info->skb;
683 if (skb) {
684 skb_trim(skb, 0);
685 goto map_skb;
686 }
687
688 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
689 if (!skb) {
690 /* Better luck next round */
691 adapter->alloc_rx_buff_failed++;
692 break;
693 }
694
695 buffer_info->skb = skb;
696map_skb:
697 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
698 adapter->rx_buffer_len,
699 DMA_FROM_DEVICE);
700 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
701 dev_err(&pdev->dev, "Rx DMA map failed\n");
702 adapter->rx_dma_failed++;
703 break;
704 }
705
706 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
707 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
708
709 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
710 /* Force memory writes to complete before letting h/w
711 * know there are new descriptors to fetch. (Only
712 * applicable for weak-ordered memory model archs,
713 * such as IA-64).
714 */
715 wmb();
716 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
717 e1000e_update_rdt_wa(rx_ring, i);
718 else
719 writel(i, rx_ring->tail);
720 }
721 i++;
722 if (i == rx_ring->count)
723 i = 0;
724 buffer_info = &rx_ring->buffer_info[i];
725 }
726
727 rx_ring->next_to_use = i;
728}
729
730/**
731 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
732 * @rx_ring: Rx descriptor ring
733 * @cleaned_count: number to reallocate
734 * @gfp: flags for allocation
735 **/
736static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring,
737 int cleaned_count, gfp_t gfp)
738{
739 struct e1000_adapter *adapter = rx_ring->adapter;
740 struct net_device *netdev = adapter->netdev;
741 struct pci_dev *pdev = adapter->pdev;
742 union e1000_rx_desc_packet_split *rx_desc;
743 struct e1000_buffer *buffer_info;
744 struct e1000_ps_page *ps_page;
745 struct sk_buff *skb;
746 unsigned int i, j;
747
748 i = rx_ring->next_to_use;
749 buffer_info = &rx_ring->buffer_info[i];
750
751 while (cleaned_count--) {
752 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
753
754 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
755 ps_page = &buffer_info->ps_pages[j];
756 if (j >= adapter->rx_ps_pages) {
757 /* all unused desc entries get hw null ptr */
758 rx_desc->read.buffer_addr[j + 1] =
759 ~cpu_to_le64(0);
760 continue;
761 }
762 if (!ps_page->page) {
763 ps_page->page = alloc_page(gfp);
764 if (!ps_page->page) {
765 adapter->alloc_rx_buff_failed++;
766 goto no_buffers;
767 }
768 ps_page->dma = dma_map_page(&pdev->dev,
769 ps_page->page,
770 0, PAGE_SIZE,
771 DMA_FROM_DEVICE);
772 if (dma_mapping_error(&pdev->dev,
773 ps_page->dma)) {
774 dev_err(&adapter->pdev->dev,
775 "Rx DMA page map failed\n");
776 adapter->rx_dma_failed++;
777 goto no_buffers;
778 }
779 }
780 /* Refresh the desc even if buffer_addrs
781 * didn't change because each write-back
782 * erases this info.
783 */
784 rx_desc->read.buffer_addr[j + 1] =
785 cpu_to_le64(ps_page->dma);
786 }
787
788 skb = __netdev_alloc_skb_ip_align(netdev, adapter->rx_ps_bsize0,
789 gfp);
790
791 if (!skb) {
792 adapter->alloc_rx_buff_failed++;
793 break;
794 }
795
796 buffer_info->skb = skb;
797 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
798 adapter->rx_ps_bsize0,
799 DMA_FROM_DEVICE);
800 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
801 dev_err(&pdev->dev, "Rx DMA map failed\n");
802 adapter->rx_dma_failed++;
803 /* cleanup skb */
804 dev_kfree_skb_any(skb);
805 buffer_info->skb = NULL;
806 break;
807 }
808
809 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
810
811 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
812 /* Force memory writes to complete before letting h/w
813 * know there are new descriptors to fetch. (Only
814 * applicable for weak-ordered memory model archs,
815 * such as IA-64).
816 */
817 wmb();
818 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
819 e1000e_update_rdt_wa(rx_ring, i << 1);
820 else
821 writel(i << 1, rx_ring->tail);
822 }
823
824 i++;
825 if (i == rx_ring->count)
826 i = 0;
827 buffer_info = &rx_ring->buffer_info[i];
828 }
829
830no_buffers:
831 rx_ring->next_to_use = i;
832}
833
834/**
835 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers
836 * @rx_ring: Rx descriptor ring
837 * @cleaned_count: number of buffers to allocate this pass
838 * @gfp: flags for allocation
839 **/
840
841static void e1000_alloc_jumbo_rx_buffers(struct e1000_ring *rx_ring,
842 int cleaned_count, gfp_t gfp)
843{
844 struct e1000_adapter *adapter = rx_ring->adapter;
845 struct net_device *netdev = adapter->netdev;
846 struct pci_dev *pdev = adapter->pdev;
847 union e1000_rx_desc_extended *rx_desc;
848 struct e1000_buffer *buffer_info;
849 struct sk_buff *skb;
850 unsigned int i;
851 unsigned int bufsz = 256 - 16; /* for skb_reserve */
852
853 i = rx_ring->next_to_use;
854 buffer_info = &rx_ring->buffer_info[i];
855
856 while (cleaned_count--) {
857 skb = buffer_info->skb;
858 if (skb) {
859 skb_trim(skb, 0);
860 goto check_page;
861 }
862
863 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
864 if (unlikely(!skb)) {
865 /* Better luck next round */
866 adapter->alloc_rx_buff_failed++;
867 break;
868 }
869
870 buffer_info->skb = skb;
871check_page:
872 /* allocate a new page if necessary */
873 if (!buffer_info->page) {
874 buffer_info->page = alloc_page(gfp);
875 if (unlikely(!buffer_info->page)) {
876 adapter->alloc_rx_buff_failed++;
877 break;
878 }
879 }
880
881 if (!buffer_info->dma) {
882 buffer_info->dma = dma_map_page(&pdev->dev,
883 buffer_info->page, 0,
884 PAGE_SIZE,
885 DMA_FROM_DEVICE);
886 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
887 adapter->alloc_rx_buff_failed++;
888 break;
889 }
890 }
891
892 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
893 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
894
895 if (unlikely(++i == rx_ring->count))
896 i = 0;
897 buffer_info = &rx_ring->buffer_info[i];
898 }
899
900 if (likely(rx_ring->next_to_use != i)) {
901 rx_ring->next_to_use = i;
902 if (unlikely(i-- == 0))
903 i = (rx_ring->count - 1);
904
905 /* Force memory writes to complete before letting h/w
906 * know there are new descriptors to fetch. (Only
907 * applicable for weak-ordered memory model archs,
908 * such as IA-64).
909 */
910 wmb();
911 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
912 e1000e_update_rdt_wa(rx_ring, i);
913 else
914 writel(i, rx_ring->tail);
915 }
916}
917
918static inline void e1000_rx_hash(struct net_device *netdev, __le32 rss,
919 struct sk_buff *skb)
920{
921 if (netdev->features & NETIF_F_RXHASH)
922 skb_set_hash(skb, le32_to_cpu(rss), PKT_HASH_TYPE_L3);
923}
924
925/**
926 * e1000_clean_rx_irq - Send received data up the network stack
927 * @rx_ring: Rx descriptor ring
928 * @work_done: output parameter for indicating completed work
929 * @work_to_do: how many packets we can clean
930 *
931 * the return value indicates whether actual cleaning was done, there
932 * is no guarantee that everything was cleaned
933 **/
934static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done,
935 int work_to_do)
936{
937 struct e1000_adapter *adapter = rx_ring->adapter;
938 struct net_device *netdev = adapter->netdev;
939 struct pci_dev *pdev = adapter->pdev;
940 struct e1000_hw *hw = &adapter->hw;
941 union e1000_rx_desc_extended *rx_desc, *next_rxd;
942 struct e1000_buffer *buffer_info, *next_buffer;
943 u32 length, staterr;
944 unsigned int i;
945 int cleaned_count = 0;
946 bool cleaned = false;
947 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
948
949 i = rx_ring->next_to_clean;
950 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
951 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
952 buffer_info = &rx_ring->buffer_info[i];
953
954 while (staterr & E1000_RXD_STAT_DD) {
955 struct sk_buff *skb;
956
957 if (*work_done >= work_to_do)
958 break;
959 (*work_done)++;
960 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */
961
962 skb = buffer_info->skb;
963 buffer_info->skb = NULL;
964
965 prefetch(skb->data - NET_IP_ALIGN);
966
967 i++;
968 if (i == rx_ring->count)
969 i = 0;
970 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
971 prefetch(next_rxd);
972
973 next_buffer = &rx_ring->buffer_info[i];
974
975 cleaned = true;
976 cleaned_count++;
977 dma_unmap_single(&pdev->dev, buffer_info->dma,
978 adapter->rx_buffer_len, DMA_FROM_DEVICE);
979 buffer_info->dma = 0;
980
981 length = le16_to_cpu(rx_desc->wb.upper.length);
982
983 /* !EOP means multiple descriptors were used to store a single
984 * packet, if that's the case we need to toss it. In fact, we
985 * need to toss every packet with the EOP bit clear and the
986 * next frame that _does_ have the EOP bit set, as it is by
987 * definition only a frame fragment
988 */
989 if (unlikely(!(staterr & E1000_RXD_STAT_EOP)))
990 adapter->flags2 |= FLAG2_IS_DISCARDING;
991
992 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
993 /* All receives must fit into a single buffer */
994 e_dbg("Receive packet consumed multiple buffers\n");
995 /* recycle */
996 buffer_info->skb = skb;
997 if (staterr & E1000_RXD_STAT_EOP)
998 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
999 goto next_desc;
1000 }
1001
1002 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1003 !(netdev->features & NETIF_F_RXALL))) {
1004 /* recycle */
1005 buffer_info->skb = skb;
1006 goto next_desc;
1007 }
1008
1009 /* adjust length to remove Ethernet CRC */
1010 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1011 /* If configured to store CRC, don't subtract FCS,
1012 * but keep the FCS bytes out of the total_rx_bytes
1013 * counter
1014 */
1015 if (netdev->features & NETIF_F_RXFCS)
1016 total_rx_bytes -= 4;
1017 else
1018 length -= 4;
1019 }
1020
1021 total_rx_bytes += length;
1022 total_rx_packets++;
1023
1024 /* code added for copybreak, this should improve
1025 * performance for small packets with large amounts
1026 * of reassembly being done in the stack
1027 */
1028 if (length < copybreak) {
1029 struct sk_buff *new_skb =
1030 napi_alloc_skb(&adapter->napi, length);
1031 if (new_skb) {
1032 skb_copy_to_linear_data_offset(new_skb,
1033 -NET_IP_ALIGN,
1034 (skb->data -
1035 NET_IP_ALIGN),
1036 (length +
1037 NET_IP_ALIGN));
1038 /* save the skb in buffer_info as good */
1039 buffer_info->skb = skb;
1040 skb = new_skb;
1041 }
1042 /* else just continue with the old one */
1043 }
1044 /* end copybreak code */
1045 skb_put(skb, length);
1046
1047 /* Receive Checksum Offload */
1048 e1000_rx_checksum(adapter, staterr, skb);
1049
1050 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1051
1052 e1000_receive_skb(adapter, netdev, skb, staterr,
1053 rx_desc->wb.upper.vlan);
1054
1055next_desc:
1056 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
1057
1058 /* return some buffers to hardware, one at a time is too slow */
1059 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
1060 adapter->alloc_rx_buf(rx_ring, cleaned_count,
1061 GFP_ATOMIC);
1062 cleaned_count = 0;
1063 }
1064
1065 /* use prefetched values */
1066 rx_desc = next_rxd;
1067 buffer_info = next_buffer;
1068
1069 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1070 }
1071 rx_ring->next_to_clean = i;
1072
1073 cleaned_count = e1000_desc_unused(rx_ring);
1074 if (cleaned_count)
1075 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
1076
1077 adapter->total_rx_bytes += total_rx_bytes;
1078 adapter->total_rx_packets += total_rx_packets;
1079 return cleaned;
1080}
1081
1082static void e1000_put_txbuf(struct e1000_ring *tx_ring,
1083 struct e1000_buffer *buffer_info,
1084 bool drop)
1085{
1086 struct e1000_adapter *adapter = tx_ring->adapter;
1087
1088 if (buffer_info->dma) {
1089 if (buffer_info->mapped_as_page)
1090 dma_unmap_page(&adapter->pdev->dev, buffer_info->dma,
1091 buffer_info->length, DMA_TO_DEVICE);
1092 else
1093 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1094 buffer_info->length, DMA_TO_DEVICE);
1095 buffer_info->dma = 0;
1096 }
1097 if (buffer_info->skb) {
1098 if (drop)
1099 dev_kfree_skb_any(buffer_info->skb);
1100 else
1101 dev_consume_skb_any(buffer_info->skb);
1102 buffer_info->skb = NULL;
1103 }
1104 buffer_info->time_stamp = 0;
1105}
1106
1107static void e1000_print_hw_hang(struct work_struct *work)
1108{
1109 struct e1000_adapter *adapter = container_of(work,
1110 struct e1000_adapter,
1111 print_hang_task);
1112 struct net_device *netdev = adapter->netdev;
1113 struct e1000_ring *tx_ring = adapter->tx_ring;
1114 unsigned int i = tx_ring->next_to_clean;
1115 unsigned int eop = tx_ring->buffer_info[i].next_to_watch;
1116 struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop);
1117 struct e1000_hw *hw = &adapter->hw;
1118 u16 phy_status, phy_1000t_status, phy_ext_status;
1119 u16 pci_status;
1120
1121 if (test_bit(__E1000_DOWN, &adapter->state))
1122 return;
1123
1124 if (!adapter->tx_hang_recheck && (adapter->flags2 & FLAG2_DMA_BURST)) {
1125 /* May be block on write-back, flush and detect again
1126 * flush pending descriptor writebacks to memory
1127 */
1128 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1129 /* execute the writes immediately */
1130 e1e_flush();
1131 /* Due to rare timing issues, write to TIDV again to ensure
1132 * the write is successful
1133 */
1134 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1135 /* execute the writes immediately */
1136 e1e_flush();
1137 adapter->tx_hang_recheck = true;
1138 return;
1139 }
1140 adapter->tx_hang_recheck = false;
1141
1142 if (er32(TDH(0)) == er32(TDT(0))) {
1143 e_dbg("false hang detected, ignoring\n");
1144 return;
1145 }
1146
1147 /* Real hang detected */
1148 netif_stop_queue(netdev);
1149
1150 e1e_rphy(hw, MII_BMSR, &phy_status);
1151 e1e_rphy(hw, MII_STAT1000, &phy_1000t_status);
1152 e1e_rphy(hw, MII_ESTATUS, &phy_ext_status);
1153
1154 pci_read_config_word(adapter->pdev, PCI_STATUS, &pci_status);
1155
1156 /* detected Hardware unit hang */
1157 e_err("Detected Hardware Unit Hang:\n"
1158 " TDH <%x>\n"
1159 " TDT <%x>\n"
1160 " next_to_use <%x>\n"
1161 " next_to_clean <%x>\n"
1162 "buffer_info[next_to_clean]:\n"
1163 " time_stamp <%lx>\n"
1164 " next_to_watch <%x>\n"
1165 " jiffies <%lx>\n"
1166 " next_to_watch.status <%x>\n"
1167 "MAC Status <%x>\n"
1168 "PHY Status <%x>\n"
1169 "PHY 1000BASE-T Status <%x>\n"
1170 "PHY Extended Status <%x>\n"
1171 "PCI Status <%x>\n",
1172 readl(tx_ring->head), readl(tx_ring->tail), tx_ring->next_to_use,
1173 tx_ring->next_to_clean, tx_ring->buffer_info[eop].time_stamp,
1174 eop, jiffies, eop_desc->upper.fields.status, er32(STATUS),
1175 phy_status, phy_1000t_status, phy_ext_status, pci_status);
1176
1177 e1000e_dump(adapter);
1178
1179 /* Suggest workaround for known h/w issue */
1180 if ((hw->mac.type == e1000_pchlan) && (er32(CTRL) & E1000_CTRL_TFCE))
1181 e_err("Try turning off Tx pause (flow control) via ethtool\n");
1182}
1183
1184/**
1185 * e1000e_tx_hwtstamp_work - check for Tx time stamp
1186 * @work: pointer to work struct
1187 *
1188 * This work function polls the TSYNCTXCTL valid bit to determine when a
1189 * timestamp has been taken for the current stored skb. The timestamp must
1190 * be for this skb because only one such packet is allowed in the queue.
1191 */
1192static void e1000e_tx_hwtstamp_work(struct work_struct *work)
1193{
1194 struct e1000_adapter *adapter = container_of(work, struct e1000_adapter,
1195 tx_hwtstamp_work);
1196 struct e1000_hw *hw = &adapter->hw;
1197
1198 if (er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID) {
1199 struct sk_buff *skb = adapter->tx_hwtstamp_skb;
1200 struct skb_shared_hwtstamps shhwtstamps;
1201 u64 txstmp;
1202
1203 txstmp = er32(TXSTMPL);
1204 txstmp |= (u64)er32(TXSTMPH) << 32;
1205
1206 e1000e_systim_to_hwtstamp(adapter, &shhwtstamps, txstmp);
1207
1208 /* Clear the global tx_hwtstamp_skb pointer and force writes
1209 * prior to notifying the stack of a Tx timestamp.
1210 */
1211 adapter->tx_hwtstamp_skb = NULL;
1212 wmb(); /* force write prior to skb_tstamp_tx */
1213
1214 skb_tstamp_tx(skb, &shhwtstamps);
1215 dev_consume_skb_any(skb);
1216 } else if (time_after(jiffies, adapter->tx_hwtstamp_start
1217 + adapter->tx_timeout_factor * HZ)) {
1218 dev_kfree_skb_any(adapter->tx_hwtstamp_skb);
1219 adapter->tx_hwtstamp_skb = NULL;
1220 adapter->tx_hwtstamp_timeouts++;
1221 e_warn("clearing Tx timestamp hang\n");
1222 } else {
1223 /* reschedule to check later */
1224 schedule_work(&adapter->tx_hwtstamp_work);
1225 }
1226}
1227
1228/**
1229 * e1000_clean_tx_irq - Reclaim resources after transmit completes
1230 * @tx_ring: Tx descriptor ring
1231 *
1232 * the return value indicates whether actual cleaning was done, there
1233 * is no guarantee that everything was cleaned
1234 **/
1235static bool e1000_clean_tx_irq(struct e1000_ring *tx_ring)
1236{
1237 struct e1000_adapter *adapter = tx_ring->adapter;
1238 struct net_device *netdev = adapter->netdev;
1239 struct e1000_hw *hw = &adapter->hw;
1240 struct e1000_tx_desc *tx_desc, *eop_desc;
1241 struct e1000_buffer *buffer_info;
1242 unsigned int i, eop;
1243 unsigned int count = 0;
1244 unsigned int total_tx_bytes = 0, total_tx_packets = 0;
1245 unsigned int bytes_compl = 0, pkts_compl = 0;
1246
1247 i = tx_ring->next_to_clean;
1248 eop = tx_ring->buffer_info[i].next_to_watch;
1249 eop_desc = E1000_TX_DESC(*tx_ring, eop);
1250
1251 while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) &&
1252 (count < tx_ring->count)) {
1253 bool cleaned = false;
1254
1255 dma_rmb(); /* read buffer_info after eop_desc */
1256 for (; !cleaned; count++) {
1257 tx_desc = E1000_TX_DESC(*tx_ring, i);
1258 buffer_info = &tx_ring->buffer_info[i];
1259 cleaned = (i == eop);
1260
1261 if (cleaned) {
1262 total_tx_packets += buffer_info->segs;
1263 total_tx_bytes += buffer_info->bytecount;
1264 if (buffer_info->skb) {
1265 bytes_compl += buffer_info->skb->len;
1266 pkts_compl++;
1267 }
1268 }
1269
1270 e1000_put_txbuf(tx_ring, buffer_info, false);
1271 tx_desc->upper.data = 0;
1272
1273 i++;
1274 if (i == tx_ring->count)
1275 i = 0;
1276 }
1277
1278 if (i == tx_ring->next_to_use)
1279 break;
1280 eop = tx_ring->buffer_info[i].next_to_watch;
1281 eop_desc = E1000_TX_DESC(*tx_ring, eop);
1282 }
1283
1284 tx_ring->next_to_clean = i;
1285
1286 netdev_completed_queue(netdev, pkts_compl, bytes_compl);
1287
1288#define TX_WAKE_THRESHOLD 32
1289 if (count && netif_carrier_ok(netdev) &&
1290 e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) {
1291 /* Make sure that anybody stopping the queue after this
1292 * sees the new next_to_clean.
1293 */
1294 smp_mb();
1295
1296 if (netif_queue_stopped(netdev) &&
1297 !(test_bit(__E1000_DOWN, &adapter->state))) {
1298 netif_wake_queue(netdev);
1299 ++adapter->restart_queue;
1300 }
1301 }
1302
1303 if (adapter->detect_tx_hung) {
1304 /* Detect a transmit hang in hardware, this serializes the
1305 * check with the clearing of time_stamp and movement of i
1306 */
1307 adapter->detect_tx_hung = false;
1308 if (tx_ring->buffer_info[i].time_stamp &&
1309 time_after(jiffies, tx_ring->buffer_info[i].time_stamp
1310 + (adapter->tx_timeout_factor * HZ)) &&
1311 !(er32(STATUS) & E1000_STATUS_TXOFF))
1312 schedule_work(&adapter->print_hang_task);
1313 else
1314 adapter->tx_hang_recheck = false;
1315 }
1316 adapter->total_tx_bytes += total_tx_bytes;
1317 adapter->total_tx_packets += total_tx_packets;
1318 return count < tx_ring->count;
1319}
1320
1321/**
1322 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
1323 * @rx_ring: Rx descriptor ring
1324 * @work_done: output parameter for indicating completed work
1325 * @work_to_do: how many packets we can clean
1326 *
1327 * the return value indicates whether actual cleaning was done, there
1328 * is no guarantee that everything was cleaned
1329 **/
1330static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done,
1331 int work_to_do)
1332{
1333 struct e1000_adapter *adapter = rx_ring->adapter;
1334 struct e1000_hw *hw = &adapter->hw;
1335 union e1000_rx_desc_packet_split *rx_desc, *next_rxd;
1336 struct net_device *netdev = adapter->netdev;
1337 struct pci_dev *pdev = adapter->pdev;
1338 struct e1000_buffer *buffer_info, *next_buffer;
1339 struct e1000_ps_page *ps_page;
1340 struct sk_buff *skb;
1341 unsigned int i, j;
1342 u32 length, staterr;
1343 int cleaned_count = 0;
1344 bool cleaned = false;
1345 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1346
1347 i = rx_ring->next_to_clean;
1348 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
1349 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1350 buffer_info = &rx_ring->buffer_info[i];
1351
1352 while (staterr & E1000_RXD_STAT_DD) {
1353 if (*work_done >= work_to_do)
1354 break;
1355 (*work_done)++;
1356 skb = buffer_info->skb;
1357 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */
1358
1359 /* in the packet split case this is header only */
1360 prefetch(skb->data - NET_IP_ALIGN);
1361
1362 i++;
1363 if (i == rx_ring->count)
1364 i = 0;
1365 next_rxd = E1000_RX_DESC_PS(*rx_ring, i);
1366 prefetch(next_rxd);
1367
1368 next_buffer = &rx_ring->buffer_info[i];
1369
1370 cleaned = true;
1371 cleaned_count++;
1372 dma_unmap_single(&pdev->dev, buffer_info->dma,
1373 adapter->rx_ps_bsize0, DMA_FROM_DEVICE);
1374 buffer_info->dma = 0;
1375
1376 /* see !EOP comment in other Rx routine */
1377 if (!(staterr & E1000_RXD_STAT_EOP))
1378 adapter->flags2 |= FLAG2_IS_DISCARDING;
1379
1380 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
1381 e_dbg("Packet Split buffers didn't pick up the full packet\n");
1382 dev_kfree_skb_irq(skb);
1383 if (staterr & E1000_RXD_STAT_EOP)
1384 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
1385 goto next_desc;
1386 }
1387
1388 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1389 !(netdev->features & NETIF_F_RXALL))) {
1390 dev_kfree_skb_irq(skb);
1391 goto next_desc;
1392 }
1393
1394 length = le16_to_cpu(rx_desc->wb.middle.length0);
1395
1396 if (!length) {
1397 e_dbg("Last part of the packet spanning multiple descriptors\n");
1398 dev_kfree_skb_irq(skb);
1399 goto next_desc;
1400 }
1401
1402 /* Good Receive */
1403 skb_put(skb, length);
1404
1405 {
1406 /* this looks ugly, but it seems compiler issues make
1407 * it more efficient than reusing j
1408 */
1409 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]);
1410
1411 /* page alloc/put takes too long and effects small
1412 * packet throughput, so unsplit small packets and
1413 * save the alloc/put
1414 */
1415 if (l1 && (l1 <= copybreak) &&
1416 ((length + l1) <= adapter->rx_ps_bsize0)) {
1417 ps_page = &buffer_info->ps_pages[0];
1418
1419 dma_sync_single_for_cpu(&pdev->dev,
1420 ps_page->dma,
1421 PAGE_SIZE,
1422 DMA_FROM_DEVICE);
1423 memcpy(skb_tail_pointer(skb),
1424 page_address(ps_page->page), l1);
1425 dma_sync_single_for_device(&pdev->dev,
1426 ps_page->dma,
1427 PAGE_SIZE,
1428 DMA_FROM_DEVICE);
1429
1430 /* remove the CRC */
1431 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1432 if (!(netdev->features & NETIF_F_RXFCS))
1433 l1 -= 4;
1434 }
1435
1436 skb_put(skb, l1);
1437 goto copydone;
1438 } /* if */
1439 }
1440
1441 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
1442 length = le16_to_cpu(rx_desc->wb.upper.length[j]);
1443 if (!length)
1444 break;
1445
1446 ps_page = &buffer_info->ps_pages[j];
1447 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1448 DMA_FROM_DEVICE);
1449 ps_page->dma = 0;
1450 skb_fill_page_desc(skb, j, ps_page->page, 0, length);
1451 ps_page->page = NULL;
1452 skb->len += length;
1453 skb->data_len += length;
1454 skb->truesize += PAGE_SIZE;
1455 }
1456
1457 /* strip the ethernet crc, problem is we're using pages now so
1458 * this whole operation can get a little cpu intensive
1459 */
1460 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1461 if (!(netdev->features & NETIF_F_RXFCS))
1462 pskb_trim(skb, skb->len - 4);
1463 }
1464
1465copydone:
1466 total_rx_bytes += skb->len;
1467 total_rx_packets++;
1468
1469 e1000_rx_checksum(adapter, staterr, skb);
1470
1471 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1472
1473 if (rx_desc->wb.upper.header_status &
1474 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP))
1475 adapter->rx_hdr_split++;
1476
1477 e1000_receive_skb(adapter, netdev, skb, staterr,
1478 rx_desc->wb.middle.vlan);
1479
1480next_desc:
1481 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF);
1482 buffer_info->skb = NULL;
1483
1484 /* return some buffers to hardware, one at a time is too slow */
1485 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
1486 adapter->alloc_rx_buf(rx_ring, cleaned_count,
1487 GFP_ATOMIC);
1488 cleaned_count = 0;
1489 }
1490
1491 /* use prefetched values */
1492 rx_desc = next_rxd;
1493 buffer_info = next_buffer;
1494
1495 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1496 }
1497 rx_ring->next_to_clean = i;
1498
1499 cleaned_count = e1000_desc_unused(rx_ring);
1500 if (cleaned_count)
1501 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
1502
1503 adapter->total_rx_bytes += total_rx_bytes;
1504 adapter->total_rx_packets += total_rx_packets;
1505 return cleaned;
1506}
1507
1508static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb,
1509 u16 length)
1510{
1511 bi->page = NULL;
1512 skb->len += length;
1513 skb->data_len += length;
1514 skb->truesize += PAGE_SIZE;
1515}
1516
1517/**
1518 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy
1519 * @rx_ring: Rx descriptor ring
1520 * @work_done: output parameter for indicating completed work
1521 * @work_to_do: how many packets we can clean
1522 *
1523 * the return value indicates whether actual cleaning was done, there
1524 * is no guarantee that everything was cleaned
1525 **/
1526static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done,
1527 int work_to_do)
1528{
1529 struct e1000_adapter *adapter = rx_ring->adapter;
1530 struct net_device *netdev = adapter->netdev;
1531 struct pci_dev *pdev = adapter->pdev;
1532 union e1000_rx_desc_extended *rx_desc, *next_rxd;
1533 struct e1000_buffer *buffer_info, *next_buffer;
1534 u32 length, staterr;
1535 unsigned int i;
1536 int cleaned_count = 0;
1537 bool cleaned = false;
1538 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1539 struct skb_shared_info *shinfo;
1540
1541 i = rx_ring->next_to_clean;
1542 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
1543 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1544 buffer_info = &rx_ring->buffer_info[i];
1545
1546 while (staterr & E1000_RXD_STAT_DD) {
1547 struct sk_buff *skb;
1548
1549 if (*work_done >= work_to_do)
1550 break;
1551 (*work_done)++;
1552 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */
1553
1554 skb = buffer_info->skb;
1555 buffer_info->skb = NULL;
1556
1557 ++i;
1558 if (i == rx_ring->count)
1559 i = 0;
1560 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
1561 prefetch(next_rxd);
1562
1563 next_buffer = &rx_ring->buffer_info[i];
1564
1565 cleaned = true;
1566 cleaned_count++;
1567 dma_unmap_page(&pdev->dev, buffer_info->dma, PAGE_SIZE,
1568 DMA_FROM_DEVICE);
1569 buffer_info->dma = 0;
1570
1571 length = le16_to_cpu(rx_desc->wb.upper.length);
1572
1573 /* errors is only valid for DD + EOP descriptors */
1574 if (unlikely((staterr & E1000_RXD_STAT_EOP) &&
1575 ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1576 !(netdev->features & NETIF_F_RXALL)))) {
1577 /* recycle both page and skb */
1578 buffer_info->skb = skb;
1579 /* an error means any chain goes out the window too */
1580 if (rx_ring->rx_skb_top)
1581 dev_kfree_skb_irq(rx_ring->rx_skb_top);
1582 rx_ring->rx_skb_top = NULL;
1583 goto next_desc;
1584 }
1585#define rxtop (rx_ring->rx_skb_top)
1586 if (!(staterr & E1000_RXD_STAT_EOP)) {
1587 /* this descriptor is only the beginning (or middle) */
1588 if (!rxtop) {
1589 /* this is the beginning of a chain */
1590 rxtop = skb;
1591 skb_fill_page_desc(rxtop, 0, buffer_info->page,
1592 0, length);
1593 } else {
1594 /* this is the middle of a chain */
1595 shinfo = skb_shinfo(rxtop);
1596 skb_fill_page_desc(rxtop, shinfo->nr_frags,
1597 buffer_info->page, 0,
1598 length);
1599 /* re-use the skb, only consumed the page */
1600 buffer_info->skb = skb;
1601 }
1602 e1000_consume_page(buffer_info, rxtop, length);
1603 goto next_desc;
1604 } else {
1605 if (rxtop) {
1606 /* end of the chain */
1607 shinfo = skb_shinfo(rxtop);
1608 skb_fill_page_desc(rxtop, shinfo->nr_frags,
1609 buffer_info->page, 0,
1610 length);
1611 /* re-use the current skb, we only consumed the
1612 * page
1613 */
1614 buffer_info->skb = skb;
1615 skb = rxtop;
1616 rxtop = NULL;
1617 e1000_consume_page(buffer_info, skb, length);
1618 } else {
1619 /* no chain, got EOP, this buf is the packet
1620 * copybreak to save the put_page/alloc_page
1621 */
1622 if (length <= copybreak &&
1623 skb_tailroom(skb) >= length) {
1624 memcpy(skb_tail_pointer(skb),
1625 page_address(buffer_info->page),
1626 length);
1627 /* re-use the page, so don't erase
1628 * buffer_info->page
1629 */
1630 skb_put(skb, length);
1631 } else {
1632 skb_fill_page_desc(skb, 0,
1633 buffer_info->page, 0,
1634 length);
1635 e1000_consume_page(buffer_info, skb,
1636 length);
1637 }
1638 }
1639 }
1640
1641 /* Receive Checksum Offload */
1642 e1000_rx_checksum(adapter, staterr, skb);
1643
1644 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1645
1646 /* probably a little skewed due to removing CRC */
1647 total_rx_bytes += skb->len;
1648 total_rx_packets++;
1649
1650 /* eth type trans needs skb->data to point to something */
1651 if (!pskb_may_pull(skb, ETH_HLEN)) {
1652 e_err("pskb_may_pull failed.\n");
1653 dev_kfree_skb_irq(skb);
1654 goto next_desc;
1655 }
1656
1657 e1000_receive_skb(adapter, netdev, skb, staterr,
1658 rx_desc->wb.upper.vlan);
1659
1660next_desc:
1661 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
1662
1663 /* return some buffers to hardware, one at a time is too slow */
1664 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
1665 adapter->alloc_rx_buf(rx_ring, cleaned_count,
1666 GFP_ATOMIC);
1667 cleaned_count = 0;
1668 }
1669
1670 /* use prefetched values */
1671 rx_desc = next_rxd;
1672 buffer_info = next_buffer;
1673
1674 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1675 }
1676 rx_ring->next_to_clean = i;
1677
1678 cleaned_count = e1000_desc_unused(rx_ring);
1679 if (cleaned_count)
1680 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
1681
1682 adapter->total_rx_bytes += total_rx_bytes;
1683 adapter->total_rx_packets += total_rx_packets;
1684 return cleaned;
1685}
1686
1687/**
1688 * e1000_clean_rx_ring - Free Rx Buffers per Queue
1689 * @rx_ring: Rx descriptor ring
1690 **/
1691static void e1000_clean_rx_ring(struct e1000_ring *rx_ring)
1692{
1693 struct e1000_adapter *adapter = rx_ring->adapter;
1694 struct e1000_buffer *buffer_info;
1695 struct e1000_ps_page *ps_page;
1696 struct pci_dev *pdev = adapter->pdev;
1697 unsigned int i, j;
1698
1699 /* Free all the Rx ring sk_buffs */
1700 for (i = 0; i < rx_ring->count; i++) {
1701 buffer_info = &rx_ring->buffer_info[i];
1702 if (buffer_info->dma) {
1703 if (adapter->clean_rx == e1000_clean_rx_irq)
1704 dma_unmap_single(&pdev->dev, buffer_info->dma,
1705 adapter->rx_buffer_len,
1706 DMA_FROM_DEVICE);
1707 else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq)
1708 dma_unmap_page(&pdev->dev, buffer_info->dma,
1709 PAGE_SIZE, DMA_FROM_DEVICE);
1710 else if (adapter->clean_rx == e1000_clean_rx_irq_ps)
1711 dma_unmap_single(&pdev->dev, buffer_info->dma,
1712 adapter->rx_ps_bsize0,
1713 DMA_FROM_DEVICE);
1714 buffer_info->dma = 0;
1715 }
1716
1717 if (buffer_info->page) {
1718 put_page(buffer_info->page);
1719 buffer_info->page = NULL;
1720 }
1721
1722 if (buffer_info->skb) {
1723 dev_kfree_skb(buffer_info->skb);
1724 buffer_info->skb = NULL;
1725 }
1726
1727 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
1728 ps_page = &buffer_info->ps_pages[j];
1729 if (!ps_page->page)
1730 break;
1731 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1732 DMA_FROM_DEVICE);
1733 ps_page->dma = 0;
1734 put_page(ps_page->page);
1735 ps_page->page = NULL;
1736 }
1737 }
1738
1739 /* there also may be some cached data from a chained receive */
1740 if (rx_ring->rx_skb_top) {
1741 dev_kfree_skb(rx_ring->rx_skb_top);
1742 rx_ring->rx_skb_top = NULL;
1743 }
1744
1745 /* Zero out the descriptor ring */
1746 memset(rx_ring->desc, 0, rx_ring->size);
1747
1748 rx_ring->next_to_clean = 0;
1749 rx_ring->next_to_use = 0;
1750 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
1751}
1752
1753static void e1000e_downshift_workaround(struct work_struct *work)
1754{
1755 struct e1000_adapter *adapter = container_of(work,
1756 struct e1000_adapter,
1757 downshift_task);
1758
1759 if (test_bit(__E1000_DOWN, &adapter->state))
1760 return;
1761
1762 e1000e_gig_downshift_workaround_ich8lan(&adapter->hw);
1763}
1764
1765/**
1766 * e1000_intr_msi - Interrupt Handler
1767 * @irq: interrupt number
1768 * @data: pointer to a network interface device structure
1769 **/
1770static irqreturn_t e1000_intr_msi(int __always_unused irq, void *data)
1771{
1772 struct net_device *netdev = data;
1773 struct e1000_adapter *adapter = netdev_priv(netdev);
1774 struct e1000_hw *hw = &adapter->hw;
1775 u32 icr = er32(ICR);
1776
1777 /* read ICR disables interrupts using IAM */
1778 if (icr & E1000_ICR_LSC) {
1779 hw->mac.get_link_status = true;
1780 /* ICH8 workaround-- Call gig speed drop workaround on cable
1781 * disconnect (LSC) before accessing any PHY registers
1782 */
1783 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1784 (!(er32(STATUS) & E1000_STATUS_LU)))
1785 schedule_work(&adapter->downshift_task);
1786
1787 /* 80003ES2LAN workaround-- For packet buffer work-around on
1788 * link down event; disable receives here in the ISR and reset
1789 * adapter in watchdog
1790 */
1791 if (netif_carrier_ok(netdev) &&
1792 adapter->flags & FLAG_RX_NEEDS_RESTART) {
1793 /* disable receives */
1794 u32 rctl = er32(RCTL);
1795
1796 ew32(RCTL, rctl & ~E1000_RCTL_EN);
1797 adapter->flags |= FLAG_RESTART_NOW;
1798 }
1799 /* guard against interrupt when we're going down */
1800 if (!test_bit(__E1000_DOWN, &adapter->state))
1801 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1802 }
1803
1804 /* Reset on uncorrectable ECC error */
1805 if ((icr & E1000_ICR_ECCER) && (hw->mac.type >= e1000_pch_lpt)) {
1806 u32 pbeccsts = er32(PBECCSTS);
1807
1808 adapter->corr_errors +=
1809 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
1810 adapter->uncorr_errors +=
1811 FIELD_GET(E1000_PBECCSTS_UNCORR_ERR_CNT_MASK, pbeccsts);
1812
1813 /* Do the reset outside of interrupt context */
1814 schedule_work(&adapter->reset_task);
1815
1816 /* return immediately since reset is imminent */
1817 return IRQ_HANDLED;
1818 }
1819
1820 if (napi_schedule_prep(&adapter->napi)) {
1821 adapter->total_tx_bytes = 0;
1822 adapter->total_tx_packets = 0;
1823 adapter->total_rx_bytes = 0;
1824 adapter->total_rx_packets = 0;
1825 __napi_schedule_irqoff(&adapter->napi);
1826 }
1827
1828 return IRQ_HANDLED;
1829}
1830
1831/**
1832 * e1000_intr - Interrupt Handler
1833 * @irq: interrupt number
1834 * @data: pointer to a network interface device structure
1835 **/
1836static irqreturn_t e1000_intr(int __always_unused irq, void *data)
1837{
1838 struct net_device *netdev = data;
1839 struct e1000_adapter *adapter = netdev_priv(netdev);
1840 struct e1000_hw *hw = &adapter->hw;
1841 u32 rctl, icr = er32(ICR);
1842
1843 if (!icr || test_bit(__E1000_DOWN, &adapter->state))
1844 return IRQ_NONE; /* Not our interrupt */
1845
1846 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
1847 * not set, then the adapter didn't send an interrupt
1848 */
1849 if (!(icr & E1000_ICR_INT_ASSERTED))
1850 return IRQ_NONE;
1851
1852 /* Interrupt Auto-Mask...upon reading ICR,
1853 * interrupts are masked. No need for the
1854 * IMC write
1855 */
1856
1857 if (icr & E1000_ICR_LSC) {
1858 hw->mac.get_link_status = true;
1859 /* ICH8 workaround-- Call gig speed drop workaround on cable
1860 * disconnect (LSC) before accessing any PHY registers
1861 */
1862 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1863 (!(er32(STATUS) & E1000_STATUS_LU)))
1864 schedule_work(&adapter->downshift_task);
1865
1866 /* 80003ES2LAN workaround--
1867 * For packet buffer work-around on link down event;
1868 * disable receives here in the ISR and
1869 * reset adapter in watchdog
1870 */
1871 if (netif_carrier_ok(netdev) &&
1872 (adapter->flags & FLAG_RX_NEEDS_RESTART)) {
1873 /* disable receives */
1874 rctl = er32(RCTL);
1875 ew32(RCTL, rctl & ~E1000_RCTL_EN);
1876 adapter->flags |= FLAG_RESTART_NOW;
1877 }
1878 /* guard against interrupt when we're going down */
1879 if (!test_bit(__E1000_DOWN, &adapter->state))
1880 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1881 }
1882
1883 /* Reset on uncorrectable ECC error */
1884 if ((icr & E1000_ICR_ECCER) && (hw->mac.type >= e1000_pch_lpt)) {
1885 u32 pbeccsts = er32(PBECCSTS);
1886
1887 adapter->corr_errors +=
1888 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
1889 adapter->uncorr_errors +=
1890 FIELD_GET(E1000_PBECCSTS_UNCORR_ERR_CNT_MASK, pbeccsts);
1891
1892 /* Do the reset outside of interrupt context */
1893 schedule_work(&adapter->reset_task);
1894
1895 /* return immediately since reset is imminent */
1896 return IRQ_HANDLED;
1897 }
1898
1899 if (napi_schedule_prep(&adapter->napi)) {
1900 adapter->total_tx_bytes = 0;
1901 adapter->total_tx_packets = 0;
1902 adapter->total_rx_bytes = 0;
1903 adapter->total_rx_packets = 0;
1904 __napi_schedule_irqoff(&adapter->napi);
1905 }
1906
1907 return IRQ_HANDLED;
1908}
1909
1910static irqreturn_t e1000_msix_other(int __always_unused irq, void *data)
1911{
1912 struct net_device *netdev = data;
1913 struct e1000_adapter *adapter = netdev_priv(netdev);
1914 struct e1000_hw *hw = &adapter->hw;
1915 u32 icr = er32(ICR);
1916
1917 if (icr & adapter->eiac_mask)
1918 ew32(ICS, (icr & adapter->eiac_mask));
1919
1920 if (icr & E1000_ICR_LSC) {
1921 hw->mac.get_link_status = true;
1922 /* guard against interrupt when we're going down */
1923 if (!test_bit(__E1000_DOWN, &adapter->state))
1924 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1925 }
1926
1927 if (!test_bit(__E1000_DOWN, &adapter->state))
1928 ew32(IMS, E1000_IMS_OTHER | IMS_OTHER_MASK);
1929
1930 return IRQ_HANDLED;
1931}
1932
1933static irqreturn_t e1000_intr_msix_tx(int __always_unused irq, void *data)
1934{
1935 struct net_device *netdev = data;
1936 struct e1000_adapter *adapter = netdev_priv(netdev);
1937 struct e1000_hw *hw = &adapter->hw;
1938 struct e1000_ring *tx_ring = adapter->tx_ring;
1939
1940 adapter->total_tx_bytes = 0;
1941 adapter->total_tx_packets = 0;
1942
1943 if (!e1000_clean_tx_irq(tx_ring))
1944 /* Ring was not completely cleaned, so fire another interrupt */
1945 ew32(ICS, tx_ring->ims_val);
1946
1947 if (!test_bit(__E1000_DOWN, &adapter->state))
1948 ew32(IMS, adapter->tx_ring->ims_val);
1949
1950 return IRQ_HANDLED;
1951}
1952
1953static irqreturn_t e1000_intr_msix_rx(int __always_unused irq, void *data)
1954{
1955 struct net_device *netdev = data;
1956 struct e1000_adapter *adapter = netdev_priv(netdev);
1957 struct e1000_ring *rx_ring = adapter->rx_ring;
1958
1959 /* Write the ITR value calculated at the end of the
1960 * previous interrupt.
1961 */
1962 if (rx_ring->set_itr) {
1963 u32 itr = rx_ring->itr_val ?
1964 1000000000 / (rx_ring->itr_val * 256) : 0;
1965
1966 writel(itr, rx_ring->itr_register);
1967 rx_ring->set_itr = 0;
1968 }
1969
1970 if (napi_schedule_prep(&adapter->napi)) {
1971 adapter->total_rx_bytes = 0;
1972 adapter->total_rx_packets = 0;
1973 __napi_schedule_irqoff(&adapter->napi);
1974 }
1975 return IRQ_HANDLED;
1976}
1977
1978/**
1979 * e1000_configure_msix - Configure MSI-X hardware
1980 * @adapter: board private structure
1981 *
1982 * e1000_configure_msix sets up the hardware to properly
1983 * generate MSI-X interrupts.
1984 **/
1985static void e1000_configure_msix(struct e1000_adapter *adapter)
1986{
1987 struct e1000_hw *hw = &adapter->hw;
1988 struct e1000_ring *rx_ring = adapter->rx_ring;
1989 struct e1000_ring *tx_ring = adapter->tx_ring;
1990 int vector = 0;
1991 u32 ctrl_ext, ivar = 0;
1992
1993 adapter->eiac_mask = 0;
1994
1995 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */
1996 if (hw->mac.type == e1000_82574) {
1997 u32 rfctl = er32(RFCTL);
1998
1999 rfctl |= E1000_RFCTL_ACK_DIS;
2000 ew32(RFCTL, rfctl);
2001 }
2002
2003 /* Configure Rx vector */
2004 rx_ring->ims_val = E1000_IMS_RXQ0;
2005 adapter->eiac_mask |= rx_ring->ims_val;
2006 if (rx_ring->itr_val)
2007 writel(1000000000 / (rx_ring->itr_val * 256),
2008 rx_ring->itr_register);
2009 else
2010 writel(1, rx_ring->itr_register);
2011 ivar = E1000_IVAR_INT_ALLOC_VALID | vector;
2012
2013 /* Configure Tx vector */
2014 tx_ring->ims_val = E1000_IMS_TXQ0;
2015 vector++;
2016 if (tx_ring->itr_val)
2017 writel(1000000000 / (tx_ring->itr_val * 256),
2018 tx_ring->itr_register);
2019 else
2020 writel(1, tx_ring->itr_register);
2021 adapter->eiac_mask |= tx_ring->ims_val;
2022 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8);
2023
2024 /* set vector for Other Causes, e.g. link changes */
2025 vector++;
2026 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16);
2027 if (rx_ring->itr_val)
2028 writel(1000000000 / (rx_ring->itr_val * 256),
2029 hw->hw_addr + E1000_EITR_82574(vector));
2030 else
2031 writel(1, hw->hw_addr + E1000_EITR_82574(vector));
2032
2033 /* Cause Tx interrupts on every write back */
2034 ivar |= BIT(31);
2035
2036 ew32(IVAR, ivar);
2037
2038 /* enable MSI-X PBA support */
2039 ctrl_ext = er32(CTRL_EXT) & ~E1000_CTRL_EXT_IAME;
2040 ctrl_ext |= E1000_CTRL_EXT_PBA_CLR | E1000_CTRL_EXT_EIAME;
2041 ew32(CTRL_EXT, ctrl_ext);
2042 e1e_flush();
2043}
2044
2045void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter)
2046{
2047 if (adapter->msix_entries) {
2048 pci_disable_msix(adapter->pdev);
2049 kfree(adapter->msix_entries);
2050 adapter->msix_entries = NULL;
2051 } else if (adapter->flags & FLAG_MSI_ENABLED) {
2052 pci_disable_msi(adapter->pdev);
2053 adapter->flags &= ~FLAG_MSI_ENABLED;
2054 }
2055}
2056
2057/**
2058 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported
2059 * @adapter: board private structure
2060 *
2061 * Attempt to configure interrupts using the best available
2062 * capabilities of the hardware and kernel.
2063 **/
2064void e1000e_set_interrupt_capability(struct e1000_adapter *adapter)
2065{
2066 int err;
2067 int i;
2068
2069 switch (adapter->int_mode) {
2070 case E1000E_INT_MODE_MSIX:
2071 if (adapter->flags & FLAG_HAS_MSIX) {
2072 adapter->num_vectors = 3; /* RxQ0, TxQ0 and other */
2073 adapter->msix_entries = kzalloc_objs(struct msix_entry,
2074 adapter->num_vectors);
2075 if (adapter->msix_entries) {
2076 struct e1000_adapter *a = adapter;
2077
2078 for (i = 0; i < adapter->num_vectors; i++)
2079 adapter->msix_entries[i].entry = i;
2080
2081 err = pci_enable_msix_range(a->pdev,
2082 a->msix_entries,
2083 a->num_vectors,
2084 a->num_vectors);
2085 if (err > 0)
2086 return;
2087 }
2088 /* MSI-X failed, so fall through and try MSI */
2089 e_err("Failed to initialize MSI-X interrupts. Falling back to MSI interrupts.\n");
2090 e1000e_reset_interrupt_capability(adapter);
2091 }
2092 adapter->int_mode = E1000E_INT_MODE_MSI;
2093 fallthrough;
2094 case E1000E_INT_MODE_MSI:
2095 if (!pci_enable_msi(adapter->pdev)) {
2096 adapter->flags |= FLAG_MSI_ENABLED;
2097 } else {
2098 adapter->int_mode = E1000E_INT_MODE_LEGACY;
2099 e_err("Failed to initialize MSI interrupts. Falling back to legacy interrupts.\n");
2100 }
2101 fallthrough;
2102 case E1000E_INT_MODE_LEGACY:
2103 /* Don't do anything; this is the system default */
2104 break;
2105 }
2106
2107 /* store the number of vectors being used */
2108 adapter->num_vectors = 1;
2109}
2110
2111/**
2112 * e1000_request_msix - Initialize MSI-X interrupts
2113 * @adapter: board private structure
2114 *
2115 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the
2116 * kernel.
2117 **/
2118static int e1000_request_msix(struct e1000_adapter *adapter)
2119{
2120 struct net_device *netdev = adapter->netdev;
2121 int err = 0, vector = 0;
2122
2123 if (strlen(netdev->name) < (IFNAMSIZ - 5))
2124 snprintf(adapter->rx_ring->name,
2125 sizeof(adapter->rx_ring->name) - 1,
2126 "%.14s-rx-0", netdev->name);
2127 else
2128 memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ);
2129 err = request_irq(adapter->msix_entries[vector].vector,
2130 e1000_intr_msix_rx, 0, adapter->rx_ring->name,
2131 netdev);
2132 if (err)
2133 return err;
2134 adapter->rx_ring->itr_register = adapter->hw.hw_addr +
2135 E1000_EITR_82574(vector);
2136 adapter->rx_ring->itr_val = adapter->itr;
2137 vector++;
2138
2139 if (strlen(netdev->name) < (IFNAMSIZ - 5))
2140 snprintf(adapter->tx_ring->name,
2141 sizeof(adapter->tx_ring->name) - 1,
2142 "%.14s-tx-0", netdev->name);
2143 else
2144 memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ);
2145 err = request_irq(adapter->msix_entries[vector].vector,
2146 e1000_intr_msix_tx, 0, adapter->tx_ring->name,
2147 netdev);
2148 if (err)
2149 return err;
2150 adapter->tx_ring->itr_register = adapter->hw.hw_addr +
2151 E1000_EITR_82574(vector);
2152 adapter->tx_ring->itr_val = adapter->itr;
2153 vector++;
2154
2155 err = request_irq(adapter->msix_entries[vector].vector,
2156 e1000_msix_other, 0, netdev->name, netdev);
2157 if (err)
2158 return err;
2159
2160 e1000_configure_msix(adapter);
2161
2162 return 0;
2163}
2164
2165/**
2166 * e1000_request_irq - initialize interrupts
2167 * @adapter: board private structure
2168 *
2169 * Attempts to configure interrupts using the best available
2170 * capabilities of the hardware and kernel.
2171 **/
2172static int e1000_request_irq(struct e1000_adapter *adapter)
2173{
2174 struct net_device *netdev = adapter->netdev;
2175 int err;
2176
2177 if (adapter->msix_entries) {
2178 err = e1000_request_msix(adapter);
2179 if (!err)
2180 return err;
2181 /* fall back to MSI */
2182 e1000e_reset_interrupt_capability(adapter);
2183 adapter->int_mode = E1000E_INT_MODE_MSI;
2184 e1000e_set_interrupt_capability(adapter);
2185 }
2186 if (adapter->flags & FLAG_MSI_ENABLED) {
2187 err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0,
2188 netdev->name, netdev);
2189 if (!err)
2190 return err;
2191
2192 /* fall back to legacy interrupt */
2193 e1000e_reset_interrupt_capability(adapter);
2194 adapter->int_mode = E1000E_INT_MODE_LEGACY;
2195 }
2196
2197 err = request_irq(adapter->pdev->irq, e1000_intr, IRQF_SHARED,
2198 netdev->name, netdev);
2199 if (err)
2200 e_err("Unable to allocate interrupt, Error: %d\n", err);
2201
2202 return err;
2203}
2204
2205static void e1000_free_irq(struct e1000_adapter *adapter)
2206{
2207 struct net_device *netdev = adapter->netdev;
2208
2209 if (adapter->msix_entries) {
2210 int vector = 0;
2211
2212 free_irq(adapter->msix_entries[vector].vector, netdev);
2213 vector++;
2214
2215 free_irq(adapter->msix_entries[vector].vector, netdev);
2216 vector++;
2217
2218 /* Other Causes interrupt vector */
2219 free_irq(adapter->msix_entries[vector].vector, netdev);
2220 return;
2221 }
2222
2223 free_irq(adapter->pdev->irq, netdev);
2224}
2225
2226/**
2227 * e1000_irq_disable - Mask off interrupt generation on the NIC
2228 * @adapter: board private structure
2229 **/
2230static void e1000_irq_disable(struct e1000_adapter *adapter)
2231{
2232 struct e1000_hw *hw = &adapter->hw;
2233
2234 ew32(IMC, ~0);
2235 if (adapter->msix_entries)
2236 ew32(EIAC_82574, 0);
2237 e1e_flush();
2238
2239 if (adapter->msix_entries) {
2240 int i;
2241
2242 for (i = 0; i < adapter->num_vectors; i++)
2243 synchronize_irq(adapter->msix_entries[i].vector);
2244 } else {
2245 synchronize_irq(adapter->pdev->irq);
2246 }
2247}
2248
2249/**
2250 * e1000_irq_enable - Enable default interrupt generation settings
2251 * @adapter: board private structure
2252 **/
2253static void e1000_irq_enable(struct e1000_adapter *adapter)
2254{
2255 struct e1000_hw *hw = &adapter->hw;
2256
2257 if (adapter->msix_entries) {
2258 ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574);
2259 ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER |
2260 IMS_OTHER_MASK);
2261 } else if (hw->mac.type >= e1000_pch_lpt) {
2262 ew32(IMS, IMS_ENABLE_MASK | E1000_IMS_ECCER);
2263 } else {
2264 ew32(IMS, IMS_ENABLE_MASK);
2265 }
2266 e1e_flush();
2267}
2268
2269/**
2270 * e1000e_get_hw_control - get control of the h/w from f/w
2271 * @adapter: address of board private structure
2272 *
2273 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit.
2274 * For ASF and Pass Through versions of f/w this means that
2275 * the driver is loaded. For AMT version (only with 82573)
2276 * of the f/w this means that the network i/f is open.
2277 **/
2278void e1000e_get_hw_control(struct e1000_adapter *adapter)
2279{
2280 struct e1000_hw *hw = &adapter->hw;
2281 u32 ctrl_ext;
2282 u32 swsm;
2283
2284 /* Let firmware know the driver has taken over */
2285 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2286 swsm = er32(SWSM);
2287 ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD);
2288 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2289 ctrl_ext = er32(CTRL_EXT);
2290 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2291 }
2292}
2293
2294/**
2295 * e1000e_release_hw_control - release control of the h/w to f/w
2296 * @adapter: address of board private structure
2297 *
2298 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit.
2299 * For ASF and Pass Through versions of f/w this means that the
2300 * driver is no longer loaded. For AMT version (only with 82573) i
2301 * of the f/w this means that the network i/f is closed.
2302 *
2303 **/
2304void e1000e_release_hw_control(struct e1000_adapter *adapter)
2305{
2306 struct e1000_hw *hw = &adapter->hw;
2307 u32 ctrl_ext;
2308 u32 swsm;
2309
2310 /* Let firmware taken over control of h/w */
2311 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2312 swsm = er32(SWSM);
2313 ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
2314 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2315 ctrl_ext = er32(CTRL_EXT);
2316 ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2317 }
2318}
2319
2320/**
2321 * e1000_alloc_ring_dma - allocate memory for a ring structure
2322 * @adapter: board private structure
2323 * @ring: ring struct for which to allocate dma
2324 **/
2325static int e1000_alloc_ring_dma(struct e1000_adapter *adapter,
2326 struct e1000_ring *ring)
2327{
2328 struct pci_dev *pdev = adapter->pdev;
2329
2330 ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma,
2331 GFP_KERNEL);
2332 if (!ring->desc)
2333 return -ENOMEM;
2334
2335 return 0;
2336}
2337
2338/**
2339 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors)
2340 * @tx_ring: Tx descriptor ring
2341 *
2342 * Return 0 on success, negative on failure
2343 **/
2344int e1000e_setup_tx_resources(struct e1000_ring *tx_ring)
2345{
2346 struct e1000_adapter *adapter = tx_ring->adapter;
2347 int err = -ENOMEM, size;
2348
2349 size = sizeof(struct e1000_buffer) * tx_ring->count;
2350 tx_ring->buffer_info = vzalloc(size);
2351 if (!tx_ring->buffer_info)
2352 goto err;
2353
2354 /* round up to nearest 4K */
2355 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
2356 tx_ring->size = ALIGN(tx_ring->size, 4096);
2357
2358 err = e1000_alloc_ring_dma(adapter, tx_ring);
2359 if (err)
2360 goto err;
2361
2362 tx_ring->next_to_use = 0;
2363 tx_ring->next_to_clean = 0;
2364
2365 return 0;
2366err:
2367 vfree(tx_ring->buffer_info);
2368 e_err("Unable to allocate memory for the transmit descriptor ring\n");
2369 return err;
2370}
2371
2372/**
2373 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors)
2374 * @rx_ring: Rx descriptor ring
2375 *
2376 * Returns 0 on success, negative on failure
2377 **/
2378int e1000e_setup_rx_resources(struct e1000_ring *rx_ring)
2379{
2380 struct e1000_adapter *adapter = rx_ring->adapter;
2381 struct e1000_buffer *buffer_info;
2382 int i, size, desc_len, err = -ENOMEM;
2383
2384 size = sizeof(struct e1000_buffer) * rx_ring->count;
2385 rx_ring->buffer_info = vzalloc(size);
2386 if (!rx_ring->buffer_info)
2387 goto err;
2388
2389 for (i = 0; i < rx_ring->count; i++) {
2390 buffer_info = &rx_ring->buffer_info[i];
2391 buffer_info->ps_pages = kzalloc_objs(struct e1000_ps_page,
2392 PS_PAGE_BUFFERS);
2393 if (!buffer_info->ps_pages)
2394 goto err_pages;
2395 }
2396
2397 desc_len = sizeof(union e1000_rx_desc_packet_split);
2398
2399 /* Round up to nearest 4K */
2400 rx_ring->size = rx_ring->count * desc_len;
2401 rx_ring->size = ALIGN(rx_ring->size, 4096);
2402
2403 err = e1000_alloc_ring_dma(adapter, rx_ring);
2404 if (err)
2405 goto err_pages;
2406
2407 rx_ring->next_to_clean = 0;
2408 rx_ring->next_to_use = 0;
2409 rx_ring->rx_skb_top = NULL;
2410
2411 return 0;
2412
2413err_pages:
2414 for (i = 0; i < rx_ring->count; i++) {
2415 buffer_info = &rx_ring->buffer_info[i];
2416 kfree(buffer_info->ps_pages);
2417 }
2418err:
2419 vfree(rx_ring->buffer_info);
2420 e_err("Unable to allocate memory for the receive descriptor ring\n");
2421 return err;
2422}
2423
2424/**
2425 * e1000_clean_tx_ring - Free Tx Buffers
2426 * @tx_ring: Tx descriptor ring
2427 **/
2428static void e1000_clean_tx_ring(struct e1000_ring *tx_ring)
2429{
2430 struct e1000_adapter *adapter = tx_ring->adapter;
2431 struct e1000_buffer *buffer_info;
2432 unsigned long size;
2433 unsigned int i;
2434
2435 for (i = 0; i < tx_ring->count; i++) {
2436 buffer_info = &tx_ring->buffer_info[i];
2437 e1000_put_txbuf(tx_ring, buffer_info, false);
2438 }
2439
2440 netdev_reset_queue(adapter->netdev);
2441 size = sizeof(struct e1000_buffer) * tx_ring->count;
2442 memset(tx_ring->buffer_info, 0, size);
2443
2444 memset(tx_ring->desc, 0, tx_ring->size);
2445
2446 tx_ring->next_to_use = 0;
2447 tx_ring->next_to_clean = 0;
2448}
2449
2450/**
2451 * e1000e_free_tx_resources - Free Tx Resources per Queue
2452 * @tx_ring: Tx descriptor ring
2453 *
2454 * Free all transmit software resources
2455 **/
2456void e1000e_free_tx_resources(struct e1000_ring *tx_ring)
2457{
2458 struct e1000_adapter *adapter = tx_ring->adapter;
2459 struct pci_dev *pdev = adapter->pdev;
2460
2461 e1000_clean_tx_ring(tx_ring);
2462
2463 vfree(tx_ring->buffer_info);
2464 tx_ring->buffer_info = NULL;
2465
2466 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
2467 tx_ring->dma);
2468 tx_ring->desc = NULL;
2469}
2470
2471/**
2472 * e1000e_free_rx_resources - Free Rx Resources
2473 * @rx_ring: Rx descriptor ring
2474 *
2475 * Free all receive software resources
2476 **/
2477void e1000e_free_rx_resources(struct e1000_ring *rx_ring)
2478{
2479 struct e1000_adapter *adapter = rx_ring->adapter;
2480 struct pci_dev *pdev = adapter->pdev;
2481 int i;
2482
2483 e1000_clean_rx_ring(rx_ring);
2484
2485 for (i = 0; i < rx_ring->count; i++)
2486 kfree(rx_ring->buffer_info[i].ps_pages);
2487
2488 vfree(rx_ring->buffer_info);
2489 rx_ring->buffer_info = NULL;
2490
2491 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
2492 rx_ring->dma);
2493 rx_ring->desc = NULL;
2494}
2495
2496/**
2497 * e1000_update_itr - update the dynamic ITR value based on statistics
2498 * @itr_setting: current adapter->itr
2499 * @packets: the number of packets during this measurement interval
2500 * @bytes: the number of bytes during this measurement interval
2501 *
2502 * Stores a new ITR value based on packets and byte
2503 * counts during the last interrupt. The advantage of per interrupt
2504 * computation is faster updates and more accurate ITR for the current
2505 * traffic pattern. Constants in this function were computed
2506 * based on theoretical maximum wire speed and thresholds were set based
2507 * on testing data as well as attempting to minimize response time
2508 * while increasing bulk throughput. This functionality is controlled
2509 * by the InterruptThrottleRate module parameter.
2510 **/
2511static unsigned int e1000_update_itr(u16 itr_setting, int packets, int bytes)
2512{
2513 unsigned int retval = itr_setting;
2514
2515 if (packets == 0)
2516 return itr_setting;
2517
2518 switch (itr_setting) {
2519 case lowest_latency:
2520 /* handle TSO and jumbo frames */
2521 if (bytes / packets > 8000)
2522 retval = bulk_latency;
2523 else if ((packets < 5) && (bytes > 512))
2524 retval = low_latency;
2525 break;
2526 case low_latency: /* 50 usec aka 20000 ints/s */
2527 if (bytes > 10000) {
2528 /* this if handles the TSO accounting */
2529 if (bytes / packets > 8000)
2530 retval = bulk_latency;
2531 else if ((packets < 10) || ((bytes / packets) > 1200))
2532 retval = bulk_latency;
2533 else if ((packets > 35))
2534 retval = lowest_latency;
2535 } else if (bytes / packets > 2000) {
2536 retval = bulk_latency;
2537 } else if (packets <= 2 && bytes < 512) {
2538 retval = lowest_latency;
2539 }
2540 break;
2541 case bulk_latency: /* 250 usec aka 4000 ints/s */
2542 if (bytes > 25000) {
2543 if (packets > 35)
2544 retval = low_latency;
2545 } else if (bytes < 6000) {
2546 retval = low_latency;
2547 }
2548 break;
2549 }
2550
2551 return retval;
2552}
2553
2554static void e1000_set_itr(struct e1000_adapter *adapter)
2555{
2556 u16 current_itr;
2557 u32 new_itr = adapter->itr;
2558
2559 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2560 if (adapter->link_speed != SPEED_1000) {
2561 new_itr = 4000;
2562 goto set_itr_now;
2563 }
2564
2565 if (adapter->flags2 & FLAG2_DISABLE_AIM) {
2566 new_itr = 0;
2567 goto set_itr_now;
2568 }
2569
2570 adapter->tx_itr = e1000_update_itr(adapter->tx_itr,
2571 adapter->total_tx_packets,
2572 adapter->total_tx_bytes);
2573 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2574 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency)
2575 adapter->tx_itr = low_latency;
2576
2577 adapter->rx_itr = e1000_update_itr(adapter->rx_itr,
2578 adapter->total_rx_packets,
2579 adapter->total_rx_bytes);
2580 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2581 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
2582 adapter->rx_itr = low_latency;
2583
2584 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2585
2586 /* counts and packets in update_itr are dependent on these numbers */
2587 switch (current_itr) {
2588 case lowest_latency:
2589 new_itr = 70000;
2590 break;
2591 case low_latency:
2592 new_itr = 20000; /* aka hwitr = ~200 */
2593 break;
2594 case bulk_latency:
2595 new_itr = 4000;
2596 break;
2597 default:
2598 break;
2599 }
2600
2601set_itr_now:
2602 if (new_itr != adapter->itr) {
2603 /* this attempts to bias the interrupt rate towards Bulk
2604 * by adding intermediate steps when interrupt rate is
2605 * increasing
2606 */
2607 new_itr = new_itr > adapter->itr ?
2608 min(adapter->itr + (new_itr >> 2), new_itr) : new_itr;
2609 adapter->itr = new_itr;
2610 adapter->rx_ring->itr_val = new_itr;
2611 if (adapter->msix_entries)
2612 adapter->rx_ring->set_itr = 1;
2613 else
2614 e1000e_write_itr(adapter, new_itr);
2615 }
2616}
2617
2618/**
2619 * e1000e_write_itr - write the ITR value to the appropriate registers
2620 * @adapter: address of board private structure
2621 * @itr: new ITR value to program
2622 *
2623 * e1000e_write_itr determines if the adapter is in MSI-X mode
2624 * and, if so, writes the EITR registers with the ITR value.
2625 * Otherwise, it writes the ITR value into the ITR register.
2626 **/
2627void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr)
2628{
2629 struct e1000_hw *hw = &adapter->hw;
2630 u32 new_itr = itr ? 1000000000 / (itr * 256) : 0;
2631
2632 if (adapter->msix_entries) {
2633 int vector;
2634
2635 for (vector = 0; vector < adapter->num_vectors; vector++)
2636 writel(new_itr, hw->hw_addr + E1000_EITR_82574(vector));
2637 } else {
2638 ew32(ITR, new_itr);
2639 }
2640}
2641
2642/**
2643 * e1000_alloc_queues - Allocate memory for all rings
2644 * @adapter: board private structure to initialize
2645 **/
2646static int e1000_alloc_queues(struct e1000_adapter *adapter)
2647{
2648 int size = sizeof(struct e1000_ring);
2649
2650 adapter->tx_ring = kzalloc(size, GFP_KERNEL);
2651 if (!adapter->tx_ring)
2652 goto err;
2653 adapter->tx_ring->count = adapter->tx_ring_count;
2654 adapter->tx_ring->adapter = adapter;
2655
2656 adapter->rx_ring = kzalloc(size, GFP_KERNEL);
2657 if (!adapter->rx_ring)
2658 goto err;
2659 adapter->rx_ring->count = adapter->rx_ring_count;
2660 adapter->rx_ring->adapter = adapter;
2661
2662 return 0;
2663err:
2664 e_err("Unable to allocate memory for queues\n");
2665 kfree(adapter->rx_ring);
2666 kfree(adapter->tx_ring);
2667 return -ENOMEM;
2668}
2669
2670/**
2671 * e1000e_poll - NAPI Rx polling callback
2672 * @napi: struct associated with this polling callback
2673 * @budget: number of packets driver is allowed to process this poll
2674 **/
2675static int e1000e_poll(struct napi_struct *napi, int budget)
2676{
2677 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter,
2678 napi);
2679 struct e1000_hw *hw = &adapter->hw;
2680 struct net_device *poll_dev = adapter->netdev;
2681 int tx_cleaned = 1, work_done = 0;
2682
2683 adapter = netdev_priv(poll_dev);
2684
2685 if (!adapter->msix_entries ||
2686 (adapter->rx_ring->ims_val & adapter->tx_ring->ims_val))
2687 tx_cleaned = e1000_clean_tx_irq(adapter->tx_ring);
2688
2689 adapter->clean_rx(adapter->rx_ring, &work_done, budget);
2690
2691 if (!tx_cleaned || work_done == budget)
2692 return budget;
2693
2694 /* Exit the polling mode, but don't re-enable interrupts if stack might
2695 * poll us due to busy-polling
2696 */
2697 if (likely(napi_complete_done(napi, work_done))) {
2698 if (adapter->itr_setting & 3)
2699 e1000_set_itr(adapter);
2700 if (!test_bit(__E1000_DOWN, &adapter->state)) {
2701 if (adapter->msix_entries)
2702 ew32(IMS, adapter->rx_ring->ims_val);
2703 else
2704 e1000_irq_enable(adapter);
2705 }
2706 }
2707
2708 return work_done;
2709}
2710
2711static int e1000_vlan_rx_add_vid(struct net_device *netdev,
2712 __always_unused __be16 proto, u16 vid)
2713{
2714 struct e1000_adapter *adapter = netdev_priv(netdev);
2715 struct e1000_hw *hw = &adapter->hw;
2716 u32 vfta, index;
2717
2718 /* don't update vlan cookie if already programmed */
2719 if ((adapter->hw.mng_cookie.status &
2720 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2721 (vid == adapter->mng_vlan_id))
2722 return 0;
2723
2724 /* add VID to filter table */
2725 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2726 index = (vid >> 5) & 0x7F;
2727 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2728 vfta |= BIT((vid & 0x1F));
2729 hw->mac.ops.write_vfta(hw, index, vfta);
2730 }
2731
2732 set_bit(vid, adapter->active_vlans);
2733
2734 return 0;
2735}
2736
2737static int e1000_vlan_rx_kill_vid(struct net_device *netdev,
2738 __always_unused __be16 proto, u16 vid)
2739{
2740 struct e1000_adapter *adapter = netdev_priv(netdev);
2741 struct e1000_hw *hw = &adapter->hw;
2742 u32 vfta, index;
2743
2744 if ((adapter->hw.mng_cookie.status &
2745 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2746 (vid == adapter->mng_vlan_id)) {
2747 /* release control to f/w */
2748 e1000e_release_hw_control(adapter);
2749 return 0;
2750 }
2751
2752 /* remove VID from filter table */
2753 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2754 index = (vid >> 5) & 0x7F;
2755 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2756 vfta &= ~BIT((vid & 0x1F));
2757 hw->mac.ops.write_vfta(hw, index, vfta);
2758 }
2759
2760 clear_bit(vid, adapter->active_vlans);
2761
2762 return 0;
2763}
2764
2765/**
2766 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering
2767 * @adapter: board private structure to initialize
2768 **/
2769static void e1000e_vlan_filter_disable(struct e1000_adapter *adapter)
2770{
2771 struct net_device *netdev = adapter->netdev;
2772 struct e1000_hw *hw = &adapter->hw;
2773 u32 rctl;
2774
2775 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2776 /* disable VLAN receive filtering */
2777 rctl = er32(RCTL);
2778 rctl &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN);
2779 ew32(RCTL, rctl);
2780
2781 if (adapter->mng_vlan_id != E1000_MNG_VLAN_NONE) {
2782 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q),
2783 adapter->mng_vlan_id);
2784 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
2785 }
2786 }
2787}
2788
2789/**
2790 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering
2791 * @adapter: board private structure to initialize
2792 **/
2793static void e1000e_vlan_filter_enable(struct e1000_adapter *adapter)
2794{
2795 struct e1000_hw *hw = &adapter->hw;
2796 u32 rctl;
2797
2798 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2799 /* enable VLAN receive filtering */
2800 rctl = er32(RCTL);
2801 rctl |= E1000_RCTL_VFE;
2802 rctl &= ~E1000_RCTL_CFIEN;
2803 ew32(RCTL, rctl);
2804 }
2805}
2806
2807/**
2808 * e1000e_vlan_strip_disable - helper to disable HW VLAN stripping
2809 * @adapter: board private structure to initialize
2810 **/
2811static void e1000e_vlan_strip_disable(struct e1000_adapter *adapter)
2812{
2813 struct e1000_hw *hw = &adapter->hw;
2814 u32 ctrl;
2815
2816 /* disable VLAN tag insert/strip */
2817 ctrl = er32(CTRL);
2818 ctrl &= ~E1000_CTRL_VME;
2819 ew32(CTRL, ctrl);
2820}
2821
2822/**
2823 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping
2824 * @adapter: board private structure to initialize
2825 **/
2826static void e1000e_vlan_strip_enable(struct e1000_adapter *adapter)
2827{
2828 struct e1000_hw *hw = &adapter->hw;
2829 u32 ctrl;
2830
2831 /* enable VLAN tag insert/strip */
2832 ctrl = er32(CTRL);
2833 ctrl |= E1000_CTRL_VME;
2834 ew32(CTRL, ctrl);
2835}
2836
2837static void e1000_update_mng_vlan(struct e1000_adapter *adapter)
2838{
2839 struct net_device *netdev = adapter->netdev;
2840 u16 vid = adapter->hw.mng_cookie.vlan_id;
2841 u16 old_vid = adapter->mng_vlan_id;
2842
2843 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
2844 e1000_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid);
2845 adapter->mng_vlan_id = vid;
2846 }
2847
2848 if (old_vid != E1000_MNG_VLAN_NONE && vid != old_vid)
2849 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), old_vid);
2850}
2851
2852static void e1000_restore_vlan(struct e1000_adapter *adapter)
2853{
2854 u16 vid;
2855
2856 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
2857
2858 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
2859 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
2860}
2861
2862static void e1000_init_manageability_pt(struct e1000_adapter *adapter)
2863{
2864 struct e1000_hw *hw = &adapter->hw;
2865 u32 manc, manc2h, mdef, i, j;
2866
2867 if (!(adapter->flags & FLAG_MNG_PT_ENABLED))
2868 return;
2869
2870 manc = er32(MANC);
2871
2872 /* enable receiving management packets to the host. this will probably
2873 * generate destination unreachable messages from the host OS, but
2874 * the packets will be handled on SMBUS
2875 */
2876 manc |= E1000_MANC_EN_MNG2HOST;
2877 manc2h = er32(MANC2H);
2878
2879 switch (hw->mac.type) {
2880 default:
2881 manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664);
2882 break;
2883 case e1000_82574:
2884 case e1000_82583:
2885 /* Check if IPMI pass-through decision filter already exists;
2886 * if so, enable it.
2887 */
2888 for (i = 0, j = 0; i < 8; i++) {
2889 mdef = er32(MDEF(i));
2890
2891 /* Ignore filters with anything other than IPMI ports */
2892 if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
2893 continue;
2894
2895 /* Enable this decision filter in MANC2H */
2896 if (mdef)
2897 manc2h |= BIT(i);
2898
2899 j |= mdef;
2900 }
2901
2902 if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
2903 break;
2904
2905 /* Create new decision filter in an empty filter */
2906 for (i = 0, j = 0; i < 8; i++)
2907 if (er32(MDEF(i)) == 0) {
2908 ew32(MDEF(i), (E1000_MDEF_PORT_623 |
2909 E1000_MDEF_PORT_664));
2910 manc2h |= BIT(1);
2911 j++;
2912 break;
2913 }
2914
2915 if (!j)
2916 e_warn("Unable to create IPMI pass-through filter\n");
2917 break;
2918 }
2919
2920 ew32(MANC2H, manc2h);
2921 ew32(MANC, manc);
2922}
2923
2924/**
2925 * e1000_configure_tx - Configure Transmit Unit after Reset
2926 * @adapter: board private structure
2927 *
2928 * Configure the Tx unit of the MAC after a reset.
2929 **/
2930static void e1000_configure_tx(struct e1000_adapter *adapter)
2931{
2932 struct e1000_hw *hw = &adapter->hw;
2933 struct e1000_ring *tx_ring = adapter->tx_ring;
2934 u64 tdba;
2935 u32 tdlen, tctl, tarc;
2936
2937 /* Setup the HW Tx Head and Tail descriptor pointers */
2938 tdba = tx_ring->dma;
2939 tdlen = tx_ring->count * sizeof(struct e1000_tx_desc);
2940 ew32(TDBAL(0), (tdba & DMA_BIT_MASK(32)));
2941 ew32(TDBAH(0), (tdba >> 32));
2942 ew32(TDLEN(0), tdlen);
2943 ew32(TDH(0), 0);
2944 ew32(TDT(0), 0);
2945 tx_ring->head = adapter->hw.hw_addr + E1000_TDH(0);
2946 tx_ring->tail = adapter->hw.hw_addr + E1000_TDT(0);
2947
2948 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
2949 e1000e_update_tdt_wa(tx_ring, 0);
2950
2951 /* Set the Tx Interrupt Delay register */
2952 ew32(TIDV, adapter->tx_int_delay);
2953 /* Tx irq moderation */
2954 ew32(TADV, adapter->tx_abs_int_delay);
2955
2956 if (adapter->flags2 & FLAG2_DMA_BURST) {
2957 u32 txdctl = er32(TXDCTL(0));
2958
2959 txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH |
2960 E1000_TXDCTL_WTHRESH);
2961 /* set up some performance related parameters to encourage the
2962 * hardware to use the bus more efficiently in bursts, depends
2963 * on the tx_int_delay to be enabled,
2964 * wthresh = 1 ==> burst write is disabled to avoid Tx stalls
2965 * hthresh = 1 ==> prefetch when one or more available
2966 * pthresh = 0x1f ==> prefetch if internal cache 31 or less
2967 * BEWARE: this seems to work but should be considered first if
2968 * there are Tx hangs or other Tx related bugs
2969 */
2970 txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE;
2971 ew32(TXDCTL(0), txdctl);
2972 }
2973 /* erratum work around: set txdctl the same for both queues */
2974 ew32(TXDCTL(1), er32(TXDCTL(0)));
2975
2976 /* Program the Transmit Control Register */
2977 tctl = er32(TCTL);
2978 tctl &= ~E1000_TCTL_CT;
2979 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2980 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2981
2982 if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) {
2983 tarc = er32(TARC(0));
2984 /* set the speed mode bit, we'll clear it if we're not at
2985 * gigabit link later
2986 */
2987#define SPEED_MODE_BIT BIT(21)
2988 tarc |= SPEED_MODE_BIT;
2989 ew32(TARC(0), tarc);
2990 }
2991
2992 /* errata: program both queues to unweighted RR */
2993 if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) {
2994 tarc = er32(TARC(0));
2995 tarc |= 1;
2996 ew32(TARC(0), tarc);
2997 tarc = er32(TARC(1));
2998 tarc |= 1;
2999 ew32(TARC(1), tarc);
3000 }
3001
3002 /* Setup Transmit Descriptor Settings for eop descriptor */
3003 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
3004
3005 /* only set IDE if we are delaying interrupts using the timers */
3006 if (adapter->tx_int_delay)
3007 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
3008
3009 /* enable Report Status bit */
3010 adapter->txd_cmd |= E1000_TXD_CMD_RS;
3011
3012 ew32(TCTL, tctl);
3013
3014 hw->mac.ops.config_collision_dist(hw);
3015
3016 /* SPT and KBL Si errata workaround to avoid data corruption */
3017 if (hw->mac.type == e1000_pch_spt) {
3018 u32 reg_val;
3019
3020 reg_val = er32(IOSFPC);
3021 reg_val |= E1000_RCTL_RDMTS_HEX;
3022 ew32(IOSFPC, reg_val);
3023
3024 reg_val = er32(TARC(0));
3025 /* SPT and KBL Si errata workaround to avoid Tx hang.
3026 * Dropping the number of outstanding requests from
3027 * 3 to 2 in order to avoid a buffer overrun.
3028 */
3029 reg_val &= ~E1000_TARC0_CB_MULTIQ_3_REQ;
3030 reg_val |= E1000_TARC0_CB_MULTIQ_2_REQ;
3031 ew32(TARC(0), reg_val);
3032 }
3033}
3034
3035#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
3036 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
3037
3038/**
3039 * e1000_setup_rctl - configure the receive control registers
3040 * @adapter: Board private structure
3041 **/
3042static void e1000_setup_rctl(struct e1000_adapter *adapter)
3043{
3044 struct e1000_hw *hw = &adapter->hw;
3045 u32 rctl, rfctl;
3046 u32 pages = 0;
3047
3048 /* Workaround Si errata on PCHx - configure jumbo frame flow.
3049 * If jumbo frames not set, program related MAC/PHY registers
3050 * to h/w defaults
3051 */
3052 if (hw->mac.type >= e1000_pch2lan) {
3053 s32 ret_val;
3054
3055 if (adapter->netdev->mtu > ETH_DATA_LEN)
3056 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true);
3057 else
3058 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false);
3059
3060 if (ret_val)
3061 e_dbg("failed to enable|disable jumbo frame workaround mode\n");
3062 }
3063
3064 /* Program MC offset vector base */
3065 rctl = er32(RCTL);
3066 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3067 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
3068 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
3069 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3070
3071 /* Do not Store bad packets */
3072 rctl &= ~E1000_RCTL_SBP;
3073
3074 /* Enable Long Packet receive */
3075 if (adapter->netdev->mtu <= ETH_DATA_LEN)
3076 rctl &= ~E1000_RCTL_LPE;
3077 else
3078 rctl |= E1000_RCTL_LPE;
3079
3080 /* Some systems expect that the CRC is included in SMBUS traffic. The
3081 * hardware strips the CRC before sending to both SMBUS (BMC) and to
3082 * host memory when this is enabled
3083 */
3084 if (adapter->flags2 & FLAG2_CRC_STRIPPING)
3085 rctl |= E1000_RCTL_SECRC;
3086
3087 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */
3088 if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) {
3089 u16 phy_data;
3090
3091 e1e_rphy(hw, PHY_REG(770, 26), &phy_data);
3092 phy_data &= 0xfff8;
3093 phy_data |= BIT(2);
3094 e1e_wphy(hw, PHY_REG(770, 26), phy_data);
3095
3096 e1e_rphy(hw, 22, &phy_data);
3097 phy_data &= 0x0fff;
3098 phy_data |= BIT(14);
3099 e1e_wphy(hw, 0x10, 0x2823);
3100 e1e_wphy(hw, 0x11, 0x0003);
3101 e1e_wphy(hw, 22, phy_data);
3102 }
3103
3104 /* Setup buffer sizes */
3105 rctl &= ~E1000_RCTL_SZ_4096;
3106 rctl |= E1000_RCTL_BSEX;
3107 switch (adapter->rx_buffer_len) {
3108 case 2048:
3109 default:
3110 rctl |= E1000_RCTL_SZ_2048;
3111 rctl &= ~E1000_RCTL_BSEX;
3112 break;
3113 case 4096:
3114 rctl |= E1000_RCTL_SZ_4096;
3115 break;
3116 case 8192:
3117 rctl |= E1000_RCTL_SZ_8192;
3118 break;
3119 case 16384:
3120 rctl |= E1000_RCTL_SZ_16384;
3121 break;
3122 }
3123
3124 /* Enable Extended Status in all Receive Descriptors */
3125 rfctl = er32(RFCTL);
3126 rfctl |= E1000_RFCTL_EXTEN;
3127 ew32(RFCTL, rfctl);
3128
3129 /* 82571 and greater support packet-split where the protocol
3130 * header is placed in skb->data and the packet data is
3131 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
3132 * In the case of a non-split, skb->data is linearly filled,
3133 * followed by the page buffers. Therefore, skb->data is
3134 * sized to hold the largest protocol header.
3135 *
3136 * allocations using alloc_page take too long for regular MTU
3137 * so only enable packet split for jumbo frames
3138 *
3139 * Using pages when the page size is greater than 16k wastes
3140 * a lot of memory, since we allocate 3 pages at all times
3141 * per packet.
3142 */
3143 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
3144 if ((pages <= 3) && (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE))
3145 adapter->rx_ps_pages = pages;
3146 else
3147 adapter->rx_ps_pages = 0;
3148
3149 if (adapter->rx_ps_pages) {
3150 u32 psrctl = 0;
3151
3152 /* Enable Packet split descriptors */
3153 rctl |= E1000_RCTL_DTYP_PS;
3154
3155 psrctl |= adapter->rx_ps_bsize0 >> E1000_PSRCTL_BSIZE0_SHIFT;
3156
3157 switch (adapter->rx_ps_pages) {
3158 case 3:
3159 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE3_SHIFT;
3160 fallthrough;
3161 case 2:
3162 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE2_SHIFT;
3163 fallthrough;
3164 case 1:
3165 psrctl |= PAGE_SIZE >> E1000_PSRCTL_BSIZE1_SHIFT;
3166 break;
3167 }
3168
3169 ew32(PSRCTL, psrctl);
3170 }
3171
3172 /* This is useful for sniffing bad packets. */
3173 if (adapter->netdev->features & NETIF_F_RXALL) {
3174 /* UPE and MPE will be handled by normal PROMISC logic
3175 * in e1000e_set_rx_mode
3176 */
3177 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3178 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3179 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3180
3181 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3182 E1000_RCTL_DPF | /* Allow filtered pause */
3183 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3184 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3185 * and that breaks VLANs.
3186 */
3187 }
3188
3189 ew32(RCTL, rctl);
3190 /* just started the receive unit, no need to restart */
3191 adapter->flags &= ~FLAG_RESTART_NOW;
3192}
3193
3194/**
3195 * e1000_configure_rx - Configure Receive Unit after Reset
3196 * @adapter: board private structure
3197 *
3198 * Configure the Rx unit of the MAC after a reset.
3199 **/
3200static void e1000_configure_rx(struct e1000_adapter *adapter)
3201{
3202 struct e1000_hw *hw = &adapter->hw;
3203 struct e1000_ring *rx_ring = adapter->rx_ring;
3204 u64 rdba;
3205 u32 rdlen, rctl, rxcsum, ctrl_ext;
3206
3207 if (adapter->rx_ps_pages) {
3208 /* this is a 32 byte descriptor */
3209 rdlen = rx_ring->count *
3210 sizeof(union e1000_rx_desc_packet_split);
3211 adapter->clean_rx = e1000_clean_rx_irq_ps;
3212 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
3213 } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) {
3214 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
3215 adapter->clean_rx = e1000_clean_jumbo_rx_irq;
3216 adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers;
3217 } else {
3218 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
3219 adapter->clean_rx = e1000_clean_rx_irq;
3220 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
3221 }
3222
3223 /* disable receives while setting up the descriptors */
3224 rctl = er32(RCTL);
3225 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
3226 ew32(RCTL, rctl & ~E1000_RCTL_EN);
3227 e1e_flush();
3228 usleep_range(10000, 11000);
3229
3230 if (adapter->flags2 & FLAG2_DMA_BURST) {
3231 /* set the writeback threshold (only takes effect if the RDTR
3232 * is set). set GRAN=1 and write back up to 0x4 worth, and
3233 * enable prefetching of 0x20 Rx descriptors
3234 * granularity = 01
3235 * wthresh = 04,
3236 * hthresh = 04,
3237 * pthresh = 0x20
3238 */
3239 ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE);
3240 ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE);
3241 }
3242
3243 /* set the Receive Delay Timer Register */
3244 ew32(RDTR, adapter->rx_int_delay);
3245
3246 /* irq moderation */
3247 ew32(RADV, adapter->rx_abs_int_delay);
3248 if ((adapter->itr_setting != 0) && (adapter->itr != 0))
3249 e1000e_write_itr(adapter, adapter->itr);
3250
3251 ctrl_ext = er32(CTRL_EXT);
3252 /* Auto-Mask interrupts upon ICR access */
3253 ctrl_ext |= E1000_CTRL_EXT_IAME;
3254 ew32(IAM, 0xffffffff);
3255 ew32(CTRL_EXT, ctrl_ext);
3256 e1e_flush();
3257
3258 /* Setup the HW Rx Head and Tail Descriptor Pointers and
3259 * the Base and Length of the Rx Descriptor Ring
3260 */
3261 rdba = rx_ring->dma;
3262 ew32(RDBAL(0), (rdba & DMA_BIT_MASK(32)));
3263 ew32(RDBAH(0), (rdba >> 32));
3264 ew32(RDLEN(0), rdlen);
3265 ew32(RDH(0), 0);
3266 ew32(RDT(0), 0);
3267 rx_ring->head = adapter->hw.hw_addr + E1000_RDH(0);
3268 rx_ring->tail = adapter->hw.hw_addr + E1000_RDT(0);
3269
3270 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
3271 e1000e_update_rdt_wa(rx_ring, 0);
3272
3273 /* Enable Receive Checksum Offload for TCP and UDP */
3274 rxcsum = er32(RXCSUM);
3275 if (adapter->netdev->features & NETIF_F_RXCSUM)
3276 rxcsum |= E1000_RXCSUM_TUOFL;
3277 else
3278 rxcsum &= ~E1000_RXCSUM_TUOFL;
3279 ew32(RXCSUM, rxcsum);
3280
3281 /* With jumbo frames, excessive C-state transition latencies result
3282 * in dropped transactions.
3283 */
3284 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3285 u32 lat =
3286 ((er32(PBA) & E1000_PBA_RXA_MASK) * 1024 -
3287 adapter->max_frame_size) * 8 / 1000;
3288
3289 if (adapter->flags & FLAG_IS_ICH) {
3290 u32 rxdctl = er32(RXDCTL(0));
3291
3292 ew32(RXDCTL(0), rxdctl | 0x3 | BIT(8));
3293 }
3294
3295 dev_info(&adapter->pdev->dev,
3296 "Some CPU C-states have been disabled in order to enable jumbo frames\n");
3297 cpu_latency_qos_update_request(&adapter->pm_qos_req, lat);
3298 } else {
3299 cpu_latency_qos_update_request(&adapter->pm_qos_req,
3300 PM_QOS_DEFAULT_VALUE);
3301 }
3302
3303 /* Enable Receives */
3304 ew32(RCTL, rctl);
3305}
3306
3307/**
3308 * e1000e_write_mc_addr_list - write multicast addresses to MTA
3309 * @netdev: network interface device structure
3310 *
3311 * Writes multicast address list to the MTA hash table.
3312 * Returns: -ENOMEM on failure
3313 * 0 on no addresses written
3314 * X on writing X addresses to MTA
3315 */
3316static int e1000e_write_mc_addr_list(struct net_device *netdev)
3317{
3318 struct e1000_adapter *adapter = netdev_priv(netdev);
3319 struct e1000_hw *hw = &adapter->hw;
3320 struct netdev_hw_addr *ha;
3321 u8 *mta_list;
3322 int i;
3323
3324 if (netdev_mc_empty(netdev)) {
3325 /* nothing to program, so clear mc list */
3326 hw->mac.ops.update_mc_addr_list(hw, NULL, 0);
3327 return 0;
3328 }
3329
3330 mta_list = kcalloc(netdev_mc_count(netdev), ETH_ALEN, GFP_ATOMIC);
3331 if (!mta_list)
3332 return -ENOMEM;
3333
3334 /* update_mc_addr_list expects a packed array of only addresses. */
3335 i = 0;
3336 netdev_for_each_mc_addr(ha, netdev)
3337 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
3338
3339 hw->mac.ops.update_mc_addr_list(hw, mta_list, i);
3340 kfree(mta_list);
3341
3342 return netdev_mc_count(netdev);
3343}
3344
3345/**
3346 * e1000e_write_uc_addr_list - write unicast addresses to RAR table
3347 * @netdev: network interface device structure
3348 *
3349 * Writes unicast address list to the RAR table.
3350 * Returns: -ENOMEM on failure/insufficient address space
3351 * 0 on no addresses written
3352 * X on writing X addresses to the RAR table
3353 **/
3354static int e1000e_write_uc_addr_list(struct net_device *netdev)
3355{
3356 struct e1000_adapter *adapter = netdev_priv(netdev);
3357 struct e1000_hw *hw = &adapter->hw;
3358 unsigned int rar_entries;
3359 int count = 0;
3360
3361 rar_entries = hw->mac.ops.rar_get_count(hw);
3362
3363 /* save a rar entry for our hardware address */
3364 rar_entries--;
3365
3366 /* save a rar entry for the LAA workaround */
3367 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA)
3368 rar_entries--;
3369
3370 /* return ENOMEM indicating insufficient memory for addresses */
3371 if (netdev_uc_count(netdev) > rar_entries)
3372 return -ENOMEM;
3373
3374 if (!netdev_uc_empty(netdev) && rar_entries) {
3375 struct netdev_hw_addr *ha;
3376
3377 /* write the addresses in reverse order to avoid write
3378 * combining
3379 */
3380 netdev_for_each_uc_addr(ha, netdev) {
3381 int ret_val;
3382
3383 if (!rar_entries)
3384 break;
3385 ret_val = hw->mac.ops.rar_set(hw, ha->addr, rar_entries--);
3386 if (ret_val < 0)
3387 return -ENOMEM;
3388 count++;
3389 }
3390 }
3391
3392 /* zero out the remaining RAR entries not used above */
3393 for (; rar_entries > 0; rar_entries--) {
3394 ew32(RAH(rar_entries), 0);
3395 ew32(RAL(rar_entries), 0);
3396 }
3397 e1e_flush();
3398
3399 return count;
3400}
3401
3402/**
3403 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set
3404 * @netdev: network interface device structure
3405 *
3406 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast
3407 * address list or the network interface flags are updated. This routine is
3408 * responsible for configuring the hardware for proper unicast, multicast,
3409 * promiscuous mode, and all-multi behavior.
3410 **/
3411static void e1000e_set_rx_mode(struct net_device *netdev)
3412{
3413 struct e1000_adapter *adapter = netdev_priv(netdev);
3414 struct e1000_hw *hw = &adapter->hw;
3415 u32 rctl;
3416
3417 if (pm_runtime_suspended(netdev->dev.parent))
3418 return;
3419
3420 /* Check for Promiscuous and All Multicast modes */
3421 rctl = er32(RCTL);
3422
3423 /* clear the affected bits */
3424 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
3425
3426 if (netdev->flags & IFF_PROMISC) {
3427 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
3428 /* Do not hardware filter VLANs in promisc mode */
3429 e1000e_vlan_filter_disable(adapter);
3430 } else {
3431 int count;
3432
3433 if (netdev->flags & IFF_ALLMULTI) {
3434 rctl |= E1000_RCTL_MPE;
3435 } else {
3436 /* Write addresses to the MTA, if the attempt fails
3437 * then we should just turn on promiscuous mode so
3438 * that we can at least receive multicast traffic
3439 */
3440 count = e1000e_write_mc_addr_list(netdev);
3441 if (count < 0)
3442 rctl |= E1000_RCTL_MPE;
3443 }
3444 e1000e_vlan_filter_enable(adapter);
3445 /* Write addresses to available RAR registers, if there is not
3446 * sufficient space to store all the addresses then enable
3447 * unicast promiscuous mode
3448 */
3449 count = e1000e_write_uc_addr_list(netdev);
3450 if (count < 0)
3451 rctl |= E1000_RCTL_UPE;
3452 }
3453
3454 ew32(RCTL, rctl);
3455
3456 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
3457 e1000e_vlan_strip_enable(adapter);
3458 else
3459 e1000e_vlan_strip_disable(adapter);
3460}
3461
3462static void e1000e_setup_rss_hash(struct e1000_adapter *adapter)
3463{
3464 struct e1000_hw *hw = &adapter->hw;
3465 u32 mrqc, rxcsum;
3466 u32 rss_key[10];
3467 int i;
3468
3469 netdev_rss_key_fill(rss_key, sizeof(rss_key));
3470 for (i = 0; i < 10; i++)
3471 ew32(RSSRK(i), rss_key[i]);
3472
3473 /* Direct all traffic to queue 0 */
3474 for (i = 0; i < 32; i++)
3475 ew32(RETA(i), 0);
3476
3477 /* Disable raw packet checksumming so that RSS hash is placed in
3478 * descriptor on writeback.
3479 */
3480 rxcsum = er32(RXCSUM);
3481 rxcsum |= E1000_RXCSUM_PCSD;
3482
3483 ew32(RXCSUM, rxcsum);
3484
3485 mrqc = (E1000_MRQC_RSS_FIELD_IPV4 |
3486 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3487 E1000_MRQC_RSS_FIELD_IPV6 |
3488 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3489 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
3490
3491 ew32(MRQC, mrqc);
3492}
3493
3494/**
3495 * e1000e_get_base_timinca - get default SYSTIM time increment attributes
3496 * @adapter: board private structure
3497 * @timinca: pointer to returned time increment attributes
3498 *
3499 * Get attributes for incrementing the System Time Register SYSTIML/H at
3500 * the default base frequency, and set the cyclecounter shift value.
3501 **/
3502s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca)
3503{
3504 struct e1000_hw *hw = &adapter->hw;
3505 u32 incvalue, incperiod, shift;
3506
3507 /* Make sure clock is enabled on I217/I218/I219 before checking
3508 * the frequency
3509 */
3510 if ((hw->mac.type >= e1000_pch_lpt) &&
3511 !(er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) &&
3512 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_ENABLED)) {
3513 u32 fextnvm7 = er32(FEXTNVM7);
3514
3515 if (!(fextnvm7 & BIT(0))) {
3516 ew32(FEXTNVM7, fextnvm7 | BIT(0));
3517 e1e_flush();
3518 }
3519 }
3520
3521 switch (hw->mac.type) {
3522 case e1000_pch2lan:
3523 /* Stable 96MHz frequency */
3524 incperiod = INCPERIOD_96MHZ;
3525 incvalue = INCVALUE_96MHZ;
3526 shift = INCVALUE_SHIFT_96MHZ;
3527 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHZ;
3528 break;
3529 case e1000_pch_lpt:
3530 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) {
3531 /* Stable 96MHz frequency */
3532 incperiod = INCPERIOD_96MHZ;
3533 incvalue = INCVALUE_96MHZ;
3534 shift = INCVALUE_SHIFT_96MHZ;
3535 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHZ;
3536 } else {
3537 /* Stable 25MHz frequency */
3538 incperiod = INCPERIOD_25MHZ;
3539 incvalue = INCVALUE_25MHZ;
3540 shift = INCVALUE_SHIFT_25MHZ;
3541 adapter->cc.shift = shift;
3542 }
3543 break;
3544 case e1000_pch_spt:
3545 /* Stable 24MHz frequency */
3546 incperiod = INCPERIOD_24MHZ;
3547 incvalue = INCVALUE_24MHZ;
3548 shift = INCVALUE_SHIFT_24MHZ;
3549 adapter->cc.shift = shift;
3550 break;
3551 case e1000_pch_cnp:
3552 case e1000_pch_tgp:
3553 case e1000_pch_adp:
3554 case e1000_pch_nvp:
3555 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) {
3556 /* Stable 24MHz frequency */
3557 incperiod = INCPERIOD_24MHZ;
3558 incvalue = INCVALUE_24MHZ;
3559 shift = INCVALUE_SHIFT_24MHZ;
3560 adapter->cc.shift = shift;
3561 } else {
3562 /* Stable 38400KHz frequency */
3563 incperiod = INCPERIOD_38400KHZ;
3564 incvalue = INCVALUE_38400KHZ;
3565 shift = INCVALUE_SHIFT_38400KHZ;
3566 adapter->cc.shift = shift;
3567 }
3568 break;
3569 case e1000_pch_mtp:
3570 case e1000_pch_lnp:
3571 case e1000_pch_ptp:
3572 /* System firmware can misreport this value, so set it to a
3573 * stable 38400KHz frequency.
3574 */
3575 incperiod = INCPERIOD_38400KHZ;
3576 incvalue = INCVALUE_38400KHZ;
3577 shift = INCVALUE_SHIFT_38400KHZ;
3578 adapter->cc.shift = shift;
3579 break;
3580 case e1000_82574:
3581 case e1000_82583:
3582 /* Stable 25MHz frequency */
3583 incperiod = INCPERIOD_25MHZ;
3584 incvalue = INCVALUE_25MHZ;
3585 shift = INCVALUE_SHIFT_25MHZ;
3586 adapter->cc.shift = shift;
3587 break;
3588 default:
3589 return -EINVAL;
3590 }
3591
3592 *timinca = ((incperiod << E1000_TIMINCA_INCPERIOD_SHIFT) |
3593 ((incvalue << shift) & E1000_TIMINCA_INCVALUE_MASK));
3594
3595 return 0;
3596}
3597
3598/**
3599 * e1000e_config_hwtstamp - configure the hwtstamp registers and enable/disable
3600 * @adapter: board private structure
3601 * @config: timestamp configuration
3602 * @extack: netlink extended ACK for error report
3603 *
3604 * Outgoing time stamping can be enabled and disabled. Play nice and
3605 * disable it when requested, although it shouldn't cause any overhead
3606 * when no packet needs it. At most one packet in the queue may be
3607 * marked for time stamping, otherwise it would be impossible to tell
3608 * for sure to which packet the hardware time stamp belongs.
3609 *
3610 * Incoming time stamping has to be configured via the hardware filters.
3611 * Not all combinations are supported, in particular event type has to be
3612 * specified. Matching the kind of event packet is not supported, with the
3613 * exception of "all V2 events regardless of level 2 or 4".
3614 **/
3615static int e1000e_config_hwtstamp(struct e1000_adapter *adapter,
3616 struct kernel_hwtstamp_config *config,
3617 struct netlink_ext_ack *extack)
3618{
3619 struct e1000_hw *hw = &adapter->hw;
3620 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
3621 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
3622 u32 rxmtrl = 0;
3623 u16 rxudp = 0;
3624 bool is_l4 = false;
3625 bool is_l2 = false;
3626 u32 regval;
3627
3628 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP)) {
3629 NL_SET_ERR_MSG(extack, "No HW timestamp support");
3630 return -EINVAL;
3631 }
3632
3633 switch (config->tx_type) {
3634 case HWTSTAMP_TX_OFF:
3635 tsync_tx_ctl = 0;
3636 break;
3637 case HWTSTAMP_TX_ON:
3638 break;
3639 default:
3640 NL_SET_ERR_MSG(extack, "Unsupported TX HW timestamp type");
3641 return -ERANGE;
3642 }
3643
3644 switch (config->rx_filter) {
3645 case HWTSTAMP_FILTER_NONE:
3646 tsync_rx_ctl = 0;
3647 break;
3648 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3649 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
3650 rxmtrl = E1000_RXMTRL_PTP_V1_SYNC_MESSAGE;
3651 is_l4 = true;
3652 break;
3653 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3654 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
3655 rxmtrl = E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE;
3656 is_l4 = true;
3657 break;
3658 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3659 /* Also time stamps V2 L2 Path Delay Request/Response */
3660 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2;
3661 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE;
3662 is_l2 = true;
3663 break;
3664 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3665 /* Also time stamps V2 L2 Path Delay Request/Response. */
3666 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2;
3667 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE;
3668 is_l2 = true;
3669 break;
3670 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3671 /* Hardware cannot filter just V2 L4 Sync messages */
3672 fallthrough;
3673 case HWTSTAMP_FILTER_PTP_V2_SYNC:
3674 /* Also time stamps V2 Path Delay Request/Response. */
3675 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
3676 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE;
3677 is_l2 = true;
3678 is_l4 = true;
3679 break;
3680 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3681 /* Hardware cannot filter just V2 L4 Delay Request messages */
3682 fallthrough;
3683 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3684 /* Also time stamps V2 Path Delay Request/Response. */
3685 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
3686 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE;
3687 is_l2 = true;
3688 is_l4 = true;
3689 break;
3690 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3691 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3692 /* Hardware cannot filter just V2 L4 or L2 Event messages */
3693 fallthrough;
3694 case HWTSTAMP_FILTER_PTP_V2_EVENT:
3695 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
3696 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
3697 is_l2 = true;
3698 is_l4 = true;
3699 break;
3700 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3701 /* For V1, the hardware can only filter Sync messages or
3702 * Delay Request messages but not both so fall-through to
3703 * time stamp all packets.
3704 */
3705 fallthrough;
3706 case HWTSTAMP_FILTER_NTP_ALL:
3707 case HWTSTAMP_FILTER_ALL:
3708 is_l2 = true;
3709 is_l4 = true;
3710 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
3711 config->rx_filter = HWTSTAMP_FILTER_ALL;
3712 break;
3713 default:
3714 NL_SET_ERR_MSG(extack, "Unsupported RX HW timestamp filter");
3715 return -ERANGE;
3716 }
3717
3718 adapter->hwtstamp_config = *config;
3719
3720 /* enable/disable Tx h/w time stamping */
3721 regval = er32(TSYNCTXCTL);
3722 regval &= ~E1000_TSYNCTXCTL_ENABLED;
3723 regval |= tsync_tx_ctl;
3724 ew32(TSYNCTXCTL, regval);
3725 if ((er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) !=
3726 (regval & E1000_TSYNCTXCTL_ENABLED)) {
3727 NL_SET_ERR_MSG(extack,
3728 "Timesync Tx Control register not set as expected");
3729 return -EAGAIN;
3730 }
3731
3732 /* enable/disable Rx h/w time stamping */
3733 regval = er32(TSYNCRXCTL);
3734 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
3735 regval |= tsync_rx_ctl;
3736 ew32(TSYNCRXCTL, regval);
3737 if ((er32(TSYNCRXCTL) & (E1000_TSYNCRXCTL_ENABLED |
3738 E1000_TSYNCRXCTL_TYPE_MASK)) !=
3739 (regval & (E1000_TSYNCRXCTL_ENABLED |
3740 E1000_TSYNCRXCTL_TYPE_MASK))) {
3741 NL_SET_ERR_MSG(extack,
3742 "Timesync Rx Control register not set as expected");
3743 return -EAGAIN;
3744 }
3745
3746 /* L2: define ethertype filter for time stamped packets */
3747 if (is_l2)
3748 rxmtrl |= ETH_P_1588;
3749
3750 /* define which PTP packets get time stamped */
3751 ew32(RXMTRL, rxmtrl);
3752
3753 /* Filter by destination port */
3754 if (is_l4) {
3755 rxudp = PTP_EV_PORT;
3756 cpu_to_be16s(&rxudp);
3757 }
3758 ew32(RXUDP, rxudp);
3759
3760 e1e_flush();
3761
3762 /* Clear TSYNCRXCTL_VALID & TSYNCTXCTL_VALID bit */
3763 er32(RXSTMPH);
3764 er32(TXSTMPH);
3765
3766 return 0;
3767}
3768
3769/**
3770 * e1000_configure - configure the hardware for Rx and Tx
3771 * @adapter: private board structure
3772 **/
3773static void e1000_configure(struct e1000_adapter *adapter)
3774{
3775 struct e1000_ring *rx_ring = adapter->rx_ring;
3776
3777 e1000e_set_rx_mode(adapter->netdev);
3778
3779 e1000_restore_vlan(adapter);
3780 e1000_init_manageability_pt(adapter);
3781
3782 e1000_configure_tx(adapter);
3783
3784 if (adapter->netdev->features & NETIF_F_RXHASH)
3785 e1000e_setup_rss_hash(adapter);
3786 e1000_setup_rctl(adapter);
3787 e1000_configure_rx(adapter);
3788 adapter->alloc_rx_buf(rx_ring, e1000_desc_unused(rx_ring), GFP_KERNEL);
3789}
3790
3791/**
3792 * e1000e_power_up_phy - restore link in case the phy was powered down
3793 * @adapter: address of board private structure
3794 *
3795 * The phy may be powered down to save power and turn off link when the
3796 * driver is unloaded and wake on lan is not enabled (among others)
3797 * *** this routine MUST be followed by a call to e1000e_reset ***
3798 **/
3799void e1000e_power_up_phy(struct e1000_adapter *adapter)
3800{
3801 if (adapter->hw.phy.ops.power_up)
3802 adapter->hw.phy.ops.power_up(&adapter->hw);
3803
3804 adapter->hw.mac.ops.setup_link(&adapter->hw);
3805}
3806
3807/**
3808 * e1000_power_down_phy - Power down the PHY
3809 * @adapter: board private structure
3810 *
3811 * Power down the PHY so no link is implied when interface is down.
3812 * The PHY cannot be powered down if management or WoL is active.
3813 */
3814static void e1000_power_down_phy(struct e1000_adapter *adapter)
3815{
3816 if (adapter->hw.phy.ops.power_down)
3817 adapter->hw.phy.ops.power_down(&adapter->hw);
3818}
3819
3820/**
3821 * e1000_flush_tx_ring - remove all descriptors from the tx_ring
3822 * @adapter: board private structure
3823 *
3824 * We want to clear all pending descriptors from the TX ring.
3825 * zeroing happens when the HW reads the regs. We assign the ring itself as
3826 * the data of the next descriptor. We don't care about the data we are about
3827 * to reset the HW.
3828 */
3829static void e1000_flush_tx_ring(struct e1000_adapter *adapter)
3830{
3831 struct e1000_hw *hw = &adapter->hw;
3832 struct e1000_ring *tx_ring = adapter->tx_ring;
3833 struct e1000_tx_desc *tx_desc = NULL;
3834 u32 tdt, tctl, txd_lower = E1000_TXD_CMD_IFCS;
3835 u16 size = 512;
3836
3837 tctl = er32(TCTL);
3838 ew32(TCTL, tctl | E1000_TCTL_EN);
3839 tdt = er32(TDT(0));
3840 BUG_ON(tdt != tx_ring->next_to_use);
3841 tx_desc = E1000_TX_DESC(*tx_ring, tx_ring->next_to_use);
3842 tx_desc->buffer_addr = cpu_to_le64(tx_ring->dma);
3843
3844 tx_desc->lower.data = cpu_to_le32(txd_lower | size);
3845 tx_desc->upper.data = 0;
3846 /* flush descriptors to memory before notifying the HW */
3847 wmb();
3848 tx_ring->next_to_use++;
3849 if (tx_ring->next_to_use == tx_ring->count)
3850 tx_ring->next_to_use = 0;
3851 ew32(TDT(0), tx_ring->next_to_use);
3852 usleep_range(200, 250);
3853}
3854
3855/**
3856 * e1000_flush_rx_ring - remove all descriptors from the rx_ring
3857 * @adapter: board private structure
3858 *
3859 * Mark all descriptors in the RX ring as consumed and disable the rx ring
3860 */
3861static void e1000_flush_rx_ring(struct e1000_adapter *adapter)
3862{
3863 u32 rctl, rxdctl;
3864 struct e1000_hw *hw = &adapter->hw;
3865
3866 rctl = er32(RCTL);
3867 ew32(RCTL, rctl & ~E1000_RCTL_EN);
3868 e1e_flush();
3869 usleep_range(100, 150);
3870
3871 rxdctl = er32(RXDCTL(0));
3872 /* zero the lower 14 bits (prefetch and host thresholds) */
3873 rxdctl &= 0xffffc000;
3874
3875 /* update thresholds: prefetch threshold to 31, host threshold to 1
3876 * and make sure the granularity is "descriptors" and not "cache lines"
3877 */
3878 rxdctl |= (0x1F | BIT(8) | E1000_RXDCTL_THRESH_UNIT_DESC);
3879
3880 ew32(RXDCTL(0), rxdctl);
3881 /* momentarily enable the RX ring for the changes to take effect */
3882 ew32(RCTL, rctl | E1000_RCTL_EN);
3883 e1e_flush();
3884 usleep_range(100, 150);
3885 ew32(RCTL, rctl & ~E1000_RCTL_EN);
3886}
3887
3888/**
3889 * e1000_flush_desc_rings - remove all descriptors from the descriptor rings
3890 * @adapter: board private structure
3891 *
3892 * In i219, the descriptor rings must be emptied before resetting the HW
3893 * or before changing the device state to D3 during runtime (runtime PM).
3894 *
3895 * Failure to do this will cause the HW to enter a unit hang state which can
3896 * only be released by PCI reset on the device
3897 *
3898 */
3899
3900static void e1000_flush_desc_rings(struct e1000_adapter *adapter)
3901{
3902 u16 hang_state;
3903 u32 fext_nvm11, tdlen;
3904 struct e1000_hw *hw = &adapter->hw;
3905
3906 /* First, disable MULR fix in FEXTNVM11 */
3907 fext_nvm11 = er32(FEXTNVM11);
3908 fext_nvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX;
3909 ew32(FEXTNVM11, fext_nvm11);
3910 /* do nothing if we're not in faulty state, or if the queue is empty */
3911 tdlen = er32(TDLEN(0));
3912 pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS,
3913 &hang_state);
3914 if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen)
3915 return;
3916 e1000_flush_tx_ring(adapter);
3917 /* recheck, maybe the fault is caused by the rx ring */
3918 pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS,
3919 &hang_state);
3920 if (hang_state & FLUSH_DESC_REQUIRED)
3921 e1000_flush_rx_ring(adapter);
3922}
3923
3924/**
3925 * e1000e_systim_reset - reset the timesync registers after a hardware reset
3926 * @adapter: board private structure
3927 *
3928 * When the MAC is reset, all hardware bits for timesync will be reset to the
3929 * default values. This function will restore the settings last in place.
3930 * Since the clock SYSTIME registers are reset, we will simply restore the
3931 * cyclecounter to the kernel real clock time.
3932 **/
3933static void e1000e_systim_reset(struct e1000_adapter *adapter)
3934{
3935 struct ptp_clock_info *info = &adapter->ptp_clock_info;
3936 struct e1000_hw *hw = &adapter->hw;
3937 struct netlink_ext_ack extack = {};
3938 unsigned long flags;
3939 u32 timinca;
3940 s32 ret_val;
3941
3942 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP))
3943 return;
3944
3945 if (info->adjfine) {
3946 /* restore the previous ptp frequency delta */
3947 ret_val = info->adjfine(info, adapter->ptp_delta);
3948 } else {
3949 /* set the default base frequency if no adjustment possible */
3950 ret_val = e1000e_get_base_timinca(adapter, &timinca);
3951 if (!ret_val)
3952 ew32(TIMINCA, timinca);
3953 }
3954
3955 if (ret_val) {
3956 dev_warn(&adapter->pdev->dev,
3957 "Failed to restore TIMINCA clock rate delta: %d\n",
3958 ret_val);
3959 return;
3960 }
3961
3962 /* reset the systim ns time counter */
3963 spin_lock_irqsave(&adapter->systim_lock, flags);
3964 timecounter_init(&adapter->tc, &adapter->cc,
3965 ktime_get_real_ns());
3966 spin_unlock_irqrestore(&adapter->systim_lock, flags);
3967
3968 /* restore the previous hwtstamp configuration settings */
3969 ret_val = e1000e_config_hwtstamp(adapter, &adapter->hwtstamp_config,
3970 &extack);
3971 if (ret_val) {
3972 if (extack._msg)
3973 e_err("%s\n", extack._msg);
3974 }
3975}
3976
3977/**
3978 * e1000e_reset - bring the hardware into a known good state
3979 * @adapter: board private structure
3980 *
3981 * This function boots the hardware and enables some settings that
3982 * require a configuration cycle of the hardware - those cannot be
3983 * set/changed during runtime. After reset the device needs to be
3984 * properly configured for Rx, Tx etc.
3985 */
3986void e1000e_reset(struct e1000_adapter *adapter)
3987{
3988 struct e1000_mac_info *mac = &adapter->hw.mac;
3989 struct e1000_fc_info *fc = &adapter->hw.fc;
3990 struct e1000_hw *hw = &adapter->hw;
3991 u32 tx_space, min_tx_space, min_rx_space;
3992 u32 pba = adapter->pba;
3993 u16 hwm;
3994
3995 /* reset Packet Buffer Allocation to default */
3996 ew32(PBA, pba);
3997
3998 if (adapter->max_frame_size > (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)) {
3999 /* To maintain wire speed transmits, the Tx FIFO should be
4000 * large enough to accommodate two full transmit packets,
4001 * rounded up to the next 1KB and expressed in KB. Likewise,
4002 * the Rx FIFO should be large enough to accommodate at least
4003 * one full receive packet and is similarly rounded up and
4004 * expressed in KB.
4005 */
4006 pba = er32(PBA);
4007 /* upper 16 bits has Tx packet buffer allocation size in KB */
4008 tx_space = pba >> 16;
4009 /* lower 16 bits has Rx packet buffer allocation size in KB */
4010 pba &= 0xffff;
4011 /* the Tx fifo also stores 16 bytes of information about the Tx
4012 * but don't include ethernet FCS because hardware appends it
4013 */
4014 min_tx_space = (adapter->max_frame_size +
4015 sizeof(struct e1000_tx_desc) - ETH_FCS_LEN) * 2;
4016 min_tx_space = ALIGN(min_tx_space, 1024);
4017 min_tx_space >>= 10;
4018 /* software strips receive CRC, so leave room for it */
4019 min_rx_space = adapter->max_frame_size;
4020 min_rx_space = ALIGN(min_rx_space, 1024);
4021 min_rx_space >>= 10;
4022
4023 /* If current Tx allocation is less than the min Tx FIFO size,
4024 * and the min Tx FIFO size is less than the current Rx FIFO
4025 * allocation, take space away from current Rx allocation
4026 */
4027 if ((tx_space < min_tx_space) &&
4028 ((min_tx_space - tx_space) < pba)) {
4029 pba -= min_tx_space - tx_space;
4030
4031 /* if short on Rx space, Rx wins and must trump Tx
4032 * adjustment
4033 */
4034 if (pba < min_rx_space)
4035 pba = min_rx_space;
4036 }
4037
4038 ew32(PBA, pba);
4039 }
4040
4041 /* flow control settings
4042 *
4043 * The high water mark must be low enough to fit one full frame
4044 * (or the size used for early receive) above it in the Rx FIFO.
4045 * Set it to the lower of:
4046 * - 90% of the Rx FIFO size, and
4047 * - the full Rx FIFO size minus one full frame
4048 */
4049 if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME)
4050 fc->pause_time = 0xFFFF;
4051 else
4052 fc->pause_time = E1000_FC_PAUSE_TIME;
4053 fc->send_xon = true;
4054 fc->current_mode = fc->requested_mode;
4055
4056 switch (hw->mac.type) {
4057 case e1000_ich9lan:
4058 case e1000_ich10lan:
4059 if (adapter->netdev->mtu > ETH_DATA_LEN) {
4060 pba = 14;
4061 ew32(PBA, pba);
4062 fc->high_water = 0x2800;
4063 fc->low_water = fc->high_water - 8;
4064 break;
4065 }
4066 fallthrough;
4067 default:
4068 hwm = min(((pba << 10) * 9 / 10),
4069 ((pba << 10) - adapter->max_frame_size));
4070
4071 fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */
4072 fc->low_water = fc->high_water - 8;
4073 break;
4074 case e1000_pchlan:
4075 /* Workaround PCH LOM adapter hangs with certain network
4076 * loads. If hangs persist, try disabling Tx flow control.
4077 */
4078 if (adapter->netdev->mtu > ETH_DATA_LEN) {
4079 fc->high_water = 0x3500;
4080 fc->low_water = 0x1500;
4081 } else {
4082 fc->high_water = 0x5000;
4083 fc->low_water = 0x3000;
4084 }
4085 fc->refresh_time = 0x1000;
4086 break;
4087 case e1000_pch2lan:
4088 case e1000_pch_lpt:
4089 case e1000_pch_spt:
4090 case e1000_pch_cnp:
4091 case e1000_pch_tgp:
4092 case e1000_pch_adp:
4093 case e1000_pch_mtp:
4094 case e1000_pch_lnp:
4095 case e1000_pch_ptp:
4096 case e1000_pch_nvp:
4097 fc->refresh_time = 0xFFFF;
4098 fc->pause_time = 0xFFFF;
4099
4100 if (adapter->netdev->mtu <= ETH_DATA_LEN) {
4101 fc->high_water = 0x05C20;
4102 fc->low_water = 0x05048;
4103 break;
4104 }
4105
4106 pba = 14;
4107 ew32(PBA, pba);
4108 fc->high_water = ((pba << 10) * 9 / 10) & E1000_FCRTH_RTH;
4109 fc->low_water = ((pba << 10) * 8 / 10) & E1000_FCRTL_RTL;
4110 break;
4111 }
4112
4113 /* Alignment of Tx data is on an arbitrary byte boundary with the
4114 * maximum size per Tx descriptor limited only to the transmit
4115 * allocation of the packet buffer minus 96 bytes with an upper
4116 * limit of 24KB due to receive synchronization limitations.
4117 */
4118 adapter->tx_fifo_limit = min_t(u32, ((er32(PBA) >> 16) << 10) - 96,
4119 24 << 10);
4120
4121 /* Disable Adaptive Interrupt Moderation if 2 full packets cannot
4122 * fit in receive buffer.
4123 */
4124 if (adapter->itr_setting & 0x3) {
4125 if ((adapter->max_frame_size * 2) > (pba << 10)) {
4126 if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) {
4127 dev_info(&adapter->pdev->dev,
4128 "Interrupt Throttle Rate off\n");
4129 adapter->flags2 |= FLAG2_DISABLE_AIM;
4130 e1000e_write_itr(adapter, 0);
4131 }
4132 } else if (adapter->flags2 & FLAG2_DISABLE_AIM) {
4133 dev_info(&adapter->pdev->dev,
4134 "Interrupt Throttle Rate on\n");
4135 adapter->flags2 &= ~FLAG2_DISABLE_AIM;
4136 adapter->itr = 20000;
4137 e1000e_write_itr(adapter, adapter->itr);
4138 }
4139 }
4140
4141 if (hw->mac.type >= e1000_pch_spt)
4142 e1000_flush_desc_rings(adapter);
4143 /* Allow time for pending master requests to run */
4144 mac->ops.reset_hw(hw);
4145
4146 /* For parts with AMT enabled, let the firmware know
4147 * that the network interface is in control
4148 */
4149 if (adapter->flags & FLAG_HAS_AMT)
4150 e1000e_get_hw_control(adapter);
4151
4152 ew32(WUC, 0);
4153
4154 if (mac->ops.init_hw(hw))
4155 e_err("Hardware Error\n");
4156
4157 e1000_update_mng_vlan(adapter);
4158
4159 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
4160 ew32(VET, ETH_P_8021Q);
4161
4162 e1000e_reset_adaptive(hw);
4163
4164 /* restore systim and hwtstamp settings */
4165 e1000e_systim_reset(adapter);
4166
4167 /* Set EEE advertisement as appropriate */
4168 if (adapter->flags2 & FLAG2_HAS_EEE) {
4169 s32 ret_val;
4170 u16 adv_addr;
4171
4172 switch (hw->phy.type) {
4173 case e1000_phy_82579:
4174 adv_addr = I82579_EEE_ADVERTISEMENT;
4175 break;
4176 case e1000_phy_i217:
4177 adv_addr = I217_EEE_ADVERTISEMENT;
4178 break;
4179 default:
4180 dev_err(&adapter->pdev->dev,
4181 "Invalid PHY type setting EEE advertisement\n");
4182 return;
4183 }
4184
4185 ret_val = hw->phy.ops.acquire(hw);
4186 if (ret_val) {
4187 dev_err(&adapter->pdev->dev,
4188 "EEE advertisement - unable to acquire PHY\n");
4189 return;
4190 }
4191
4192 e1000_write_emi_reg_locked(hw, adv_addr,
4193 hw->dev_spec.ich8lan.eee_disable ?
4194 0 : adapter->eee_advert);
4195
4196 hw->phy.ops.release(hw);
4197 }
4198
4199 if (!netif_running(adapter->netdev) &&
4200 !test_bit(__E1000_TESTING, &adapter->state))
4201 e1000_power_down_phy(adapter);
4202
4203 e1000_get_phy_info(hw);
4204
4205 if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) &&
4206 !(adapter->flags & FLAG_SMART_POWER_DOWN)) {
4207 u16 phy_data = 0;
4208 /* speed up time to link by disabling smart power down, ignore
4209 * the return value of this function because there is nothing
4210 * different we would do if it failed
4211 */
4212 e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
4213 phy_data &= ~IGP02E1000_PM_SPD;
4214 e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
4215 }
4216 if (hw->mac.type >= e1000_pch_spt && adapter->int_mode == 0) {
4217 u32 reg;
4218
4219 /* Fextnvm7 @ 0xe4[2] = 1 */
4220 reg = er32(FEXTNVM7);
4221 reg |= E1000_FEXTNVM7_SIDE_CLK_UNGATE;
4222 ew32(FEXTNVM7, reg);
4223 /* Fextnvm9 @ 0x5bb4[13:12] = 11 */
4224 reg = er32(FEXTNVM9);
4225 reg |= E1000_FEXTNVM9_IOSFSB_CLKGATE_DIS |
4226 E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS;
4227 ew32(FEXTNVM9, reg);
4228 }
4229
4230}
4231
4232/**
4233 * e1000e_trigger_lsc - trigger an LSC interrupt
4234 * @adapter: board private structure
4235 *
4236 * Fire a link status change interrupt to start the watchdog.
4237 **/
4238static void e1000e_trigger_lsc(struct e1000_adapter *adapter)
4239{
4240 struct e1000_hw *hw = &adapter->hw;
4241
4242 if (adapter->msix_entries)
4243 ew32(ICS, E1000_ICS_LSC | E1000_ICS_OTHER);
4244 else
4245 ew32(ICS, E1000_ICS_LSC);
4246}
4247
4248void e1000e_up(struct e1000_adapter *adapter)
4249{
4250 /* hardware has been reset, we need to reload some things */
4251 e1000_configure(adapter);
4252
4253 clear_bit(__E1000_DOWN, &adapter->state);
4254
4255 if (adapter->msix_entries)
4256 e1000_configure_msix(adapter);
4257 e1000_irq_enable(adapter);
4258
4259 /* Tx queue started by watchdog timer when link is up */
4260
4261 e1000e_trigger_lsc(adapter);
4262}
4263
4264static void e1000e_flush_descriptors(struct e1000_adapter *adapter)
4265{
4266 struct e1000_hw *hw = &adapter->hw;
4267
4268 if (!(adapter->flags2 & FLAG2_DMA_BURST))
4269 return;
4270
4271 /* flush pending descriptor writebacks to memory */
4272 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
4273 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
4274
4275 /* execute the writes immediately */
4276 e1e_flush();
4277
4278 /* due to rare timing issues, write to TIDV/RDTR again to ensure the
4279 * write is successful
4280 */
4281 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
4282 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
4283
4284 /* execute the writes immediately */
4285 e1e_flush();
4286}
4287
4288static void e1000e_update_stats(struct e1000_adapter *adapter);
4289
4290/**
4291 * e1000e_down - quiesce the device and optionally reset the hardware
4292 * @adapter: board private structure
4293 * @reset: boolean flag to reset the hardware or not
4294 */
4295void e1000e_down(struct e1000_adapter *adapter, bool reset)
4296{
4297 struct net_device *netdev = adapter->netdev;
4298 struct e1000_hw *hw = &adapter->hw;
4299 u32 tctl, rctl;
4300
4301 /* signal that we're down so the interrupt handler does not
4302 * reschedule our watchdog timer
4303 */
4304 set_bit(__E1000_DOWN, &adapter->state);
4305
4306 netif_carrier_off(netdev);
4307
4308 /* disable receives in the hardware */
4309 rctl = er32(RCTL);
4310 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
4311 ew32(RCTL, rctl & ~E1000_RCTL_EN);
4312 /* flush and sleep below */
4313
4314 netif_stop_queue(netdev);
4315
4316 /* disable transmits in the hardware */
4317 tctl = er32(TCTL);
4318 tctl &= ~E1000_TCTL_EN;
4319 ew32(TCTL, tctl);
4320
4321 /* flush both disables and wait for them to finish */
4322 e1e_flush();
4323 usleep_range(10000, 11000);
4324
4325 e1000_irq_disable(adapter);
4326
4327 napi_synchronize(&adapter->napi);
4328
4329 timer_delete_sync(&adapter->watchdog_timer);
4330 timer_delete_sync(&adapter->phy_info_timer);
4331
4332 spin_lock(&adapter->stats64_lock);
4333 e1000e_update_stats(adapter);
4334 spin_unlock(&adapter->stats64_lock);
4335
4336 e1000e_flush_descriptors(adapter);
4337
4338 adapter->link_speed = 0;
4339 adapter->link_duplex = 0;
4340
4341 /* Disable Si errata workaround on PCHx for jumbo frame flow */
4342 if ((hw->mac.type >= e1000_pch2lan) &&
4343 (adapter->netdev->mtu > ETH_DATA_LEN) &&
4344 e1000_lv_jumbo_workaround_ich8lan(hw, false))
4345 e_dbg("failed to disable jumbo frame workaround mode\n");
4346
4347 if (!pci_channel_offline(adapter->pdev)) {
4348 if (reset)
4349 e1000e_reset(adapter);
4350 else if (hw->mac.type >= e1000_pch_spt)
4351 e1000_flush_desc_rings(adapter);
4352 }
4353 e1000_clean_tx_ring(adapter->tx_ring);
4354 e1000_clean_rx_ring(adapter->rx_ring);
4355}
4356
4357void e1000e_reinit_locked(struct e1000_adapter *adapter)
4358{
4359 might_sleep();
4360 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
4361 usleep_range(1000, 1100);
4362 e1000e_down(adapter, true);
4363 e1000e_up(adapter);
4364 clear_bit(__E1000_RESETTING, &adapter->state);
4365}
4366
4367/**
4368 * e1000e_sanitize_systim - sanitize raw cycle counter reads
4369 * @hw: pointer to the HW structure
4370 * @systim: PHC time value read, sanitized and returned
4371 * @sts: structure to hold system time before and after reading SYSTIML,
4372 * may be NULL
4373 *
4374 * Errata for 82574/82583 possible bad bits read from SYSTIMH/L:
4375 * check to see that the time is incrementing at a reasonable
4376 * rate and is a multiple of incvalue.
4377 **/
4378static u64 e1000e_sanitize_systim(struct e1000_hw *hw, u64 systim,
4379 struct ptp_system_timestamp *sts)
4380{
4381 u64 time_delta, rem, temp;
4382 u64 systim_next;
4383 u32 incvalue;
4384 int i;
4385
4386 incvalue = er32(TIMINCA) & E1000_TIMINCA_INCVALUE_MASK;
4387 for (i = 0; i < E1000_MAX_82574_SYSTIM_REREADS; i++) {
4388 /* latch SYSTIMH on read of SYSTIML */
4389 ptp_read_system_prets(sts);
4390 systim_next = (u64)er32(SYSTIML);
4391 ptp_read_system_postts(sts);
4392 systim_next |= (u64)er32(SYSTIMH) << 32;
4393
4394 time_delta = systim_next - systim;
4395 temp = time_delta;
4396 /* VMWare users have seen incvalue of zero, don't div / 0 */
4397 rem = incvalue ? do_div(temp, incvalue) : (time_delta != 0);
4398
4399 systim = systim_next;
4400
4401 if ((time_delta < E1000_82574_SYSTIM_EPSILON) && (rem == 0))
4402 break;
4403 }
4404
4405 return systim;
4406}
4407
4408/**
4409 * e1000e_read_systim - read SYSTIM register
4410 * @adapter: board private structure
4411 * @sts: structure which will contain system time before and after reading
4412 * SYSTIML, may be NULL
4413 **/
4414u64 e1000e_read_systim(struct e1000_adapter *adapter,
4415 struct ptp_system_timestamp *sts)
4416{
4417 struct e1000_hw *hw = &adapter->hw;
4418 u32 systimel, systimel_2, systimeh;
4419 u64 systim;
4420 /* SYSTIMH latching upon SYSTIML read does not work well.
4421 * This means that if SYSTIML overflows after we read it but before
4422 * we read SYSTIMH, the value of SYSTIMH has been incremented and we
4423 * will experience a huge non linear increment in the systime value
4424 * to fix that we test for overflow and if true, we re-read systime.
4425 */
4426 ptp_read_system_prets(sts);
4427 systimel = er32(SYSTIML);
4428 ptp_read_system_postts(sts);
4429 systimeh = er32(SYSTIMH);
4430 /* Is systimel is so large that overflow is possible? */
4431 if (systimel >= (u32)0xffffffff - E1000_TIMINCA_INCVALUE_MASK) {
4432 ptp_read_system_prets(sts);
4433 systimel_2 = er32(SYSTIML);
4434 ptp_read_system_postts(sts);
4435 if (systimel > systimel_2) {
4436 /* There was an overflow, read again SYSTIMH, and use
4437 * systimel_2
4438 */
4439 systimeh = er32(SYSTIMH);
4440 systimel = systimel_2;
4441 }
4442 }
4443 systim = (u64)systimel;
4444 systim |= (u64)systimeh << 32;
4445
4446 if (adapter->flags2 & FLAG2_CHECK_SYSTIM_OVERFLOW)
4447 systim = e1000e_sanitize_systim(hw, systim, sts);
4448
4449 return systim;
4450}
4451
4452/**
4453 * e1000e_cyclecounter_read - read raw cycle counter (used by time counter)
4454 * @cc: cyclecounter structure
4455 **/
4456static u64 e1000e_cyclecounter_read(struct cyclecounter *cc)
4457{
4458 struct e1000_adapter *adapter = container_of(cc, struct e1000_adapter,
4459 cc);
4460
4461 return e1000e_read_systim(adapter, NULL);
4462}
4463
4464/**
4465 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
4466 * @adapter: board private structure to initialize
4467 *
4468 * e1000_sw_init initializes the Adapter private data structure.
4469 * Fields are initialized based on PCI device information and
4470 * OS network device settings (MTU size).
4471 **/
4472static int e1000_sw_init(struct e1000_adapter *adapter)
4473{
4474 struct net_device *netdev = adapter->netdev;
4475
4476 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
4477 adapter->rx_ps_bsize0 = 128;
4478 adapter->max_frame_size = netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
4479 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
4480 adapter->tx_ring_count = E1000_DEFAULT_TXD;
4481 adapter->rx_ring_count = E1000_DEFAULT_RXD;
4482
4483 spin_lock_init(&adapter->stats64_lock);
4484
4485 e1000e_set_interrupt_capability(adapter);
4486
4487 if (e1000_alloc_queues(adapter))
4488 return -ENOMEM;
4489
4490 /* Setup hardware time stamping cyclecounter */
4491 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
4492 adapter->cc.read = e1000e_cyclecounter_read;
4493 adapter->cc.mask = CYCLECOUNTER_MASK(64);
4494 adapter->cc.mult = 1;
4495 /* cc.shift set in e1000e_get_base_tininca() */
4496
4497 spin_lock_init(&adapter->systim_lock);
4498 INIT_WORK(&adapter->tx_hwtstamp_work, e1000e_tx_hwtstamp_work);
4499 }
4500
4501 /* Explicitly disable IRQ since the NIC can be in any state. */
4502 e1000_irq_disable(adapter);
4503
4504 set_bit(__E1000_DOWN, &adapter->state);
4505 return 0;
4506}
4507
4508/**
4509 * e1000_intr_msi_test - Interrupt Handler
4510 * @irq: interrupt number
4511 * @data: pointer to a network interface device structure
4512 **/
4513static irqreturn_t e1000_intr_msi_test(int __always_unused irq, void *data)
4514{
4515 struct net_device *netdev = data;
4516 struct e1000_adapter *adapter = netdev_priv(netdev);
4517 struct e1000_hw *hw = &adapter->hw;
4518 u32 icr = er32(ICR);
4519
4520 e_dbg("icr is %08X\n", icr);
4521 if (icr & E1000_ICR_RXSEQ) {
4522 adapter->flags &= ~FLAG_MSI_TEST_FAILED;
4523 /* Force memory writes to complete before acknowledging the
4524 * interrupt is handled.
4525 */
4526 wmb();
4527 }
4528
4529 return IRQ_HANDLED;
4530}
4531
4532/**
4533 * e1000_test_msi_interrupt - Returns 0 for successful test
4534 * @adapter: board private struct
4535 *
4536 * code flow taken from tg3.c
4537 **/
4538static int e1000_test_msi_interrupt(struct e1000_adapter *adapter)
4539{
4540 struct net_device *netdev = adapter->netdev;
4541 struct e1000_hw *hw = &adapter->hw;
4542 int err;
4543
4544 /* poll_enable hasn't been called yet, so don't need disable */
4545 /* clear any pending events */
4546 er32(ICR);
4547
4548 /* free the real vector and request a test handler */
4549 e1000_free_irq(adapter);
4550 e1000e_reset_interrupt_capability(adapter);
4551
4552 /* Assume that the test fails, if it succeeds then the test
4553 * MSI irq handler will unset this flag
4554 */
4555 adapter->flags |= FLAG_MSI_TEST_FAILED;
4556
4557 err = pci_enable_msi(adapter->pdev);
4558 if (err)
4559 goto msi_test_failed;
4560
4561 err = request_irq(adapter->pdev->irq, e1000_intr_msi_test, 0,
4562 netdev->name, netdev);
4563 if (err) {
4564 pci_disable_msi(adapter->pdev);
4565 goto msi_test_failed;
4566 }
4567
4568 /* Force memory writes to complete before enabling and firing an
4569 * interrupt.
4570 */
4571 wmb();
4572
4573 e1000_irq_enable(adapter);
4574
4575 /* fire an unusual interrupt on the test handler */
4576 ew32(ICS, E1000_ICS_RXSEQ);
4577 e1e_flush();
4578 msleep(100);
4579
4580 e1000_irq_disable(adapter);
4581
4582 rmb(); /* read flags after interrupt has been fired */
4583
4584 if (adapter->flags & FLAG_MSI_TEST_FAILED) {
4585 adapter->int_mode = E1000E_INT_MODE_LEGACY;
4586 e_info("MSI interrupt test failed, using legacy interrupt.\n");
4587 } else {
4588 e_dbg("MSI interrupt test succeeded!\n");
4589 }
4590
4591 free_irq(adapter->pdev->irq, netdev);
4592 pci_disable_msi(adapter->pdev);
4593
4594msi_test_failed:
4595 e1000e_set_interrupt_capability(adapter);
4596 return e1000_request_irq(adapter);
4597}
4598
4599/**
4600 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored
4601 * @adapter: board private struct
4602 *
4603 * code flow taken from tg3.c, called with e1000 interrupts disabled.
4604 **/
4605static int e1000_test_msi(struct e1000_adapter *adapter)
4606{
4607 int err;
4608 u16 pci_cmd;
4609
4610 if (!(adapter->flags & FLAG_MSI_ENABLED))
4611 return 0;
4612
4613 /* disable SERR in case the MSI write causes a master abort */
4614 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
4615 if (pci_cmd & PCI_COMMAND_SERR)
4616 pci_write_config_word(adapter->pdev, PCI_COMMAND,
4617 pci_cmd & ~PCI_COMMAND_SERR);
4618
4619 err = e1000_test_msi_interrupt(adapter);
4620
4621 /* re-enable SERR */
4622 if (pci_cmd & PCI_COMMAND_SERR) {
4623 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
4624 pci_cmd |= PCI_COMMAND_SERR;
4625 pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd);
4626 }
4627
4628 return err;
4629}
4630
4631/**
4632 * e1000e_open - Called when a network interface is made active
4633 * @netdev: network interface device structure
4634 *
4635 * Returns 0 on success, negative value on failure
4636 *
4637 * The open entry point is called when a network interface is made
4638 * active by the system (IFF_UP). At this point all resources needed
4639 * for transmit and receive operations are allocated, the interrupt
4640 * handler is registered with the OS, the watchdog timer is started,
4641 * and the stack is notified that the interface is ready.
4642 **/
4643int e1000e_open(struct net_device *netdev)
4644{
4645 struct e1000_adapter *adapter = netdev_priv(netdev);
4646 struct e1000_hw *hw = &adapter->hw;
4647 struct pci_dev *pdev = adapter->pdev;
4648 int err;
4649 int irq;
4650
4651 /* disallow open during test */
4652 if (test_bit(__E1000_TESTING, &adapter->state))
4653 return -EBUSY;
4654
4655 pm_runtime_get_sync(&pdev->dev);
4656
4657 netif_carrier_off(netdev);
4658 netif_stop_queue(netdev);
4659
4660 /* allocate transmit descriptors */
4661 err = e1000e_setup_tx_resources(adapter->tx_ring);
4662 if (err)
4663 goto err_setup_tx;
4664
4665 /* allocate receive descriptors */
4666 err = e1000e_setup_rx_resources(adapter->rx_ring);
4667 if (err)
4668 goto err_setup_rx;
4669
4670 /* If AMT is enabled, let the firmware know that the network
4671 * interface is now open and reset the part to a known state.
4672 */
4673 if (adapter->flags & FLAG_HAS_AMT) {
4674 e1000e_get_hw_control(adapter);
4675 e1000e_reset(adapter);
4676 }
4677
4678 e1000e_power_up_phy(adapter);
4679
4680 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
4681 if ((adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
4682 e1000_update_mng_vlan(adapter);
4683
4684 /* DMA latency requirement to workaround jumbo issue */
4685 cpu_latency_qos_add_request(&adapter->pm_qos_req, PM_QOS_DEFAULT_VALUE);
4686
4687 /* before we allocate an interrupt, we must be ready to handle it.
4688 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
4689 * as soon as we call pci_request_irq, so we have to setup our
4690 * clean_rx handler before we do so.
4691 */
4692 e1000_configure(adapter);
4693
4694 err = e1000_request_irq(adapter);
4695 if (err)
4696 goto err_req_irq;
4697
4698 /* Work around PCIe errata with MSI interrupts causing some chipsets to
4699 * ignore e1000e MSI messages, which means we need to test our MSI
4700 * interrupt now
4701 */
4702 if (adapter->int_mode != E1000E_INT_MODE_LEGACY) {
4703 err = e1000_test_msi(adapter);
4704 if (err) {
4705 e_err("Interrupt allocation failed\n");
4706 goto err_req_irq;
4707 }
4708 }
4709
4710 /* From here on the code is the same as e1000e_up() */
4711 clear_bit(__E1000_DOWN, &adapter->state);
4712
4713 if (adapter->int_mode == E1000E_INT_MODE_MSIX)
4714 irq = adapter->msix_entries[0].vector;
4715 else
4716 irq = adapter->pdev->irq;
4717
4718 netif_napi_set_irq(&adapter->napi, irq);
4719 napi_enable(&adapter->napi);
4720 netif_queue_set_napi(netdev, 0, NETDEV_QUEUE_TYPE_RX, &adapter->napi);
4721 netif_queue_set_napi(netdev, 0, NETDEV_QUEUE_TYPE_TX, &adapter->napi);
4722
4723 e1000_irq_enable(adapter);
4724
4725 adapter->tx_hang_recheck = false;
4726
4727 hw->mac.get_link_status = true;
4728 pm_runtime_put(&pdev->dev);
4729
4730 e1000e_trigger_lsc(adapter);
4731
4732 return 0;
4733
4734err_req_irq:
4735 cpu_latency_qos_remove_request(&adapter->pm_qos_req);
4736 e1000e_release_hw_control(adapter);
4737 e1000_power_down_phy(adapter);
4738 e1000e_free_rx_resources(adapter->rx_ring);
4739err_setup_rx:
4740 e1000e_free_tx_resources(adapter->tx_ring);
4741err_setup_tx:
4742 e1000e_reset(adapter);
4743 pm_runtime_put_sync(&pdev->dev);
4744
4745 return err;
4746}
4747
4748/**
4749 * e1000e_close - Disables a network interface
4750 * @netdev: network interface device structure
4751 *
4752 * Returns 0, this is not allowed to fail
4753 *
4754 * The close entry point is called when an interface is de-activated
4755 * by the OS. The hardware is still under the drivers control, but
4756 * needs to be disabled. A global MAC reset is issued to stop the
4757 * hardware, and all transmit and receive resources are freed.
4758 **/
4759int e1000e_close(struct net_device *netdev)
4760{
4761 struct e1000_adapter *adapter = netdev_priv(netdev);
4762 struct pci_dev *pdev = adapter->pdev;
4763 int count = E1000_CHECK_RESET_COUNT;
4764
4765 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
4766 usleep_range(10000, 11000);
4767
4768 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
4769
4770 pm_runtime_get_sync(&pdev->dev);
4771
4772 if (netif_device_present(netdev)) {
4773 e1000e_down(adapter, true);
4774 e1000_free_irq(adapter);
4775
4776 /* Link status message must follow this format */
4777 netdev_info(netdev, "NIC Link is Down\n");
4778 }
4779
4780 netif_queue_set_napi(netdev, 0, NETDEV_QUEUE_TYPE_RX, NULL);
4781 netif_queue_set_napi(netdev, 0, NETDEV_QUEUE_TYPE_TX, NULL);
4782 napi_disable(&adapter->napi);
4783
4784 e1000e_free_tx_resources(adapter->tx_ring);
4785 e1000e_free_rx_resources(adapter->rx_ring);
4786
4787 /* kill manageability vlan ID if supported, but not if a vlan with
4788 * the same ID is registered on the host OS (let 8021q kill it)
4789 */
4790 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN)
4791 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q),
4792 adapter->mng_vlan_id);
4793
4794 /* If AMT is enabled, let the firmware know that the network
4795 * interface is now closed
4796 */
4797 if ((adapter->flags & FLAG_HAS_AMT) &&
4798 !test_bit(__E1000_TESTING, &adapter->state))
4799 e1000e_release_hw_control(adapter);
4800
4801 cpu_latency_qos_remove_request(&adapter->pm_qos_req);
4802
4803 pm_runtime_put_sync(&pdev->dev);
4804
4805 return 0;
4806}
4807
4808/**
4809 * e1000_set_mac - Change the Ethernet Address of the NIC
4810 * @netdev: network interface device structure
4811 * @p: pointer to an address structure
4812 *
4813 * Returns 0 on success, negative on failure
4814 **/
4815static int e1000_set_mac(struct net_device *netdev, void *p)
4816{
4817 struct e1000_adapter *adapter = netdev_priv(netdev);
4818 struct e1000_hw *hw = &adapter->hw;
4819 struct sockaddr *addr = p;
4820
4821 if (!is_valid_ether_addr(addr->sa_data))
4822 return -EADDRNOTAVAIL;
4823
4824 eth_hw_addr_set(netdev, addr->sa_data);
4825 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
4826
4827 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
4828
4829 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) {
4830 /* activate the work around */
4831 e1000e_set_laa_state_82571(&adapter->hw, 1);
4832
4833 /* Hold a copy of the LAA in RAR[14] This is done so that
4834 * between the time RAR[0] gets clobbered and the time it
4835 * gets fixed (in e1000_watchdog), the actual LAA is in one
4836 * of the RARs and no incoming packets directed to this port
4837 * are dropped. Eventually the LAA will be in RAR[0] and
4838 * RAR[14]
4839 */
4840 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr,
4841 adapter->hw.mac.rar_entry_count - 1);
4842 }
4843
4844 return 0;
4845}
4846
4847/**
4848 * e1000e_update_phy_task - work thread to update phy
4849 * @work: pointer to our work struct
4850 *
4851 * this worker thread exists because we must acquire a
4852 * semaphore to read the phy, which we could msleep while
4853 * waiting for it, and we can't msleep in a timer.
4854 **/
4855static void e1000e_update_phy_task(struct work_struct *work)
4856{
4857 struct e1000_adapter *adapter = container_of(work,
4858 struct e1000_adapter,
4859 update_phy_task);
4860 struct e1000_hw *hw = &adapter->hw;
4861
4862 if (test_bit(__E1000_DOWN, &adapter->state))
4863 return;
4864
4865 e1000_get_phy_info(hw);
4866
4867 /* Enable EEE on 82579 after link up */
4868 if (hw->phy.type >= e1000_phy_82579)
4869 e1000_set_eee_pchlan(hw);
4870}
4871
4872/**
4873 * e1000_update_phy_info - timre call-back to update PHY info
4874 * @t: pointer to timer_list containing private info adapter
4875 *
4876 * Need to wait a few seconds after link up to get diagnostic information from
4877 * the phy
4878 **/
4879static void e1000_update_phy_info(struct timer_list *t)
4880{
4881 struct e1000_adapter *adapter = timer_container_of(adapter, t,
4882 phy_info_timer);
4883
4884 if (test_bit(__E1000_DOWN, &adapter->state))
4885 return;
4886
4887 schedule_work(&adapter->update_phy_task);
4888}
4889
4890/**
4891 * e1000e_update_phy_stats - Update the PHY statistics counters
4892 * @adapter: board private structure
4893 *
4894 * Read/clear the upper 16-bit PHY registers and read/accumulate lower
4895 **/
4896static void e1000e_update_phy_stats(struct e1000_adapter *adapter)
4897{
4898 struct e1000_hw *hw = &adapter->hw;
4899 s32 ret_val;
4900 u16 phy_data;
4901
4902 ret_val = hw->phy.ops.acquire(hw);
4903 if (ret_val)
4904 return;
4905
4906 /* A page set is expensive so check if already on desired page.
4907 * If not, set to the page with the PHY status registers.
4908 */
4909 hw->phy.addr = 1;
4910 ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
4911 &phy_data);
4912 if (ret_val)
4913 goto release;
4914 if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) {
4915 ret_val = hw->phy.ops.set_page(hw,
4916 HV_STATS_PAGE << IGP_PAGE_SHIFT);
4917 if (ret_val)
4918 goto release;
4919 }
4920
4921 /* Single Collision Count */
4922 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4923 ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
4924 if (!ret_val)
4925 adapter->stats.scc += phy_data;
4926
4927 /* Excessive Collision Count */
4928 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4929 ret_val = hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
4930 if (!ret_val)
4931 adapter->stats.ecol += phy_data;
4932
4933 /* Multiple Collision Count */
4934 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4935 ret_val = hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
4936 if (!ret_val)
4937 adapter->stats.mcc += phy_data;
4938
4939 /* Late Collision Count */
4940 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4941 ret_val = hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
4942 if (!ret_val)
4943 adapter->stats.latecol += phy_data;
4944
4945 /* Collision Count - also used for adaptive IFS */
4946 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4947 ret_val = hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
4948 if (!ret_val)
4949 hw->mac.collision_delta = phy_data;
4950
4951 /* Defer Count */
4952 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4953 ret_val = hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
4954 if (!ret_val)
4955 adapter->stats.dc += phy_data;
4956
4957 /* Transmit with no CRS */
4958 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4959 ret_val = hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
4960 if (!ret_val)
4961 adapter->stats.tncrs += phy_data;
4962
4963release:
4964 hw->phy.ops.release(hw);
4965}
4966
4967/**
4968 * e1000e_update_stats - Update the board statistics counters
4969 * @adapter: board private structure
4970 **/
4971static void e1000e_update_stats(struct e1000_adapter *adapter)
4972{
4973 struct net_device *netdev = adapter->netdev;
4974 struct e1000_hw *hw = &adapter->hw;
4975 struct pci_dev *pdev = adapter->pdev;
4976
4977 /* Prevent stats update while adapter is being reset, or if the pci
4978 * connection is down.
4979 */
4980 if (adapter->link_speed == 0)
4981 return;
4982 if (pci_channel_offline(pdev))
4983 return;
4984
4985 adapter->stats.crcerrs += er32(CRCERRS);
4986 adapter->stats.gprc += er32(GPRC);
4987 adapter->stats.gorc += er32(GORCL);
4988 er32(GORCH); /* Clear gorc */
4989 adapter->stats.bprc += er32(BPRC);
4990 adapter->stats.mprc += er32(MPRC);
4991 adapter->stats.roc += er32(ROC);
4992
4993 adapter->stats.mpc += er32(MPC);
4994
4995 /* Half-duplex statistics */
4996 if (adapter->link_duplex == HALF_DUPLEX) {
4997 if (adapter->flags2 & FLAG2_HAS_PHY_STATS) {
4998 e1000e_update_phy_stats(adapter);
4999 } else {
5000 adapter->stats.scc += er32(SCC);
5001 adapter->stats.ecol += er32(ECOL);
5002 adapter->stats.mcc += er32(MCC);
5003 adapter->stats.latecol += er32(LATECOL);
5004 adapter->stats.dc += er32(DC);
5005
5006 hw->mac.collision_delta = er32(COLC);
5007
5008 if ((hw->mac.type != e1000_82574) &&
5009 (hw->mac.type != e1000_82583))
5010 adapter->stats.tncrs += er32(TNCRS);
5011 }
5012 adapter->stats.colc += hw->mac.collision_delta;
5013 }
5014
5015 adapter->stats.xonrxc += er32(XONRXC);
5016 adapter->stats.xontxc += er32(XONTXC);
5017 adapter->stats.xoffrxc += er32(XOFFRXC);
5018 adapter->stats.xofftxc += er32(XOFFTXC);
5019 adapter->stats.gptc += er32(GPTC);
5020 adapter->stats.gotc += er32(GOTCL);
5021 er32(GOTCH); /* Clear gotc */
5022 adapter->stats.rnbc += er32(RNBC);
5023 adapter->stats.ruc += er32(RUC);
5024
5025 adapter->stats.mptc += er32(MPTC);
5026 adapter->stats.bptc += er32(BPTC);
5027
5028 /* used for adaptive IFS */
5029
5030 hw->mac.tx_packet_delta = er32(TPT);
5031 adapter->stats.tpt += hw->mac.tx_packet_delta;
5032
5033 adapter->stats.algnerrc += er32(ALGNERRC);
5034 adapter->stats.rxerrc += er32(RXERRC);
5035 adapter->stats.cexterr += er32(CEXTERR);
5036 adapter->stats.tsctc += er32(TSCTC);
5037 adapter->stats.tsctfc += er32(TSCTFC);
5038
5039 /* Fill out the OS statistics structure */
5040 netdev->stats.multicast = adapter->stats.mprc;
5041 netdev->stats.collisions = adapter->stats.colc;
5042
5043 /* Rx Errors */
5044
5045 /* RLEC on some newer hardware can be incorrect so build
5046 * our own version based on RUC and ROC
5047 */
5048 netdev->stats.rx_errors = adapter->stats.rxerrc +
5049 adapter->stats.crcerrs + adapter->stats.algnerrc +
5050 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr;
5051 netdev->stats.rx_length_errors = adapter->stats.ruc +
5052 adapter->stats.roc;
5053 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
5054 netdev->stats.rx_frame_errors = adapter->stats.algnerrc;
5055 netdev->stats.rx_missed_errors = adapter->stats.mpc;
5056
5057 /* Tx Errors */
5058 netdev->stats.tx_errors = adapter->stats.ecol + adapter->stats.latecol;
5059 netdev->stats.tx_aborted_errors = adapter->stats.ecol;
5060 netdev->stats.tx_window_errors = adapter->stats.latecol;
5061 netdev->stats.tx_carrier_errors = adapter->stats.tncrs;
5062
5063 /* Tx Dropped needs to be maintained elsewhere */
5064
5065 /* Management Stats */
5066 adapter->stats.mgptc += er32(MGTPTC);
5067 adapter->stats.mgprc += er32(MGTPRC);
5068 adapter->stats.mgpdc += er32(MGTPDC);
5069
5070 /* Correctable ECC Errors */
5071 if (hw->mac.type >= e1000_pch_lpt) {
5072 u32 pbeccsts = er32(PBECCSTS);
5073
5074 adapter->corr_errors +=
5075 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
5076 adapter->uncorr_errors +=
5077 FIELD_GET(E1000_PBECCSTS_UNCORR_ERR_CNT_MASK, pbeccsts);
5078 }
5079}
5080
5081/**
5082 * e1000_phy_read_status - Update the PHY register status snapshot
5083 * @adapter: board private structure
5084 **/
5085static void e1000_phy_read_status(struct e1000_adapter *adapter)
5086{
5087 struct e1000_hw *hw = &adapter->hw;
5088 struct e1000_phy_regs *phy = &adapter->phy_regs;
5089
5090 if (!pm_runtime_suspended((&adapter->pdev->dev)->parent) &&
5091 (er32(STATUS) & E1000_STATUS_LU) &&
5092 (adapter->hw.phy.media_type == e1000_media_type_copper)) {
5093 int ret_val;
5094
5095 ret_val = e1e_rphy(hw, MII_BMCR, &phy->bmcr);
5096 ret_val |= e1e_rphy(hw, MII_BMSR, &phy->bmsr);
5097 ret_val |= e1e_rphy(hw, MII_ADVERTISE, &phy->advertise);
5098 ret_val |= e1e_rphy(hw, MII_LPA, &phy->lpa);
5099 ret_val |= e1e_rphy(hw, MII_EXPANSION, &phy->expansion);
5100 ret_val |= e1e_rphy(hw, MII_CTRL1000, &phy->ctrl1000);
5101 ret_val |= e1e_rphy(hw, MII_STAT1000, &phy->stat1000);
5102 ret_val |= e1e_rphy(hw, MII_ESTATUS, &phy->estatus);
5103 if (ret_val)
5104 e_warn("Error reading PHY register\n");
5105 } else {
5106 /* Do not read PHY registers if link is not up
5107 * Set values to typical power-on defaults
5108 */
5109 phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX);
5110 phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL |
5111 BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE |
5112 BMSR_ERCAP);
5113 phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP |
5114 ADVERTISE_ALL | ADVERTISE_CSMA);
5115 phy->lpa = 0;
5116 phy->expansion = EXPANSION_ENABLENPAGE;
5117 phy->ctrl1000 = ADVERTISE_1000FULL;
5118 phy->stat1000 = 0;
5119 phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF);
5120 }
5121}
5122
5123static void e1000_print_link_info(struct e1000_adapter *adapter)
5124{
5125 struct e1000_hw *hw = &adapter->hw;
5126 u32 ctrl = er32(CTRL);
5127
5128 /* Link status message must follow this format for user tools */
5129 netdev_info(adapter->netdev,
5130 "NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
5131 adapter->link_speed,
5132 adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half",
5133 (ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE) ? "Rx/Tx" :
5134 (ctrl & E1000_CTRL_RFCE) ? "Rx" :
5135 (ctrl & E1000_CTRL_TFCE) ? "Tx" : "None");
5136}
5137
5138static bool e1000e_has_link(struct e1000_adapter *adapter)
5139{
5140 struct e1000_hw *hw = &adapter->hw;
5141 bool link_active = false;
5142 s32 ret_val = 0;
5143
5144 /* get_link_status is set on LSC (link status) interrupt or
5145 * Rx sequence error interrupt. get_link_status will stay
5146 * true until the check_for_link establishes link
5147 * for copper adapters ONLY
5148 */
5149 switch (hw->phy.media_type) {
5150 case e1000_media_type_copper:
5151 if (hw->mac.get_link_status) {
5152 ret_val = hw->mac.ops.check_for_link(hw);
5153 link_active = !hw->mac.get_link_status;
5154 } else {
5155 link_active = true;
5156 }
5157 break;
5158 case e1000_media_type_fiber:
5159 ret_val = hw->mac.ops.check_for_link(hw);
5160 link_active = !!(er32(STATUS) & E1000_STATUS_LU);
5161 break;
5162 case e1000_media_type_internal_serdes:
5163 ret_val = hw->mac.ops.check_for_link(hw);
5164 link_active = hw->mac.serdes_has_link;
5165 break;
5166 default:
5167 case e1000_media_type_unknown:
5168 break;
5169 }
5170
5171 if ((ret_val == -E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) &&
5172 (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) {
5173 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */
5174 e_info("Gigabit has been disabled, downgrading speed\n");
5175 }
5176
5177 return link_active;
5178}
5179
5180static void e1000e_enable_receives(struct e1000_adapter *adapter)
5181{
5182 /* make sure the receive unit is started */
5183 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) &&
5184 (adapter->flags & FLAG_RESTART_NOW)) {
5185 struct e1000_hw *hw = &adapter->hw;
5186 u32 rctl = er32(RCTL);
5187
5188 ew32(RCTL, rctl | E1000_RCTL_EN);
5189 adapter->flags &= ~FLAG_RESTART_NOW;
5190 }
5191}
5192
5193static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter)
5194{
5195 struct e1000_hw *hw = &adapter->hw;
5196
5197 /* With 82574 controllers, PHY needs to be checked periodically
5198 * for hung state and reset, if two calls return true
5199 */
5200 if (e1000_check_phy_82574(hw))
5201 adapter->phy_hang_count++;
5202 else
5203 adapter->phy_hang_count = 0;
5204
5205 if (adapter->phy_hang_count > 1) {
5206 adapter->phy_hang_count = 0;
5207 e_dbg("PHY appears hung - resetting\n");
5208 schedule_work(&adapter->reset_task);
5209 }
5210}
5211
5212/**
5213 * e1000_watchdog - Timer Call-back
5214 * @t: pointer to timer_list containing private info adapter
5215 **/
5216static void e1000_watchdog(struct timer_list *t)
5217{
5218 struct e1000_adapter *adapter = timer_container_of(adapter, t,
5219 watchdog_timer);
5220
5221 /* Do the rest outside of interrupt context */
5222 schedule_work(&adapter->watchdog_task);
5223
5224 /* TODO: make this use queue_delayed_work() */
5225}
5226
5227static void e1000_watchdog_task(struct work_struct *work)
5228{
5229 struct e1000_adapter *adapter = container_of(work,
5230 struct e1000_adapter,
5231 watchdog_task);
5232 struct net_device *netdev = adapter->netdev;
5233 struct e1000_mac_info *mac = &adapter->hw.mac;
5234 struct e1000_phy_info *phy = &adapter->hw.phy;
5235 struct e1000_ring *tx_ring = adapter->tx_ring;
5236 u32 dmoff_exit_timeout = 100, tries = 0;
5237 struct e1000_hw *hw = &adapter->hw;
5238 u32 link, tctl, pcim_state;
5239
5240 if (test_bit(__E1000_DOWN, &adapter->state))
5241 return;
5242
5243 link = e1000e_has_link(adapter);
5244 if ((netif_carrier_ok(netdev)) && link) {
5245 /* Cancel scheduled suspend requests. */
5246 pm_runtime_resume(netdev->dev.parent);
5247
5248 e1000e_enable_receives(adapter);
5249 goto link_up;
5250 }
5251
5252 if ((e1000e_enable_tx_pkt_filtering(hw)) &&
5253 (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id))
5254 e1000_update_mng_vlan(adapter);
5255
5256 if (link) {
5257 if (!netif_carrier_ok(netdev)) {
5258 bool txb2b = true;
5259
5260 /* Cancel scheduled suspend requests. */
5261 pm_runtime_resume(netdev->dev.parent);
5262
5263 /* Checking if MAC is in DMoff state*/
5264 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
5265 pcim_state = er32(STATUS);
5266 while (pcim_state & E1000_STATUS_PCIM_STATE) {
5267 if (tries++ == dmoff_exit_timeout) {
5268 e_dbg("Error in exiting dmoff\n");
5269 break;
5270 }
5271 usleep_range(10000, 20000);
5272 pcim_state = er32(STATUS);
5273
5274 /* Checking if MAC exited DMoff state */
5275 if (!(pcim_state & E1000_STATUS_PCIM_STATE))
5276 e1000_phy_hw_reset(&adapter->hw);
5277 }
5278 }
5279
5280 /* update snapshot of PHY registers on LSC */
5281 e1000_phy_read_status(adapter);
5282 mac->ops.get_link_up_info(&adapter->hw,
5283 &adapter->link_speed,
5284 &adapter->link_duplex);
5285 e1000_print_link_info(adapter);
5286
5287 /* check if SmartSpeed worked */
5288 e1000e_check_downshift(hw);
5289 if (phy->speed_downgraded)
5290 netdev_warn(netdev,
5291 "Link Speed was downgraded by SmartSpeed\n");
5292
5293 /* On supported PHYs, check for duplex mismatch only
5294 * if link has autonegotiated at 10/100 half
5295 */
5296 if ((hw->phy.type == e1000_phy_igp_3 ||
5297 hw->phy.type == e1000_phy_bm) &&
5298 hw->mac.autoneg &&
5299 (adapter->link_speed == SPEED_10 ||
5300 adapter->link_speed == SPEED_100) &&
5301 (adapter->link_duplex == HALF_DUPLEX)) {
5302 u16 autoneg_exp;
5303
5304 e1e_rphy(hw, MII_EXPANSION, &autoneg_exp);
5305
5306 if (!(autoneg_exp & EXPANSION_NWAY))
5307 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n");
5308 }
5309
5310 /* adjust timeout factor according to speed/duplex */
5311 adapter->tx_timeout_factor = 1;
5312 switch (adapter->link_speed) {
5313 case SPEED_10:
5314 txb2b = false;
5315 adapter->tx_timeout_factor = 16;
5316 break;
5317 case SPEED_100:
5318 txb2b = false;
5319 adapter->tx_timeout_factor = 10;
5320 break;
5321 }
5322
5323 /* workaround: re-program speed mode bit after
5324 * link-up event
5325 */
5326 if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) &&
5327 !txb2b) {
5328 u32 tarc0;
5329
5330 tarc0 = er32(TARC(0));
5331 tarc0 &= ~SPEED_MODE_BIT;
5332 ew32(TARC(0), tarc0);
5333 }
5334
5335 /* enable transmits in the hardware, need to do this
5336 * after setting TARC(0)
5337 */
5338 tctl = er32(TCTL);
5339 tctl |= E1000_TCTL_EN;
5340 ew32(TCTL, tctl);
5341
5342 /* Perform any post-link-up configuration before
5343 * reporting link up.
5344 */
5345 if (phy->ops.cfg_on_link_up)
5346 phy->ops.cfg_on_link_up(hw);
5347
5348 netif_wake_queue(netdev);
5349 netif_carrier_on(netdev);
5350
5351 if (!test_bit(__E1000_DOWN, &adapter->state))
5352 mod_timer(&adapter->phy_info_timer,
5353 round_jiffies(jiffies + 2 * HZ));
5354 }
5355 } else {
5356 if (netif_carrier_ok(netdev)) {
5357 adapter->link_speed = 0;
5358 adapter->link_duplex = 0;
5359 /* Link status message must follow this format */
5360 netdev_info(netdev, "NIC Link is Down\n");
5361 netif_carrier_off(netdev);
5362 netif_stop_queue(netdev);
5363 if (!test_bit(__E1000_DOWN, &adapter->state))
5364 mod_timer(&adapter->phy_info_timer,
5365 round_jiffies(jiffies + 2 * HZ));
5366
5367 /* 8000ES2LAN requires a Rx packet buffer work-around
5368 * on link down event; reset the controller to flush
5369 * the Rx packet buffer.
5370 */
5371 if (adapter->flags & FLAG_RX_NEEDS_RESTART)
5372 adapter->flags |= FLAG_RESTART_NOW;
5373 else
5374 pm_schedule_suspend(netdev->dev.parent,
5375 LINK_TIMEOUT);
5376 }
5377 }
5378
5379link_up:
5380 spin_lock(&adapter->stats64_lock);
5381 e1000e_update_stats(adapter);
5382
5383 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
5384 adapter->tpt_old = adapter->stats.tpt;
5385 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
5386 adapter->colc_old = adapter->stats.colc;
5387
5388 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
5389 adapter->gorc_old = adapter->stats.gorc;
5390 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
5391 adapter->gotc_old = adapter->stats.gotc;
5392 spin_unlock(&adapter->stats64_lock);
5393
5394 /* If the link is lost the controller stops DMA, but
5395 * if there is queued Tx work it cannot be done. So
5396 * reset the controller to flush the Tx packet buffers.
5397 */
5398 if (!netif_carrier_ok(netdev) &&
5399 (e1000_desc_unused(tx_ring) + 1 < tx_ring->count))
5400 adapter->flags |= FLAG_RESTART_NOW;
5401
5402 /* If reset is necessary, do it outside of interrupt context. */
5403 if (adapter->flags & FLAG_RESTART_NOW) {
5404 schedule_work(&adapter->reset_task);
5405 /* return immediately since reset is imminent */
5406 return;
5407 }
5408
5409 e1000e_update_adaptive(&adapter->hw);
5410
5411 /* Simple mode for Interrupt Throttle Rate (ITR) */
5412 if (adapter->itr_setting == 4) {
5413 /* Symmetric Tx/Rx gets a reduced ITR=2000;
5414 * Total asymmetrical Tx or Rx gets ITR=8000;
5415 * everyone else is between 2000-8000.
5416 */
5417 u32 goc = (adapter->gotc + adapter->gorc) / 10000;
5418 u32 dif = (adapter->gotc > adapter->gorc ?
5419 adapter->gotc - adapter->gorc :
5420 adapter->gorc - adapter->gotc) / 10000;
5421 u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
5422
5423 e1000e_write_itr(adapter, itr);
5424 }
5425
5426 /* Cause software interrupt to ensure Rx ring is cleaned */
5427 if (adapter->msix_entries)
5428 ew32(ICS, adapter->rx_ring->ims_val);
5429 else
5430 ew32(ICS, E1000_ICS_RXDMT0);
5431
5432 /* flush pending descriptors to memory before detecting Tx hang */
5433 e1000e_flush_descriptors(adapter);
5434
5435 /* Force detection of hung controller every watchdog period */
5436 adapter->detect_tx_hung = true;
5437
5438 /* With 82571 controllers, LAA may be overwritten due to controller
5439 * reset from the other port. Set the appropriate LAA in RAR[0]
5440 */
5441 if (e1000e_get_laa_state_82571(hw))
5442 hw->mac.ops.rar_set(hw, adapter->hw.mac.addr, 0);
5443
5444 if (adapter->flags2 & FLAG2_CHECK_PHY_HANG)
5445 e1000e_check_82574_phy_workaround(adapter);
5446
5447 /* Clear valid timestamp stuck in RXSTMPL/H due to a Rx error */
5448 if (adapter->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) {
5449 if ((adapter->flags2 & FLAG2_CHECK_RX_HWTSTAMP) &&
5450 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) {
5451 er32(RXSTMPH);
5452 adapter->rx_hwtstamp_cleared++;
5453 } else {
5454 adapter->flags2 |= FLAG2_CHECK_RX_HWTSTAMP;
5455 }
5456 }
5457
5458 /* Reset the timer */
5459 if (!test_bit(__E1000_DOWN, &adapter->state))
5460 mod_timer(&adapter->watchdog_timer,
5461 round_jiffies(jiffies + 2 * HZ));
5462}
5463
5464#define E1000_TX_FLAGS_CSUM 0x00000001
5465#define E1000_TX_FLAGS_VLAN 0x00000002
5466#define E1000_TX_FLAGS_TSO 0x00000004
5467#define E1000_TX_FLAGS_IPV4 0x00000008
5468#define E1000_TX_FLAGS_NO_FCS 0x00000010
5469#define E1000_TX_FLAGS_HWTSTAMP 0x00000020
5470#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
5471#define E1000_TX_FLAGS_VLAN_SHIFT 16
5472
5473static int e1000_tso(struct e1000_ring *tx_ring, struct sk_buff *skb,
5474 __be16 protocol)
5475{
5476 struct e1000_context_desc *context_desc;
5477 struct e1000_buffer *buffer_info;
5478 unsigned int i;
5479 u32 cmd_length = 0;
5480 u16 ipcse = 0, mss;
5481 u8 ipcss, ipcso, tucss, tucso, hdr_len;
5482 int err;
5483
5484 if (!skb_is_gso(skb))
5485 return 0;
5486
5487 err = skb_cow_head(skb, 0);
5488 if (err < 0)
5489 return err;
5490
5491 hdr_len = skb_tcp_all_headers(skb);
5492 mss = skb_shinfo(skb)->gso_size;
5493 if (protocol == htons(ETH_P_IP)) {
5494 struct iphdr *iph = ip_hdr(skb);
5495 iph->tot_len = 0;
5496 iph->check = 0;
5497 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
5498 0, IPPROTO_TCP, 0);
5499 cmd_length = E1000_TXD_CMD_IP;
5500 ipcse = skb_transport_offset(skb) - 1;
5501 } else if (skb_is_gso_v6(skb)) {
5502 tcp_v6_gso_csum_prep(skb);
5503 ipcse = 0;
5504 }
5505 ipcss = skb_network_offset(skb);
5506 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data;
5507 tucss = skb_transport_offset(skb);
5508 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data;
5509
5510 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
5511 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
5512
5513 i = tx_ring->next_to_use;
5514 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
5515 buffer_info = &tx_ring->buffer_info[i];
5516
5517 context_desc->lower_setup.ip_fields.ipcss = ipcss;
5518 context_desc->lower_setup.ip_fields.ipcso = ipcso;
5519 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
5520 context_desc->upper_setup.tcp_fields.tucss = tucss;
5521 context_desc->upper_setup.tcp_fields.tucso = tucso;
5522 context_desc->upper_setup.tcp_fields.tucse = 0;
5523 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
5524 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
5525 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
5526
5527 buffer_info->time_stamp = jiffies;
5528 buffer_info->next_to_watch = i;
5529
5530 i++;
5531 if (i == tx_ring->count)
5532 i = 0;
5533 tx_ring->next_to_use = i;
5534
5535 return 1;
5536}
5537
5538static bool e1000_tx_csum(struct e1000_ring *tx_ring, struct sk_buff *skb,
5539 __be16 protocol)
5540{
5541 struct e1000_adapter *adapter = tx_ring->adapter;
5542 struct e1000_context_desc *context_desc;
5543 struct e1000_buffer *buffer_info;
5544 unsigned int i;
5545 u8 css;
5546 u32 cmd_len = E1000_TXD_CMD_DEXT;
5547
5548 if (skb->ip_summed != CHECKSUM_PARTIAL)
5549 return false;
5550
5551 switch (protocol) {
5552 case cpu_to_be16(ETH_P_IP):
5553 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5554 cmd_len |= E1000_TXD_CMD_TCP;
5555 break;
5556 case cpu_to_be16(ETH_P_IPV6):
5557 /* XXX not handling all IPV6 headers */
5558 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5559 cmd_len |= E1000_TXD_CMD_TCP;
5560 break;
5561 default:
5562 if (unlikely(net_ratelimit()))
5563 e_warn("checksum_partial proto=%x!\n",
5564 be16_to_cpu(protocol));
5565 break;
5566 }
5567
5568 css = skb_checksum_start_offset(skb);
5569
5570 i = tx_ring->next_to_use;
5571 buffer_info = &tx_ring->buffer_info[i];
5572 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
5573
5574 context_desc->lower_setup.ip_config = 0;
5575 context_desc->upper_setup.tcp_fields.tucss = css;
5576 context_desc->upper_setup.tcp_fields.tucso = css + skb->csum_offset;
5577 context_desc->upper_setup.tcp_fields.tucse = 0;
5578 context_desc->tcp_seg_setup.data = 0;
5579 context_desc->cmd_and_length = cpu_to_le32(cmd_len);
5580
5581 buffer_info->time_stamp = jiffies;
5582 buffer_info->next_to_watch = i;
5583
5584 i++;
5585 if (i == tx_ring->count)
5586 i = 0;
5587 tx_ring->next_to_use = i;
5588
5589 return true;
5590}
5591
5592static int e1000_tx_map(struct e1000_ring *tx_ring, struct sk_buff *skb,
5593 unsigned int first, unsigned int max_per_txd,
5594 unsigned int nr_frags)
5595{
5596 struct e1000_adapter *adapter = tx_ring->adapter;
5597 struct pci_dev *pdev = adapter->pdev;
5598 struct e1000_buffer *buffer_info;
5599 unsigned int len = skb_headlen(skb);
5600 unsigned int offset = 0, size, count = 0, i;
5601 unsigned int f, bytecount, segs;
5602
5603 i = tx_ring->next_to_use;
5604
5605 while (len) {
5606 buffer_info = &tx_ring->buffer_info[i];
5607 size = min(len, max_per_txd);
5608
5609 buffer_info->length = size;
5610 buffer_info->time_stamp = jiffies;
5611 buffer_info->next_to_watch = i;
5612 buffer_info->dma = dma_map_single(&pdev->dev,
5613 skb->data + offset,
5614 size, DMA_TO_DEVICE);
5615 buffer_info->mapped_as_page = false;
5616 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
5617 goto dma_error;
5618
5619 len -= size;
5620 offset += size;
5621 count++;
5622
5623 if (len) {
5624 i++;
5625 if (i == tx_ring->count)
5626 i = 0;
5627 }
5628 }
5629
5630 for (f = 0; f < nr_frags; f++) {
5631 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
5632
5633 len = skb_frag_size(frag);
5634 offset = 0;
5635
5636 while (len) {
5637 i++;
5638 if (i == tx_ring->count)
5639 i = 0;
5640
5641 buffer_info = &tx_ring->buffer_info[i];
5642 size = min(len, max_per_txd);
5643
5644 buffer_info->length = size;
5645 buffer_info->time_stamp = jiffies;
5646 buffer_info->next_to_watch = i;
5647 buffer_info->dma = skb_frag_dma_map(&pdev->dev, frag,
5648 offset, size,
5649 DMA_TO_DEVICE);
5650 buffer_info->mapped_as_page = true;
5651 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
5652 goto dma_error;
5653
5654 len -= size;
5655 offset += size;
5656 count++;
5657 }
5658 }
5659
5660 segs = skb_shinfo(skb)->gso_segs ? : 1;
5661 /* multiply data chunks by size of headers */
5662 bytecount = ((segs - 1) * skb_headlen(skb)) + skb->len;
5663
5664 tx_ring->buffer_info[i].skb = skb;
5665 tx_ring->buffer_info[i].segs = segs;
5666 tx_ring->buffer_info[i].bytecount = bytecount;
5667 tx_ring->buffer_info[first].next_to_watch = i;
5668
5669 return count;
5670
5671dma_error:
5672 dev_err(&pdev->dev, "Tx DMA map failed\n");
5673 buffer_info->dma = 0;
5674
5675 while (count--) {
5676 if (i == 0)
5677 i += tx_ring->count;
5678 i--;
5679 buffer_info = &tx_ring->buffer_info[i];
5680 e1000_put_txbuf(tx_ring, buffer_info, true);
5681 }
5682
5683 return 0;
5684}
5685
5686static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count)
5687{
5688 struct e1000_adapter *adapter = tx_ring->adapter;
5689 struct e1000_tx_desc *tx_desc = NULL;
5690 struct e1000_buffer *buffer_info;
5691 u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
5692 unsigned int i;
5693
5694 if (tx_flags & E1000_TX_FLAGS_TSO) {
5695 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
5696 E1000_TXD_CMD_TSE;
5697 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
5698
5699 if (tx_flags & E1000_TX_FLAGS_IPV4)
5700 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
5701 }
5702
5703 if (tx_flags & E1000_TX_FLAGS_CSUM) {
5704 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
5705 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
5706 }
5707
5708 if (tx_flags & E1000_TX_FLAGS_VLAN) {
5709 txd_lower |= E1000_TXD_CMD_VLE;
5710 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
5711 }
5712
5713 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
5714 txd_lower &= ~(E1000_TXD_CMD_IFCS);
5715
5716 if (unlikely(tx_flags & E1000_TX_FLAGS_HWTSTAMP)) {
5717 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
5718 txd_upper |= E1000_TXD_EXTCMD_TSTAMP;
5719 }
5720
5721 i = tx_ring->next_to_use;
5722
5723 do {
5724 buffer_info = &tx_ring->buffer_info[i];
5725 tx_desc = E1000_TX_DESC(*tx_ring, i);
5726 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
5727 tx_desc->lower.data = cpu_to_le32(txd_lower |
5728 buffer_info->length);
5729 tx_desc->upper.data = cpu_to_le32(txd_upper);
5730
5731 i++;
5732 if (i == tx_ring->count)
5733 i = 0;
5734 } while (--count > 0);
5735
5736 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
5737
5738 /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */
5739 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
5740 tx_desc->lower.data &= ~(cpu_to_le32(E1000_TXD_CMD_IFCS));
5741
5742 /* Force memory writes to complete before letting h/w
5743 * know there are new descriptors to fetch. (Only
5744 * applicable for weak-ordered memory model archs,
5745 * such as IA-64).
5746 */
5747 wmb();
5748
5749 tx_ring->next_to_use = i;
5750}
5751
5752#define MINIMUM_DHCP_PACKET_SIZE 282
5753static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter,
5754 struct sk_buff *skb)
5755{
5756 struct e1000_hw *hw = &adapter->hw;
5757 u16 length, offset;
5758
5759 if (skb_vlan_tag_present(skb) &&
5760 !((skb_vlan_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
5761 (adapter->hw.mng_cookie.status &
5762 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)))
5763 return 0;
5764
5765 if (skb->len <= MINIMUM_DHCP_PACKET_SIZE)
5766 return 0;
5767
5768 if (((struct ethhdr *)skb->data)->h_proto != htons(ETH_P_IP))
5769 return 0;
5770
5771 {
5772 const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data + 14);
5773 struct udphdr *udp;
5774
5775 if (ip->protocol != IPPROTO_UDP)
5776 return 0;
5777
5778 udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2));
5779 if (ntohs(udp->dest) != 67)
5780 return 0;
5781
5782 offset = (u8 *)udp + 8 - skb->data;
5783 length = skb->len - offset;
5784 return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length);
5785 }
5786
5787 return 0;
5788}
5789
5790static int __e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
5791{
5792 struct e1000_adapter *adapter = tx_ring->adapter;
5793
5794 netif_stop_queue(adapter->netdev);
5795 /* Herbert's original patch had:
5796 * smp_mb__after_netif_stop_queue();
5797 * but since that doesn't exist yet, just open code it.
5798 */
5799 smp_mb();
5800
5801 /* We need to check again in a case another CPU has just
5802 * made room available.
5803 */
5804 if (e1000_desc_unused(tx_ring) < size)
5805 return -EBUSY;
5806
5807 /* A reprieve! */
5808 netif_start_queue(adapter->netdev);
5809 ++adapter->restart_queue;
5810 return 0;
5811}
5812
5813static int e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
5814{
5815 BUG_ON(size > tx_ring->count);
5816
5817 if (e1000_desc_unused(tx_ring) >= size)
5818 return 0;
5819 return __e1000_maybe_stop_tx(tx_ring, size);
5820}
5821
5822static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
5823 struct net_device *netdev)
5824{
5825 struct e1000_adapter *adapter = netdev_priv(netdev);
5826 struct e1000_ring *tx_ring = adapter->tx_ring;
5827 unsigned int first;
5828 unsigned int tx_flags = 0;
5829 unsigned int len = skb_headlen(skb);
5830 unsigned int nr_frags;
5831 unsigned int mss;
5832 int count = 0;
5833 int tso;
5834 unsigned int f;
5835 __be16 protocol = vlan_get_protocol(skb);
5836
5837 if (test_bit(__E1000_DOWN, &adapter->state)) {
5838 dev_kfree_skb_any(skb);
5839 return NETDEV_TX_OK;
5840 }
5841
5842 if (skb->len <= 0) {
5843 dev_kfree_skb_any(skb);
5844 return NETDEV_TX_OK;
5845 }
5846
5847 /* The minimum packet size with TCTL.PSP set is 17 bytes so
5848 * pad skb in order to meet this minimum size requirement
5849 */
5850 if (skb_put_padto(skb, 17))
5851 return NETDEV_TX_OK;
5852
5853 mss = skb_shinfo(skb)->gso_size;
5854 if (mss) {
5855 u8 hdr_len;
5856
5857 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data
5858 * points to just header, pull a few bytes of payload from
5859 * frags into skb->data
5860 */
5861 hdr_len = skb_tcp_all_headers(skb);
5862 /* we do this workaround for ES2LAN, but it is un-necessary,
5863 * avoiding it could save a lot of cycles
5864 */
5865 if (skb->data_len && (hdr_len == len)) {
5866 unsigned int pull_size;
5867
5868 pull_size = min_t(unsigned int, 4, skb->data_len);
5869 if (!__pskb_pull_tail(skb, pull_size)) {
5870 e_err("__pskb_pull_tail failed.\n");
5871 dev_kfree_skb_any(skb);
5872 return NETDEV_TX_OK;
5873 }
5874 len = skb_headlen(skb);
5875 }
5876 }
5877
5878 /* reserve a descriptor for the offload context */
5879 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL))
5880 count++;
5881 count++;
5882
5883 count += DIV_ROUND_UP(len, adapter->tx_fifo_limit);
5884
5885 nr_frags = skb_shinfo(skb)->nr_frags;
5886 for (f = 0; f < nr_frags; f++)
5887 count += DIV_ROUND_UP(skb_frag_size(&skb_shinfo(skb)->frags[f]),
5888 adapter->tx_fifo_limit);
5889
5890 if (adapter->hw.mac.tx_pkt_filtering)
5891 e1000_transfer_dhcp_info(adapter, skb);
5892
5893 /* need: count + 2 desc gap to keep tail from touching
5894 * head, otherwise try next time
5895 */
5896 if (e1000_maybe_stop_tx(tx_ring, count + 2))
5897 return NETDEV_TX_BUSY;
5898
5899 if (skb_vlan_tag_present(skb)) {
5900 tx_flags |= E1000_TX_FLAGS_VLAN;
5901 tx_flags |= (skb_vlan_tag_get(skb) <<
5902 E1000_TX_FLAGS_VLAN_SHIFT);
5903 }
5904
5905 first = tx_ring->next_to_use;
5906
5907 tso = e1000_tso(tx_ring, skb, protocol);
5908 if (tso < 0) {
5909 dev_kfree_skb_any(skb);
5910 return NETDEV_TX_OK;
5911 }
5912
5913 if (tso)
5914 tx_flags |= E1000_TX_FLAGS_TSO;
5915 else if (e1000_tx_csum(tx_ring, skb, protocol))
5916 tx_flags |= E1000_TX_FLAGS_CSUM;
5917
5918 /* Old method was to assume IPv4 packet by default if TSO was enabled.
5919 * 82571 hardware supports TSO capabilities for IPv6 as well...
5920 * no longer assume, we must.
5921 */
5922 if (protocol == htons(ETH_P_IP))
5923 tx_flags |= E1000_TX_FLAGS_IPV4;
5924
5925 if (unlikely(skb->no_fcs))
5926 tx_flags |= E1000_TX_FLAGS_NO_FCS;
5927
5928 /* if count is 0 then mapping error has occurred */
5929 count = e1000_tx_map(tx_ring, skb, first, adapter->tx_fifo_limit,
5930 nr_frags);
5931 if (count) {
5932 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
5933 (adapter->flags & FLAG_HAS_HW_TIMESTAMP)) {
5934 if (!adapter->tx_hwtstamp_skb) {
5935 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
5936 tx_flags |= E1000_TX_FLAGS_HWTSTAMP;
5937 adapter->tx_hwtstamp_skb = skb_get(skb);
5938 adapter->tx_hwtstamp_start = jiffies;
5939 schedule_work(&adapter->tx_hwtstamp_work);
5940 } else {
5941 adapter->tx_hwtstamp_skipped++;
5942 }
5943 }
5944
5945 skb_tx_timestamp(skb);
5946
5947 netdev_sent_queue(netdev, skb->len);
5948 e1000_tx_queue(tx_ring, tx_flags, count);
5949 /* Make sure there is space in the ring for the next send. */
5950 e1000_maybe_stop_tx(tx_ring,
5951 ((MAX_SKB_FRAGS + 1) *
5952 DIV_ROUND_UP(PAGE_SIZE,
5953 adapter->tx_fifo_limit) + 4));
5954
5955 if (!netdev_xmit_more() ||
5956 netif_xmit_stopped(netdev_get_tx_queue(netdev, 0))) {
5957 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
5958 e1000e_update_tdt_wa(tx_ring,
5959 tx_ring->next_to_use);
5960 else
5961 writel(tx_ring->next_to_use, tx_ring->tail);
5962 }
5963 } else {
5964 dev_kfree_skb_any(skb);
5965 tx_ring->buffer_info[first].time_stamp = 0;
5966 tx_ring->next_to_use = first;
5967 }
5968
5969 return NETDEV_TX_OK;
5970}
5971
5972/**
5973 * e1000_tx_timeout - Respond to a Tx Hang
5974 * @netdev: network interface device structure
5975 * @txqueue: index of the hung queue (unused)
5976 **/
5977static void e1000_tx_timeout(struct net_device *netdev, unsigned int __always_unused txqueue)
5978{
5979 struct e1000_adapter *adapter = netdev_priv(netdev);
5980
5981 /* Do the reset outside of interrupt context */
5982 adapter->tx_timeout_count++;
5983 schedule_work(&adapter->reset_task);
5984}
5985
5986static void e1000_reset_task(struct work_struct *work)
5987{
5988 struct e1000_adapter *adapter;
5989 adapter = container_of(work, struct e1000_adapter, reset_task);
5990
5991 rtnl_lock();
5992 /* don't run the task if already down */
5993 if (test_bit(__E1000_DOWN, &adapter->state)) {
5994 rtnl_unlock();
5995 return;
5996 }
5997
5998 if (!(adapter->flags & FLAG_RESTART_NOW)) {
5999 e1000e_dump(adapter);
6000 e_err("Reset adapter unexpectedly\n");
6001 }
6002 e1000e_reinit_locked(adapter);
6003 rtnl_unlock();
6004}
6005
6006/**
6007 * e1000e_get_stats64 - Get System Network Statistics
6008 * @netdev: network interface device structure
6009 * @stats: rtnl_link_stats64 pointer
6010 *
6011 * Returns the address of the device statistics structure.
6012 **/
6013void e1000e_get_stats64(struct net_device *netdev,
6014 struct rtnl_link_stats64 *stats)
6015{
6016 struct e1000_adapter *adapter = netdev_priv(netdev);
6017
6018 spin_lock(&adapter->stats64_lock);
6019 e1000e_update_stats(adapter);
6020 /* Fill out the OS statistics structure */
6021 stats->rx_bytes = adapter->stats.gorc;
6022 stats->rx_packets = adapter->stats.gprc;
6023 stats->tx_bytes = adapter->stats.gotc;
6024 stats->tx_packets = adapter->stats.gptc;
6025 stats->multicast = adapter->stats.mprc;
6026 stats->collisions = adapter->stats.colc;
6027
6028 /* Rx Errors */
6029
6030 /* RLEC on some newer hardware can be incorrect so build
6031 * our own version based on RUC and ROC
6032 */
6033 stats->rx_errors = adapter->stats.rxerrc +
6034 adapter->stats.crcerrs + adapter->stats.algnerrc +
6035 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr;
6036 stats->rx_length_errors = adapter->stats.ruc + adapter->stats.roc;
6037 stats->rx_crc_errors = adapter->stats.crcerrs;
6038 stats->rx_frame_errors = adapter->stats.algnerrc;
6039 stats->rx_missed_errors = adapter->stats.mpc;
6040
6041 /* Tx Errors */
6042 stats->tx_errors = adapter->stats.ecol + adapter->stats.latecol;
6043 stats->tx_aborted_errors = adapter->stats.ecol;
6044 stats->tx_window_errors = adapter->stats.latecol;
6045 stats->tx_carrier_errors = adapter->stats.tncrs;
6046
6047 /* Tx Dropped needs to be maintained elsewhere */
6048
6049 spin_unlock(&adapter->stats64_lock);
6050}
6051
6052/**
6053 * e1000_change_mtu - Change the Maximum Transfer Unit
6054 * @netdev: network interface device structure
6055 * @new_mtu: new value for maximum frame size
6056 *
6057 * Returns 0 on success, negative on failure
6058 **/
6059static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
6060{
6061 struct e1000_adapter *adapter = netdev_priv(netdev);
6062 int max_frame = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
6063
6064 /* Jumbo frame support */
6065 if ((new_mtu > ETH_DATA_LEN) &&
6066 !(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) {
6067 e_err("Jumbo Frames not supported.\n");
6068 return -EINVAL;
6069 }
6070
6071 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
6072 if ((adapter->hw.mac.type >= e1000_pch2lan) &&
6073 !(adapter->flags2 & FLAG2_CRC_STRIPPING) &&
6074 (new_mtu > ETH_DATA_LEN)) {
6075 e_err("Jumbo Frames not supported on this device when CRC stripping is disabled.\n");
6076 return -EINVAL;
6077 }
6078
6079 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
6080 usleep_range(1000, 1100);
6081 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */
6082 adapter->max_frame_size = max_frame;
6083 netdev_dbg(netdev, "changing MTU from %d to %d\n",
6084 netdev->mtu, new_mtu);
6085 WRITE_ONCE(netdev->mtu, new_mtu);
6086
6087 pm_runtime_get_sync(netdev->dev.parent);
6088
6089 if (netif_running(netdev))
6090 e1000e_down(adapter, true);
6091
6092 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
6093 * means we reserve 2 more, this pushes us to allocate from the next
6094 * larger slab size.
6095 * i.e. RXBUFFER_2048 --> size-4096 slab
6096 * However with the new *_jumbo_rx* routines, jumbo receives will use
6097 * fragmented skbs
6098 */
6099
6100 if (max_frame <= 2048)
6101 adapter->rx_buffer_len = 2048;
6102 else
6103 adapter->rx_buffer_len = 4096;
6104
6105 /* adjust allocation if LPE protects us, and we aren't using SBP */
6106 if (max_frame <= (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN))
6107 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
6108
6109 if (netif_running(netdev))
6110 e1000e_up(adapter);
6111 else
6112 e1000e_reset(adapter);
6113
6114 pm_runtime_put_sync(netdev->dev.parent);
6115
6116 clear_bit(__E1000_RESETTING, &adapter->state);
6117
6118 return 0;
6119}
6120
6121static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6122{
6123 struct e1000_adapter *adapter = netdev_priv(netdev);
6124 struct mii_ioctl_data *data = if_mii(ifr);
6125
6126 if (adapter->hw.phy.media_type != e1000_media_type_copper)
6127 return -EOPNOTSUPP;
6128
6129 switch (cmd) {
6130 case SIOCGMIIPHY:
6131 data->phy_id = adapter->hw.phy.addr;
6132 break;
6133 case SIOCGMIIREG:
6134 e1000_phy_read_status(adapter);
6135
6136 switch (data->reg_num & 0x1F) {
6137 case MII_BMCR:
6138 data->val_out = adapter->phy_regs.bmcr;
6139 break;
6140 case MII_BMSR:
6141 data->val_out = adapter->phy_regs.bmsr;
6142 break;
6143 case MII_PHYSID1:
6144 data->val_out = (adapter->hw.phy.id >> 16);
6145 break;
6146 case MII_PHYSID2:
6147 data->val_out = (adapter->hw.phy.id & 0xFFFF);
6148 break;
6149 case MII_ADVERTISE:
6150 data->val_out = adapter->phy_regs.advertise;
6151 break;
6152 case MII_LPA:
6153 data->val_out = adapter->phy_regs.lpa;
6154 break;
6155 case MII_EXPANSION:
6156 data->val_out = adapter->phy_regs.expansion;
6157 break;
6158 case MII_CTRL1000:
6159 data->val_out = adapter->phy_regs.ctrl1000;
6160 break;
6161 case MII_STAT1000:
6162 data->val_out = adapter->phy_regs.stat1000;
6163 break;
6164 case MII_ESTATUS:
6165 data->val_out = adapter->phy_regs.estatus;
6166 break;
6167 default:
6168 return -EIO;
6169 }
6170 break;
6171 case SIOCSMIIREG:
6172 default:
6173 return -EOPNOTSUPP;
6174 }
6175 return 0;
6176}
6177
6178/**
6179 * e1000e_hwtstamp_set - control hardware time stamping
6180 * @netdev: network interface device structure
6181 * @config: timestamp configuration
6182 * @extack: netlink extended ACK report
6183 *
6184 * Outgoing time stamping can be enabled and disabled. Play nice and
6185 * disable it when requested, although it shouldn't cause any overhead
6186 * when no packet needs it. At most one packet in the queue may be
6187 * marked for time stamping, otherwise it would be impossible to tell
6188 * for sure to which packet the hardware time stamp belongs.
6189 *
6190 * Incoming time stamping has to be configured via the hardware filters.
6191 * Not all combinations are supported, in particular event type has to be
6192 * specified. Matching the kind of event packet is not supported, with the
6193 * exception of "all V2 events regardless of level 2 or 4".
6194 **/
6195static int e1000e_hwtstamp_set(struct net_device *netdev,
6196 struct kernel_hwtstamp_config *config,
6197 struct netlink_ext_ack *extack)
6198{
6199 struct e1000_adapter *adapter = netdev_priv(netdev);
6200 int ret_val;
6201
6202 ret_val = e1000e_config_hwtstamp(adapter, config, extack);
6203 if (ret_val)
6204 return ret_val;
6205
6206 switch (config->rx_filter) {
6207 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
6208 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
6209 case HWTSTAMP_FILTER_PTP_V2_SYNC:
6210 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
6211 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
6212 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
6213 /* With V2 type filters which specify a Sync or Delay Request,
6214 * Path Delay Request/Response messages are also time stamped
6215 * by hardware so notify the caller the requested packets plus
6216 * some others are time stamped.
6217 */
6218 config->rx_filter = HWTSTAMP_FILTER_SOME;
6219 break;
6220 default:
6221 break;
6222 }
6223
6224 return 0;
6225}
6226
6227static int e1000e_hwtstamp_get(struct net_device *netdev,
6228 struct kernel_hwtstamp_config *kernel_config)
6229{
6230 struct e1000_adapter *adapter = netdev_priv(netdev);
6231
6232 *kernel_config = adapter->hwtstamp_config;
6233
6234 return 0;
6235}
6236
6237static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc)
6238{
6239 struct e1000_hw *hw = &adapter->hw;
6240 u32 i, mac_reg, wuc;
6241 u16 phy_reg, wuc_enable;
6242 int retval;
6243
6244 /* copy MAC RARs to PHY RARs */
6245 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
6246
6247 retval = hw->phy.ops.acquire(hw);
6248 if (retval) {
6249 e_err("Could not acquire PHY\n");
6250 return retval;
6251 }
6252
6253 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */
6254 retval = e1000_enable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
6255 if (retval)
6256 goto release;
6257
6258 /* copy MAC MTA to PHY MTA - only needed for pchlan */
6259 for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) {
6260 mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
6261 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
6262 (u16)(mac_reg & 0xFFFF));
6263 hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1,
6264 (u16)((mac_reg >> 16) & 0xFFFF));
6265 }
6266
6267 /* configure PHY Rx Control register */
6268 hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg);
6269 mac_reg = er32(RCTL);
6270 if (mac_reg & E1000_RCTL_UPE)
6271 phy_reg |= BM_RCTL_UPE;
6272 if (mac_reg & E1000_RCTL_MPE)
6273 phy_reg |= BM_RCTL_MPE;
6274 phy_reg &= ~(BM_RCTL_MO_MASK);
6275 if (mac_reg & E1000_RCTL_MO_3)
6276 phy_reg |= (FIELD_GET(E1000_RCTL_MO_3, mac_reg)
6277 << BM_RCTL_MO_SHIFT);
6278 if (mac_reg & E1000_RCTL_BAM)
6279 phy_reg |= BM_RCTL_BAM;
6280 if (mac_reg & E1000_RCTL_PMCF)
6281 phy_reg |= BM_RCTL_PMCF;
6282 mac_reg = er32(CTRL);
6283 if (mac_reg & E1000_CTRL_RFCE)
6284 phy_reg |= BM_RCTL_RFCE;
6285 hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg);
6286
6287 wuc = E1000_WUC_PME_EN;
6288 if (wufc & (E1000_WUFC_MAG | E1000_WUFC_LNKC))
6289 wuc |= E1000_WUC_APME;
6290
6291 /* enable PHY wakeup in MAC register */
6292 ew32(WUFC, wufc);
6293 ew32(WUC, (E1000_WUC_PHY_WAKE | E1000_WUC_APMPME |
6294 E1000_WUC_PME_STATUS | wuc));
6295
6296 /* configure and enable PHY wakeup in PHY registers */
6297 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUFC, wufc);
6298 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUC, wuc);
6299
6300 /* activate PHY wakeup */
6301 wuc_enable |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
6302 retval = e1000_disable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
6303 if (retval)
6304 e_err("Could not set PHY Host Wakeup bit\n");
6305release:
6306 hw->phy.ops.release(hw);
6307
6308 return retval;
6309}
6310
6311static void e1000e_flush_lpic(struct pci_dev *pdev)
6312{
6313 struct net_device *netdev = pci_get_drvdata(pdev);
6314 struct e1000_adapter *adapter = netdev_priv(netdev);
6315 struct e1000_hw *hw = &adapter->hw;
6316 u32 ret_val;
6317
6318 pm_runtime_get_sync(netdev->dev.parent);
6319
6320 ret_val = hw->phy.ops.acquire(hw);
6321 if (ret_val)
6322 goto fl_out;
6323
6324 pr_info("EEE TX LPI TIMER: %08X\n",
6325 er32(LPIC) >> E1000_LPIC_LPIET_SHIFT);
6326
6327 hw->phy.ops.release(hw);
6328
6329fl_out:
6330 pm_runtime_put_sync(netdev->dev.parent);
6331}
6332
6333/* S0ix implementation */
6334static void e1000e_s0ix_entry_flow(struct e1000_adapter *adapter)
6335{
6336 struct e1000_hw *hw = &adapter->hw;
6337 u32 mac_data;
6338 u16 phy_data;
6339
6340 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID &&
6341 hw->mac.type >= e1000_pch_adp) {
6342 /* Request ME configure the device for S0ix */
6343 mac_data = er32(H2ME);
6344 mac_data |= E1000_H2ME_START_DPG;
6345 mac_data &= ~E1000_H2ME_EXIT_DPG;
6346 trace_e1000e_trace_mac_register(mac_data);
6347 ew32(H2ME, mac_data);
6348 } else {
6349 /* Request driver configure the device to S0ix */
6350 /* Disable the periodic inband message,
6351 * don't request PCIe clock in K1 page770_17[10:9] = 10b
6352 */
6353 e1e_rphy(hw, HV_PM_CTRL, &phy_data);
6354 phy_data &= ~HV_PM_CTRL_K1_CLK_REQ;
6355 phy_data |= BIT(10);
6356 e1e_wphy(hw, HV_PM_CTRL, phy_data);
6357
6358 /* Make sure we don't exit K1 every time a new packet arrives
6359 * 772_29[5] = 1 CS_Mode_Stay_In_K1
6360 */
6361 e1e_rphy(hw, I217_CGFREG, &phy_data);
6362 phy_data |= BIT(5);
6363 e1e_wphy(hw, I217_CGFREG, phy_data);
6364
6365 /* Change the MAC/PHY interface to SMBus
6366 * Force the SMBus in PHY page769_23[0] = 1
6367 * Force the SMBus in MAC CTRL_EXT[11] = 1
6368 */
6369 e1e_rphy(hw, CV_SMB_CTRL, &phy_data);
6370 phy_data |= CV_SMB_CTRL_FORCE_SMBUS;
6371 e1e_wphy(hw, CV_SMB_CTRL, phy_data);
6372 mac_data = er32(CTRL_EXT);
6373 mac_data |= E1000_CTRL_EXT_FORCE_SMBUS;
6374 ew32(CTRL_EXT, mac_data);
6375
6376 /* DFT control: PHY bit: page769_20[0] = 1
6377 * page769_20[7] - PHY PLL stop
6378 * page769_20[8] - PHY go to the electrical idle
6379 * page769_20[9] - PHY serdes disable
6380 * Gate PPW via EXTCNF_CTRL - set 0x0F00[7] = 1
6381 */
6382 e1e_rphy(hw, I82579_DFT_CTRL, &phy_data);
6383 phy_data |= BIT(0);
6384 phy_data |= BIT(7);
6385 phy_data |= BIT(8);
6386 phy_data |= BIT(9);
6387 e1e_wphy(hw, I82579_DFT_CTRL, phy_data);
6388
6389 mac_data = er32(EXTCNF_CTRL);
6390 mac_data |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
6391 ew32(EXTCNF_CTRL, mac_data);
6392
6393 /* Disable disconnected cable conditioning for Power Gating */
6394 mac_data = er32(DPGFR);
6395 mac_data |= BIT(2);
6396 ew32(DPGFR, mac_data);
6397
6398 /* Enable the Dynamic Clock Gating in the DMA and MAC */
6399 mac_data = er32(CTRL_EXT);
6400 mac_data |= E1000_CTRL_EXT_DMA_DYN_CLK_EN;
6401 ew32(CTRL_EXT, mac_data);
6402 }
6403
6404 /* Enable the Dynamic Power Gating in the MAC */
6405 mac_data = er32(FEXTNVM7);
6406 mac_data |= BIT(22);
6407 ew32(FEXTNVM7, mac_data);
6408
6409 /* Don't wake from dynamic Power Gating with clock request */
6410 mac_data = er32(FEXTNVM12);
6411 mac_data |= BIT(12);
6412 ew32(FEXTNVM12, mac_data);
6413
6414 /* Ungate PGCB clock */
6415 mac_data = er32(FEXTNVM9);
6416 mac_data &= ~BIT(28);
6417 ew32(FEXTNVM9, mac_data);
6418
6419 /* Enable K1 off to enable mPHY Power Gating */
6420 mac_data = er32(FEXTNVM6);
6421 mac_data |= BIT(31);
6422 ew32(FEXTNVM6, mac_data);
6423
6424 /* Enable mPHY power gating for any link and speed */
6425 mac_data = er32(FEXTNVM8);
6426 mac_data |= BIT(9);
6427 ew32(FEXTNVM8, mac_data);
6428
6429 /* No MAC DPG gating SLP_S0 in modern standby
6430 * Switch the logic of the lanphypc to use PMC counter
6431 */
6432 mac_data = er32(FEXTNVM5);
6433 mac_data |= BIT(7);
6434 ew32(FEXTNVM5, mac_data);
6435
6436 /* Disable the time synchronization clock */
6437 mac_data = er32(FEXTNVM7);
6438 mac_data |= BIT(31);
6439 mac_data &= ~BIT(0);
6440 ew32(FEXTNVM7, mac_data);
6441
6442 /* Dynamic Power Gating Enable */
6443 mac_data = er32(CTRL_EXT);
6444 mac_data |= BIT(3);
6445 ew32(CTRL_EXT, mac_data);
6446
6447 /* Check MAC Tx/Rx packet buffer pointers.
6448 * Reset MAC Tx/Rx packet buffer pointers to suppress any
6449 * pending traffic indication that would prevent power gating.
6450 */
6451 mac_data = er32(TDFH);
6452 if (mac_data)
6453 ew32(TDFH, 0);
6454 mac_data = er32(TDFT);
6455 if (mac_data)
6456 ew32(TDFT, 0);
6457 mac_data = er32(TDFHS);
6458 if (mac_data)
6459 ew32(TDFHS, 0);
6460 mac_data = er32(TDFTS);
6461 if (mac_data)
6462 ew32(TDFTS, 0);
6463 mac_data = er32(TDFPC);
6464 if (mac_data)
6465 ew32(TDFPC, 0);
6466 mac_data = er32(RDFH);
6467 if (mac_data)
6468 ew32(RDFH, 0);
6469 mac_data = er32(RDFT);
6470 if (mac_data)
6471 ew32(RDFT, 0);
6472 mac_data = er32(RDFHS);
6473 if (mac_data)
6474 ew32(RDFHS, 0);
6475 mac_data = er32(RDFTS);
6476 if (mac_data)
6477 ew32(RDFTS, 0);
6478 mac_data = er32(RDFPC);
6479 if (mac_data)
6480 ew32(RDFPC, 0);
6481}
6482
6483static void e1000e_s0ix_exit_flow(struct e1000_adapter *adapter)
6484{
6485 struct e1000_hw *hw = &adapter->hw;
6486 bool firmware_bug = false;
6487 u32 mac_data;
6488 u16 phy_data;
6489 u32 i = 0;
6490
6491 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID &&
6492 hw->mac.type >= e1000_pch_adp) {
6493 /* Keep the GPT clock enabled for CSME */
6494 mac_data = er32(FEXTNVM);
6495 mac_data |= BIT(3);
6496 ew32(FEXTNVM, mac_data);
6497 /* Request ME unconfigure the device from S0ix */
6498 mac_data = er32(H2ME);
6499 mac_data &= ~E1000_H2ME_START_DPG;
6500 mac_data |= E1000_H2ME_EXIT_DPG;
6501 trace_e1000e_trace_mac_register(mac_data);
6502 ew32(H2ME, mac_data);
6503
6504 /* Poll up to 2.5 seconds for ME to unconfigure DPG.
6505 * If this takes more than 1 second, show a warning indicating a
6506 * firmware bug
6507 */
6508 while (!(er32(EXFWSM) & E1000_EXFWSM_DPG_EXIT_DONE)) {
6509 if (i > 100 && !firmware_bug)
6510 firmware_bug = true;
6511
6512 if (i++ == 250) {
6513 e_dbg("Timeout (firmware bug): %d msec\n",
6514 i * 10);
6515 break;
6516 }
6517
6518 usleep_range(10000, 11000);
6519 }
6520 if (firmware_bug)
6521 e_warn("DPG_EXIT_DONE took %d msec. This is a firmware bug\n",
6522 i * 10);
6523 else
6524 e_dbg("DPG_EXIT_DONE cleared after %d msec\n", i * 10);
6525 } else {
6526 /* Request driver unconfigure the device from S0ix */
6527
6528 /* Cancel disable disconnected cable conditioning
6529 * for Power Gating
6530 */
6531 mac_data = er32(DPGFR);
6532 mac_data &= ~BIT(2);
6533 ew32(DPGFR, mac_data);
6534
6535 /* Disable the Dynamic Clock Gating in the DMA and MAC */
6536 mac_data = er32(CTRL_EXT);
6537 mac_data &= 0xFFF7FFFF;
6538 ew32(CTRL_EXT, mac_data);
6539
6540 /* Enable the periodic inband message,
6541 * Request PCIe clock in K1 page770_17[10:9] =01b
6542 */
6543 e1e_rphy(hw, HV_PM_CTRL, &phy_data);
6544 phy_data &= 0xFBFF;
6545 phy_data |= HV_PM_CTRL_K1_CLK_REQ;
6546 e1e_wphy(hw, HV_PM_CTRL, phy_data);
6547
6548 /* Return back configuration
6549 * 772_29[5] = 0 CS_Mode_Stay_In_K1
6550 */
6551 e1e_rphy(hw, I217_CGFREG, &phy_data);
6552 phy_data &= 0xFFDF;
6553 e1e_wphy(hw, I217_CGFREG, phy_data);
6554
6555 /* Change the MAC/PHY interface to Kumeran
6556 * Unforce the SMBus in PHY page769_23[0] = 0
6557 * Unforce the SMBus in MAC CTRL_EXT[11] = 0
6558 */
6559 e1e_rphy(hw, CV_SMB_CTRL, &phy_data);
6560 phy_data &= ~CV_SMB_CTRL_FORCE_SMBUS;
6561 e1e_wphy(hw, CV_SMB_CTRL, phy_data);
6562 mac_data = er32(CTRL_EXT);
6563 mac_data &= ~E1000_CTRL_EXT_FORCE_SMBUS;
6564 ew32(CTRL_EXT, mac_data);
6565 }
6566
6567 /* Disable Dynamic Power Gating */
6568 mac_data = er32(CTRL_EXT);
6569 mac_data &= 0xFFFFFFF7;
6570 ew32(CTRL_EXT, mac_data);
6571
6572 /* Enable the time synchronization clock */
6573 mac_data = er32(FEXTNVM7);
6574 mac_data &= ~BIT(31);
6575 mac_data |= BIT(0);
6576 ew32(FEXTNVM7, mac_data);
6577
6578 /* Disable the Dynamic Power Gating in the MAC */
6579 mac_data = er32(FEXTNVM7);
6580 mac_data &= 0xFFBFFFFF;
6581 ew32(FEXTNVM7, mac_data);
6582
6583 /* Disable mPHY power gating for any link and speed */
6584 mac_data = er32(FEXTNVM8);
6585 mac_data &= ~BIT(9);
6586 ew32(FEXTNVM8, mac_data);
6587
6588 /* Disable K1 off */
6589 mac_data = er32(FEXTNVM6);
6590 mac_data &= ~BIT(31);
6591 ew32(FEXTNVM6, mac_data);
6592
6593 /* Disable Ungate PGCB clock */
6594 mac_data = er32(FEXTNVM9);
6595 mac_data |= BIT(28);
6596 ew32(FEXTNVM9, mac_data);
6597
6598 /* Cancel not waking from dynamic
6599 * Power Gating with clock request
6600 */
6601 mac_data = er32(FEXTNVM12);
6602 mac_data &= ~BIT(12);
6603 ew32(FEXTNVM12, mac_data);
6604
6605 /* Revert the lanphypc logic to use the internal Gbe counter
6606 * and not the PMC counter
6607 */
6608 mac_data = er32(FEXTNVM5);
6609 mac_data &= 0xFFFFFF7F;
6610 ew32(FEXTNVM5, mac_data);
6611}
6612
6613static int e1000e_pm_freeze(struct device *dev)
6614{
6615 struct net_device *netdev = dev_get_drvdata(dev);
6616 struct e1000_adapter *adapter = netdev_priv(netdev);
6617 bool present;
6618
6619 rtnl_lock();
6620
6621 present = netif_device_present(netdev);
6622 netif_device_detach(netdev);
6623
6624 if (present && netif_running(netdev)) {
6625 int count = E1000_CHECK_RESET_COUNT;
6626
6627 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
6628 usleep_range(10000, 11000);
6629
6630 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
6631
6632 /* Quiesce the device without resetting the hardware */
6633 e1000e_down(adapter, false);
6634 e1000_free_irq(adapter);
6635 }
6636 rtnl_unlock();
6637
6638 e1000e_reset_interrupt_capability(adapter);
6639
6640 /* Allow time for pending master requests to run */
6641 e1000e_disable_pcie_master(&adapter->hw);
6642
6643 return 0;
6644}
6645
6646static int __e1000_shutdown(struct pci_dev *pdev, bool runtime)
6647{
6648 struct net_device *netdev = pci_get_drvdata(pdev);
6649 struct e1000_adapter *adapter = netdev_priv(netdev);
6650 struct e1000_hw *hw = &adapter->hw;
6651 u32 ctrl, ctrl_ext, rctl, status, wufc;
6652 int retval = 0;
6653
6654 /* Runtime suspend should only enable wakeup for link changes */
6655 if (runtime)
6656 wufc = E1000_WUFC_LNKC;
6657 else if (device_may_wakeup(&pdev->dev))
6658 wufc = adapter->wol;
6659 else
6660 wufc = 0;
6661
6662 status = er32(STATUS);
6663 if (status & E1000_STATUS_LU)
6664 wufc &= ~E1000_WUFC_LNKC;
6665
6666 if (wufc) {
6667 e1000_setup_rctl(adapter);
6668 e1000e_set_rx_mode(netdev);
6669
6670 /* turn on all-multi mode if wake on multicast is enabled */
6671 if (wufc & E1000_WUFC_MC) {
6672 rctl = er32(RCTL);
6673 rctl |= E1000_RCTL_MPE;
6674 ew32(RCTL, rctl);
6675 }
6676
6677 ctrl = er32(CTRL);
6678 ctrl |= E1000_CTRL_ADVD3WUC;
6679 if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP))
6680 ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT;
6681 ew32(CTRL, ctrl);
6682
6683 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
6684 adapter->hw.phy.media_type ==
6685 e1000_media_type_internal_serdes) {
6686 /* keep the laser running in D3 */
6687 ctrl_ext = er32(CTRL_EXT);
6688 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
6689 ew32(CTRL_EXT, ctrl_ext);
6690 }
6691
6692 if (!runtime)
6693 e1000e_power_up_phy(adapter);
6694
6695 if (adapter->flags & FLAG_IS_ICH)
6696 e1000_suspend_workarounds_ich8lan(&adapter->hw);
6697
6698 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
6699 /* enable wakeup by the PHY */
6700 retval = e1000_init_phy_wakeup(adapter, wufc);
6701 if (retval) {
6702 e_err("Failed to enable wakeup\n");
6703 goto skip_phy_configurations;
6704 }
6705 } else {
6706 /* enable wakeup by the MAC */
6707 ew32(WUFC, wufc);
6708 ew32(WUC, E1000_WUC_PME_EN);
6709 }
6710 } else {
6711 ew32(WUC, 0);
6712 ew32(WUFC, 0);
6713
6714 e1000_power_down_phy(adapter);
6715 }
6716
6717 if (adapter->hw.phy.type == e1000_phy_igp_3) {
6718 e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
6719 } else if (hw->mac.type >= e1000_pch_lpt) {
6720 if (wufc && !(wufc & (E1000_WUFC_EX | E1000_WUFC_MC | E1000_WUFC_BC))) {
6721 /* ULP does not support wake from unicast, multicast
6722 * or broadcast.
6723 */
6724 retval = e1000_enable_ulp_lpt_lp(hw, !runtime);
6725 if (retval) {
6726 e_err("Failed to enable ULP\n");
6727 goto skip_phy_configurations;
6728 }
6729 }
6730 }
6731
6732 /* Ensure that the appropriate bits are set in LPI_CTRL
6733 * for EEE in Sx
6734 */
6735 if ((hw->phy.type >= e1000_phy_i217) &&
6736 adapter->eee_advert && hw->dev_spec.ich8lan.eee_lp_ability) {
6737 u16 lpi_ctrl = 0;
6738
6739 retval = hw->phy.ops.acquire(hw);
6740 if (!retval) {
6741 retval = e1e_rphy_locked(hw, I82579_LPI_CTRL,
6742 &lpi_ctrl);
6743 if (!retval) {
6744 if (adapter->eee_advert &
6745 hw->dev_spec.ich8lan.eee_lp_ability &
6746 I82579_EEE_100_SUPPORTED)
6747 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
6748 if (adapter->eee_advert &
6749 hw->dev_spec.ich8lan.eee_lp_ability &
6750 I82579_EEE_1000_SUPPORTED)
6751 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
6752
6753 retval = e1e_wphy_locked(hw, I82579_LPI_CTRL,
6754 lpi_ctrl);
6755 }
6756 }
6757 hw->phy.ops.release(hw);
6758 }
6759
6760skip_phy_configurations:
6761 /* Release control of h/w to f/w. If f/w is AMT enabled, this
6762 * would have already happened in close and is redundant.
6763 */
6764 e1000e_release_hw_control(adapter);
6765
6766 pci_clear_master(pdev);
6767
6768 /* The pci-e switch on some quad port adapters will report a
6769 * correctable error when the MAC transitions from D0 to D3. To
6770 * prevent this we need to mask off the correctable errors on the
6771 * downstream port of the pci-e switch.
6772 *
6773 * We don't have the associated upstream bridge while assigning
6774 * the PCI device into guest. For example, the KVM on power is
6775 * one of the cases.
6776 */
6777 if (adapter->flags & FLAG_IS_QUAD_PORT) {
6778 struct pci_dev *us_dev = pdev->bus->self;
6779 u16 devctl;
6780
6781 if (!us_dev)
6782 return 0;
6783
6784 pcie_capability_read_word(us_dev, PCI_EXP_DEVCTL, &devctl);
6785 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL,
6786 (devctl & ~PCI_EXP_DEVCTL_CERE));
6787
6788 pci_save_state(pdev);
6789 pci_prepare_to_sleep(pdev);
6790
6791 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, devctl);
6792 }
6793
6794 return 0;
6795}
6796
6797/**
6798 * __e1000e_disable_aspm - Disable ASPM states
6799 * @pdev: pointer to PCI device struct
6800 * @state: bit-mask of ASPM states to disable
6801 * @locked: indication if this context holds pci_bus_sem locked.
6802 *
6803 * Some devices *must* have certain ASPM states disabled per hardware errata.
6804 **/
6805static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state, int locked)
6806{
6807 struct pci_dev *parent = pdev->bus->self;
6808 u16 aspm_dis_mask = 0;
6809 u16 pdev_aspmc, parent_aspmc;
6810
6811 switch (state) {
6812 case PCIE_LINK_STATE_L0S:
6813 case PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1:
6814 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L0S;
6815 fallthrough; /* can't have L1 without L0s */
6816 case PCIE_LINK_STATE_L1:
6817 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L1;
6818 break;
6819 default:
6820 return;
6821 }
6822
6823 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc);
6824 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6825
6826 if (parent) {
6827 pcie_capability_read_word(parent, PCI_EXP_LNKCTL,
6828 &parent_aspmc);
6829 parent_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6830 }
6831
6832 /* Nothing to do if the ASPM states to be disabled already are */
6833 if (!(pdev_aspmc & aspm_dis_mask) &&
6834 (!parent || !(parent_aspmc & aspm_dis_mask)))
6835 return;
6836
6837 dev_info(&pdev->dev, "Disabling ASPM %s %s\n",
6838 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L0S) ?
6839 "L0s" : "",
6840 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L1) ?
6841 "L1" : "");
6842
6843#ifdef CONFIG_PCIEASPM
6844 if (locked)
6845 pci_disable_link_state_locked(pdev, state);
6846 else
6847 pci_disable_link_state(pdev, state);
6848
6849 /* Double-check ASPM control. If not disabled by the above, the
6850 * BIOS is preventing that from happening (or CONFIG_PCIEASPM is
6851 * not enabled); override by writing PCI config space directly.
6852 */
6853 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc);
6854 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6855
6856 if (!(aspm_dis_mask & pdev_aspmc))
6857 return;
6858#endif
6859
6860 /* Both device and parent should have the same ASPM setting.
6861 * Disable ASPM in downstream component first and then upstream.
6862 */
6863 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, aspm_dis_mask);
6864
6865 if (parent)
6866 pcie_capability_clear_word(parent, PCI_EXP_LNKCTL,
6867 aspm_dis_mask);
6868}
6869
6870/**
6871 * e1000e_disable_aspm - Disable ASPM states.
6872 * @pdev: pointer to PCI device struct
6873 * @state: bit-mask of ASPM states to disable
6874 *
6875 * This function acquires the pci_bus_sem!
6876 * Some devices *must* have certain ASPM states disabled per hardware errata.
6877 **/
6878static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
6879{
6880 __e1000e_disable_aspm(pdev, state, 0);
6881}
6882
6883/**
6884 * e1000e_disable_aspm_locked - Disable ASPM states.
6885 * @pdev: pointer to PCI device struct
6886 * @state: bit-mask of ASPM states to disable
6887 *
6888 * This function must be called with pci_bus_sem acquired!
6889 * Some devices *must* have certain ASPM states disabled per hardware errata.
6890 **/
6891static void e1000e_disable_aspm_locked(struct pci_dev *pdev, u16 state)
6892{
6893 __e1000e_disable_aspm(pdev, state, 1);
6894}
6895
6896static int e1000e_pm_thaw(struct device *dev)
6897{
6898 struct net_device *netdev = dev_get_drvdata(dev);
6899 struct e1000_adapter *adapter = netdev_priv(netdev);
6900 int rc = 0;
6901
6902 e1000e_set_interrupt_capability(adapter);
6903
6904 rtnl_lock();
6905 if (netif_running(netdev)) {
6906 rc = e1000_request_irq(adapter);
6907 if (rc)
6908 goto err_irq;
6909
6910 e1000e_up(adapter);
6911 }
6912
6913 netif_device_attach(netdev);
6914err_irq:
6915 rtnl_unlock();
6916
6917 return rc;
6918}
6919
6920static int __e1000_resume(struct pci_dev *pdev)
6921{
6922 struct net_device *netdev = pci_get_drvdata(pdev);
6923 struct e1000_adapter *adapter = netdev_priv(netdev);
6924 struct e1000_hw *hw = &adapter->hw;
6925 u16 aspm_disable_flag = 0;
6926
6927 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
6928 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6929 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
6930 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6931 if (aspm_disable_flag)
6932 e1000e_disable_aspm(pdev, aspm_disable_flag);
6933
6934 pci_set_master(pdev);
6935
6936 if (hw->mac.type >= e1000_pch2lan)
6937 e1000_resume_workarounds_pchlan(&adapter->hw);
6938
6939 e1000e_power_up_phy(adapter);
6940
6941 /* report the system wakeup cause from S3/S4 */
6942 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
6943 u16 phy_data;
6944
6945 e1e_rphy(&adapter->hw, BM_WUS, &phy_data);
6946 if (phy_data) {
6947 e_info("PHY Wakeup cause - %s\n",
6948 phy_data & E1000_WUS_EX ? "Unicast Packet" :
6949 phy_data & E1000_WUS_MC ? "Multicast Packet" :
6950 phy_data & E1000_WUS_BC ? "Broadcast Packet" :
6951 phy_data & E1000_WUS_MAG ? "Magic Packet" :
6952 phy_data & E1000_WUS_LNKC ?
6953 "Link Status Change" : "other");
6954 }
6955 e1e_wphy(&adapter->hw, BM_WUS, ~0);
6956 } else {
6957 u32 wus = er32(WUS);
6958
6959 if (wus) {
6960 e_info("MAC Wakeup cause - %s\n",
6961 wus & E1000_WUS_EX ? "Unicast Packet" :
6962 wus & E1000_WUS_MC ? "Multicast Packet" :
6963 wus & E1000_WUS_BC ? "Broadcast Packet" :
6964 wus & E1000_WUS_MAG ? "Magic Packet" :
6965 wus & E1000_WUS_LNKC ? "Link Status Change" :
6966 "other");
6967 }
6968 ew32(WUS, ~0);
6969 }
6970
6971 e1000e_reset(adapter);
6972
6973 e1000_init_manageability_pt(adapter);
6974
6975 /* If the controller has AMT, do not set DRV_LOAD until the interface
6976 * is up. For all other cases, let the f/w know that the h/w is now
6977 * under the control of the driver.
6978 */
6979 if (!(adapter->flags & FLAG_HAS_AMT))
6980 e1000e_get_hw_control(adapter);
6981
6982 return 0;
6983}
6984
6985static int e1000e_pm_prepare(struct device *dev)
6986{
6987 return pm_runtime_suspended(dev) &&
6988 pm_suspend_via_firmware();
6989}
6990
6991static int e1000e_pm_suspend(struct device *dev)
6992{
6993 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev));
6994 struct e1000_adapter *adapter = netdev_priv(netdev);
6995 struct pci_dev *pdev = to_pci_dev(dev);
6996 int rc;
6997
6998 e1000e_flush_lpic(pdev);
6999
7000 e1000e_pm_freeze(dev);
7001
7002 rc = __e1000_shutdown(pdev, false);
7003 if (!rc) {
7004 /* Introduce S0ix implementation */
7005 if (adapter->flags2 & FLAG2_ENABLE_S0IX_FLOWS)
7006 e1000e_s0ix_entry_flow(adapter);
7007 }
7008
7009 return 0;
7010}
7011
7012static int e1000e_pm_resume(struct device *dev)
7013{
7014 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev));
7015 struct e1000_adapter *adapter = netdev_priv(netdev);
7016 struct pci_dev *pdev = to_pci_dev(dev);
7017 int rc;
7018
7019 /* Introduce S0ix implementation */
7020 if (adapter->flags2 & FLAG2_ENABLE_S0IX_FLOWS)
7021 e1000e_s0ix_exit_flow(adapter);
7022
7023 rc = __e1000_resume(pdev);
7024 if (rc)
7025 return rc;
7026
7027 return e1000e_pm_thaw(dev);
7028}
7029
7030static __maybe_unused int e1000e_pm_runtime_idle(struct device *dev)
7031{
7032 struct net_device *netdev = dev_get_drvdata(dev);
7033 struct e1000_adapter *adapter = netdev_priv(netdev);
7034 u16 eee_lp;
7035
7036 eee_lp = adapter->hw.dev_spec.ich8lan.eee_lp_ability;
7037
7038 if (!e1000e_has_link(adapter)) {
7039 adapter->hw.dev_spec.ich8lan.eee_lp_ability = eee_lp;
7040 pm_schedule_suspend(dev, 5 * MSEC_PER_SEC);
7041 }
7042
7043 return -EBUSY;
7044}
7045
7046static int e1000e_pm_runtime_resume(struct device *dev)
7047{
7048 struct pci_dev *pdev = to_pci_dev(dev);
7049 struct net_device *netdev = pci_get_drvdata(pdev);
7050 struct e1000_adapter *adapter = netdev_priv(netdev);
7051 int rc;
7052
7053 pdev->pme_poll = true;
7054
7055 rc = __e1000_resume(pdev);
7056 if (rc)
7057 return rc;
7058
7059 if (netdev->flags & IFF_UP)
7060 e1000e_up(adapter);
7061
7062 return rc;
7063}
7064
7065static int e1000e_pm_runtime_suspend(struct device *dev)
7066{
7067 struct pci_dev *pdev = to_pci_dev(dev);
7068 struct net_device *netdev = pci_get_drvdata(pdev);
7069 struct e1000_adapter *adapter = netdev_priv(netdev);
7070
7071 if (netdev->flags & IFF_UP) {
7072 int count = E1000_CHECK_RESET_COUNT;
7073
7074 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
7075 usleep_range(10000, 11000);
7076
7077 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
7078
7079 /* Down the device without resetting the hardware */
7080 e1000e_down(adapter, false);
7081 }
7082
7083 if (__e1000_shutdown(pdev, true)) {
7084 e1000e_pm_runtime_resume(dev);
7085 return -EBUSY;
7086 }
7087
7088 return 0;
7089}
7090
7091static void e1000_shutdown(struct pci_dev *pdev)
7092{
7093 e1000e_flush_lpic(pdev);
7094
7095 e1000e_pm_freeze(&pdev->dev);
7096
7097 __e1000_shutdown(pdev, false);
7098}
7099
7100#ifdef CONFIG_NET_POLL_CONTROLLER
7101
7102static irqreturn_t e1000_intr_msix(int __always_unused irq, void *data)
7103{
7104 struct net_device *netdev = data;
7105 struct e1000_adapter *adapter = netdev_priv(netdev);
7106
7107 if (adapter->msix_entries) {
7108 int vector, msix_irq;
7109
7110 vector = 0;
7111 msix_irq = adapter->msix_entries[vector].vector;
7112 if (disable_hardirq(msix_irq))
7113 e1000_intr_msix_rx(msix_irq, netdev);
7114 enable_irq(msix_irq);
7115
7116 vector++;
7117 msix_irq = adapter->msix_entries[vector].vector;
7118 if (disable_hardirq(msix_irq))
7119 e1000_intr_msix_tx(msix_irq, netdev);
7120 enable_irq(msix_irq);
7121
7122 vector++;
7123 msix_irq = adapter->msix_entries[vector].vector;
7124 if (disable_hardirq(msix_irq))
7125 e1000_msix_other(msix_irq, netdev);
7126 enable_irq(msix_irq);
7127 }
7128
7129 return IRQ_HANDLED;
7130}
7131
7132/**
7133 * e1000_netpoll
7134 * @netdev: network interface device structure
7135 *
7136 * Polling 'interrupt' - used by things like netconsole to send skbs
7137 * without having to re-enable interrupts. It's not called while
7138 * the interrupt routine is executing.
7139 */
7140static void e1000_netpoll(struct net_device *netdev)
7141{
7142 struct e1000_adapter *adapter = netdev_priv(netdev);
7143
7144 switch (adapter->int_mode) {
7145 case E1000E_INT_MODE_MSIX:
7146 e1000_intr_msix(adapter->pdev->irq, netdev);
7147 break;
7148 case E1000E_INT_MODE_MSI:
7149 if (disable_hardirq(adapter->pdev->irq))
7150 e1000_intr_msi(adapter->pdev->irq, netdev);
7151 enable_irq(adapter->pdev->irq);
7152 break;
7153 default: /* E1000E_INT_MODE_LEGACY */
7154 if (disable_hardirq(adapter->pdev->irq))
7155 e1000_intr(adapter->pdev->irq, netdev);
7156 enable_irq(adapter->pdev->irq);
7157 break;
7158 }
7159}
7160#endif
7161
7162/**
7163 * e1000_io_error_detected - called when PCI error is detected
7164 * @pdev: Pointer to PCI device
7165 * @state: The current pci connection state
7166 *
7167 * This function is called after a PCI bus error affecting
7168 * this device has been detected.
7169 */
7170static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev,
7171 pci_channel_state_t state)
7172{
7173 e1000e_pm_freeze(&pdev->dev);
7174
7175 if (state == pci_channel_io_perm_failure)
7176 return PCI_ERS_RESULT_DISCONNECT;
7177
7178 pci_disable_device(pdev);
7179
7180 /* Request a slot reset. */
7181 return PCI_ERS_RESULT_NEED_RESET;
7182}
7183
7184/**
7185 * e1000_io_slot_reset - called after the pci bus has been reset.
7186 * @pdev: Pointer to PCI device
7187 *
7188 * Restart the card from scratch, as if from a cold-boot. Implementation
7189 * resembles the first-half of the e1000e_pm_resume routine.
7190 */
7191static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev)
7192{
7193 struct net_device *netdev = pci_get_drvdata(pdev);
7194 struct e1000_adapter *adapter = netdev_priv(netdev);
7195 struct e1000_hw *hw = &adapter->hw;
7196 u16 aspm_disable_flag = 0;
7197 int err;
7198 pci_ers_result_t result;
7199
7200 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
7201 aspm_disable_flag = PCIE_LINK_STATE_L0S;
7202 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
7203 aspm_disable_flag |= PCIE_LINK_STATE_L1;
7204 if (aspm_disable_flag)
7205 e1000e_disable_aspm_locked(pdev, aspm_disable_flag);
7206
7207 err = pci_enable_device_mem(pdev);
7208 if (err) {
7209 dev_err(&pdev->dev,
7210 "Cannot re-enable PCI device after reset.\n");
7211 result = PCI_ERS_RESULT_DISCONNECT;
7212 } else {
7213 pci_restore_state(pdev);
7214 pci_set_master(pdev);
7215
7216 pci_enable_wake(pdev, PCI_D3hot, 0);
7217 pci_enable_wake(pdev, PCI_D3cold, 0);
7218
7219 e1000e_reset(adapter);
7220 ew32(WUS, ~0);
7221 result = PCI_ERS_RESULT_RECOVERED;
7222 }
7223
7224 return result;
7225}
7226
7227/**
7228 * e1000_io_resume - called when traffic can start flowing again.
7229 * @pdev: Pointer to PCI device
7230 *
7231 * This callback is called when the error recovery driver tells us that
7232 * its OK to resume normal operation. Implementation resembles the
7233 * second-half of the e1000e_pm_resume routine.
7234 */
7235static void e1000_io_resume(struct pci_dev *pdev)
7236{
7237 struct net_device *netdev = pci_get_drvdata(pdev);
7238 struct e1000_adapter *adapter = netdev_priv(netdev);
7239
7240 e1000_init_manageability_pt(adapter);
7241
7242 e1000e_pm_thaw(&pdev->dev);
7243
7244 /* If the controller has AMT, do not set DRV_LOAD until the interface
7245 * is up. For all other cases, let the f/w know that the h/w is now
7246 * under the control of the driver.
7247 */
7248 if (!(adapter->flags & FLAG_HAS_AMT))
7249 e1000e_get_hw_control(adapter);
7250}
7251
7252static void e1000_print_device_info(struct e1000_adapter *adapter)
7253{
7254 struct e1000_hw *hw = &adapter->hw;
7255 struct net_device *netdev = adapter->netdev;
7256 u32 ret_val;
7257 u8 pba_str[E1000_PBANUM_LENGTH];
7258
7259 /* print bus type/speed/width info */
7260 e_info("(PCI Express:2.5GT/s:%s) %pM\n",
7261 /* bus width */
7262 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
7263 "Width x1"),
7264 /* MAC address */
7265 netdev->dev_addr);
7266 e_info("Intel(R) PRO/%s Network Connection\n",
7267 (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000");
7268 ret_val = e1000_read_pba_string_generic(hw, pba_str,
7269 E1000_PBANUM_LENGTH);
7270 if (ret_val)
7271 strscpy((char *)pba_str, "Unknown", sizeof(pba_str));
7272 e_info("MAC: %d, PHY: %d, PBA No: %s\n",
7273 hw->mac.type, hw->phy.type, pba_str);
7274}
7275
7276static void e1000_eeprom_checks(struct e1000_adapter *adapter)
7277{
7278 struct e1000_hw *hw = &adapter->hw;
7279 int ret_val;
7280 u16 buf = 0;
7281
7282 if (hw->mac.type != e1000_82573)
7283 return;
7284
7285 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf);
7286 le16_to_cpus(&buf);
7287 if (!ret_val && (!(buf & BIT(0)))) {
7288 /* Deep Smart Power Down (DSPD) */
7289 dev_warn(&adapter->pdev->dev,
7290 "Warning: detected DSPD enabled in EEPROM\n");
7291 }
7292}
7293
7294static netdev_features_t e1000_fix_features(struct net_device *netdev,
7295 netdev_features_t features)
7296{
7297 struct e1000_adapter *adapter = netdev_priv(netdev);
7298 struct e1000_hw *hw = &adapter->hw;
7299
7300 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
7301 if ((hw->mac.type >= e1000_pch2lan) && (netdev->mtu > ETH_DATA_LEN))
7302 features &= ~NETIF_F_RXFCS;
7303
7304 /* Since there is no support for separate Rx/Tx vlan accel
7305 * enable/disable make sure Tx flag is always in same state as Rx.
7306 */
7307 if (features & NETIF_F_HW_VLAN_CTAG_RX)
7308 features |= NETIF_F_HW_VLAN_CTAG_TX;
7309 else
7310 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
7311
7312 return features;
7313}
7314
7315static int e1000_set_features(struct net_device *netdev,
7316 netdev_features_t features)
7317{
7318 struct e1000_adapter *adapter = netdev_priv(netdev);
7319 netdev_features_t changed = features ^ netdev->features;
7320
7321 if (changed & (NETIF_F_TSO | NETIF_F_TSO6))
7322 adapter->flags |= FLAG_TSO_FORCE;
7323
7324 if (!(changed & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
7325 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_RXFCS |
7326 NETIF_F_RXALL)))
7327 return 0;
7328
7329 if (changed & NETIF_F_RXFCS) {
7330 if (features & NETIF_F_RXFCS) {
7331 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
7332 } else {
7333 /* We need to take it back to defaults, which might mean
7334 * stripping is still disabled at the adapter level.
7335 */
7336 if (adapter->flags2 & FLAG2_DFLT_CRC_STRIPPING)
7337 adapter->flags2 |= FLAG2_CRC_STRIPPING;
7338 else
7339 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
7340 }
7341 }
7342
7343 netdev->features = features;
7344
7345 if (netif_running(netdev))
7346 e1000e_reinit_locked(adapter);
7347 else
7348 e1000e_reset(adapter);
7349
7350 return 1;
7351}
7352
7353static const struct net_device_ops e1000e_netdev_ops = {
7354 .ndo_open = e1000e_open,
7355 .ndo_stop = e1000e_close,
7356 .ndo_start_xmit = e1000_xmit_frame,
7357 .ndo_get_stats64 = e1000e_get_stats64,
7358 .ndo_set_rx_mode = e1000e_set_rx_mode,
7359 .ndo_set_mac_address = e1000_set_mac,
7360 .ndo_change_mtu = e1000_change_mtu,
7361 .ndo_eth_ioctl = e1000_ioctl,
7362 .ndo_tx_timeout = e1000_tx_timeout,
7363 .ndo_validate_addr = eth_validate_addr,
7364
7365 .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid,
7366 .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid,
7367#ifdef CONFIG_NET_POLL_CONTROLLER
7368 .ndo_poll_controller = e1000_netpoll,
7369#endif
7370 .ndo_set_features = e1000_set_features,
7371 .ndo_fix_features = e1000_fix_features,
7372 .ndo_features_check = passthru_features_check,
7373 .ndo_hwtstamp_get = e1000e_hwtstamp_get,
7374 .ndo_hwtstamp_set = e1000e_hwtstamp_set,
7375};
7376
7377/**
7378 * e1000_probe - Device Initialization Routine
7379 * @pdev: PCI device information struct
7380 * @ent: entry in e1000_pci_tbl
7381 *
7382 * Returns 0 on success, negative on failure
7383 *
7384 * e1000_probe initializes an adapter identified by a pci_dev structure.
7385 * The OS initialization, configuring of the adapter private structure,
7386 * and a hardware reset occur.
7387 **/
7388static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
7389{
7390 struct net_device *netdev;
7391 struct e1000_adapter *adapter;
7392 struct e1000_hw *hw;
7393 const struct e1000_info *ei = e1000_info_tbl[ent->driver_data];
7394 resource_size_t mmio_start, mmio_len;
7395 resource_size_t flash_start, flash_len;
7396 static int cards_found;
7397 u16 aspm_disable_flag = 0;
7398 u16 eeprom_data = 0;
7399 u16 eeprom_apme_mask = E1000_EEPROM_APME;
7400 int bars, i, err;
7401 s32 ret_val = 0;
7402
7403 if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S)
7404 aspm_disable_flag = PCIE_LINK_STATE_L0S;
7405 if (ei->flags2 & FLAG2_DISABLE_ASPM_L1)
7406 aspm_disable_flag |= PCIE_LINK_STATE_L1;
7407 if (aspm_disable_flag)
7408 e1000e_disable_aspm(pdev, aspm_disable_flag);
7409
7410 err = pci_enable_device_mem(pdev);
7411 if (err)
7412 return err;
7413
7414 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
7415 if (err) {
7416 dev_err(&pdev->dev,
7417 "No usable DMA configuration, aborting\n");
7418 goto err_dma;
7419 }
7420
7421 bars = pci_select_bars(pdev, IORESOURCE_MEM);
7422 err = pci_request_selected_regions_exclusive(pdev, bars,
7423 e1000e_driver_name);
7424 if (err)
7425 goto err_pci_reg;
7426
7427 pci_set_master(pdev);
7428 /* PCI config space info */
7429 err = pci_save_state(pdev);
7430 if (err)
7431 goto err_alloc_etherdev;
7432
7433 err = -ENOMEM;
7434 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
7435 if (!netdev)
7436 goto err_alloc_etherdev;
7437
7438 SET_NETDEV_DEV(netdev, &pdev->dev);
7439
7440 netdev->irq = pdev->irq;
7441
7442 pci_set_drvdata(pdev, netdev);
7443 adapter = netdev_priv(netdev);
7444 hw = &adapter->hw;
7445 adapter->netdev = netdev;
7446 adapter->pdev = pdev;
7447 adapter->ei = ei;
7448 adapter->pba = ei->pba;
7449 adapter->flags = ei->flags;
7450 adapter->flags2 = ei->flags2;
7451 adapter->hw.adapter = adapter;
7452 adapter->hw.mac.type = ei->mac;
7453 adapter->max_hw_frame_size = ei->max_hw_frame_size;
7454 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
7455
7456 mmio_start = pci_resource_start(pdev, 0);
7457 mmio_len = pci_resource_len(pdev, 0);
7458
7459 err = -EIO;
7460 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
7461 if (!adapter->hw.hw_addr)
7462 goto err_ioremap;
7463
7464 if ((adapter->flags & FLAG_HAS_FLASH) &&
7465 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM) &&
7466 (hw->mac.type < e1000_pch_spt)) {
7467 flash_start = pci_resource_start(pdev, 1);
7468 flash_len = pci_resource_len(pdev, 1);
7469 adapter->hw.flash_address = ioremap(flash_start, flash_len);
7470 if (!adapter->hw.flash_address)
7471 goto err_flashmap;
7472 }
7473
7474 /* Set default EEE advertisement */
7475 if (adapter->flags2 & FLAG2_HAS_EEE)
7476 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
7477
7478 /* construct the net_device struct */
7479 netdev->netdev_ops = &e1000e_netdev_ops;
7480 e1000e_set_ethtool_ops(netdev);
7481 netdev->watchdog_timeo = 5 * HZ;
7482 netif_napi_add(netdev, &adapter->napi, e1000e_poll);
7483 strscpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
7484
7485 netdev->mem_start = mmio_start;
7486 netdev->mem_end = mmio_start + mmio_len;
7487
7488 adapter->bd_number = cards_found++;
7489
7490 e1000e_check_options(adapter);
7491
7492 /* setup adapter struct */
7493 err = e1000_sw_init(adapter);
7494 if (err)
7495 goto err_sw_init;
7496
7497 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
7498 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
7499 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
7500
7501 err = ei->get_variants(adapter);
7502 if (err)
7503 goto err_hw_init;
7504
7505 if ((adapter->flags & FLAG_IS_ICH) &&
7506 (adapter->flags & FLAG_READ_ONLY_NVM) &&
7507 (hw->mac.type < e1000_pch_spt))
7508 e1000e_write_protect_nvm_ich8lan(&adapter->hw);
7509
7510 hw->mac.ops.get_bus_info(&adapter->hw);
7511
7512 adapter->hw.phy.autoneg_wait_to_complete = 0;
7513
7514 /* Copper options */
7515 if (adapter->hw.phy.media_type == e1000_media_type_copper) {
7516 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7517 adapter->hw.phy.disable_polarity_correction = 0;
7518 adapter->hw.phy.ms_type = e1000_ms_hw_default;
7519 }
7520
7521 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
7522 dev_info(&pdev->dev,
7523 "PHY reset is blocked due to SOL/IDER session.\n");
7524
7525 /* Set initial default active device features */
7526 netdev->features = (NETIF_F_SG |
7527 NETIF_F_HW_VLAN_CTAG_RX |
7528 NETIF_F_HW_VLAN_CTAG_TX |
7529 NETIF_F_TSO |
7530 NETIF_F_TSO6 |
7531 NETIF_F_RXHASH |
7532 NETIF_F_RXCSUM |
7533 NETIF_F_HW_CSUM);
7534
7535 /* disable TSO for pcie and 10/100 speeds to avoid
7536 * some hardware issues and for i219 to fix transfer
7537 * speed being capped at 60%
7538 */
7539 if (!(adapter->flags & FLAG_TSO_FORCE)) {
7540 switch (adapter->link_speed) {
7541 case SPEED_10:
7542 case SPEED_100:
7543 e_info("10/100 speed: disabling TSO\n");
7544 netdev->features &= ~NETIF_F_TSO;
7545 netdev->features &= ~NETIF_F_TSO6;
7546 break;
7547 case SPEED_1000:
7548 netdev->features |= NETIF_F_TSO;
7549 netdev->features |= NETIF_F_TSO6;
7550 break;
7551 default:
7552 /* oops */
7553 break;
7554 }
7555 if (hw->mac.type == e1000_pch_spt) {
7556 netdev->features &= ~NETIF_F_TSO;
7557 netdev->features &= ~NETIF_F_TSO6;
7558 }
7559 }
7560
7561 /* Set user-changeable features (subset of all device features) */
7562 netdev->hw_features = netdev->features;
7563 netdev->hw_features |= NETIF_F_RXFCS;
7564 netdev->priv_flags |= IFF_SUPP_NOFCS;
7565 netdev->hw_features |= NETIF_F_RXALL;
7566
7567 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER)
7568 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
7569
7570 netdev->vlan_features |= (NETIF_F_SG |
7571 NETIF_F_TSO |
7572 NETIF_F_TSO6 |
7573 NETIF_F_HW_CSUM);
7574
7575 netdev->priv_flags |= IFF_UNICAST_FLT;
7576
7577 netdev->features |= NETIF_F_HIGHDMA;
7578 netdev->vlan_features |= NETIF_F_HIGHDMA;
7579
7580 /* MTU range: 68 - max_hw_frame_size */
7581 netdev->min_mtu = ETH_MIN_MTU;
7582 netdev->max_mtu = adapter->max_hw_frame_size -
7583 (VLAN_ETH_HLEN + ETH_FCS_LEN);
7584
7585 if (e1000e_enable_mng_pass_thru(&adapter->hw))
7586 adapter->flags |= FLAG_MNG_PT_ENABLED;
7587
7588 /* before reading the NVM, reset the controller to
7589 * put the device in a known good starting state
7590 */
7591 adapter->hw.mac.ops.reset_hw(&adapter->hw);
7592
7593 /* systems with ASPM and others may see the checksum fail on the first
7594 * attempt. Let's give it a few tries
7595 */
7596 for (i = 0;; i++) {
7597 if (e1000_validate_nvm_checksum(&adapter->hw) >= 0)
7598 break;
7599 if (i == 2) {
7600 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
7601 err = -EIO;
7602 goto err_eeprom;
7603 }
7604 }
7605
7606 e1000_eeprom_checks(adapter);
7607
7608 /* copy the MAC address */
7609 if (e1000e_read_mac_addr(&adapter->hw))
7610 dev_err(&pdev->dev,
7611 "NVM Read Error while reading MAC address\n");
7612
7613 eth_hw_addr_set(netdev, adapter->hw.mac.addr);
7614
7615 if (!is_valid_ether_addr(netdev->dev_addr)) {
7616 dev_err(&pdev->dev, "Invalid MAC Address: %pM\n",
7617 netdev->dev_addr);
7618 err = -EIO;
7619 goto err_eeprom;
7620 }
7621
7622 timer_setup(&adapter->watchdog_timer, e1000_watchdog, 0);
7623 timer_setup(&adapter->phy_info_timer, e1000_update_phy_info, 0);
7624
7625 INIT_WORK(&adapter->reset_task, e1000_reset_task);
7626 INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task);
7627 INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround);
7628 INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task);
7629 INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang);
7630
7631 /* Initialize link parameters. User can change them with ethtool */
7632 adapter->hw.mac.autoneg = 1;
7633 adapter->fc_autoneg = true;
7634 adapter->hw.fc.requested_mode = e1000_fc_default;
7635 adapter->hw.fc.current_mode = e1000_fc_default;
7636 adapter->hw.phy.autoneg_advertised = 0x2f;
7637
7638 /* Initial Wake on LAN setting - If APM wake is enabled in
7639 * the EEPROM, enable the ACPI Magic Packet filter
7640 */
7641 if (adapter->flags & FLAG_APME_IN_WUC) {
7642 /* APME bit in EEPROM is mapped to WUC.APME */
7643 eeprom_data = er32(WUC);
7644 eeprom_apme_mask = E1000_WUC_APME;
7645 if ((hw->mac.type > e1000_ich10lan) &&
7646 (eeprom_data & E1000_WUC_PHY_WAKE))
7647 adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP;
7648 } else if (adapter->flags & FLAG_APME_IN_CTRL3) {
7649 if (adapter->flags & FLAG_APME_CHECK_PORT_B &&
7650 (adapter->hw.bus.func == 1))
7651 ret_val = e1000_read_nvm(&adapter->hw,
7652 NVM_INIT_CONTROL3_PORT_B,
7653 1, &eeprom_data);
7654 else
7655 ret_val = e1000_read_nvm(&adapter->hw,
7656 NVM_INIT_CONTROL3_PORT_A,
7657 1, &eeprom_data);
7658 }
7659
7660 /* fetch WoL from EEPROM */
7661 if (ret_val)
7662 e_dbg("NVM read error getting WoL initial values: %d\n", ret_val);
7663 else if (eeprom_data & eeprom_apme_mask)
7664 adapter->eeprom_wol |= E1000_WUFC_MAG;
7665
7666 /* now that we have the eeprom settings, apply the special cases
7667 * where the eeprom may be wrong or the board simply won't support
7668 * wake on lan on a particular port
7669 */
7670 if (!(adapter->flags & FLAG_HAS_WOL))
7671 adapter->eeprom_wol = 0;
7672
7673 /* initialize the wol settings based on the eeprom settings */
7674 adapter->wol = adapter->eeprom_wol;
7675
7676 /* make sure adapter isn't asleep if manageability is enabled */
7677 if (adapter->wol || (adapter->flags & FLAG_MNG_PT_ENABLED) ||
7678 (hw->mac.ops.check_mng_mode(hw)))
7679 device_wakeup_enable(&pdev->dev);
7680
7681 /* save off EEPROM version number */
7682 ret_val = e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers);
7683
7684 if (ret_val) {
7685 e_dbg("NVM read error getting EEPROM version: %d\n", ret_val);
7686 adapter->eeprom_vers = 0;
7687 }
7688
7689 /* init PTP hardware clock */
7690 e1000e_ptp_init(adapter);
7691
7692 /* disable K1 by default on known problematic systems */
7693 if (hw->mac.type >= e1000_pch_mtp && dmi_check_system(disable_k1_list))
7694 adapter->flags2 |= FLAG2_DISABLE_K1;
7695
7696 /* reset the hardware with the new settings */
7697 e1000e_reset(adapter);
7698
7699 /* If the controller has AMT, do not set DRV_LOAD until the interface
7700 * is up. For all other cases, let the f/w know that the h/w is now
7701 * under the control of the driver.
7702 */
7703 if (!(adapter->flags & FLAG_HAS_AMT))
7704 e1000e_get_hw_control(adapter);
7705
7706 if (hw->mac.type >= e1000_pch_cnp)
7707 adapter->flags2 |= FLAG2_ENABLE_S0IX_FLOWS;
7708
7709 strscpy(netdev->name, "eth%d", sizeof(netdev->name));
7710 err = register_netdev(netdev);
7711 if (err)
7712 goto err_register;
7713
7714 /* carrier off reporting is important to ethtool even BEFORE open */
7715 netif_carrier_off(netdev);
7716
7717 e1000_print_device_info(adapter);
7718
7719 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_SMART_PREPARE);
7720
7721 if (pci_dev_run_wake(pdev))
7722 pm_runtime_put_noidle(&pdev->dev);
7723
7724 return 0;
7725
7726err_register:
7727 if (!(adapter->flags & FLAG_HAS_AMT))
7728 e1000e_release_hw_control(adapter);
7729 e1000e_ptp_remove(adapter);
7730err_eeprom:
7731 if (hw->phy.ops.check_reset_block && !hw->phy.ops.check_reset_block(hw))
7732 e1000_phy_hw_reset(&adapter->hw);
7733err_hw_init:
7734 kfree(adapter->tx_ring);
7735 kfree(adapter->rx_ring);
7736err_sw_init:
7737 if ((adapter->hw.flash_address) && (hw->mac.type < e1000_pch_spt))
7738 iounmap(adapter->hw.flash_address);
7739 e1000e_reset_interrupt_capability(adapter);
7740err_flashmap:
7741 iounmap(adapter->hw.hw_addr);
7742err_ioremap:
7743 free_netdev(netdev);
7744err_alloc_etherdev:
7745 pci_release_mem_regions(pdev);
7746err_pci_reg:
7747err_dma:
7748 pci_disable_device(pdev);
7749 return err;
7750}
7751
7752/**
7753 * e1000_remove - Device Removal Routine
7754 * @pdev: PCI device information struct
7755 *
7756 * e1000_remove is called by the PCI subsystem to alert the driver
7757 * that it should release a PCI device. This could be caused by a
7758 * Hot-Plug event, or because the driver is going to be removed from
7759 * memory.
7760 **/
7761static void e1000_remove(struct pci_dev *pdev)
7762{
7763 struct net_device *netdev = pci_get_drvdata(pdev);
7764 struct e1000_adapter *adapter = netdev_priv(netdev);
7765
7766 e1000e_ptp_remove(adapter);
7767
7768 /* The timers may be rescheduled, so explicitly disable them
7769 * from being rescheduled.
7770 */
7771 set_bit(__E1000_DOWN, &adapter->state);
7772 timer_delete_sync(&adapter->watchdog_timer);
7773 timer_delete_sync(&adapter->phy_info_timer);
7774
7775 cancel_work_sync(&adapter->reset_task);
7776 cancel_work_sync(&adapter->watchdog_task);
7777 cancel_work_sync(&adapter->downshift_task);
7778 cancel_work_sync(&adapter->update_phy_task);
7779 cancel_work_sync(&adapter->print_hang_task);
7780
7781 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
7782 cancel_work_sync(&adapter->tx_hwtstamp_work);
7783 if (adapter->tx_hwtstamp_skb) {
7784 dev_consume_skb_any(adapter->tx_hwtstamp_skb);
7785 adapter->tx_hwtstamp_skb = NULL;
7786 }
7787 }
7788
7789 unregister_netdev(netdev);
7790
7791 if (pci_dev_run_wake(pdev))
7792 pm_runtime_get_noresume(&pdev->dev);
7793
7794 /* Release control of h/w to f/w. If f/w is AMT enabled, this
7795 * would have already happened in close and is redundant.
7796 */
7797 e1000e_release_hw_control(adapter);
7798
7799 e1000e_reset_interrupt_capability(adapter);
7800 kfree(adapter->tx_ring);
7801 kfree(adapter->rx_ring);
7802
7803 iounmap(adapter->hw.hw_addr);
7804 if ((adapter->hw.flash_address) &&
7805 (adapter->hw.mac.type < e1000_pch_spt))
7806 iounmap(adapter->hw.flash_address);
7807 pci_release_mem_regions(pdev);
7808
7809 free_netdev(netdev);
7810
7811 pci_disable_device(pdev);
7812}
7813
7814/* PCI Error Recovery (ERS) */
7815static const struct pci_error_handlers e1000_err_handler = {
7816 .error_detected = e1000_io_error_detected,
7817 .slot_reset = e1000_io_slot_reset,
7818 .resume = e1000_io_resume,
7819};
7820
7821static const struct pci_device_id e1000_pci_tbl[] = {
7822 {
7823 PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER),
7824 .driver_data = board_82571,
7825 }, {
7826 PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER),
7827 .driver_data = board_82571,
7828 }, {
7829 PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER),
7830 .driver_data = board_82571,
7831 }, {
7832 PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP),
7833 .driver_data = board_82571,
7834 }, {
7835 PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER),
7836 .driver_data = board_82571,
7837 }, {
7838 PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES),
7839 .driver_data = board_82571,
7840 }, {
7841 PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL),
7842 .driver_data = board_82571,
7843 }, {
7844 PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD),
7845 .driver_data = board_82571,
7846 }, {
7847 PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER),
7848 .driver_data = board_82571,
7849 },
7850
7851 {
7852 PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI),
7853 .driver_data = board_82572,
7854 }, {
7855 PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER),
7856 .driver_data = board_82572,
7857 }, {
7858 PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER),
7859 .driver_data = board_82572,
7860 }, {
7861 PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES),
7862 .driver_data = board_82572,
7863 },
7864
7865 {
7866 PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E),
7867 .driver_data = board_82573,
7868 }, {
7869 PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT),
7870 .driver_data = board_82573,
7871 }, {
7872 PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L),
7873 .driver_data = board_82573,
7874 },
7875
7876 {
7877 PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L),
7878 .driver_data = board_82574,
7879 }, {
7880 PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA),
7881 .driver_data = board_82574,
7882 }, {
7883 PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V),
7884 .driver_data = board_82583,
7885 },
7886
7887 {
7888 PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT),
7889 .driver_data = board_80003es2lan,
7890 }, {
7891 PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT),
7892 .driver_data = board_80003es2lan,
7893 }, {
7894 PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT),
7895 .driver_data = board_80003es2lan,
7896 }, {
7897 PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT),
7898 .driver_data = board_80003es2lan,
7899 },
7900
7901 {
7902 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE),
7903 .driver_data = board_ich8lan,
7904 }, {
7905 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G),
7906 .driver_data = board_ich8lan,
7907 }, {
7908 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT),
7909 .driver_data = board_ich8lan,
7910 }, {
7911 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT),
7912 .driver_data = board_ich8lan,
7913 }, {
7914 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C),
7915 .driver_data = board_ich8lan,
7916 }, {
7917 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M),
7918 .driver_data = board_ich8lan,
7919 }, {
7920 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT),
7921 .driver_data = board_ich8lan,
7922 }, {
7923 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3),
7924 .driver_data = board_ich8lan,
7925 },
7926
7927 {
7928 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE),
7929 .driver_data = board_ich9lan,
7930 }, {
7931 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G),
7932 .driver_data = board_ich9lan,
7933 }, {
7934 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT),
7935 .driver_data = board_ich9lan,
7936 }, {
7937 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT),
7938 .driver_data = board_ich9lan,
7939 }, {
7940 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C),
7941 .driver_data = board_ich9lan,
7942 }, {
7943 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM),
7944 .driver_data = board_ich9lan,
7945 }, {
7946 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M),
7947 .driver_data = board_ich9lan,
7948 }, {
7949 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT),
7950 .driver_data = board_ich9lan,
7951 }, {
7952 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V),
7953 .driver_data = board_ich9lan
7954 },
7955
7956 {
7957 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM),
7958 .driver_data = board_ich9lan,
7959 }, {
7960 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF),
7961 .driver_data = board_ich9lan,
7962 }, {
7963 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V),
7964 .driver_data = board_ich9lan,
7965 },
7966
7967 {
7968 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM),
7969 .driver_data = board_ich10lan,
7970 }, {
7971 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF),
7972 .driver_data = board_ich10lan,
7973 }, {
7974 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V),
7975 .driver_data = board_ich10lan,
7976 },
7977
7978 {
7979 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM),
7980 .driver_data = board_pchlan,
7981 }, {
7982 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC),
7983 .driver_data = board_pchlan,
7984 }, {
7985 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM),
7986 .driver_data = board_pchlan,
7987 }, {
7988 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC),
7989 .driver_data = board_pchlan
7990 },
7991
7992 {
7993 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM),
7994 .driver_data = board_pch2lan,
7995 }, {
7996 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V),
7997 .driver_data = board_pch2lan
7998 },
7999
8000 {
8001 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_LM),
8002 .driver_data = board_pch_lpt,
8003 }, {
8004 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_V),
8005 .driver_data = board_pch_lpt,
8006 }, {
8007 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_LM),
8008 .driver_data = board_pch_lpt,
8009 }, {
8010 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_V),
8011 .driver_data = board_pch_lpt,
8012 }, {
8013 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM2),
8014 .driver_data = board_pch_lpt,
8015 }, {
8016 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V2),
8017 .driver_data = board_pch_lpt,
8018 }, {
8019 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM3),
8020 .driver_data = board_pch_lpt,
8021 }, {
8022 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V3),
8023 .driver_data = board_pch_lpt,
8024 }, {
8025 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM),
8026 .driver_data = board_pch_spt,
8027 }, {
8028 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V),
8029 .driver_data = board_pch_spt,
8030 }, {
8031 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM2),
8032 .driver_data = board_pch_spt,
8033 }, {
8034 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V2),
8035 .driver_data = board_pch_spt,
8036 }, {
8037 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LBG_I219_LM3),
8038 .driver_data = board_pch_spt,
8039 }, {
8040 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM4),
8041 .driver_data = board_pch_spt,
8042 }, {
8043 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V4),
8044 .driver_data = board_pch_spt,
8045 }, {
8046 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM5),
8047 .driver_data = board_pch_spt,
8048 }, {
8049 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V5),
8050 .driver_data = board_pch_spt,
8051 }, {
8052 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_LM6),
8053 .driver_data = board_pch_cnp,
8054 }, {
8055 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V6),
8056 .driver_data = board_pch_cnp,
8057 }, {
8058 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_LM7),
8059 .driver_data = board_pch_cnp,
8060 }, {
8061 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V7),
8062 .driver_data = board_pch_cnp,
8063 }, {
8064 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_LM8),
8065 .driver_data = board_pch_cnp,
8066 }, {
8067 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_V8),
8068 .driver_data = board_pch_cnp,
8069 }, {
8070 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_LM9),
8071 .driver_data = board_pch_cnp,
8072 }, {
8073 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_V9),
8074 .driver_data = board_pch_cnp,
8075 }, {
8076 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM10),
8077 .driver_data = board_pch_cnp,
8078 }, {
8079 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V10),
8080 .driver_data = board_pch_cnp,
8081 }, {
8082 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM11),
8083 .driver_data = board_pch_cnp,
8084 }, {
8085 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V11),
8086 .driver_data = board_pch_cnp,
8087 }, {
8088 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM12),
8089 .driver_data = board_pch_spt,
8090 }, {
8091 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V12),
8092 .driver_data = board_pch_spt,
8093 }, {
8094 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM13),
8095 .driver_data = board_pch_tgp,
8096 }, {
8097 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V13),
8098 .driver_data = board_pch_tgp,
8099 }, {
8100 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM14),
8101 .driver_data = board_pch_tgp,
8102 }, {
8103 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V14),
8104 .driver_data = board_pch_tgp,
8105 }, {
8106 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM15),
8107 .driver_data = board_pch_tgp,
8108 }, {
8109 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V15),
8110 .driver_data = board_pch_tgp,
8111 }, {
8112 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_LM23),
8113 .driver_data = board_pch_adp,
8114 }, {
8115 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_V23),
8116 .driver_data = board_pch_adp,
8117 }, {
8118 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_LM16),
8119 .driver_data = board_pch_adp,
8120 }, {
8121 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_V16),
8122 .driver_data = board_pch_adp,
8123 }, {
8124 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_LM17),
8125 .driver_data = board_pch_adp,
8126 }, {
8127 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_V17),
8128 .driver_data = board_pch_adp,
8129 }, {
8130 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_LM22),
8131 .driver_data = board_pch_adp,
8132 }, {
8133 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_V22),
8134 .driver_data = board_pch_adp,
8135 }, {
8136 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_LM19),
8137 .driver_data = board_pch_adp,
8138 }, {
8139 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_V19),
8140 .driver_data = board_pch_adp,
8141 }, {
8142 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_LM18),
8143 .driver_data = board_pch_mtp,
8144 }, {
8145 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_V18),
8146 .driver_data = board_pch_mtp,
8147 }, {
8148 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_LM20),
8149 .driver_data = board_pch_mtp,
8150 }, {
8151 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_V20),
8152 .driver_data = board_pch_mtp,
8153 }, {
8154 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_LM21),
8155 .driver_data = board_pch_mtp,
8156 }, {
8157 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_V21),
8158 .driver_data = board_pch_mtp,
8159 }, {
8160 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ARL_I219_LM24),
8161 .driver_data = board_pch_mtp,
8162 }, {
8163 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ARL_I219_V24),
8164 .driver_data = board_pch_mtp,
8165 }, {
8166 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_LM25),
8167 .driver_data = board_pch_ptp,
8168 }, {
8169 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_V25),
8170 .driver_data = board_pch_ptp,
8171 }, {
8172 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_LM27),
8173 .driver_data = board_pch_ptp,
8174 }, {
8175 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_V27),
8176 .driver_data = board_pch_ptp,
8177 }, {
8178 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_NVL_I219_LM29),
8179 .driver_data = board_pch_ptp,
8180 }, {
8181 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_NVL_I219_V29),
8182 .driver_data = board_pch_ptp
8183 },
8184
8185 { } /* terminate list */
8186};
8187MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
8188
8189static const struct dev_pm_ops e1000e_pm_ops = {
8190 .prepare = e1000e_pm_prepare,
8191 .suspend = e1000e_pm_suspend,
8192 .resume = e1000e_pm_resume,
8193 .freeze = e1000e_pm_freeze,
8194 .thaw = e1000e_pm_thaw,
8195 .poweroff = e1000e_pm_suspend,
8196 .restore = e1000e_pm_resume,
8197 RUNTIME_PM_OPS(e1000e_pm_runtime_suspend, e1000e_pm_runtime_resume,
8198 e1000e_pm_runtime_idle)
8199};
8200
8201/* PCI Device API Driver */
8202static struct pci_driver e1000_driver = {
8203 .name = e1000e_driver_name,
8204 .id_table = e1000_pci_tbl,
8205 .probe = e1000_probe,
8206 .remove = e1000_remove,
8207 .driver.pm = pm_ptr(&e1000e_pm_ops),
8208 .shutdown = e1000_shutdown,
8209 .err_handler = &e1000_err_handler
8210};
8211
8212/**
8213 * e1000_init_module - Driver Registration Routine
8214 *
8215 * e1000_init_module is the first routine called when the driver is
8216 * loaded. All it does is register with the PCI subsystem.
8217 **/
8218static int __init e1000_init_module(void)
8219{
8220 pr_info("Intel(R) PRO/1000 Network Driver\n");
8221 pr_info("Copyright(c) 1999 - 2015 Intel Corporation.\n");
8222
8223 return pci_register_driver(&e1000_driver);
8224}
8225module_init(e1000_init_module);
8226
8227/**
8228 * e1000_exit_module - Driver Exit Cleanup Routine
8229 *
8230 * e1000_exit_module is called just before the driver is removed
8231 * from memory.
8232 **/
8233static void __exit e1000_exit_module(void)
8234{
8235 pci_unregister_driver(&e1000_driver);
8236}
8237module_exit(e1000_exit_module);
8238
8239MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
8240MODULE_LICENSE("GPL v2");
8241
8242/* netdev.c */