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1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 2017 - 2021 Pensando Systems, Inc */
3
4#include <linux/netdevice.h>
5#include <linux/etherdevice.h>
6#include <uapi/rdma/ib_user_verbs.h>
7
8#include "ionic.h"
9#include "ionic_bus.h"
10#include "ionic_lif.h"
11#include "ionic_ethtool.h"
12
13static int ionic_hwstamp_tx_mode(int config_tx_type)
14{
15 switch (config_tx_type) {
16 case HWTSTAMP_TX_OFF:
17 return IONIC_TXSTAMP_OFF;
18 case HWTSTAMP_TX_ON:
19 return IONIC_TXSTAMP_ON;
20 case HWTSTAMP_TX_ONESTEP_SYNC:
21 return IONIC_TXSTAMP_ONESTEP_SYNC;
22 case HWTSTAMP_TX_ONESTEP_P2P:
23 return IONIC_TXSTAMP_ONESTEP_P2P;
24 default:
25 return -ERANGE;
26 }
27}
28
29static u64 ionic_hwstamp_rx_filt(int config_rx_filter)
30{
31 switch (config_rx_filter) {
32 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
33 return IONIC_PKT_CLS_PTP1_ALL;
34 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
35 return IONIC_PKT_CLS_PTP1_SYNC;
36 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
37 return IONIC_PKT_CLS_PTP1_SYNC | IONIC_PKT_CLS_PTP1_DREQ;
38
39 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
40 return IONIC_PKT_CLS_PTP2_L4_ALL;
41 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
42 return IONIC_PKT_CLS_PTP2_L4_SYNC;
43 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
44 return IONIC_PKT_CLS_PTP2_L4_SYNC | IONIC_PKT_CLS_PTP2_L4_DREQ;
45
46 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
47 return IONIC_PKT_CLS_PTP2_L2_ALL;
48 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
49 return IONIC_PKT_CLS_PTP2_L2_SYNC;
50 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
51 return IONIC_PKT_CLS_PTP2_L2_SYNC | IONIC_PKT_CLS_PTP2_L2_DREQ;
52
53 case HWTSTAMP_FILTER_PTP_V2_EVENT:
54 return IONIC_PKT_CLS_PTP2_ALL;
55 case HWTSTAMP_FILTER_PTP_V2_SYNC:
56 return IONIC_PKT_CLS_PTP2_SYNC;
57 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
58 return IONIC_PKT_CLS_PTP2_SYNC | IONIC_PKT_CLS_PTP2_DREQ;
59
60 case HWTSTAMP_FILTER_NTP_ALL:
61 return IONIC_PKT_CLS_NTP_ALL;
62
63 default:
64 return 0;
65 }
66}
67
68static int ionic_lif_hwstamp_set_ts_config(struct ionic_lif *lif,
69 struct kernel_hwtstamp_config *new_ts,
70 struct netlink_ext_ack *extack)
71{
72 struct kernel_hwtstamp_config *config;
73 struct kernel_hwtstamp_config ts = {};
74 struct ionic *ionic = lif->ionic;
75 int tx_mode = 0;
76 u64 rx_filt = 0;
77 int err, err2;
78 bool rx_all;
79 __le64 mask;
80
81 if (!lif->phc || !lif->phc->ptp ||
82 !(lif->hw_features & IONIC_ETH_HW_TIMESTAMP))
83 return -EOPNOTSUPP;
84
85 mutex_lock(&lif->phc->config_lock);
86
87 if (new_ts) {
88 config = new_ts;
89 } else {
90 /* If called with new_ts == NULL, replay the previous request
91 * primarily for recovery after a FW_RESET.
92 * We saved the previous configuration request info, so copy
93 * the previous request for reference, clear the current state
94 * to match the device's reset state, and run with it.
95 */
96 config = &ts;
97 memcpy(config, &lif->phc->ts_config, sizeof(*config));
98 memset(&lif->phc->ts_config, 0, sizeof(lif->phc->ts_config));
99 lif->phc->ts_config_tx_mode = 0;
100 lif->phc->ts_config_rx_filt = 0;
101 }
102
103 tx_mode = ionic_hwstamp_tx_mode(config->tx_type);
104 if (tx_mode < 0) {
105 NL_SET_ERR_MSG_MOD(extack,
106 "TX time stamping mode isn't supported");
107 err = tx_mode;
108 goto err_queues;
109 }
110
111 mask = cpu_to_le64(BIT_ULL(tx_mode));
112 if ((ionic->ident.lif.eth.hwstamp_tx_modes & mask) != mask) {
113 NL_SET_ERR_MSG_MOD(extack,
114 "TX time stamping mode isn't supported");
115 err = -ERANGE;
116 goto err_queues;
117 }
118
119 rx_filt = ionic_hwstamp_rx_filt(config->rx_filter);
120 rx_all = config->rx_filter != HWTSTAMP_FILTER_NONE && !rx_filt;
121
122 mask = cpu_to_le64(rx_filt);
123 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) != mask) {
124 rx_filt = 0;
125 rx_all = true;
126 config->rx_filter = HWTSTAMP_FILTER_ALL;
127 }
128
129 dev_dbg(ionic->dev, "%s: config_rx_filter %d rx_filt %#llx rx_all %d\n",
130 __func__, config->rx_filter, rx_filt, rx_all);
131
132 if (tx_mode) {
133 err = ionic_lif_create_hwstamp_txq(lif);
134 if (err) {
135 NL_SET_ERR_MSG_MOD(extack,
136 "Error creating TX timestamp queue");
137 goto err_queues;
138 }
139 }
140
141 if (rx_filt) {
142 err = ionic_lif_create_hwstamp_rxq(lif);
143 if (err) {
144 NL_SET_ERR_MSG_MOD(extack,
145 "Error creating RX timestamp queue");
146 goto err_queues;
147 }
148 }
149
150 if (tx_mode != lif->phc->ts_config_tx_mode) {
151 err = ionic_lif_set_hwstamp_txmode(lif, tx_mode);
152 if (err) {
153 NL_SET_ERR_MSG_MOD(extack,
154 "Error enabling TX timestamp mode");
155 goto err_txmode;
156 }
157 }
158
159 if (rx_filt != lif->phc->ts_config_rx_filt) {
160 err = ionic_lif_set_hwstamp_rxfilt(lif, rx_filt);
161 if (err) {
162 NL_SET_ERR_MSG_MOD(extack,
163 "Error enabling RX timestamp mode");
164 goto err_rxfilt;
165 }
166 }
167
168 if (rx_all != (lif->phc->ts_config.rx_filter == HWTSTAMP_FILTER_ALL)) {
169 err = ionic_lif_config_hwstamp_rxq_all(lif, rx_all);
170 if (err) {
171 NL_SET_ERR_MSG_MOD(extack,
172 "Error enabling RX timestamp mode");
173 goto err_rxall;
174 }
175 }
176
177 memcpy(&lif->phc->ts_config, config, sizeof(*config));
178 lif->phc->ts_config_rx_filt = rx_filt;
179 lif->phc->ts_config_tx_mode = tx_mode;
180
181 mutex_unlock(&lif->phc->config_lock);
182
183 return 0;
184
185err_rxall:
186 if (rx_filt != lif->phc->ts_config_rx_filt) {
187 rx_filt = lif->phc->ts_config_rx_filt;
188 err2 = ionic_lif_set_hwstamp_rxfilt(lif, rx_filt);
189 if (err2)
190 dev_err(ionic->dev,
191 "Failed to revert rx timestamp filter: %d\n", err2);
192 }
193err_rxfilt:
194 if (tx_mode != lif->phc->ts_config_tx_mode) {
195 tx_mode = lif->phc->ts_config_tx_mode;
196 err2 = ionic_lif_set_hwstamp_txmode(lif, tx_mode);
197 if (err2)
198 dev_err(ionic->dev,
199 "Failed to revert tx timestamp mode: %d\n", err2);
200 }
201err_txmode:
202 /* special queues remain allocated, just unused */
203err_queues:
204 mutex_unlock(&lif->phc->config_lock);
205 return err;
206}
207
208int ionic_hwstamp_set(struct net_device *netdev,
209 struct kernel_hwtstamp_config *config,
210 struct netlink_ext_ack *extack)
211{
212 struct ionic_lif *lif = netdev_priv(netdev);
213 int err;
214
215 if (!lif->phc || !lif->phc->ptp ||
216 !(lif->hw_features & IONIC_ETH_HW_TIMESTAMP))
217 return -EOPNOTSUPP;
218
219 mutex_lock(&lif->queue_lock);
220 err = ionic_lif_hwstamp_set_ts_config(lif, config, extack);
221 mutex_unlock(&lif->queue_lock);
222 if (err) {
223 netdev_info(lif->netdev, "hwstamp set failed: %d\n", err);
224 return err;
225 }
226
227 return 0;
228}
229
230void ionic_lif_hwstamp_replay(struct ionic_lif *lif)
231{
232 int err;
233
234 if (!lif->phc || !lif->phc->ptp ||
235 !(lif->hw_features & IONIC_ETH_HW_TIMESTAMP))
236 return;
237
238 mutex_lock(&lif->queue_lock);
239 err = ionic_lif_hwstamp_set_ts_config(lif, NULL, NULL);
240 mutex_unlock(&lif->queue_lock);
241 if (err)
242 netdev_info(lif->netdev, "hwstamp replay failed: %d\n", err);
243}
244
245void ionic_lif_hwstamp_recreate_queues(struct ionic_lif *lif)
246{
247 int err;
248
249 if (!lif->phc || !lif->phc->ptp ||
250 !(lif->hw_features & IONIC_ETH_HW_TIMESTAMP))
251 return;
252
253 mutex_lock(&lif->phc->config_lock);
254
255 if (lif->phc->ts_config_tx_mode) {
256 err = ionic_lif_create_hwstamp_txq(lif);
257 if (err)
258 netdev_info(lif->netdev, "hwstamp recreate txq failed: %d\n", err);
259 }
260
261 if (lif->phc->ts_config_rx_filt) {
262 err = ionic_lif_create_hwstamp_rxq(lif);
263 if (err)
264 netdev_info(lif->netdev, "hwstamp recreate rxq failed: %d\n", err);
265 }
266
267 mutex_unlock(&lif->phc->config_lock);
268}
269
270int ionic_hwstamp_get(struct net_device *netdev,
271 struct kernel_hwtstamp_config *config)
272{
273 struct ionic_lif *lif = netdev_priv(netdev);
274
275 if (!lif->phc || !lif->phc->ptp ||
276 !(lif->hw_features & IONIC_ETH_HW_TIMESTAMP))
277 return -EOPNOTSUPP;
278
279 mutex_lock(&lif->phc->config_lock);
280 memcpy(config, &lif->phc->ts_config, sizeof(*config));
281 mutex_unlock(&lif->phc->config_lock);
282
283 return 0;
284}
285
286static u64 ionic_hwstamp_read(struct ionic *ionic,
287 struct ptp_system_timestamp *sts)
288{
289 u32 tick_high_before, tick_high, tick_low;
290
291 /* read and discard low part to defeat hw staging of high part */
292 ioread32(&ionic->idev.hwstamp_regs->tick_low);
293
294 tick_high_before = ioread32(&ionic->idev.hwstamp_regs->tick_high);
295
296 ptp_read_system_prets(sts);
297 tick_low = ioread32(&ionic->idev.hwstamp_regs->tick_low);
298 ptp_read_system_postts(sts);
299
300 tick_high = ioread32(&ionic->idev.hwstamp_regs->tick_high);
301
302 /* If tick_high changed, re-read tick_low once more. Assume tick_high
303 * cannot change again so soon as in the span of re-reading tick_low.
304 */
305 if (tick_high != tick_high_before) {
306 ptp_read_system_prets(sts);
307 tick_low = ioread32(&ionic->idev.hwstamp_regs->tick_low);
308 ptp_read_system_postts(sts);
309 }
310
311 return (u64)tick_low | ((u64)tick_high << 32);
312}
313
314static u64 ionic_cc_read(struct cyclecounter *cc)
315{
316 struct ionic_phc *phc = container_of(cc, struct ionic_phc, cc);
317 struct ionic *ionic = phc->lif->ionic;
318
319 return ionic_hwstamp_read(ionic, NULL);
320}
321
322static int ionic_setphc_cmd(struct ionic_phc *phc, struct ionic_admin_ctx *ctx)
323{
324 ctx->work = COMPLETION_INITIALIZER_ONSTACK(ctx->work);
325
326 ctx->cmd.lif_setphc.opcode = IONIC_CMD_LIF_SETPHC;
327 ctx->cmd.lif_setphc.lif_index = cpu_to_le16(phc->lif->index);
328
329 ctx->cmd.lif_setphc.tick = cpu_to_le64(phc->tc.cycle_last);
330 ctx->cmd.lif_setphc.nsec = cpu_to_le64(phc->tc.nsec);
331 ctx->cmd.lif_setphc.frac = cpu_to_le64(phc->tc.frac);
332 ctx->cmd.lif_setphc.mult = cpu_to_le32(phc->cc.mult);
333 ctx->cmd.lif_setphc.shift = cpu_to_le32(phc->cc.shift);
334
335 return ionic_adminq_post(phc->lif, ctx);
336}
337
338static void ionic_phc_state_page_update(struct ionic_phc *phc)
339{
340 struct ib_uverbs_clock_info *state = phc->state_page;
341 u32 sign;
342
343 /* read current sign */
344 sign = smp_load_acquire(&state->sign) & ~1;
345
346 /* make sign odd for updating */
347 smp_store_mb(state->sign, sign | 1);
348
349 state->cycles = phc->tc.cycle_last;
350 state->nsec = phc->tc.nsec;
351 state->frac = phc->tc.frac;
352 state->mult = phc->cc.mult;
353
354 /* make sign the next even number for update completed */
355 smp_store_release(&state->sign, sign + 2);
356}
357
358static int ionic_phc_adjfine(struct ptp_clock_info *info, long scaled_ppm)
359{
360 struct ionic_phc *phc = container_of(info, struct ionic_phc, ptp_info);
361 struct ionic_admin_ctx ctx = {};
362 unsigned long irqflags;
363 s64 adj;
364 int err;
365
366 /* Reject phc adjustments during device upgrade */
367 if (test_bit(IONIC_LIF_F_FW_RESET, phc->lif->state))
368 return -EBUSY;
369
370 /* Adjustment value scaled by 2^16 million */
371 adj = (s64)scaled_ppm * phc->init_cc_mult;
372
373 /* Adjustment value to scale */
374 adj /= (s64)SCALED_PPM;
375
376 /* Final adjusted multiplier */
377 adj += phc->init_cc_mult;
378
379 spin_lock_irqsave(&phc->lock, irqflags);
380
381 /* update the point-in-time basis to now, before adjusting the rate */
382 timecounter_read(&phc->tc);
383 phc->cc.mult = adj;
384
385 ionic_phc_state_page_update(phc);
386
387 /* Setphc commands are posted in-order, sequenced by phc->lock. We
388 * need to drop the lock before waiting for the command to complete.
389 */
390 err = ionic_setphc_cmd(phc, &ctx);
391
392 spin_unlock_irqrestore(&phc->lock, irqflags);
393
394 return ionic_adminq_wait(phc->lif, &ctx, err, true);
395}
396
397static int ionic_phc_adjtime(struct ptp_clock_info *info, s64 delta)
398{
399 struct ionic_phc *phc = container_of(info, struct ionic_phc, ptp_info);
400 struct ionic_admin_ctx ctx = {};
401 unsigned long irqflags;
402 int err;
403
404 /* Reject phc adjustments during device upgrade */
405 if (test_bit(IONIC_LIF_F_FW_RESET, phc->lif->state))
406 return -EBUSY;
407
408 spin_lock_irqsave(&phc->lock, irqflags);
409
410 timecounter_adjtime(&phc->tc, delta);
411
412 ionic_phc_state_page_update(phc);
413
414 /* Setphc commands are posted in-order, sequenced by phc->lock. We
415 * need to drop the lock before waiting for the command to complete.
416 */
417 err = ionic_setphc_cmd(phc, &ctx);
418
419 spin_unlock_irqrestore(&phc->lock, irqflags);
420
421 return ionic_adminq_wait(phc->lif, &ctx, err, true);
422}
423
424static int ionic_phc_settime64(struct ptp_clock_info *info,
425 const struct timespec64 *ts)
426{
427 struct ionic_phc *phc = container_of(info, struct ionic_phc, ptp_info);
428 struct ionic_admin_ctx ctx = {};
429 unsigned long irqflags;
430 int err;
431 u64 ns;
432
433 /* Reject phc adjustments during device upgrade */
434 if (test_bit(IONIC_LIF_F_FW_RESET, phc->lif->state))
435 return -EBUSY;
436
437 ns = timespec64_to_ns(ts);
438
439 spin_lock_irqsave(&phc->lock, irqflags);
440
441 timecounter_init(&phc->tc, &phc->cc, ns);
442
443 ionic_phc_state_page_update(phc);
444
445 /* Setphc commands are posted in-order, sequenced by phc->lock. We
446 * need to drop the lock before waiting for the command to complete.
447 */
448 err = ionic_setphc_cmd(phc, &ctx);
449
450 spin_unlock_irqrestore(&phc->lock, irqflags);
451
452 return ionic_adminq_wait(phc->lif, &ctx, err, true);
453}
454
455static int ionic_phc_gettimex64(struct ptp_clock_info *info,
456 struct timespec64 *ts,
457 struct ptp_system_timestamp *sts)
458{
459 struct ionic_phc *phc = container_of(info, struct ionic_phc, ptp_info);
460 struct ionic *ionic = phc->lif->ionic;
461 unsigned long irqflags;
462 u64 tick, ns;
463
464 /* Do not attempt to read device time during upgrade */
465 if (test_bit(IONIC_LIF_F_FW_RESET, phc->lif->state))
466 return -EBUSY;
467
468 spin_lock_irqsave(&phc->lock, irqflags);
469
470 tick = ionic_hwstamp_read(ionic, sts);
471
472 ns = timecounter_cyc2time(&phc->tc, tick);
473
474 spin_unlock_irqrestore(&phc->lock, irqflags);
475
476 *ts = ns_to_timespec64(ns);
477
478 return 0;
479}
480
481static long ionic_phc_aux_work(struct ptp_clock_info *info)
482{
483 struct ionic_phc *phc = container_of(info, struct ionic_phc, ptp_info);
484 struct ionic_admin_ctx ctx = {};
485 unsigned long irqflags;
486 int err;
487
488 /* Do not update phc during device upgrade, but keep polling to resume
489 * after upgrade. Since we don't update the point in time basis, there
490 * is no expectation that we are maintaining the phc time during the
491 * upgrade. After upgrade, it will need to be readjusted back to the
492 * correct time by the ptp daemon.
493 */
494 if (test_bit(IONIC_LIF_F_FW_RESET, phc->lif->state))
495 return phc->aux_work_delay;
496
497 spin_lock_irqsave(&phc->lock, irqflags);
498
499 /* update point-in-time basis to now */
500 timecounter_read(&phc->tc);
501
502 ionic_phc_state_page_update(phc);
503
504 /* Setphc commands are posted in-order, sequenced by phc->lock. We
505 * need to drop the lock before waiting for the command to complete.
506 */
507 err = ionic_setphc_cmd(phc, &ctx);
508
509 spin_unlock_irqrestore(&phc->lock, irqflags);
510
511 ionic_adminq_wait(phc->lif, &ctx, err, true);
512
513 return phc->aux_work_delay;
514}
515
516ktime_t ionic_lif_phc_ktime(struct ionic_lif *lif, u64 tick)
517{
518 unsigned long irqflags;
519 u64 ns;
520
521 if (!lif->phc)
522 return 0;
523
524 spin_lock_irqsave(&lif->phc->lock, irqflags);
525 ns = timecounter_cyc2time(&lif->phc->tc, tick);
526 spin_unlock_irqrestore(&lif->phc->lock, irqflags);
527
528 return ns_to_ktime(ns);
529}
530
531static const struct ptp_clock_info ionic_ptp_info = {
532 .owner = THIS_MODULE,
533 .name = "ionic_ptp",
534 .adjfine = ionic_phc_adjfine,
535 .adjtime = ionic_phc_adjtime,
536 .gettimex64 = ionic_phc_gettimex64,
537 .settime64 = ionic_phc_settime64,
538 .do_aux_work = ionic_phc_aux_work,
539};
540
541void ionic_lif_register_phc(struct ionic_lif *lif)
542{
543 if (!lif->phc ||
544 !(lif->hw_features & (IONIC_ETH_HW_TIMESTAMP | IONIC_ETH_HW_RDMA_TIMESTAMP)))
545 return;
546
547 lif->phc->ptp = ptp_clock_register(&lif->phc->ptp_info, lif->ionic->dev);
548
549 if (IS_ERR(lif->phc->ptp)) {
550 dev_warn(lif->ionic->dev, "Cannot register phc device: %ld\n",
551 PTR_ERR(lif->phc->ptp));
552
553 lif->phc->ptp = NULL;
554 }
555
556 if (lif->phc->ptp)
557 ptp_schedule_worker(lif->phc->ptp, lif->phc->aux_work_delay);
558}
559
560void ionic_lif_unregister_phc(struct ionic_lif *lif)
561{
562 if (!lif->phc || !lif->phc->ptp)
563 return;
564
565 ptp_clock_unregister(lif->phc->ptp);
566
567 lif->phc->ptp = NULL;
568}
569
570void ionic_lif_alloc_phc(struct ionic_lif *lif)
571{
572 struct ionic *ionic = lif->ionic;
573 struct ionic_phc *phc;
574 u64 delay, diff, mult;
575 u64 frac = 0;
576 u64 features;
577 u32 shift;
578
579 if (!ionic->idev.hwstamp_regs)
580 return;
581
582 features = le64_to_cpu(ionic->ident.lif.eth.config.features);
583 if (!(features & (IONIC_ETH_HW_TIMESTAMP | IONIC_ETH_HW_RDMA_TIMESTAMP)))
584 return;
585
586 phc = devm_kzalloc(ionic->dev, sizeof(*phc), GFP_KERNEL);
587 if (!phc)
588 return;
589
590 phc->state_page = (void *)get_zeroed_page(GFP_KERNEL);
591 if (!phc->state_page) {
592 devm_kfree(ionic->dev, phc);
593 return;
594 }
595
596 phc->lif = lif;
597
598 phc->cc.read = ionic_cc_read;
599 phc->cc.mask = le64_to_cpu(ionic->ident.dev.hwstamp_mask);
600 phc->cc.mult = le32_to_cpu(ionic->ident.dev.hwstamp_mult);
601 phc->cc.shift = le32_to_cpu(ionic->ident.dev.hwstamp_shift);
602
603 if (!phc->cc.mult) {
604 dev_err(lif->ionic->dev,
605 "Invalid device PHC mask multiplier %u, disabling HW timestamp support\n",
606 phc->cc.mult);
607 free_page((unsigned long)phc->state_page);
608 devm_kfree(lif->ionic->dev, phc);
609 lif->phc = NULL;
610 return;
611 }
612
613 dev_dbg(lif->ionic->dev, "Device PHC mask %#llx mult %u shift %u\n",
614 phc->cc.mask, phc->cc.mult, phc->cc.shift);
615
616 spin_lock_init(&phc->lock);
617 mutex_init(&phc->config_lock);
618
619 /* max ticks is limited by the multiplier, or by the update period. */
620 if (phc->cc.shift + 2 + ilog2(IONIC_PHC_UPDATE_NS) >= 64) {
621 /* max ticks that do not overflow when multiplied by max
622 * adjusted multiplier (twice the initial multiplier)
623 */
624 diff = U64_MAX / phc->cc.mult / 2;
625 } else {
626 /* approx ticks at four times the update period */
627 diff = (u64)IONIC_PHC_UPDATE_NS << (phc->cc.shift + 2);
628 diff = DIV_ROUND_UP(diff, phc->cc.mult);
629 }
630
631 /* transform to bitmask */
632 diff |= diff >> 1;
633 diff |= diff >> 2;
634 diff |= diff >> 4;
635 diff |= diff >> 8;
636 diff |= diff >> 16;
637 diff |= diff >> 32;
638
639 /* constrain to the hardware bitmask */
640 diff &= phc->cc.mask;
641
642 /* the wrap period is now defined by diff
643 *
644 * we will update the time basis at about 1/4 the wrap period, so
645 * should not see a difference of more than +/- diff/4.
646 *
647 * this is sufficient not see a difference of more than +/- diff/2, as
648 * required by timecounter_cyc2time, to detect an old time stamp.
649 *
650 * adjust the initial multiplier, being careful to avoid overflow:
651 * - do not overflow 63 bits: init_cc_mult * SCALED_PPM
652 * - do not overflow 64 bits: max_mult * (diff / 2)
653 *
654 * we want to increase the initial multiplier as much as possible, to
655 * allow for more precise adjustment in ionic_phc_adjfine.
656 *
657 * only adjust the multiplier if we can double it or more.
658 */
659 mult = U64_MAX / 2 / max(diff / 2, SCALED_PPM);
660 shift = mult / phc->cc.mult;
661 if (shift >= 2) {
662 /* initial multiplier will be 2^n of hardware cc.mult */
663 shift = fls(shift);
664 /* increase cc.mult and cc.shift by the same 2^n and n. */
665 phc->cc.mult <<= shift;
666 phc->cc.shift += shift;
667 }
668
669 dev_dbg(lif->ionic->dev, "Initial PHC mask %#llx mult %u shift %u\n",
670 phc->cc.mask, phc->cc.mult, phc->cc.shift);
671
672 /* frequency adjustments are relative to the initial multiplier */
673 phc->init_cc_mult = phc->cc.mult;
674
675 timecounter_init(&phc->tc, &phc->cc, ktime_get_real_ns());
676
677 /* Update cycle_last at 1/4 the wrap period, or IONIC_PHC_UPDATE_NS */
678 delay = min_t(u64, IONIC_PHC_UPDATE_NS,
679 cyclecounter_cyc2ns(&phc->cc, diff / 4, 0, &frac));
680 dev_dbg(lif->ionic->dev, "Work delay %llu ms\n", delay / NSEC_PER_MSEC);
681
682 phc->aux_work_delay = nsecs_to_jiffies(delay);
683
684 phc->ptp_info = ionic_ptp_info;
685
686 /* We have allowed to adjust the multiplier up to +/- 1 part per 1.
687 * Here expressed as NORMAL_PPB (1 billion parts per billion).
688 */
689 phc->ptp_info.max_adj = NORMAL_PPB;
690
691 phc->state_page->mask = phc->cc.mask;
692 phc->state_page->shift = phc->cc.shift;
693 phc->state_page->overflow_period = delay;
694
695 ionic_phc_state_page_update(phc);
696
697 lif->phc = phc;
698}
699
700void ionic_lif_free_phc(struct ionic_lif *lif)
701{
702 if (!lif->phc)
703 return;
704
705 mutex_destroy(&lif->phc->config_lock);
706
707 free_page((unsigned long)lif->phc->state_page);
708 devm_kfree(lif->ionic->dev, lif->phc);
709 lif->phc = NULL;
710}