| 1 | |
| 2 |
|
| 3 | |
| 4 | * Copyright (C) 2018-2024 Linaro Ltd.
|
| 5 |
|
| 6 |
|
| 7 | #include <linux/delay.h>
|
| 8 | #include <linux/io.h>
|
| 9 | #include <linux/pm_runtime.h>
|
| 10 | #include <linux/types.h>
|
| 11 |
|
| 12 | #include "ipa.h"
|
| 13 | #include "ipa_interrupt.h"
|
| 14 | #include "ipa_power.h"
|
| 15 | #include "ipa_reg.h"
|
| 16 | #include "ipa_uc.h"
|
| 17 |
|
| 18 | |
| 19 | * DOC: The IPA embedded microcontroller
|
| 20 | *
|
| 21 | * The IPA incorporates a microcontroller that is able to do some additional
|
| 22 | * handling/offloading of network activity. The current code makes
|
| 23 | * essentially no use of the microcontroller, but it still requires some
|
| 24 | * initialization. It needs to be notified in the event the AP crashes.
|
| 25 | *
|
| 26 | * The microcontroller can generate two interrupts to the AP. One interrupt
|
| 27 | * is used to indicate that a response to a request from the AP is available.
|
| 28 | * The other is used to notify the AP of the occurrence of an event. In
|
| 29 | * addition, the AP can interrupt the microcontroller by writing a register.
|
| 30 | *
|
| 31 | * A 128 byte block of structured memory within the IPA SRAM is used together
|
| 32 | * with these interrupts to implement the communication interface between the
|
| 33 | * AP and the IPA microcontroller. Each side writes data to the shared area
|
| 34 | * before interrupting its peer, which will read the written data in response
|
| 35 | * to the interrupt. Some information found in the shared area is currently
|
| 36 | * unused. All remaining space in the shared area is reserved, and must not
|
| 37 | * be read or written by the AP.
|
| 38 |
|
| 39 |
|
| 40 |
|
| 41 |
|
| 42 | #define IPA_SEND_DELAY 100
|
| 43 |
|
| 44 | |
| 45 | * struct ipa_uc_mem_area - AP/microcontroller shared memory area
|
| 46 | * @command: command code (AP->microcontroller)
|
| 47 | * @reserved0: reserved bytes; avoid reading or writing
|
| 48 | * @command_param: low 32 bits of command parameter (AP->microcontroller)
|
| 49 | * @command_param_hi: high 32 bits of command parameter (AP->microcontroller)
|
| 50 | *
|
| 51 | * @response: response code (microcontroller->AP)
|
| 52 | * @reserved1: reserved bytes; avoid reading or writing
|
| 53 | * @response_param: response parameter (microcontroller->AP)
|
| 54 | *
|
| 55 | * @event: event code (microcontroller->AP)
|
| 56 | * @reserved2: reserved bytes; avoid reading or writing
|
| 57 | * @event_param: event parameter (microcontroller->AP)
|
| 58 | *
|
| 59 | * @first_error_address: address of first error-source on SNOC
|
| 60 | * @hw_state: state of hardware (including error type information)
|
| 61 | * @warning_counter: counter of non-fatal hardware errors
|
| 62 | * @reserved3: reserved bytes; avoid reading or writing
|
| 63 | * @interface_version: hardware-reported interface version
|
| 64 | * @reserved4: reserved bytes; avoid reading or writing
|
| 65 | *
|
| 66 | * A shared memory area at the base of IPA resident memory is used for
|
| 67 | * communication with the microcontroller. The region is 128 bytes in
|
| 68 | * size, but only the first 40 bytes (structured this way) are used.
|
| 69 |
|
| 70 | struct ipa_uc_mem_area {
|
| 71 | u8 command;
|
| 72 | u8 reserved0[3];
|
| 73 | __le32 command_param;
|
| 74 | __le32 command_param_hi;
|
| 75 | u8 response;
|
| 76 | u8 reserved1[3];
|
| 77 | __le32 response_param;
|
| 78 | u8 event;
|
| 79 | u8 reserved2[3];
|
| 80 |
|
| 81 | __le32 event_param;
|
| 82 | __le32 first_error_address;
|
| 83 | u8 hw_state;
|
| 84 | u8 warning_counter;
|
| 85 | __le16 reserved3;
|
| 86 | __le16 interface_version;
|
| 87 | __le16 reserved4;
|
| 88 | };
|
| 89 |
|
| 90 |
|
| 91 | enum ipa_uc_command {
|
| 92 | IPA_UC_COMMAND_NO_OP = 0x0,
|
| 93 | IPA_UC_COMMAND_UPDATE_FLAGS = 0x1,
|
| 94 | IPA_UC_COMMAND_DEBUG_RUN_TEST = 0x2,
|
| 95 | IPA_UC_COMMAND_DEBUG_GET_INFO = 0x3,
|
| 96 | IPA_UC_COMMAND_ERR_FATAL = 0x4,
|
| 97 | IPA_UC_COMMAND_CLK_GATE = 0x5,
|
| 98 | IPA_UC_COMMAND_CLK_UNGATE = 0x6,
|
| 99 | IPA_UC_COMMAND_MEMCPY = 0x7,
|
| 100 | IPA_UC_COMMAND_RESET_PIPE = 0x8,
|
| 101 | IPA_UC_COMMAND_REG_WRITE = 0x9,
|
| 102 | IPA_UC_COMMAND_GSI_CH_EMPTY = 0xa,
|
| 103 | };
|
| 104 |
|
| 105 |
|
| 106 | enum ipa_uc_response {
|
| 107 | IPA_UC_RESPONSE_NO_OP = 0x0,
|
| 108 | IPA_UC_RESPONSE_INIT_COMPLETED = 0x1,
|
| 109 | IPA_UC_RESPONSE_CMD_COMPLETED = 0x2,
|
| 110 | IPA_UC_RESPONSE_DEBUG_GET_INFO = 0x3,
|
| 111 | };
|
| 112 |
|
| 113 |
|
| 114 | enum ipa_uc_event {
|
| 115 | IPA_UC_EVENT_NO_OP = 0x0,
|
| 116 | IPA_UC_EVENT_ERROR = 0x1,
|
| 117 | IPA_UC_EVENT_LOG_INFO = 0x2,
|
| 118 | };
|
| 119 |
|
| 120 | static struct ipa_uc_mem_area *ipa_uc_shared(struct ipa *ipa)
|
| 121 | {
|
| 122 | const struct ipa_mem *mem = ipa_mem_find(ipa, IPA_MEM_UC_SHARED);
|
| 123 | u32 offset = ipa->mem_offset + mem->offset;
|
| 124 |
|
| 125 | return ipa->mem_virt + offset;
|
| 126 | }
|
| 127 |
|
| 128 |
|
| 129 | static void ipa_uc_event_handler(struct ipa *ipa)
|
| 130 | {
|
| 131 | struct ipa_uc_mem_area *shared = ipa_uc_shared(ipa);
|
| 132 | struct device *dev = ipa->dev;
|
| 133 |
|
| 134 | if (shared->event == IPA_UC_EVENT_ERROR)
|
| 135 | dev_err(dev, "microcontroller error event\n");
|
| 136 | else if (shared->event != IPA_UC_EVENT_LOG_INFO)
|
| 137 | dev_err(dev, "unsupported microcontroller event %u\n",
|
| 138 | shared->event);
|
| 139 |
|
| 140 | }
|
| 141 |
|
| 142 |
|
| 143 | static void ipa_uc_response_hdlr(struct ipa *ipa)
|
| 144 | {
|
| 145 | struct ipa_uc_mem_area *shared = ipa_uc_shared(ipa);
|
| 146 | struct device *dev = ipa->dev;
|
| 147 |
|
| 148 | |
| 149 | * microcontroller when it is operational. Other than this, the AP
|
| 150 | * should only receive responses from the microcontroller when it has
|
| 151 | * sent it a request message.
|
| 152 | *
|
| 153 | * We can drop the power reference taken in ipa_uc_power() once we
|
| 154 | * know the microcontroller has finished its initialization.
|
| 155 |
|
| 156 | switch (shared->response) {
|
| 157 | case IPA_UC_RESPONSE_INIT_COMPLETED:
|
| 158 | if (ipa->uc_powered) {
|
| 159 | ipa->uc_loaded = true;
|
| 160 | ipa_power_retention(ipa, true);
|
| 161 | (void)pm_runtime_put_autosuspend(dev);
|
| 162 | ipa->uc_powered = false;
|
| 163 | } else {
|
| 164 | dev_warn(dev, "unexpected init_completed response\n");
|
| 165 | }
|
| 166 | break;
|
| 167 | default:
|
| 168 | dev_warn(dev, "unsupported microcontroller response %u\n",
|
| 169 | shared->response);
|
| 170 | break;
|
| 171 | }
|
| 172 | }
|
| 173 |
|
| 174 | void ipa_uc_interrupt_handler(struct ipa *ipa, enum ipa_irq_id irq_id)
|
| 175 | {
|
| 176 |
|
| 177 | if (irq_id == IPA_IRQ_UC_0)
|
| 178 | ipa_uc_event_handler(ipa);
|
| 179 | else if (irq_id == IPA_IRQ_UC_1)
|
| 180 | ipa_uc_response_hdlr(ipa);
|
| 181 | }
|
| 182 |
|
| 183 |
|
| 184 | void ipa_uc_config(struct ipa *ipa)
|
| 185 | {
|
| 186 | ipa->uc_powered = false;
|
| 187 | ipa->uc_loaded = false;
|
| 188 | ipa_interrupt_enable(ipa, IPA_IRQ_UC_0);
|
| 189 | ipa_interrupt_enable(ipa, IPA_IRQ_UC_1);
|
| 190 | }
|
| 191 |
|
| 192 |
|
| 193 | void ipa_uc_deconfig(struct ipa *ipa)
|
| 194 | {
|
| 195 | struct device *dev = ipa->dev;
|
| 196 |
|
| 197 | ipa_interrupt_disable(ipa, IPA_IRQ_UC_1);
|
| 198 | ipa_interrupt_disable(ipa, IPA_IRQ_UC_0);
|
| 199 | if (ipa->uc_loaded)
|
| 200 | ipa_power_retention(ipa, false);
|
| 201 |
|
| 202 | if (!ipa->uc_powered)
|
| 203 | return;
|
| 204 |
|
| 205 | (void)pm_runtime_put_autosuspend(dev);
|
| 206 | }
|
| 207 |
|
| 208 |
|
| 209 | void ipa_uc_power(struct ipa *ipa)
|
| 210 | {
|
| 211 | struct device *dev = ipa->dev;
|
| 212 | static bool already;
|
| 213 | int ret;
|
| 214 |
|
| 215 | if (already)
|
| 216 | return;
|
| 217 | already = true;
|
| 218 |
|
| 219 |
|
| 220 | ret = pm_runtime_get_sync(dev);
|
| 221 | if (ret < 0) {
|
| 222 | pm_runtime_put_noidle(dev);
|
| 223 | dev_err(dev, "error %d getting proxy power\n", ret);
|
| 224 | } else {
|
| 225 | ipa->uc_powered = true;
|
| 226 | }
|
| 227 | }
|
| 228 |
|
| 229 |
|
| 230 | static void send_uc_command(struct ipa *ipa, u32 command, u32 command_param)
|
| 231 | {
|
| 232 | struct ipa_uc_mem_area *shared = ipa_uc_shared(ipa);
|
| 233 | const struct reg *reg;
|
| 234 | u32 val;
|
| 235 |
|
| 236 |
|
| 237 | shared->command = command;
|
| 238 | shared->command_param = cpu_to_le32(command_param);
|
| 239 | shared->command_param_hi = 0;
|
| 240 | shared->response = 0;
|
| 241 | shared->response_param = 0;
|
| 242 |
|
| 243 |
|
| 244 | reg = ipa_reg(ipa, IPA_IRQ_UC);
|
| 245 | val = reg_bit(reg, UC_INTR);
|
| 246 |
|
| 247 | iowrite32(val, ipa->reg_virt + reg_offset(reg));
|
| 248 | }
|
| 249 |
|
| 250 |
|
| 251 | void ipa_uc_panic_notifier(struct ipa *ipa)
|
| 252 | {
|
| 253 | if (!ipa->uc_loaded)
|
| 254 | return;
|
| 255 |
|
| 256 | send_uc_command(ipa, IPA_UC_COMMAND_ERR_FATAL, 0);
|
| 257 |
|
| 258 |
|
| 259 | udelay(IPA_SEND_DELAY);
|
| 260 | }
|