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1// SPDX-License-Identifier: GPL-2.0
2// Copyright (C) 2018 Microchip Technology
3
4#include <linux/kernel.h>
5#include <linux/module.h>
6#include <linux/delay.h>
7#include <linux/mii.h>
8#include <linux/phy.h>
9#include <linux/sort.h>
10#include <linux/ethtool.h>
11#include <linux/ethtool_netlink.h>
12#include <linux/bitfield.h>
13#include "microchip_rds_ptp.h"
14
15#define PHY_ID_LAN87XX 0x0007c150
16#define PHY_ID_LAN937X 0x0007c180
17#define PHY_ID_LAN887X 0x0007c1f0
18
19#define MCHP_RDS_PTP_LTC_BASE_ADDR 0xe000
20#define MCHP_RDS_PTP_PORT_BASE_ADDR (MCHP_RDS_PTP_LTC_BASE_ADDR + 0x800)
21
22/* External Register Control Register */
23#define LAN87XX_EXT_REG_CTL (0x14)
24#define LAN87XX_EXT_REG_CTL_RD_CTL (0x1000)
25#define LAN87XX_EXT_REG_CTL_WR_CTL (0x0800)
26#define LAN87XX_REG_BANK_SEL_MASK GENMASK(10, 8)
27#define LAN87XX_REG_ADDR_MASK GENMASK(7, 0)
28
29/* External Register Read Data Register */
30#define LAN87XX_EXT_REG_RD_DATA (0x15)
31
32/* External Register Write Data Register */
33#define LAN87XX_EXT_REG_WR_DATA (0x16)
34
35/* Interrupt Source Register */
36#define LAN87XX_INTERRUPT_SOURCE (0x18)
37#define LAN87XX_INTERRUPT_SOURCE_2 (0x08)
38
39/* Interrupt Mask Register */
40#define LAN87XX_INTERRUPT_MASK (0x19)
41#define LAN87XX_MASK_LINK_UP (0x0004)
42#define LAN87XX_MASK_LINK_DOWN (0x0002)
43
44#define LAN87XX_INTERRUPT_MASK_2 (0x09)
45#define LAN87XX_MASK_COMM_RDY BIT(10)
46
47/* MISC Control 1 Register */
48#define LAN87XX_CTRL_1 (0x11)
49#define LAN87XX_MASK_RGMII_TXC_DLY_EN (0x4000)
50#define LAN87XX_MASK_RGMII_RXC_DLY_EN (0x2000)
51
52/* phyaccess nested types */
53#define PHYACC_ATTR_MODE_READ 0
54#define PHYACC_ATTR_MODE_WRITE 1
55#define PHYACC_ATTR_MODE_MODIFY 2
56#define PHYACC_ATTR_MODE_POLL 3
57
58#define PHYACC_ATTR_BANK_SMI 0
59#define PHYACC_ATTR_BANK_MISC 1
60#define PHYACC_ATTR_BANK_PCS 2
61#define PHYACC_ATTR_BANK_AFE 3
62#define PHYACC_ATTR_BANK_DSP 4
63#define PHYACC_ATTR_BANK_MAX 7
64
65/* measurement defines */
66#define LAN87XX_CABLE_TEST_OK 0
67#define LAN87XX_CABLE_TEST_OPEN 1
68#define LAN87XX_CABLE_TEST_SAME_SHORT 2
69
70/* T1 Registers */
71#define T1_AFE_PORT_CFG1_REG 0x0B
72#define T1_POWER_DOWN_CONTROL_REG 0x1A
73#define T1_SLV_FD_MULT_CFG_REG 0x18
74#define T1_CDR_CFG_PRE_LOCK_REG 0x05
75#define T1_CDR_CFG_POST_LOCK_REG 0x06
76#define T1_LCK_STG2_MUFACT_CFG_REG 0x1A
77#define T1_LCK_STG3_MUFACT_CFG_REG 0x1B
78#define T1_POST_LCK_MUFACT_CFG_REG 0x1C
79#define T1_TX_RX_FIFO_CFG_REG 0x02
80#define T1_TX_LPF_FIR_CFG_REG 0x55
81#define T1_COEF_CLK_PWR_DN_CFG 0x04
82#define T1_COEF_RW_CTL_CFG 0x0D
83#define T1_SQI_CONFIG_REG 0x2E
84#define T1_SQI_CONFIG2_REG 0x4A
85#define T1_DCQ_SQI_REG 0xC3
86#define T1_DCQ_SQI_MSK GENMASK(3, 1)
87#define T1_MDIO_CONTROL2_REG 0x10
88#define T1_INTERRUPT_SOURCE_REG 0x18
89#define T1_INTERRUPT2_SOURCE_REG 0x08
90#define T1_EQ_FD_STG1_FRZ_CFG 0x69
91#define T1_EQ_FD_STG2_FRZ_CFG 0x6A
92#define T1_EQ_FD_STG3_FRZ_CFG 0x6B
93#define T1_EQ_FD_STG4_FRZ_CFG 0x6C
94#define T1_EQ_WT_FD_LCK_FRZ_CFG 0x6D
95#define T1_PST_EQ_LCK_STG1_FRZ_CFG 0x6E
96
97#define T1_MODE_STAT_REG 0x11
98#define T1_LINK_UP_MSK BIT(0)
99
100/* SQI defines */
101#define LAN87XX_MAX_SQI 0x07
102
103/* Chiptop registers */
104#define LAN887X_PMA_EXT_ABILITY_2 0x12
105#define LAN887X_PMA_EXT_ABILITY_2_1000T1 BIT(1)
106#define LAN887X_PMA_EXT_ABILITY_2_100T1 BIT(0)
107
108/* DSP 100M registers */
109#define LAN887x_CDR_CONFIG1_100 0x0405
110#define LAN887x_LOCK1_EQLSR_CONFIG_100 0x0411
111#define LAN887x_SLV_HD_MUFAC_CONFIG_100 0x0417
112#define LAN887x_PLOCK_MUFAC_CONFIG_100 0x041c
113#define LAN887x_PROT_DISABLE_100 0x0425
114#define LAN887x_KF_LOOP_SAT_CONFIG_100 0x0454
115
116/* DSP 1000M registers */
117#define LAN887X_LOCK1_EQLSR_CONFIG 0x0811
118#define LAN887X_LOCK3_EQLSR_CONFIG 0x0813
119#define LAN887X_PROT_DISABLE 0x0825
120#define LAN887X_FFE_GAIN6 0x0843
121#define LAN887X_FFE_GAIN7 0x0844
122#define LAN887X_FFE_GAIN8 0x0845
123#define LAN887X_FFE_GAIN9 0x0846
124#define LAN887X_ECHO_DELAY_CONFIG 0x08ec
125#define LAN887X_FFE_MAX_CONFIG 0x08ee
126
127/* PCS 1000M registers */
128#define LAN887X_SCR_CONFIG_3 0x8043
129#define LAN887X_INFO_FLD_CONFIG_5 0x8048
130
131/* T1 afe registers */
132#define LAN887X_ZQCAL_CONTROL_1 0x8080
133#define LAN887X_AFE_PORT_TESTBUS_CTRL2 0x8089
134#define LAN887X_AFE_PORT_TESTBUS_CTRL4 0x808b
135#define LAN887X_AFE_PORT_TESTBUS_CTRL6 0x808d
136#define LAN887X_TX_AMPLT_1000T1_REG 0x80b0
137#define LAN887X_INIT_COEFF_DFE1_100 0x0422
138
139/* PMA registers */
140#define LAN887X_DSP_PMA_CONTROL 0x810e
141#define LAN887X_DSP_PMA_CONTROL_LNK_SYNC BIT(4)
142
143/* PCS 100M registers */
144#define LAN887X_IDLE_ERR_TIMER_WIN 0x8204
145#define LAN887X_IDLE_ERR_CNT_THRESH 0x8213
146
147/* Misc registers */
148#define LAN887X_REG_REG26 0x001a
149#define LAN887X_REG_REG26_HW_INIT_SEQ_EN BIT(8)
150
151/* Mis registers */
152#define LAN887X_MIS_CFG_REG0 0xa00
153#define LAN887X_MIS_CFG_REG0_RCLKOUT_DIS BIT(5)
154#define LAN887X_MIS_CFG_REG0_MAC_MODE_SEL GENMASK(1, 0)
155
156#define LAN887X_MAC_MODE_RGMII 0x01
157#define LAN887X_MAC_MODE_SGMII 0x03
158
159#define LAN887X_MIS_DLL_CFG_REG0 0xa01
160#define LAN887X_MIS_DLL_CFG_REG1 0xa02
161
162#define LAN887X_MIS_DLL_DELAY_EN BIT(15)
163#define LAN887X_MIS_DLL_EN BIT(0)
164#define LAN887X_MIS_DLL_CONF (LAN887X_MIS_DLL_DELAY_EN |\
165 LAN887X_MIS_DLL_EN)
166
167#define LAN887X_MIS_CFG_REG2 0xa03
168#define LAN887X_MIS_CFG_REG2_FE_LPBK_EN BIT(2)
169
170#define LAN887X_MIS_PKT_STAT_REG0 0xa06
171#define LAN887X_MIS_PKT_STAT_REG1 0xa07
172#define LAN887X_MIS_PKT_STAT_REG3 0xa09
173#define LAN887X_MIS_PKT_STAT_REG4 0xa0a
174#define LAN887X_MIS_PKT_STAT_REG5 0xa0b
175#define LAN887X_MIS_PKT_STAT_REG6 0xa0c
176
177/* Chiptop common registers */
178#define LAN887X_COMMON_LED3_LED2 0xc05
179#define LAN887X_COMMON_LED2_MODE_SEL_MASK GENMASK(4, 0)
180#define LAN887X_LED_LINK_ACT_ANY_SPEED 0x0
181
182/* MX chip top registers */
183#define LAN887X_CHIP_HARD_RST 0xf03e
184#define LAN887X_CHIP_HARD_RST_RESET BIT(0)
185
186#define LAN887X_CHIP_SOFT_RST 0xf03f
187#define LAN887X_CHIP_SOFT_RST_RESET BIT(0)
188
189#define LAN887X_SGMII_CTL 0xf01a
190#define LAN887X_SGMII_CTL_SGMII_MUX_EN BIT(0)
191
192#define LAN887X_SGMII_PCS_CFG 0xf034
193#define LAN887X_SGMII_PCS_CFG_PCS_ENA BIT(9)
194
195#define LAN887X_EFUSE_READ_DAT9 0xf209
196#define LAN887X_EFUSE_READ_DAT9_SGMII_DIS BIT(9)
197#define LAN887X_EFUSE_READ_DAT9_MAC_MODE GENMASK(1, 0)
198
199#define LAN887X_CALIB_CONFIG_100 0x437
200#define LAN887X_CALIB_CONFIG_100_CBL_DIAG_USE_LOCAL_SMPL BIT(5)
201#define LAN887X_CALIB_CONFIG_100_CBL_DIAG_STB_SYNC_MODE BIT(4)
202#define LAN887X_CALIB_CONFIG_100_CBL_DIAG_CLK_ALGN_MODE BIT(3)
203#define LAN887X_CALIB_CONFIG_100_VAL \
204 (LAN887X_CALIB_CONFIG_100_CBL_DIAG_CLK_ALGN_MODE |\
205 LAN887X_CALIB_CONFIG_100_CBL_DIAG_STB_SYNC_MODE |\
206 LAN887X_CALIB_CONFIG_100_CBL_DIAG_USE_LOCAL_SMPL)
207
208#define LAN887X_MAX_PGA_GAIN_100 0x44f
209#define LAN887X_MIN_PGA_GAIN_100 0x450
210#define LAN887X_START_CBL_DIAG_100 0x45a
211#define LAN887X_CBL_DIAG_DONE BIT(1)
212#define LAN887X_CBL_DIAG_START BIT(0)
213#define LAN887X_CBL_DIAG_STOP 0x0
214
215#define LAN887X_CBL_DIAG_TDR_THRESH_100 0x45b
216#define LAN887X_CBL_DIAG_AGC_THRESH_100 0x45c
217#define LAN887X_CBL_DIAG_MIN_WAIT_CONFIG_100 0x45d
218#define LAN887X_CBL_DIAG_MAX_WAIT_CONFIG_100 0x45e
219#define LAN887X_CBL_DIAG_CYC_CONFIG_100 0x45f
220#define LAN887X_CBL_DIAG_TX_PULSE_CONFIG_100 0x460
221#define LAN887X_CBL_DIAG_MIN_PGA_GAIN_100 0x462
222#define LAN887X_CBL_DIAG_AGC_GAIN_100 0x497
223#define LAN887X_CBL_DIAG_POS_PEAK_VALUE_100 0x499
224#define LAN887X_CBL_DIAG_NEG_PEAK_VALUE_100 0x49a
225#define LAN887X_CBL_DIAG_POS_PEAK_TIME_100 0x49c
226#define LAN887X_CBL_DIAG_NEG_PEAK_TIME_100 0x49d
227
228#define MICROCHIP_CABLE_NOISE_MARGIN 20
229#define MICROCHIP_CABLE_TIME_MARGIN 89
230#define MICROCHIP_CABLE_MIN_TIME_DIFF 96
231#define MICROCHIP_CABLE_MAX_TIME_DIFF \
232 (MICROCHIP_CABLE_MIN_TIME_DIFF + MICROCHIP_CABLE_TIME_MARGIN)
233
234#define LAN887X_INT_STS 0xf000
235#define LAN887X_INT_MSK 0xf001
236#define LAN887X_INT_MSK_P1588_MOD_INT_MSK BIT(3)
237#define LAN887X_INT_MSK_T1_PHY_INT_MSK BIT(2)
238#define LAN887X_INT_MSK_LINK_UP_MSK BIT(1)
239#define LAN887X_INT_MSK_LINK_DOWN_MSK BIT(0)
240
241#define LAN887X_MX_CHIP_TOP_REG_CONTROL1 0xF002
242#define LAN887X_MX_CHIP_TOP_REG_CONTROL1_EVT_EN BIT(8)
243
244#define LAN887X_MX_CHIP_TOP_LINK_MSK (LAN887X_INT_MSK_LINK_UP_MSK |\
245 LAN887X_INT_MSK_LINK_DOWN_MSK)
246
247#define LAN887X_MX_CHIP_TOP_ALL_MSK (LAN887X_INT_MSK_T1_PHY_INT_MSK |\
248 LAN887X_MX_CHIP_TOP_LINK_MSK)
249
250#define LAN887X_COEFF_PWR_DN_CONFIG_100 0x0404
251#define LAN887X_COEFF_PWR_DN_CONFIG_100_V 0x16d6
252#define LAN887X_SQI_CONFIG_100 0x042e
253#define LAN887X_SQI_CONFIG_100_V 0x9572
254#define LAN887X_SQI_MSE_100 0x483
255
256#define LAN887X_POKE_PEEK_100 0x040d
257#define LAN887X_POKE_PEEK_100_EN BIT(0)
258
259#define LAN887X_COEFF_MOD_CONFIG 0x080d
260#define LAN887X_COEFF_MOD_CONFIG_DCQ_COEFF_EN BIT(8)
261
262#define LAN887X_DCQ_SQI_STATUS 0x08b2
263
264/* SQI raw samples count */
265#define SQI_SAMPLES 200
266
267/* Samples percentage considered for SQI calculation */
268#define SQI_INLINERS_PERCENT 60
269
270/* Samples count considered for SQI calculation */
271#define SQI_INLIERS_NUM (SQI_SAMPLES * SQI_INLINERS_PERCENT / 100)
272
273/* Start offset of samples */
274#define SQI_INLIERS_START ((SQI_SAMPLES - SQI_INLIERS_NUM) / 2)
275
276/* End offset of samples */
277#define SQI_INLIERS_END (SQI_INLIERS_START + SQI_INLIERS_NUM)
278
279#define DRIVER_AUTHOR "Nisar Sayed <[email protected]>"
280#define DRIVER_DESC "Microchip LAN87XX/LAN937x/LAN887x T1 PHY driver"
281
282/* TEST_MODE_NORMAL: Non-hybrid results to calculate cable status(open/short/ok)
283 * TEST_MODE_HYBRID: Hybrid results to calculate distance to fault
284 */
285enum cable_diag_mode {
286 TEST_MODE_NORMAL,
287 TEST_MODE_HYBRID
288};
289
290/* CD_TEST_INIT: Cable test is initated
291 * CD_TEST_DONE: Cable test is done
292 */
293enum cable_diag_state {
294 CD_TEST_INIT,
295 CD_TEST_DONE
296};
297
298struct access_ereg_val {
299 u8 mode;
300 u8 bank;
301 u8 offset;
302 u16 val;
303 u16 mask;
304};
305
306struct lan887x_hw_stat {
307 const char *string;
308 u8 mmd;
309 u16 reg;
310 u8 bits;
311};
312
313static const struct lan887x_hw_stat lan887x_hw_stats[] = {
314 { "TX Good Count", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG0, 14},
315 { "RX Good Count", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG1, 14},
316 { "RX ERR Count detected by PCS", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG3, 16},
317 { "TX CRC ERR Count", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG4, 8},
318 { "RX CRC ERR Count", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG5, 8},
319 { "RX ERR Count for SGMII MII2GMII", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG6, 8},
320};
321
322struct lan887x_regwr_map {
323 u8 mmd;
324 u16 reg;
325 u16 val;
326};
327
328struct lan887x_priv {
329 u64 stats[ARRAY_SIZE(lan887x_hw_stats)];
330 struct mchp_rds_ptp_clock *clock;
331 bool init_done;
332};
333
334static int lan937x_dsp_workaround(struct phy_device *phydev, u16 ereg, u8 bank)
335{
336 u8 prev_bank;
337 int rc = 0;
338 u16 val;
339
340 mutex_lock(&phydev->lock);
341 /* Read previous selected bank */
342 rc = phy_read(phydev, LAN87XX_EXT_REG_CTL);
343 if (rc < 0)
344 goto out_unlock;
345
346 /* store the prev_bank */
347 prev_bank = FIELD_GET(LAN87XX_REG_BANK_SEL_MASK, rc);
348
349 if (bank != prev_bank && bank == PHYACC_ATTR_BANK_DSP) {
350 val = ereg & ~LAN87XX_REG_ADDR_MASK;
351
352 val &= ~LAN87XX_EXT_REG_CTL_WR_CTL;
353 val |= LAN87XX_EXT_REG_CTL_RD_CTL;
354
355 /* access twice for DSP bank change,dummy access */
356 rc = phy_write(phydev, LAN87XX_EXT_REG_CTL, val);
357 }
358
359out_unlock:
360 mutex_unlock(&phydev->lock);
361
362 return rc;
363}
364
365static int access_ereg(struct phy_device *phydev, u8 mode, u8 bank,
366 u8 offset, u16 val)
367{
368 u16 ereg = 0;
369 int rc = 0;
370
371 if (mode > PHYACC_ATTR_MODE_WRITE || bank > PHYACC_ATTR_BANK_MAX)
372 return -EINVAL;
373
374 if (bank == PHYACC_ATTR_BANK_SMI) {
375 if (mode == PHYACC_ATTR_MODE_WRITE)
376 rc = phy_write(phydev, offset, val);
377 else
378 rc = phy_read(phydev, offset);
379 return rc;
380 }
381
382 if (mode == PHYACC_ATTR_MODE_WRITE) {
383 ereg = LAN87XX_EXT_REG_CTL_WR_CTL;
384 rc = phy_write(phydev, LAN87XX_EXT_REG_WR_DATA, val);
385 if (rc < 0)
386 return rc;
387 } else {
388 ereg = LAN87XX_EXT_REG_CTL_RD_CTL;
389 }
390
391 ereg |= (bank << 8) | offset;
392
393 /* DSP bank access workaround for lan937x */
394 if (phydev->phy_id == PHY_ID_LAN937X) {
395 rc = lan937x_dsp_workaround(phydev, ereg, bank);
396 if (rc < 0)
397 return rc;
398 }
399
400 rc = phy_write(phydev, LAN87XX_EXT_REG_CTL, ereg);
401 if (rc < 0)
402 return rc;
403
404 if (mode == PHYACC_ATTR_MODE_READ)
405 rc = phy_read(phydev, LAN87XX_EXT_REG_RD_DATA);
406
407 return rc;
408}
409
410static int access_ereg_modify_changed(struct phy_device *phydev,
411 u8 bank, u8 offset, u16 val, u16 mask)
412{
413 int new = 0, rc = 0;
414
415 if (bank > PHYACC_ATTR_BANK_MAX)
416 return -EINVAL;
417
418 rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ, bank, offset, val);
419 if (rc < 0)
420 return rc;
421
422 new = val | (rc & (mask ^ 0xFFFF));
423 rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE, bank, offset, new);
424
425 return rc;
426}
427
428static int access_smi_poll_timeout(struct phy_device *phydev,
429 u8 offset, u16 mask, u16 clr)
430{
431 int val;
432
433 return phy_read_poll_timeout(phydev, offset, val, (val & mask) == clr,
434 150, 30000, true);
435}
436
437static int lan87xx_config_rgmii_delay(struct phy_device *phydev)
438{
439 int rc;
440
441 if (!phy_interface_is_rgmii(phydev))
442 return 0;
443
444 rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ,
445 PHYACC_ATTR_BANK_MISC, LAN87XX_CTRL_1, 0);
446 if (rc < 0)
447 return rc;
448
449 switch (phydev->interface) {
450 case PHY_INTERFACE_MODE_RGMII:
451 rc &= ~LAN87XX_MASK_RGMII_TXC_DLY_EN;
452 rc &= ~LAN87XX_MASK_RGMII_RXC_DLY_EN;
453 break;
454 case PHY_INTERFACE_MODE_RGMII_ID:
455 rc |= LAN87XX_MASK_RGMII_TXC_DLY_EN;
456 rc |= LAN87XX_MASK_RGMII_RXC_DLY_EN;
457 break;
458 case PHY_INTERFACE_MODE_RGMII_RXID:
459 rc &= ~LAN87XX_MASK_RGMII_TXC_DLY_EN;
460 rc |= LAN87XX_MASK_RGMII_RXC_DLY_EN;
461 break;
462 case PHY_INTERFACE_MODE_RGMII_TXID:
463 rc |= LAN87XX_MASK_RGMII_TXC_DLY_EN;
464 rc &= ~LAN87XX_MASK_RGMII_RXC_DLY_EN;
465 break;
466 default:
467 return 0;
468 }
469
470 return access_ereg(phydev, PHYACC_ATTR_MODE_WRITE,
471 PHYACC_ATTR_BANK_MISC, LAN87XX_CTRL_1, rc);
472}
473
474static int lan87xx_phy_init_cmd(struct phy_device *phydev,
475 const struct access_ereg_val *cmd_seq, int cnt)
476{
477 int ret, i;
478
479 for (i = 0; i < cnt; i++) {
480 if (cmd_seq[i].mode == PHYACC_ATTR_MODE_POLL &&
481 cmd_seq[i].bank == PHYACC_ATTR_BANK_SMI) {
482 ret = access_smi_poll_timeout(phydev,
483 cmd_seq[i].offset,
484 cmd_seq[i].val,
485 cmd_seq[i].mask);
486 } else {
487 ret = access_ereg(phydev, cmd_seq[i].mode,
488 cmd_seq[i].bank, cmd_seq[i].offset,
489 cmd_seq[i].val);
490 }
491 if (ret < 0)
492 return ret;
493 }
494
495 return ret;
496}
497
498static int lan87xx_phy_init(struct phy_device *phydev)
499{
500 static const struct access_ereg_val hw_init[] = {
501 /* TXPD/TXAMP6 Configs */
502 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_AFE,
503 T1_AFE_PORT_CFG1_REG, 0x002D, 0 },
504 /* HW_Init Hi and Force_ED */
505 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_SMI,
506 T1_POWER_DOWN_CONTROL_REG, 0x0308, 0 },
507 };
508
509 static const struct access_ereg_val slave_init[] = {
510 /* Equalizer Full Duplex Freeze - T1 Slave */
511 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
512 T1_EQ_FD_STG1_FRZ_CFG, 0x0002, 0 },
513 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
514 T1_EQ_FD_STG2_FRZ_CFG, 0x0002, 0 },
515 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
516 T1_EQ_FD_STG3_FRZ_CFG, 0x0002, 0 },
517 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
518 T1_EQ_FD_STG4_FRZ_CFG, 0x0002, 0 },
519 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
520 T1_EQ_WT_FD_LCK_FRZ_CFG, 0x0002, 0 },
521 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
522 T1_PST_EQ_LCK_STG1_FRZ_CFG, 0x0002, 0 },
523 };
524
525 static const struct access_ereg_val phy_init[] = {
526 /* Slave Full Duplex Multi Configs */
527 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
528 T1_SLV_FD_MULT_CFG_REG, 0x0D53, 0 },
529 /* CDR Pre and Post Lock Configs */
530 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
531 T1_CDR_CFG_PRE_LOCK_REG, 0x0AB2, 0 },
532 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
533 T1_CDR_CFG_POST_LOCK_REG, 0x0AB3, 0 },
534 /* Lock Stage 2-3 Multi Factor Config */
535 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
536 T1_LCK_STG2_MUFACT_CFG_REG, 0x0AEA, 0 },
537 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
538 T1_LCK_STG3_MUFACT_CFG_REG, 0x0AEB, 0 },
539 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
540 T1_POST_LCK_MUFACT_CFG_REG, 0x0AEB, 0 },
541 /* Pointer delay */
542 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
543 T1_TX_RX_FIFO_CFG_REG, 0x1C00, 0 },
544 /* Tx iir edits */
545 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
546 T1_TX_LPF_FIR_CFG_REG, 0x1000, 0 },
547 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
548 T1_TX_LPF_FIR_CFG_REG, 0x1861, 0 },
549 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
550 T1_TX_LPF_FIR_CFG_REG, 0x1061, 0 },
551 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
552 T1_TX_LPF_FIR_CFG_REG, 0x1922, 0 },
553 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
554 T1_TX_LPF_FIR_CFG_REG, 0x1122, 0 },
555 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
556 T1_TX_LPF_FIR_CFG_REG, 0x1983, 0 },
557 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
558 T1_TX_LPF_FIR_CFG_REG, 0x1183, 0 },
559 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
560 T1_TX_LPF_FIR_CFG_REG, 0x1944, 0 },
561 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
562 T1_TX_LPF_FIR_CFG_REG, 0x1144, 0 },
563 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
564 T1_TX_LPF_FIR_CFG_REG, 0x18c5, 0 },
565 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
566 T1_TX_LPF_FIR_CFG_REG, 0x10c5, 0 },
567 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
568 T1_TX_LPF_FIR_CFG_REG, 0x1846, 0 },
569 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
570 T1_TX_LPF_FIR_CFG_REG, 0x1046, 0 },
571 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
572 T1_TX_LPF_FIR_CFG_REG, 0x1807, 0 },
573 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
574 T1_TX_LPF_FIR_CFG_REG, 0x1007, 0 },
575 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
576 T1_TX_LPF_FIR_CFG_REG, 0x1808, 0 },
577 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
578 T1_TX_LPF_FIR_CFG_REG, 0x1008, 0 },
579 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
580 T1_TX_LPF_FIR_CFG_REG, 0x1809, 0 },
581 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
582 T1_TX_LPF_FIR_CFG_REG, 0x1009, 0 },
583 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
584 T1_TX_LPF_FIR_CFG_REG, 0x180A, 0 },
585 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
586 T1_TX_LPF_FIR_CFG_REG, 0x100A, 0 },
587 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
588 T1_TX_LPF_FIR_CFG_REG, 0x180B, 0 },
589 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
590 T1_TX_LPF_FIR_CFG_REG, 0x100B, 0 },
591 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
592 T1_TX_LPF_FIR_CFG_REG, 0x180C, 0 },
593 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
594 T1_TX_LPF_FIR_CFG_REG, 0x100C, 0 },
595 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
596 T1_TX_LPF_FIR_CFG_REG, 0x180D, 0 },
597 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
598 T1_TX_LPF_FIR_CFG_REG, 0x100D, 0 },
599 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
600 T1_TX_LPF_FIR_CFG_REG, 0x180E, 0 },
601 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
602 T1_TX_LPF_FIR_CFG_REG, 0x100E, 0 },
603 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
604 T1_TX_LPF_FIR_CFG_REG, 0x180F, 0 },
605 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
606 T1_TX_LPF_FIR_CFG_REG, 0x100F, 0 },
607 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
608 T1_TX_LPF_FIR_CFG_REG, 0x1810, 0 },
609 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
610 T1_TX_LPF_FIR_CFG_REG, 0x1010, 0 },
611 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
612 T1_TX_LPF_FIR_CFG_REG, 0x1811, 0 },
613 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
614 T1_TX_LPF_FIR_CFG_REG, 0x1011, 0 },
615 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
616 T1_TX_LPF_FIR_CFG_REG, 0x1000, 0 },
617 /* Setup SQI measurement */
618 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
619 T1_COEF_CLK_PWR_DN_CFG, 0x16d6, 0 },
620 /* SQI enable */
621 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
622 T1_SQI_CONFIG_REG, 0x9572, 0 },
623 /* SQI select mode 5 */
624 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
625 T1_SQI_CONFIG2_REG, 0x0001, 0 },
626 /* Throws the first SQI reading */
627 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
628 T1_COEF_RW_CTL_CFG, 0x0301, 0 },
629 { PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_DSP,
630 T1_DCQ_SQI_REG, 0, 0 },
631 /* Flag LPS and WUR as idle errors */
632 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_SMI,
633 T1_MDIO_CONTROL2_REG, 0x0014, 0 },
634 /* HW_Init toggle, undo force ED, TXPD off */
635 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_SMI,
636 T1_POWER_DOWN_CONTROL_REG, 0x0200, 0 },
637 /* Reset PCS to trigger hardware initialization */
638 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_SMI,
639 T1_MDIO_CONTROL2_REG, 0x0094, 0 },
640 /* Poll till Hardware is initialized */
641 { PHYACC_ATTR_MODE_POLL, PHYACC_ATTR_BANK_SMI,
642 T1_MDIO_CONTROL2_REG, 0x0080, 0 },
643 /* Tx AMP - 0x06 */
644 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_AFE,
645 T1_AFE_PORT_CFG1_REG, 0x000C, 0 },
646 /* Read INTERRUPT_SOURCE Register */
647 { PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_SMI,
648 T1_INTERRUPT_SOURCE_REG, 0, 0 },
649 /* Read INTERRUPT_SOURCE Register */
650 { PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_MISC,
651 T1_INTERRUPT2_SOURCE_REG, 0, 0 },
652 /* HW_Init Hi */
653 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_SMI,
654 T1_POWER_DOWN_CONTROL_REG, 0x0300, 0 },
655 };
656 int rc;
657
658 /* phy Soft reset */
659 rc = genphy_soft_reset(phydev);
660 if (rc < 0)
661 return rc;
662
663 /* PHY Initialization */
664 rc = lan87xx_phy_init_cmd(phydev, hw_init, ARRAY_SIZE(hw_init));
665 if (rc < 0)
666 return rc;
667
668 rc = genphy_read_master_slave(phydev);
669 if (rc)
670 return rc;
671
672 /* The following squence needs to run only if phydev is in
673 * slave mode.
674 */
675 if (phydev->master_slave_state == MASTER_SLAVE_STATE_SLAVE) {
676 rc = lan87xx_phy_init_cmd(phydev, slave_init,
677 ARRAY_SIZE(slave_init));
678 if (rc < 0)
679 return rc;
680 }
681
682 rc = lan87xx_phy_init_cmd(phydev, phy_init, ARRAY_SIZE(phy_init));
683 if (rc < 0)
684 return rc;
685
686 return lan87xx_config_rgmii_delay(phydev);
687}
688
689static int lan87xx_phy_config_intr(struct phy_device *phydev)
690{
691 int rc, val = 0;
692
693 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
694 /* clear all interrupt */
695 rc = phy_write(phydev, LAN87XX_INTERRUPT_MASK, val);
696 if (rc < 0)
697 return rc;
698
699 rc = phy_read(phydev, LAN87XX_INTERRUPT_SOURCE);
700 if (rc < 0)
701 return rc;
702
703 rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE,
704 PHYACC_ATTR_BANK_MISC,
705 LAN87XX_INTERRUPT_MASK_2, val);
706 if (rc < 0)
707 return rc;
708
709 rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ,
710 PHYACC_ATTR_BANK_MISC,
711 LAN87XX_INTERRUPT_SOURCE_2, 0);
712 if (rc < 0)
713 return rc;
714
715 /* enable link down and comm ready interrupt */
716 val = LAN87XX_MASK_LINK_DOWN;
717 rc = phy_write(phydev, LAN87XX_INTERRUPT_MASK, val);
718 if (rc < 0)
719 return rc;
720
721 val = LAN87XX_MASK_COMM_RDY;
722 rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE,
723 PHYACC_ATTR_BANK_MISC,
724 LAN87XX_INTERRUPT_MASK_2, val);
725 } else {
726 rc = phy_write(phydev, LAN87XX_INTERRUPT_MASK, val);
727 if (rc < 0)
728 return rc;
729
730 rc = phy_read(phydev, LAN87XX_INTERRUPT_SOURCE);
731 if (rc < 0)
732 return rc;
733
734 rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE,
735 PHYACC_ATTR_BANK_MISC,
736 LAN87XX_INTERRUPT_MASK_2, val);
737 if (rc < 0)
738 return rc;
739
740 rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ,
741 PHYACC_ATTR_BANK_MISC,
742 LAN87XX_INTERRUPT_SOURCE_2, 0);
743 }
744
745 return rc < 0 ? rc : 0;
746}
747
748static irqreturn_t lan87xx_handle_interrupt(struct phy_device *phydev)
749{
750 int irq_status;
751
752 irq_status = access_ereg(phydev, PHYACC_ATTR_MODE_READ,
753 PHYACC_ATTR_BANK_MISC,
754 LAN87XX_INTERRUPT_SOURCE_2, 0);
755 if (irq_status < 0) {
756 phy_error(phydev);
757 return IRQ_NONE;
758 }
759
760 irq_status = phy_read(phydev, LAN87XX_INTERRUPT_SOURCE);
761 if (irq_status < 0) {
762 phy_error(phydev);
763 return IRQ_NONE;
764 }
765
766 if (irq_status == 0)
767 return IRQ_NONE;
768
769 phy_trigger_machine(phydev);
770
771 return IRQ_HANDLED;
772}
773
774static int lan87xx_config_init(struct phy_device *phydev)
775{
776 int rc = lan87xx_phy_init(phydev);
777
778 return rc < 0 ? rc : 0;
779}
780
781static int microchip_cable_test_start_common(struct phy_device *phydev)
782{
783 int bmcr, bmsr, ret;
784
785 /* If auto-negotiation is enabled, but not complete, the cable
786 * test never completes. So disable auto-neg.
787 */
788 bmcr = phy_read(phydev, MII_BMCR);
789 if (bmcr < 0)
790 return bmcr;
791
792 bmsr = phy_read(phydev, MII_BMSR);
793
794 if (bmsr < 0)
795 return bmsr;
796
797 if (bmcr & BMCR_ANENABLE) {
798 ret = phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0);
799 if (ret < 0)
800 return ret;
801 ret = genphy_soft_reset(phydev);
802 if (ret < 0)
803 return ret;
804 }
805
806 /* If the link is up, allow it some time to go down */
807 if (bmsr & BMSR_LSTATUS)
808 msleep(1500);
809
810 return 0;
811}
812
813static int lan87xx_cable_test_start(struct phy_device *phydev)
814{
815 static const struct access_ereg_val cable_test[] = {
816 /* min wait */
817 {PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 93,
818 0, 0},
819 /* max wait */
820 {PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 94,
821 10, 0},
822 /* pulse cycle */
823 {PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 95,
824 90, 0},
825 /* cable diag thresh */
826 {PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 92,
827 60, 0},
828 /* max gain */
829 {PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 79,
830 31, 0},
831 /* clock align for each iteration */
832 {PHYACC_ATTR_MODE_MODIFY, PHYACC_ATTR_BANK_DSP, 55,
833 0, 0x0038},
834 /* max cycle wait config */
835 {PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 94,
836 70, 0},
837 /* start cable diag*/
838 {PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 90,
839 1, 0},
840 };
841 int rc, i;
842
843 rc = microchip_cable_test_start_common(phydev);
844 if (rc < 0)
845 return rc;
846
847 /* start cable diag */
848 /* check if part is alive - if not, return diagnostic error */
849 rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_SMI,
850 0x00, 0);
851 if (rc < 0)
852 return rc;
853
854 /* master/slave specific configs */
855 rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_SMI,
856 0x0A, 0);
857 if (rc < 0)
858 return rc;
859
860 if ((rc & 0x4000) != 0x4000) {
861 /* DUT is Slave */
862 rc = access_ereg_modify_changed(phydev, PHYACC_ATTR_BANK_AFE,
863 0x0E, 0x5, 0x7);
864 if (rc < 0)
865 return rc;
866 rc = access_ereg_modify_changed(phydev, PHYACC_ATTR_BANK_SMI,
867 0x1A, 0x8, 0x8);
868 if (rc < 0)
869 return rc;
870 } else {
871 /* DUT is Master */
872 rc = access_ereg_modify_changed(phydev, PHYACC_ATTR_BANK_SMI,
873 0x10, 0x8, 0x40);
874 if (rc < 0)
875 return rc;
876 }
877
878 for (i = 0; i < ARRAY_SIZE(cable_test); i++) {
879 if (cable_test[i].mode == PHYACC_ATTR_MODE_MODIFY) {
880 rc = access_ereg_modify_changed(phydev,
881 cable_test[i].bank,
882 cable_test[i].offset,
883 cable_test[i].val,
884 cable_test[i].mask);
885 /* wait 50ms */
886 msleep(50);
887 } else {
888 rc = access_ereg(phydev, cable_test[i].mode,
889 cable_test[i].bank,
890 cable_test[i].offset,
891 cable_test[i].val);
892 }
893 if (rc < 0)
894 return rc;
895 }
896 /* cable diag started */
897
898 return 0;
899}
900
901static int lan87xx_cable_test_report_trans(u32 result)
902{
903 switch (result) {
904 case LAN87XX_CABLE_TEST_OK:
905 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
906 case LAN87XX_CABLE_TEST_OPEN:
907 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
908 case LAN87XX_CABLE_TEST_SAME_SHORT:
909 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
910 default:
911 /* DIAGNOSTIC_ERROR */
912 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
913 }
914}
915
916static int lan87xx_cable_test_report(struct phy_device *phydev)
917{
918 int pos_peak_cycle = 0, pos_peak_in_phases = 0, pos_peak_phase = 0;
919 int neg_peak_cycle = 0, neg_peak_in_phases = 0, neg_peak_phase = 0;
920 int noise_margin = 20, time_margin = 89, jitter_var = 30;
921 int min_time_diff = 96, max_time_diff = 96 + time_margin;
922 bool fault = false, check_a = false, check_b = false;
923 int gain_idx = 0, pos_peak = 0, neg_peak = 0;
924 int pos_peak_time = 0, neg_peak_time = 0;
925 int pos_peak_in_phases_hybrid = 0;
926 int detect = -1;
927
928 gain_idx = access_ereg(phydev, PHYACC_ATTR_MODE_READ,
929 PHYACC_ATTR_BANK_DSP, 151, 0);
930 /* read non-hybrid results */
931 pos_peak = access_ereg(phydev, PHYACC_ATTR_MODE_READ,
932 PHYACC_ATTR_BANK_DSP, 153, 0);
933 neg_peak = access_ereg(phydev, PHYACC_ATTR_MODE_READ,
934 PHYACC_ATTR_BANK_DSP, 154, 0);
935 pos_peak_time = access_ereg(phydev, PHYACC_ATTR_MODE_READ,
936 PHYACC_ATTR_BANK_DSP, 156, 0);
937 neg_peak_time = access_ereg(phydev, PHYACC_ATTR_MODE_READ,
938 PHYACC_ATTR_BANK_DSP, 157, 0);
939
940 pos_peak_cycle = (pos_peak_time >> 7) & 0x7F;
941 /* calculate non-hybrid values */
942 pos_peak_phase = pos_peak_time & 0x7F;
943 pos_peak_in_phases = (pos_peak_cycle * 96) + pos_peak_phase;
944 neg_peak_cycle = (neg_peak_time >> 7) & 0x7F;
945 neg_peak_phase = neg_peak_time & 0x7F;
946 neg_peak_in_phases = (neg_peak_cycle * 96) + neg_peak_phase;
947
948 /* process values */
949 check_a =
950 ((pos_peak_in_phases - neg_peak_in_phases) >= min_time_diff) &&
951 ((pos_peak_in_phases - neg_peak_in_phases) < max_time_diff) &&
952 pos_peak_in_phases_hybrid < pos_peak_in_phases &&
953 (pos_peak_in_phases_hybrid < (neg_peak_in_phases + jitter_var));
954 check_b =
955 ((neg_peak_in_phases - pos_peak_in_phases) >= min_time_diff) &&
956 ((neg_peak_in_phases - pos_peak_in_phases) < max_time_diff) &&
957 pos_peak_in_phases_hybrid < neg_peak_in_phases &&
958 (pos_peak_in_phases_hybrid < (pos_peak_in_phases + jitter_var));
959
960 if (pos_peak_in_phases > neg_peak_in_phases && check_a)
961 detect = 2;
962 else if ((neg_peak_in_phases > pos_peak_in_phases) && check_b)
963 detect = 1;
964
965 if (pos_peak > noise_margin && neg_peak > noise_margin &&
966 gain_idx >= 0) {
967 if (detect == 1 || detect == 2)
968 fault = true;
969 }
970
971 if (!fault)
972 detect = 0;
973
974 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A,
975 lan87xx_cable_test_report_trans(detect));
976
977 return phy_init_hw(phydev);
978}
979
980static int lan87xx_cable_test_get_status(struct phy_device *phydev,
981 bool *finished)
982{
983 int rc = 0;
984
985 *finished = false;
986
987 /* check if cable diag was finished */
988 rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_DSP,
989 90, 0);
990 if (rc < 0)
991 return rc;
992
993 if ((rc & 2) == 2) {
994 /* stop cable diag*/
995 rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE,
996 PHYACC_ATTR_BANK_DSP,
997 90, 0);
998 if (rc < 0)
999 return rc;
1000
1001 *finished = true;
1002
1003 return lan87xx_cable_test_report(phydev);
1004 }
1005
1006 return 0;
1007}
1008
1009static int lan87xx_read_status(struct phy_device *phydev)
1010{
1011 int rc = 0;
1012
1013 rc = phy_read(phydev, T1_MODE_STAT_REG);
1014 if (rc < 0)
1015 return rc;
1016
1017 if (rc & T1_LINK_UP_MSK)
1018 phydev->link = 1;
1019 else
1020 phydev->link = 0;
1021
1022 phydev->speed = SPEED_UNKNOWN;
1023 phydev->duplex = DUPLEX_UNKNOWN;
1024 phydev->pause = 0;
1025 phydev->asym_pause = 0;
1026
1027 rc = genphy_read_master_slave(phydev);
1028 if (rc < 0)
1029 return rc;
1030
1031 return genphy_read_status_fixed(phydev);
1032}
1033
1034static int lan87xx_config_aneg(struct phy_device *phydev)
1035{
1036 u16 ctl = 0;
1037 int ret;
1038
1039 switch (phydev->master_slave_set) {
1040 case MASTER_SLAVE_CFG_MASTER_FORCE:
1041 ctl |= CTL1000_AS_MASTER;
1042 break;
1043 case MASTER_SLAVE_CFG_SLAVE_FORCE:
1044 break;
1045 case MASTER_SLAVE_CFG_UNKNOWN:
1046 case MASTER_SLAVE_CFG_UNSUPPORTED:
1047 return 0;
1048 default:
1049 phydev_warn(phydev, "Unsupported Master/Slave mode\n");
1050 return -EOPNOTSUPP;
1051 }
1052
1053 ret = phy_modify_changed(phydev, MII_CTRL1000, CTL1000_AS_MASTER, ctl);
1054 if (ret == 1)
1055 return phy_init_hw(phydev);
1056
1057 return ret;
1058}
1059
1060static int lan87xx_get_sqi(struct phy_device *phydev)
1061{
1062 u8 sqi_value = 0;
1063 int rc;
1064
1065 rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE,
1066 PHYACC_ATTR_BANK_DSP, T1_COEF_RW_CTL_CFG, 0x0301);
1067 if (rc < 0)
1068 return rc;
1069
1070 rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ,
1071 PHYACC_ATTR_BANK_DSP, T1_DCQ_SQI_REG, 0x0);
1072 if (rc < 0)
1073 return rc;
1074
1075 sqi_value = FIELD_GET(T1_DCQ_SQI_MSK, rc);
1076
1077 return sqi_value;
1078}
1079
1080static int lan87xx_get_sqi_max(struct phy_device *phydev)
1081{
1082 return LAN87XX_MAX_SQI;
1083}
1084
1085static int lan887x_rgmii_init(struct phy_device *phydev)
1086{
1087 int ret;
1088
1089 /* SGMII mux disable */
1090 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
1091 LAN887X_SGMII_CTL,
1092 LAN887X_SGMII_CTL_SGMII_MUX_EN);
1093 if (ret < 0)
1094 return ret;
1095
1096 /* Select MAC_MODE as RGMII */
1097 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_CFG_REG0,
1098 LAN887X_MIS_CFG_REG0_MAC_MODE_SEL,
1099 LAN887X_MAC_MODE_RGMII);
1100 if (ret < 0)
1101 return ret;
1102
1103 /* Disable PCS */
1104 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
1105 LAN887X_SGMII_PCS_CFG,
1106 LAN887X_SGMII_PCS_CFG_PCS_ENA);
1107 if (ret < 0)
1108 return ret;
1109
1110 /* LAN887x Errata: RGMII rx clock active in SGMII mode
1111 * Disabled it for SGMII mode
1112 * Re-enabling it for RGMII mode
1113 */
1114 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
1115 LAN887X_MIS_CFG_REG0,
1116 LAN887X_MIS_CFG_REG0_RCLKOUT_DIS);
1117}
1118
1119static int lan887x_sgmii_init(struct phy_device *phydev)
1120{
1121 int ret;
1122
1123 /* SGMII mux enable */
1124 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
1125 LAN887X_SGMII_CTL,
1126 LAN887X_SGMII_CTL_SGMII_MUX_EN);
1127 if (ret < 0)
1128 return ret;
1129
1130 /* Select MAC_MODE as SGMII */
1131 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_CFG_REG0,
1132 LAN887X_MIS_CFG_REG0_MAC_MODE_SEL,
1133 LAN887X_MAC_MODE_SGMII);
1134 if (ret < 0)
1135 return ret;
1136
1137 /* LAN887x Errata: RGMII rx clock active in SGMII mode.
1138 * So disabling it for SGMII mode
1139 */
1140 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_CFG_REG0,
1141 LAN887X_MIS_CFG_REG0_RCLKOUT_DIS);
1142 if (ret < 0)
1143 return ret;
1144
1145 /* Enable PCS */
1146 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, LAN887X_SGMII_PCS_CFG,
1147 LAN887X_SGMII_PCS_CFG_PCS_ENA);
1148}
1149
1150static int lan887x_config_rgmii_en(struct phy_device *phydev)
1151{
1152 int txc;
1153 int rxc;
1154 int ret;
1155
1156 ret = lan887x_rgmii_init(phydev);
1157 if (ret < 0)
1158 return ret;
1159
1160 /* Control bit to enable/disable TX DLL delay line in signal path */
1161 txc = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_DLL_CFG_REG0);
1162 if (txc < 0)
1163 return txc;
1164
1165 /* Control bit to enable/disable RX DLL delay line in signal path */
1166 rxc = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_DLL_CFG_REG1);
1167 if (rxc < 0)
1168 return rxc;
1169
1170 /* Configures the phy to enable RX/TX delay
1171 * RGMII - TX & RX delays are either added by MAC or not needed,
1172 * phy should not add
1173 * RGMII_ID - Configures phy to enable TX & RX delays, MAC shouldn't add
1174 * RGMII_RX_ID - Configures the PHY to enable the RX delay.
1175 * The MAC shouldn't add the RX delay
1176 * RGMII_TX_ID - Configures the PHY to enable the TX delay.
1177 * The MAC shouldn't add the TX delay in this case
1178 */
1179 switch (phydev->interface) {
1180 case PHY_INTERFACE_MODE_RGMII:
1181 txc &= ~LAN887X_MIS_DLL_CONF;
1182 rxc &= ~LAN887X_MIS_DLL_CONF;
1183 break;
1184 case PHY_INTERFACE_MODE_RGMII_ID:
1185 txc |= LAN887X_MIS_DLL_CONF;
1186 rxc |= LAN887X_MIS_DLL_CONF;
1187 break;
1188 case PHY_INTERFACE_MODE_RGMII_RXID:
1189 txc &= ~LAN887X_MIS_DLL_CONF;
1190 rxc |= LAN887X_MIS_DLL_CONF;
1191 break;
1192 case PHY_INTERFACE_MODE_RGMII_TXID:
1193 txc |= LAN887X_MIS_DLL_CONF;
1194 rxc &= ~LAN887X_MIS_DLL_CONF;
1195 break;
1196 default:
1197 WARN_ONCE(1, "Invalid phydev interface %d\n", phydev->interface);
1198 return 0;
1199 }
1200
1201 /* Configures the PHY to enable/disable RX delay in signal path */
1202 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_DLL_CFG_REG1,
1203 LAN887X_MIS_DLL_CONF, rxc);
1204 if (ret < 0)
1205 return ret;
1206
1207 /* Configures the PHY to enable/disable the TX delay in signal path */
1208 return phy_modify_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_DLL_CFG_REG0,
1209 LAN887X_MIS_DLL_CONF, txc);
1210}
1211
1212static int lan887x_config_phy_interface(struct phy_device *phydev)
1213{
1214 int interface_mode;
1215 int sgmii_dis;
1216 int ret;
1217
1218 /* Read sku efuse data for interfaces supported by sku */
1219 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_EFUSE_READ_DAT9);
1220 if (ret < 0)
1221 return ret;
1222
1223 /* If interface_mode is 1 then efuse sets RGMII operations.
1224 * If interface mode is 3 then efuse sets SGMII operations.
1225 */
1226 interface_mode = ret & LAN887X_EFUSE_READ_DAT9_MAC_MODE;
1227 /* SGMII disable is set for RGMII operations */
1228 sgmii_dis = ret & LAN887X_EFUSE_READ_DAT9_SGMII_DIS;
1229
1230 switch (phydev->interface) {
1231 case PHY_INTERFACE_MODE_RGMII:
1232 case PHY_INTERFACE_MODE_RGMII_ID:
1233 case PHY_INTERFACE_MODE_RGMII_RXID:
1234 case PHY_INTERFACE_MODE_RGMII_TXID:
1235 /* Reject RGMII settings for SGMII only sku */
1236 ret = -EOPNOTSUPP;
1237
1238 if (!((interface_mode & LAN887X_MAC_MODE_SGMII) ==
1239 LAN887X_MAC_MODE_SGMII))
1240 ret = lan887x_config_rgmii_en(phydev);
1241 break;
1242 case PHY_INTERFACE_MODE_SGMII:
1243 /* Reject SGMII setting for RGMII only sku */
1244 ret = -EOPNOTSUPP;
1245
1246 if (!sgmii_dis)
1247 ret = lan887x_sgmii_init(phydev);
1248 break;
1249 default:
1250 /* Reject setting for unsupported interfaces */
1251 ret = -EOPNOTSUPP;
1252 }
1253
1254 return ret;
1255}
1256
1257static int lan887x_get_features(struct phy_device *phydev)
1258{
1259 int ret;
1260
1261 ret = genphy_c45_pma_read_abilities(phydev);
1262 if (ret < 0)
1263 return ret;
1264
1265 /* Enable twisted pair */
1266 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, phydev->supported);
1267
1268 /* First patch only supports 100Mbps and 1000Mbps force-mode.
1269 * T1 Auto-Negotiation (Clause 98 of IEEE 802.3) will be added later.
1270 */
1271 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);
1272
1273 return 0;
1274}
1275
1276static int lan887x_phy_init(struct phy_device *phydev)
1277{
1278 struct lan887x_priv *priv = phydev->priv;
1279 int ret;
1280
1281 if (!priv->init_done && phy_interrupt_is_valid(phydev)) {
1282 priv->clock = mchp_rds_ptp_probe(phydev, MDIO_MMD_VEND1,
1283 MCHP_RDS_PTP_LTC_BASE_ADDR,
1284 MCHP_RDS_PTP_PORT_BASE_ADDR);
1285 if (IS_ERR(priv->clock))
1286 return PTR_ERR(priv->clock);
1287
1288 /* Enable pin mux for EVT */
1289 phy_modify_mmd(phydev, MDIO_MMD_VEND1,
1290 LAN887X_MX_CHIP_TOP_REG_CONTROL1,
1291 LAN887X_MX_CHIP_TOP_REG_CONTROL1_EVT_EN,
1292 LAN887X_MX_CHIP_TOP_REG_CONTROL1_EVT_EN);
1293
1294 /* Initialize pin numbers specific to PEROUT */
1295 priv->clock->event_pin = 3;
1296
1297 priv->init_done = true;
1298 }
1299
1300 /* Clear loopback */
1301 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
1302 LAN887X_MIS_CFG_REG2,
1303 LAN887X_MIS_CFG_REG2_FE_LPBK_EN);
1304 if (ret < 0)
1305 return ret;
1306
1307 /* Configure default behavior of led to link and activity for any
1308 * speed
1309 */
1310 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1,
1311 LAN887X_COMMON_LED3_LED2,
1312 LAN887X_COMMON_LED2_MODE_SEL_MASK,
1313 LAN887X_LED_LINK_ACT_ANY_SPEED);
1314 if (ret < 0)
1315 return ret;
1316
1317 /* PHY interface setup */
1318 return lan887x_config_phy_interface(phydev);
1319}
1320
1321static int lan887x_phy_config(struct phy_device *phydev,
1322 const struct lan887x_regwr_map *reg_map, int cnt)
1323{
1324 int ret;
1325
1326 for (int i = 0; i < cnt; i++) {
1327 ret = phy_write_mmd(phydev, reg_map[i].mmd,
1328 reg_map[i].reg, reg_map[i].val);
1329 if (ret < 0)
1330 return ret;
1331 }
1332
1333 return 0;
1334}
1335
1336static int lan887x_phy_setup(struct phy_device *phydev)
1337{
1338 static const struct lan887x_regwr_map phy_cfg[] = {
1339 /* PORT_AFE writes */
1340 {MDIO_MMD_PMAPMD, LAN887X_ZQCAL_CONTROL_1, 0x4008},
1341 {MDIO_MMD_PMAPMD, LAN887X_AFE_PORT_TESTBUS_CTRL2, 0x0000},
1342 {MDIO_MMD_PMAPMD, LAN887X_AFE_PORT_TESTBUS_CTRL6, 0x0040},
1343 /* 100T1_PCS_VENDOR writes */
1344 {MDIO_MMD_PCS, LAN887X_IDLE_ERR_CNT_THRESH, 0x0008},
1345 {MDIO_MMD_PCS, LAN887X_IDLE_ERR_TIMER_WIN, 0x800d},
1346 /* 100T1 DSP writes */
1347 {MDIO_MMD_VEND1, LAN887x_CDR_CONFIG1_100, 0x0ab1},
1348 {MDIO_MMD_VEND1, LAN887x_LOCK1_EQLSR_CONFIG_100, 0x5274},
1349 {MDIO_MMD_VEND1, LAN887x_SLV_HD_MUFAC_CONFIG_100, 0x0d74},
1350 {MDIO_MMD_VEND1, LAN887x_PLOCK_MUFAC_CONFIG_100, 0x0aea},
1351 {MDIO_MMD_VEND1, LAN887x_PROT_DISABLE_100, 0x0360},
1352 {MDIO_MMD_VEND1, LAN887x_KF_LOOP_SAT_CONFIG_100, 0x0c30},
1353 /* 1000T1 DSP writes */
1354 {MDIO_MMD_VEND1, LAN887X_LOCK1_EQLSR_CONFIG, 0x2a78},
1355 {MDIO_MMD_VEND1, LAN887X_LOCK3_EQLSR_CONFIG, 0x1368},
1356 {MDIO_MMD_VEND1, LAN887X_PROT_DISABLE, 0x1354},
1357 {MDIO_MMD_VEND1, LAN887X_FFE_GAIN6, 0x3C84},
1358 {MDIO_MMD_VEND1, LAN887X_FFE_GAIN7, 0x3ca5},
1359 {MDIO_MMD_VEND1, LAN887X_FFE_GAIN8, 0x3ca5},
1360 {MDIO_MMD_VEND1, LAN887X_FFE_GAIN9, 0x3ca5},
1361 {MDIO_MMD_VEND1, LAN887X_ECHO_DELAY_CONFIG, 0x0024},
1362 {MDIO_MMD_VEND1, LAN887X_FFE_MAX_CONFIG, 0x227f},
1363 /* 1000T1 PCS writes */
1364 {MDIO_MMD_PCS, LAN887X_SCR_CONFIG_3, 0x1e00},
1365 {MDIO_MMD_PCS, LAN887X_INFO_FLD_CONFIG_5, 0x0fa1},
1366 };
1367
1368 return lan887x_phy_config(phydev, phy_cfg, ARRAY_SIZE(phy_cfg));
1369}
1370
1371static int lan887x_100M_setup(struct phy_device *phydev)
1372{
1373 int ret;
1374
1375 /* (Re)configure the speed/mode dependent T1 settings */
1376 if (phydev->master_slave_set == MASTER_SLAVE_CFG_MASTER_FORCE ||
1377 phydev->master_slave_set == MASTER_SLAVE_CFG_MASTER_PREFERRED){
1378 static const struct lan887x_regwr_map phy_cfg[] = {
1379 {MDIO_MMD_PMAPMD, LAN887X_AFE_PORT_TESTBUS_CTRL4, 0x00b8},
1380 {MDIO_MMD_PMAPMD, LAN887X_TX_AMPLT_1000T1_REG, 0x0038},
1381 {MDIO_MMD_VEND1, LAN887X_INIT_COEFF_DFE1_100, 0x000f},
1382 };
1383
1384 ret = lan887x_phy_config(phydev, phy_cfg, ARRAY_SIZE(phy_cfg));
1385 } else {
1386 static const struct lan887x_regwr_map phy_cfg[] = {
1387 {MDIO_MMD_PMAPMD, LAN887X_AFE_PORT_TESTBUS_CTRL4, 0x0038},
1388 {MDIO_MMD_VEND1, LAN887X_INIT_COEFF_DFE1_100, 0x0014},
1389 };
1390
1391 ret = lan887x_phy_config(phydev, phy_cfg, ARRAY_SIZE(phy_cfg));
1392 }
1393 if (ret < 0)
1394 return ret;
1395
1396 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, LAN887X_REG_REG26,
1397 LAN887X_REG_REG26_HW_INIT_SEQ_EN);
1398}
1399
1400static int lan887x_1000M_setup(struct phy_device *phydev)
1401{
1402 static const struct lan887x_regwr_map phy_cfg[] = {
1403 {MDIO_MMD_PMAPMD, LAN887X_TX_AMPLT_1000T1_REG, 0x003f},
1404 {MDIO_MMD_PMAPMD, LAN887X_AFE_PORT_TESTBUS_CTRL4, 0x00b8},
1405 };
1406 int ret;
1407
1408 /* (Re)configure the speed/mode dependent T1 settings */
1409 ret = lan887x_phy_config(phydev, phy_cfg, ARRAY_SIZE(phy_cfg));
1410 if (ret < 0)
1411 return ret;
1412
1413 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, LAN887X_DSP_PMA_CONTROL,
1414 LAN887X_DSP_PMA_CONTROL_LNK_SYNC);
1415}
1416
1417static int lan887x_link_setup(struct phy_device *phydev)
1418{
1419 int ret = -EINVAL;
1420
1421 if (phydev->speed == SPEED_1000)
1422 ret = lan887x_1000M_setup(phydev);
1423 else if (phydev->speed == SPEED_100)
1424 ret = lan887x_100M_setup(phydev);
1425
1426 return ret;
1427}
1428
1429/* LAN887x Errata: speed configuration changes require soft reset
1430 * and chip soft reset
1431 */
1432static int lan887x_phy_reset(struct phy_device *phydev)
1433{
1434 int ret, val;
1435
1436 /* Clear 1000M link sync */
1437 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, LAN887X_DSP_PMA_CONTROL,
1438 LAN887X_DSP_PMA_CONTROL_LNK_SYNC);
1439 if (ret < 0)
1440 return ret;
1441
1442 /* Clear 100M link sync */
1443 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, LAN887X_REG_REG26,
1444 LAN887X_REG_REG26_HW_INIT_SEQ_EN);
1445 if (ret < 0)
1446 return ret;
1447
1448 /* Chiptop soft-reset to allow the speed/mode change */
1449 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, LAN887X_CHIP_SOFT_RST,
1450 LAN887X_CHIP_SOFT_RST_RESET);
1451 if (ret < 0)
1452 return ret;
1453
1454 /* CL22 soft-reset to let the link re-train */
1455 ret = phy_modify(phydev, MII_BMCR, BMCR_RESET, BMCR_RESET);
1456 if (ret < 0)
1457 return ret;
1458
1459 /* Wait for reset complete or timeout if > 10ms */
1460 return phy_read_poll_timeout(phydev, MII_BMCR, val, !(val & BMCR_RESET),
1461 5000, 10000, true);
1462}
1463
1464static int lan887x_phy_reconfig(struct phy_device *phydev)
1465{
1466 int ret;
1467
1468 linkmode_zero(phydev->advertising);
1469
1470 ret = genphy_c45_pma_setup_forced(phydev);
1471 if (ret < 0)
1472 return ret;
1473
1474 return lan887x_link_setup(phydev);
1475}
1476
1477static int lan887x_config_aneg(struct phy_device *phydev)
1478{
1479 int ret;
1480
1481 /* LAN887x Errata: speed configuration changes require soft reset
1482 * and chip soft reset
1483 */
1484 ret = lan887x_phy_reset(phydev);
1485 if (ret < 0)
1486 return ret;
1487
1488 return lan887x_phy_reconfig(phydev);
1489}
1490
1491static int lan887x_probe(struct phy_device *phydev)
1492{
1493 struct lan887x_priv *priv;
1494
1495 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
1496 if (!priv)
1497 return -ENOMEM;
1498
1499 priv->init_done = false;
1500 phydev->priv = priv;
1501
1502 return lan887x_phy_setup(phydev);
1503}
1504
1505static u64 lan887x_get_stat(struct phy_device *phydev, int i)
1506{
1507 struct lan887x_hw_stat stat = lan887x_hw_stats[i];
1508 struct lan887x_priv *priv = phydev->priv;
1509 int val;
1510 u64 ret;
1511
1512 if (stat.mmd)
1513 val = phy_read_mmd(phydev, stat.mmd, stat.reg);
1514 else
1515 val = phy_read(phydev, stat.reg);
1516
1517 if (val < 0) {
1518 ret = U64_MAX;
1519 } else {
1520 val = val & ((1 << stat.bits) - 1);
1521 priv->stats[i] += val;
1522 ret = priv->stats[i];
1523 }
1524
1525 return ret;
1526}
1527
1528static void lan887x_get_stats(struct phy_device *phydev,
1529 struct ethtool_stats *stats, u64 *data)
1530{
1531 for (int i = 0; i < ARRAY_SIZE(lan887x_hw_stats); i++)
1532 data[i] = lan887x_get_stat(phydev, i);
1533}
1534
1535static int lan887x_get_sset_count(struct phy_device *phydev)
1536{
1537 return ARRAY_SIZE(lan887x_hw_stats);
1538}
1539
1540static void lan887x_get_strings(struct phy_device *phydev, u8 *data)
1541{
1542 for (int i = 0; i < ARRAY_SIZE(lan887x_hw_stats); i++)
1543 ethtool_puts(&data, lan887x_hw_stats[i].string);
1544}
1545
1546static int lan887x_config_intr(struct phy_device *phydev)
1547{
1548 struct lan887x_priv *priv = phydev->priv;
1549 int rc;
1550
1551 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
1552 /* Clear the interrupt status before enabling interrupts */
1553 rc = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_INT_STS);
1554 if (rc < 0)
1555 return rc;
1556
1557 /* Unmask for enabling interrupt */
1558 rc = phy_write_mmd(phydev, MDIO_MMD_VEND1, LAN887X_INT_MSK,
1559 (u16)~LAN887X_MX_CHIP_TOP_ALL_MSK);
1560 } else {
1561 rc = phy_write_mmd(phydev, MDIO_MMD_VEND1, LAN887X_INT_MSK,
1562 GENMASK(15, 0));
1563 if (rc < 0)
1564 return rc;
1565
1566 rc = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_INT_STS);
1567 }
1568 if (rc < 0)
1569 return rc;
1570
1571 if (phy_is_default_hwtstamp(phydev)) {
1572 return mchp_rds_ptp_top_config_intr(priv->clock,
1573 LAN887X_INT_MSK,
1574 LAN887X_INT_MSK_P1588_MOD_INT_MSK,
1575 (phydev->interrupts ==
1576 PHY_INTERRUPT_ENABLED));
1577 }
1578
1579 return 0;
1580}
1581
1582static irqreturn_t lan887x_handle_interrupt(struct phy_device *phydev)
1583{
1584 struct lan887x_priv *priv = phydev->priv;
1585 int rc = IRQ_NONE;
1586 int irq_status;
1587
1588 irq_status = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_INT_STS);
1589 if (irq_status < 0) {
1590 phy_error(phydev);
1591 return IRQ_NONE;
1592 }
1593
1594 if (irq_status & LAN887X_MX_CHIP_TOP_LINK_MSK) {
1595 phy_trigger_machine(phydev);
1596 rc = IRQ_HANDLED;
1597 }
1598
1599 if (irq_status & LAN887X_INT_MSK_P1588_MOD_INT_MSK)
1600 rc = mchp_rds_ptp_handle_interrupt(priv->clock);
1601
1602 return rc;
1603}
1604
1605static int lan887x_cd_reset(struct phy_device *phydev,
1606 enum cable_diag_state cd_done)
1607{
1608 u16 val;
1609 int rc;
1610
1611 /* Chip hard-reset */
1612 rc = phy_write_mmd(phydev, MDIO_MMD_VEND1, LAN887X_CHIP_HARD_RST,
1613 LAN887X_CHIP_HARD_RST_RESET);
1614 if (rc < 0)
1615 return rc;
1616
1617 /* Wait for reset to complete */
1618 rc = phy_read_poll_timeout(phydev, MII_PHYSID2, val,
1619 ((val & GENMASK(15, 4)) ==
1620 (PHY_ID_LAN887X & GENMASK(15, 4))),
1621 5000, 50000, true);
1622 if (rc < 0)
1623 return rc;
1624
1625 if (cd_done == CD_TEST_DONE) {
1626 /* Cable diagnostics complete. Restore PHY. */
1627 rc = lan887x_phy_setup(phydev);
1628 if (rc < 0)
1629 return rc;
1630
1631 rc = lan887x_phy_init(phydev);
1632 if (rc < 0)
1633 return rc;
1634
1635 rc = lan887x_config_intr(phydev);
1636 if (rc < 0)
1637 return rc;
1638
1639 rc = lan887x_phy_reconfig(phydev);
1640 if (rc < 0)
1641 return rc;
1642 }
1643
1644 return 0;
1645}
1646
1647static int lan887x_cable_test_prep(struct phy_device *phydev,
1648 enum cable_diag_mode mode)
1649{
1650 static const struct lan887x_regwr_map values[] = {
1651 {MDIO_MMD_VEND1, LAN887X_MAX_PGA_GAIN_100, 0x1f},
1652 {MDIO_MMD_VEND1, LAN887X_MIN_PGA_GAIN_100, 0x0},
1653 {MDIO_MMD_VEND1, LAN887X_CBL_DIAG_TDR_THRESH_100, 0x1},
1654 {MDIO_MMD_VEND1, LAN887X_CBL_DIAG_AGC_THRESH_100, 0x3c},
1655 {MDIO_MMD_VEND1, LAN887X_CBL_DIAG_MIN_WAIT_CONFIG_100, 0x0},
1656 {MDIO_MMD_VEND1, LAN887X_CBL_DIAG_MAX_WAIT_CONFIG_100, 0x46},
1657 {MDIO_MMD_VEND1, LAN887X_CBL_DIAG_CYC_CONFIG_100, 0x5a},
1658 {MDIO_MMD_VEND1, LAN887X_CBL_DIAG_TX_PULSE_CONFIG_100, 0x44d5},
1659 {MDIO_MMD_VEND1, LAN887X_CBL_DIAG_MIN_PGA_GAIN_100, 0x0},
1660
1661 };
1662 int rc;
1663
1664 rc = lan887x_cd_reset(phydev, CD_TEST_INIT);
1665 if (rc < 0)
1666 return rc;
1667
1668 /* Forcing DUT to master mode, as we don't care about
1669 * mode during diagnostics
1670 */
1671 rc = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL,
1672 MDIO_PMA_PMD_BT1_CTRL_CFG_MST);
1673 if (rc < 0)
1674 return rc;
1675
1676 rc = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, 0x80b0, 0x0038);
1677 if (rc < 0)
1678 return rc;
1679
1680 rc = phy_modify_mmd(phydev, MDIO_MMD_VEND1,
1681 LAN887X_CALIB_CONFIG_100, 0,
1682 LAN887X_CALIB_CONFIG_100_VAL);
1683 if (rc < 0)
1684 return rc;
1685
1686 for (int i = 0; i < ARRAY_SIZE(values); i++) {
1687 rc = phy_write_mmd(phydev, values[i].mmd, values[i].reg,
1688 values[i].val);
1689 if (rc < 0)
1690 return rc;
1691
1692 if (mode &&
1693 values[i].reg == LAN887X_CBL_DIAG_MAX_WAIT_CONFIG_100) {
1694 rc = phy_write_mmd(phydev, values[i].mmd,
1695 values[i].reg, 0xa);
1696 if (rc < 0)
1697 return rc;
1698 }
1699 }
1700
1701 if (mode == TEST_MODE_HYBRID) {
1702 rc = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD,
1703 LAN887X_AFE_PORT_TESTBUS_CTRL4,
1704 BIT(0), BIT(0));
1705 if (rc < 0)
1706 return rc;
1707 }
1708
1709 /* HW_INIT 100T1, Get DUT running in 100T1 mode */
1710 rc = phy_modify_mmd(phydev, MDIO_MMD_VEND1, LAN887X_REG_REG26,
1711 LAN887X_REG_REG26_HW_INIT_SEQ_EN,
1712 LAN887X_REG_REG26_HW_INIT_SEQ_EN);
1713 if (rc < 0)
1714 return rc;
1715
1716 /* Cable diag requires hard reset and is sensitive regarding the delays.
1717 * Hard reset is expected into and out of cable diag.
1718 * Wait for 50ms
1719 */
1720 msleep(50);
1721
1722 /* Start cable diag */
1723 return phy_write_mmd(phydev, MDIO_MMD_VEND1,
1724 LAN887X_START_CBL_DIAG_100,
1725 LAN887X_CBL_DIAG_START);
1726}
1727
1728static int lan887x_cable_test_chk(struct phy_device *phydev,
1729 enum cable_diag_mode mode)
1730{
1731 int val;
1732 int rc;
1733
1734 if (mode == TEST_MODE_HYBRID) {
1735 /* Cable diag requires hard reset and is sensitive regarding the delays.
1736 * Hard reset is expected into and out of cable diag.
1737 * Wait for cable diag to complete.
1738 * Minimum wait time is 50ms if the condition is not a match.
1739 */
1740 rc = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
1741 LAN887X_START_CBL_DIAG_100, val,
1742 ((val & LAN887X_CBL_DIAG_DONE) ==
1743 LAN887X_CBL_DIAG_DONE),
1744 50000, 500000, false);
1745 if (rc < 0)
1746 return rc;
1747 } else {
1748 rc = phy_read_mmd(phydev, MDIO_MMD_VEND1,
1749 LAN887X_START_CBL_DIAG_100);
1750 if (rc < 0)
1751 return rc;
1752
1753 if ((rc & LAN887X_CBL_DIAG_DONE) != LAN887X_CBL_DIAG_DONE)
1754 return -EAGAIN;
1755 }
1756
1757 /* Stop cable diag */
1758 return phy_write_mmd(phydev, MDIO_MMD_VEND1,
1759 LAN887X_START_CBL_DIAG_100,
1760 LAN887X_CBL_DIAG_STOP);
1761}
1762
1763static int lan887x_cable_test_start(struct phy_device *phydev)
1764{
1765 int rc, ret;
1766
1767 rc = lan887x_cable_test_prep(phydev, TEST_MODE_NORMAL);
1768 if (rc < 0) {
1769 ret = lan887x_cd_reset(phydev, CD_TEST_DONE);
1770 if (ret < 0)
1771 return ret;
1772
1773 return rc;
1774 }
1775
1776 return 0;
1777}
1778
1779static int lan887x_cable_test_report(struct phy_device *phydev)
1780{
1781 int pos_peak_cycle, pos_peak_cycle_hybrid, pos_peak_in_phases;
1782 int pos_peak_time, pos_peak_time_hybrid, neg_peak_time;
1783 int neg_peak_cycle, neg_peak_in_phases;
1784 int pos_peak_in_phases_hybrid;
1785 int gain_idx, gain_idx_hybrid;
1786 int pos_peak_phase_hybrid;
1787 int pos_peak, neg_peak;
1788 int distance;
1789 int detect;
1790 int length;
1791 int ret;
1792 int rc;
1793
1794 /* Read non-hybrid results */
1795 gain_idx = phy_read_mmd(phydev, MDIO_MMD_VEND1,
1796 LAN887X_CBL_DIAG_AGC_GAIN_100);
1797 if (gain_idx < 0) {
1798 rc = gain_idx;
1799 goto error;
1800 }
1801
1802 pos_peak = phy_read_mmd(phydev, MDIO_MMD_VEND1,
1803 LAN887X_CBL_DIAG_POS_PEAK_VALUE_100);
1804 if (pos_peak < 0) {
1805 rc = pos_peak;
1806 goto error;
1807 }
1808
1809 neg_peak = phy_read_mmd(phydev, MDIO_MMD_VEND1,
1810 LAN887X_CBL_DIAG_NEG_PEAK_VALUE_100);
1811 if (neg_peak < 0) {
1812 rc = neg_peak;
1813 goto error;
1814 }
1815
1816 pos_peak_time = phy_read_mmd(phydev, MDIO_MMD_VEND1,
1817 LAN887X_CBL_DIAG_POS_PEAK_TIME_100);
1818 if (pos_peak_time < 0) {
1819 rc = pos_peak_time;
1820 goto error;
1821 }
1822
1823 neg_peak_time = phy_read_mmd(phydev, MDIO_MMD_VEND1,
1824 LAN887X_CBL_DIAG_NEG_PEAK_TIME_100);
1825 if (neg_peak_time < 0) {
1826 rc = neg_peak_time;
1827 goto error;
1828 }
1829
1830 /* Calculate non-hybrid values */
1831 pos_peak_cycle = (pos_peak_time >> 7) & 0x7f;
1832 pos_peak_in_phases = (pos_peak_cycle * 96) + (pos_peak_time & 0x7f);
1833 neg_peak_cycle = (neg_peak_time >> 7) & 0x7f;
1834 neg_peak_in_phases = (neg_peak_cycle * 96) + (neg_peak_time & 0x7f);
1835
1836 /* Deriving the status of cable */
1837 if (pos_peak > MICROCHIP_CABLE_NOISE_MARGIN &&
1838 neg_peak > MICROCHIP_CABLE_NOISE_MARGIN && gain_idx >= 0) {
1839 if (pos_peak_in_phases > neg_peak_in_phases &&
1840 ((pos_peak_in_phases - neg_peak_in_phases) >=
1841 MICROCHIP_CABLE_MIN_TIME_DIFF) &&
1842 ((pos_peak_in_phases - neg_peak_in_phases) <
1843 MICROCHIP_CABLE_MAX_TIME_DIFF) &&
1844 pos_peak_in_phases > 0) {
1845 detect = LAN87XX_CABLE_TEST_SAME_SHORT;
1846 } else if (neg_peak_in_phases > pos_peak_in_phases &&
1847 ((neg_peak_in_phases - pos_peak_in_phases) >=
1848 MICROCHIP_CABLE_MIN_TIME_DIFF) &&
1849 ((neg_peak_in_phases - pos_peak_in_phases) <
1850 MICROCHIP_CABLE_MAX_TIME_DIFF) &&
1851 neg_peak_in_phases > 0) {
1852 detect = LAN87XX_CABLE_TEST_OPEN;
1853 } else {
1854 detect = LAN87XX_CABLE_TEST_OK;
1855 }
1856 } else {
1857 detect = LAN87XX_CABLE_TEST_OK;
1858 }
1859
1860 if (detect == LAN87XX_CABLE_TEST_OK) {
1861 distance = 0;
1862 goto get_len;
1863 }
1864
1865 /* Re-initialize PHY and start cable diag test */
1866 rc = lan887x_cable_test_prep(phydev, TEST_MODE_HYBRID);
1867 if (rc < 0)
1868 goto cd_stop;
1869
1870 /* Wait for cable diag test completion */
1871 rc = lan887x_cable_test_chk(phydev, TEST_MODE_HYBRID);
1872 if (rc < 0)
1873 goto cd_stop;
1874
1875 /* Read hybrid results */
1876 gain_idx_hybrid = phy_read_mmd(phydev, MDIO_MMD_VEND1,
1877 LAN887X_CBL_DIAG_AGC_GAIN_100);
1878 if (gain_idx_hybrid < 0) {
1879 rc = gain_idx_hybrid;
1880 goto error;
1881 }
1882
1883 pos_peak_time_hybrid = phy_read_mmd(phydev, MDIO_MMD_VEND1,
1884 LAN887X_CBL_DIAG_POS_PEAK_TIME_100);
1885 if (pos_peak_time_hybrid < 0) {
1886 rc = pos_peak_time_hybrid;
1887 goto error;
1888 }
1889
1890 /* Calculate hybrid values to derive cable length to fault */
1891 pos_peak_cycle_hybrid = (pos_peak_time_hybrid >> 7) & 0x7f;
1892 pos_peak_phase_hybrid = pos_peak_time_hybrid & 0x7f;
1893 pos_peak_in_phases_hybrid = pos_peak_cycle_hybrid * 96 +
1894 pos_peak_phase_hybrid;
1895
1896 /* Distance to fault calculation.
1897 * distance = (peak_in_phases - peak_in_phases_hybrid) *
1898 * propagationconstant.
1899 * constant to convert number of phases to meters
1900 * propagationconstant = 0.015953
1901 * (0.6811 * 2.9979 * 156.2499 * 0.0001 * 0.5)
1902 * Applying constant 1.5953 as ethtool further devides by 100 to
1903 * convert to meters.
1904 */
1905 if (detect == LAN87XX_CABLE_TEST_OPEN) {
1906 distance = (((pos_peak_in_phases - pos_peak_in_phases_hybrid)
1907 * 15953) / 10000);
1908 } else if (detect == LAN87XX_CABLE_TEST_SAME_SHORT) {
1909 distance = (((neg_peak_in_phases - pos_peak_in_phases_hybrid)
1910 * 15953) / 10000);
1911 } else {
1912 distance = 0;
1913 }
1914
1915get_len:
1916 rc = lan887x_cd_reset(phydev, CD_TEST_DONE);
1917 if (rc < 0)
1918 return rc;
1919
1920 length = ((u32)distance & GENMASK(15, 0));
1921 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A,
1922 lan87xx_cable_test_report_trans(detect));
1923 ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_A, length);
1924
1925 return 0;
1926
1927cd_stop:
1928 /* Stop cable diag */
1929 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1,
1930 LAN887X_START_CBL_DIAG_100,
1931 LAN887X_CBL_DIAG_STOP);
1932 if (ret < 0)
1933 return ret;
1934
1935error:
1936 /* Cable diag test failed */
1937 ret = lan887x_cd_reset(phydev, CD_TEST_DONE);
1938 if (ret < 0)
1939 return ret;
1940
1941 /* Return error in failure case */
1942 return rc;
1943}
1944
1945static int lan887x_cable_test_get_status(struct phy_device *phydev,
1946 bool *finished)
1947{
1948 int rc;
1949
1950 rc = lan887x_cable_test_chk(phydev, TEST_MODE_NORMAL);
1951 if (rc < 0) {
1952 /* Let PHY statemachine poll again */
1953 if (rc == -EAGAIN)
1954 return 0;
1955 return rc;
1956 }
1957
1958 /* Cable diag test complete */
1959 *finished = true;
1960
1961 /* Retrieve test status and cable length to fault */
1962 return lan887x_cable_test_report(phydev);
1963}
1964
1965/* Compare block to sort in ascending order */
1966static int sqi_compare(const void *a, const void *b)
1967{
1968 return *(u16 *)a - *(u16 *)b;
1969}
1970
1971static int lan887x_get_sqi_100M(struct phy_device *phydev)
1972{
1973 u16 rawtable[SQI_SAMPLES];
1974 u32 sqiavg = 0;
1975 u8 sqinum = 0;
1976 int rc, i;
1977
1978 /* Configuration of SQI 100M */
1979 rc = phy_write_mmd(phydev, MDIO_MMD_VEND1,
1980 LAN887X_COEFF_PWR_DN_CONFIG_100,
1981 LAN887X_COEFF_PWR_DN_CONFIG_100_V);
1982 if (rc < 0)
1983 return rc;
1984
1985 rc = phy_write_mmd(phydev, MDIO_MMD_VEND1, LAN887X_SQI_CONFIG_100,
1986 LAN887X_SQI_CONFIG_100_V);
1987 if (rc < 0)
1988 return rc;
1989
1990 rc = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_SQI_CONFIG_100);
1991 if (rc != LAN887X_SQI_CONFIG_100_V)
1992 return -EINVAL;
1993
1994 rc = phy_modify_mmd(phydev, MDIO_MMD_VEND1, LAN887X_POKE_PEEK_100,
1995 LAN887X_POKE_PEEK_100_EN,
1996 LAN887X_POKE_PEEK_100_EN);
1997 if (rc < 0)
1998 return rc;
1999
2000 /* Required before reading register
2001 * otherwise it will return high value
2002 */
2003 msleep(50);
2004
2005 /* Link check before raw readings */
2006 rc = genphy_c45_read_link(phydev);
2007 if (rc < 0)
2008 return rc;
2009
2010 if (!phydev->link)
2011 return -ENETDOWN;
2012
2013 /* Get 200 SQI raw readings */
2014 for (i = 0; i < SQI_SAMPLES; i++) {
2015 rc = phy_write_mmd(phydev, MDIO_MMD_VEND1,
2016 LAN887X_POKE_PEEK_100,
2017 LAN887X_POKE_PEEK_100_EN);
2018 if (rc < 0)
2019 return rc;
2020
2021 rc = phy_read_mmd(phydev, MDIO_MMD_VEND1,
2022 LAN887X_SQI_MSE_100);
2023 if (rc < 0)
2024 return rc;
2025
2026 rawtable[i] = (u16)rc;
2027 }
2028
2029 /* Link check after raw readings */
2030 rc = genphy_c45_read_link(phydev);
2031 if (rc < 0)
2032 return rc;
2033
2034 if (!phydev->link)
2035 return -ENETDOWN;
2036
2037 /* Sort SQI raw readings in ascending order */
2038 sort(rawtable, SQI_SAMPLES, sizeof(u16), sqi_compare, NULL);
2039
2040 /* Keep inliers and discard outliers */
2041 for (i = SQI_INLIERS_START; i < SQI_INLIERS_END; i++)
2042 sqiavg += rawtable[i];
2043
2044 /* Handle invalid samples */
2045 if (sqiavg != 0) {
2046 /* Get SQI average */
2047 sqiavg /= SQI_INLIERS_NUM;
2048
2049 if (sqiavg < 75)
2050 sqinum = 7;
2051 else if (sqiavg < 94)
2052 sqinum = 6;
2053 else if (sqiavg < 119)
2054 sqinum = 5;
2055 else if (sqiavg < 150)
2056 sqinum = 4;
2057 else if (sqiavg < 189)
2058 sqinum = 3;
2059 else if (sqiavg < 237)
2060 sqinum = 2;
2061 else if (sqiavg < 299)
2062 sqinum = 1;
2063 else
2064 sqinum = 0;
2065 }
2066
2067 return sqinum;
2068}
2069
2070static int lan887x_get_sqi(struct phy_device *phydev)
2071{
2072 int rc, val;
2073
2074 if (phydev->speed != SPEED_1000 &&
2075 phydev->speed != SPEED_100)
2076 return -ENETDOWN;
2077
2078 if (phydev->speed == SPEED_100)
2079 return lan887x_get_sqi_100M(phydev);
2080
2081 /* Writing DCQ_COEFF_EN to trigger a SQI read */
2082 rc = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
2083 LAN887X_COEFF_MOD_CONFIG,
2084 LAN887X_COEFF_MOD_CONFIG_DCQ_COEFF_EN);
2085 if (rc < 0)
2086 return rc;
2087
2088 /* Wait for DCQ done */
2089 rc = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
2090 LAN887X_COEFF_MOD_CONFIG, val, ((val &
2091 LAN887X_COEFF_MOD_CONFIG_DCQ_COEFF_EN) !=
2092 LAN887X_COEFF_MOD_CONFIG_DCQ_COEFF_EN),
2093 10, 200, true);
2094 if (rc < 0)
2095 return rc;
2096
2097 rc = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_DCQ_SQI_STATUS);
2098 if (rc < 0)
2099 return rc;
2100
2101 return FIELD_GET(T1_DCQ_SQI_MSK, rc);
2102}
2103
2104static struct phy_driver microchip_t1_phy_driver[] = {
2105 {
2106 PHY_ID_MATCH_MODEL(PHY_ID_LAN87XX),
2107 .name = "Microchip LAN87xx T1",
2108 .flags = PHY_POLL_CABLE_TEST,
2109 .features = PHY_BASIC_T1_FEATURES,
2110 .config_init = lan87xx_config_init,
2111 .config_intr = lan87xx_phy_config_intr,
2112 .handle_interrupt = lan87xx_handle_interrupt,
2113 .suspend = genphy_suspend,
2114 .resume = genphy_resume,
2115 .config_aneg = lan87xx_config_aneg,
2116 .read_status = lan87xx_read_status,
2117 .get_sqi = lan87xx_get_sqi,
2118 .get_sqi_max = lan87xx_get_sqi_max,
2119 .cable_test_start = lan87xx_cable_test_start,
2120 .cable_test_get_status = lan87xx_cable_test_get_status,
2121 },
2122 {
2123 PHY_ID_MATCH_MODEL(PHY_ID_LAN937X),
2124 .name = "Microchip LAN937x T1",
2125 .flags = PHY_POLL_CABLE_TEST,
2126 .features = PHY_BASIC_T1_FEATURES,
2127 .config_init = lan87xx_config_init,
2128 .config_intr = lan87xx_phy_config_intr,
2129 .handle_interrupt = lan87xx_handle_interrupt,
2130 .suspend = genphy_suspend,
2131 .resume = genphy_resume,
2132 .config_aneg = lan87xx_config_aneg,
2133 .read_status = lan87xx_read_status,
2134 .get_sqi = lan87xx_get_sqi,
2135 .get_sqi_max = lan87xx_get_sqi_max,
2136 .cable_test_start = lan87xx_cable_test_start,
2137 .cable_test_get_status = lan87xx_cable_test_get_status,
2138 },
2139 {
2140 PHY_ID_MATCH_MODEL(PHY_ID_LAN887X),
2141 .name = "Microchip LAN887x T1 PHY",
2142 .flags = PHY_POLL_CABLE_TEST,
2143 .probe = lan887x_probe,
2144 .get_features = lan887x_get_features,
2145 .config_init = lan887x_phy_init,
2146 .config_aneg = lan887x_config_aneg,
2147 .get_stats = lan887x_get_stats,
2148 .get_sset_count = lan887x_get_sset_count,
2149 .get_strings = lan887x_get_strings,
2150 .suspend = genphy_suspend,
2151 .resume = genphy_resume,
2152 .read_status = genphy_c45_read_status,
2153 .cable_test_start = lan887x_cable_test_start,
2154 .cable_test_get_status = lan887x_cable_test_get_status,
2155 .config_intr = lan887x_config_intr,
2156 .handle_interrupt = lan887x_handle_interrupt,
2157 .get_sqi = lan887x_get_sqi,
2158 .get_sqi_max = lan87xx_get_sqi_max,
2159 .set_loopback = genphy_c45_loopback,
2160 }
2161};
2162
2163module_phy_driver(microchip_t1_phy_driver);
2164
2165static struct mdio_device_id __maybe_unused microchip_t1_tbl[] = {
2166 { PHY_ID_MATCH_MODEL(PHY_ID_LAN87XX) },
2167 { PHY_ID_MATCH_MODEL(PHY_ID_LAN937X) },
2168 { PHY_ID_MATCH_MODEL(PHY_ID_LAN887X) },
2169 { }
2170};
2171
2172MODULE_DEVICE_TABLE(mdio, microchip_t1_tbl);
2173
2174MODULE_AUTHOR(DRIVER_AUTHOR);
2175MODULE_DESCRIPTION(DRIVER_DESC);
2176MODULE_LICENSE("GPL");