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1// SPDX-License-Identifier: GPL-2.0-or-later
2/* FarSync WAN driver for Linux (2.6.x kernel version)
3 *
4 * Actually sync driver for X.21, V.35 and V.24 on FarSync T-series cards
5 *
6 * Copyright (C) 2001-2004 FarSite Communications Ltd.
7 * www.farsite.co.uk
8 *
9 * Author: R.J.Dunlop <[email protected]>
10 * Maintainer: Kevin Curtis <[email protected]>
11 */
12
13#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14
15#include <linux/module.h>
16#include <linux/kernel.h>
17#include <linux/version.h>
18#include <linux/pci.h>
19#include <linux/sched.h>
20#include <linux/slab.h>
21#include <linux/ioport.h>
22#include <linux/init.h>
23#include <linux/interrupt.h>
24#include <linux/delay.h>
25#include <linux/if.h>
26#include <linux/hdlc.h>
27#include <asm/io.h>
28#include <linux/uaccess.h>
29
30#include "farsync.h"
31
32/* Module info
33 */
34MODULE_AUTHOR("R.J.Dunlop <[email protected]>");
35MODULE_DESCRIPTION("FarSync T-Series WAN driver. FarSite Communications Ltd.");
36MODULE_LICENSE("GPL");
37
38/* Driver configuration and global parameters
39 * ==========================================
40 */
41
42/* Number of ports (per card) and cards supported
43 */
44#define FST_MAX_PORTS 4
45#define FST_MAX_CARDS 32
46
47/* Default parameters for the link
48 */
49#define FST_TX_QUEUE_LEN 100 /* At 8Mbps a longer queue length is
50 * useful
51 */
52#define FST_TXQ_DEPTH 16 /* This one is for the buffering
53 * of frames on the way down to the card
54 * so that we can keep the card busy
55 * and maximise throughput
56 */
57#define FST_HIGH_WATER_MARK 12 /* Point at which we flow control
58 * network layer
59 */
60#define FST_LOW_WATER_MARK 8 /* Point at which we remove flow
61 * control from network layer
62 */
63#define FST_MAX_MTU 8000 /* Huge but possible */
64#define FST_DEF_MTU 1500 /* Common sane value */
65
66#define FST_TX_TIMEOUT (2 * HZ)
67
68#ifdef ARPHRD_RAWHDLC
69#define ARPHRD_MYTYPE ARPHRD_RAWHDLC /* Raw frames */
70#else
71#define ARPHRD_MYTYPE ARPHRD_HDLC /* Cisco-HDLC (keepalives etc) */
72#endif
73
74/* Modules parameters and associated variables
75 */
76static int fst_txq_low = FST_LOW_WATER_MARK;
77static int fst_txq_high = FST_HIGH_WATER_MARK;
78static int fst_max_reads = 7;
79static int fst_excluded_cards;
80static int fst_excluded_list[FST_MAX_CARDS];
81
82module_param(fst_txq_low, int, 0);
83module_param(fst_txq_high, int, 0);
84module_param(fst_max_reads, int, 0);
85module_param(fst_excluded_cards, int, 0);
86module_param_array(fst_excluded_list, int, NULL, 0);
87
88/* Card shared memory layout
89 * =========================
90 */
91#pragma pack(1)
92
93/* This information is derived in part from the FarSite FarSync Smc.h
94 * file. Unfortunately various name clashes and the non-portability of the
95 * bit field declarations in that file have meant that I have chosen to
96 * recreate the information here.
97 *
98 * The SMC (Shared Memory Configuration) has a version number that is
99 * incremented every time there is a significant change. This number can
100 * be used to check that we have not got out of step with the firmware
101 * contained in the .CDE files.
102 */
103#define SMC_VERSION 24
104
105#define FST_MEMSIZE 0x100000 /* Size of card memory (1Mb) */
106
107#define SMC_BASE 0x00002000L /* Base offset of the shared memory window main
108 * configuration structure
109 */
110#define BFM_BASE 0x00010000L /* Base offset of the shared memory window DMA
111 * buffers
112 */
113
114#define LEN_TX_BUFFER 8192 /* Size of packet buffers */
115#define LEN_RX_BUFFER 8192
116
117#define LEN_SMALL_TX_BUFFER 256 /* Size of obsolete buffs used for DOS diags */
118#define LEN_SMALL_RX_BUFFER 256
119
120#define NUM_TX_BUFFER 2 /* Must be power of 2. Fixed by firmware */
121#define NUM_RX_BUFFER 8
122
123/* Interrupt retry time in milliseconds */
124#define INT_RETRY_TIME 2
125
126/* The Am186CH/CC processors support a SmartDMA mode using circular pools
127 * of buffer descriptors. The structure is almost identical to that used
128 * in the LANCE Ethernet controllers. Details available as PDF from the
129 * AMD web site: https://www.amd.com/products/epd/processors/\
130 * 2.16bitcont/3.am186cxfa/a21914/21914.pdf
131 */
132struct txdesc { /* Transmit descriptor */
133 volatile u16 ladr; /* Low order address of packet. This is a
134 * linear address in the Am186 memory space
135 */
136 volatile u8 hadr; /* High order address. Low 4 bits only, high 4
137 * bits must be zero
138 */
139 volatile u8 bits; /* Status and config */
140 volatile u16 bcnt; /* 2s complement of packet size in low 15 bits.
141 * Transmit terminal count interrupt enable in
142 * top bit.
143 */
144 u16 unused; /* Not used in Tx */
145};
146
147struct rxdesc { /* Receive descriptor */
148 volatile u16 ladr; /* Low order address of packet */
149 volatile u8 hadr; /* High order address */
150 volatile u8 bits; /* Status and config */
151 volatile u16 bcnt; /* 2s complement of buffer size in low 15 bits.
152 * Receive terminal count interrupt enable in
153 * top bit.
154 */
155 volatile u16 mcnt; /* Message byte count (15 bits) */
156};
157
158/* Convert a length into the 15 bit 2's complement */
159/* #define cnv_bcnt(len) (( ~(len) + 1 ) & 0x7FFF ) */
160/* Since we need to set the high bit to enable the completion interrupt this
161 * can be made a lot simpler
162 */
163#define cnv_bcnt(len) (-(len))
164
165/* Status and config bits for the above */
166#define DMA_OWN 0x80 /* SmartDMA owns the descriptor */
167#define TX_STP 0x02 /* Tx: start of packet */
168#define TX_ENP 0x01 /* Tx: end of packet */
169#define RX_ERR 0x40 /* Rx: error (OR of next 4 bits) */
170#define RX_FRAM 0x20 /* Rx: framing error */
171#define RX_OFLO 0x10 /* Rx: overflow error */
172#define RX_CRC 0x08 /* Rx: CRC error */
173#define RX_HBUF 0x04 /* Rx: buffer error */
174#define RX_STP 0x02 /* Rx: start of packet */
175#define RX_ENP 0x01 /* Rx: end of packet */
176
177/* Interrupts from the card are caused by various events which are presented
178 * in a circular buffer as several events may be processed on one physical int
179 */
180#define MAX_CIRBUFF 32
181
182struct cirbuff {
183 u8 rdindex; /* read, then increment and wrap */
184 u8 wrindex; /* write, then increment and wrap */
185 u8 evntbuff[MAX_CIRBUFF];
186};
187
188/* Interrupt event codes.
189 * Where appropriate the two low order bits indicate the port number
190 */
191#define CTLA_CHG 0x18 /* Control signal changed */
192#define CTLB_CHG 0x19
193#define CTLC_CHG 0x1A
194#define CTLD_CHG 0x1B
195
196#define INIT_CPLT 0x20 /* Initialisation complete */
197#define INIT_FAIL 0x21 /* Initialisation failed */
198
199#define ABTA_SENT 0x24 /* Abort sent */
200#define ABTB_SENT 0x25
201#define ABTC_SENT 0x26
202#define ABTD_SENT 0x27
203
204#define TXA_UNDF 0x28 /* Transmission underflow */
205#define TXB_UNDF 0x29
206#define TXC_UNDF 0x2A
207#define TXD_UNDF 0x2B
208
209#define F56_INT 0x2C
210#define M32_INT 0x2D
211
212#define TE1_ALMA 0x30
213
214/* Port physical configuration. See farsync.h for field values */
215struct port_cfg {
216 u16 lineInterface; /* Physical interface type */
217 u8 x25op; /* Unused at present */
218 u8 internalClock; /* 1 => internal clock, 0 => external */
219 u8 transparentMode; /* 1 => on, 0 => off */
220 u8 invertClock; /* 0 => normal, 1 => inverted */
221 u8 padBytes[6]; /* Padding */
222 u32 lineSpeed; /* Speed in bps */
223};
224
225/* TE1 port physical configuration */
226struct su_config {
227 u32 dataRate;
228 u8 clocking;
229 u8 framing;
230 u8 structure;
231 u8 interface;
232 u8 coding;
233 u8 lineBuildOut;
234 u8 equalizer;
235 u8 transparentMode;
236 u8 loopMode;
237 u8 range;
238 u8 txBufferMode;
239 u8 rxBufferMode;
240 u8 startingSlot;
241 u8 losThreshold;
242 u8 enableIdleCode;
243 u8 idleCode;
244 u8 spare[44];
245};
246
247/* TE1 Status */
248struct su_status {
249 u32 receiveBufferDelay;
250 u32 framingErrorCount;
251 u32 codeViolationCount;
252 u32 crcErrorCount;
253 u32 lineAttenuation;
254 u8 portStarted;
255 u8 lossOfSignal;
256 u8 receiveRemoteAlarm;
257 u8 alarmIndicationSignal;
258 u8 spare[40];
259};
260
261/* Finally sling all the above together into the shared memory structure.
262 * Sorry it's a hodge podge of arrays, structures and unused bits, it's been
263 * evolving under NT for some time so I guess we're stuck with it.
264 * The structure starts at offset SMC_BASE.
265 * See farsync.h for some field values.
266 */
267struct fst_shared {
268 /* DMA descriptor rings */
269 struct rxdesc rxDescrRing[FST_MAX_PORTS][NUM_RX_BUFFER];
270 struct txdesc txDescrRing[FST_MAX_PORTS][NUM_TX_BUFFER];
271
272 /* Obsolete small buffers */
273 u8 smallRxBuffer[FST_MAX_PORTS][NUM_RX_BUFFER][LEN_SMALL_RX_BUFFER];
274 u8 smallTxBuffer[FST_MAX_PORTS][NUM_TX_BUFFER][LEN_SMALL_TX_BUFFER];
275
276 u8 taskStatus; /* 0x00 => initialising, 0x01 => running,
277 * 0xFF => halted
278 */
279
280 u8 interruptHandshake; /* Set to 0x01 by adapter to signal interrupt,
281 * set to 0xEE by host to acknowledge interrupt
282 */
283
284 u16 smcVersion; /* Must match SMC_VERSION */
285
286 u32 smcFirmwareVersion; /* 0xIIVVRRBB where II = product ID, VV = major
287 * version, RR = revision and BB = build
288 */
289
290 u16 txa_done; /* Obsolete completion flags */
291 u16 rxa_done;
292 u16 txb_done;
293 u16 rxb_done;
294 u16 txc_done;
295 u16 rxc_done;
296 u16 txd_done;
297 u16 rxd_done;
298
299 u16 mailbox[4]; /* Diagnostics mailbox. Not used */
300
301 struct cirbuff interruptEvent; /* interrupt causes */
302
303 u32 v24IpSts[FST_MAX_PORTS]; /* V.24 control input status */
304 u32 v24OpSts[FST_MAX_PORTS]; /* V.24 control output status */
305
306 struct port_cfg portConfig[FST_MAX_PORTS];
307
308 u16 clockStatus[FST_MAX_PORTS]; /* lsb: 0=> present, 1=> absent */
309
310 u16 cableStatus; /* lsb: 0=> present, 1=> absent */
311
312 u16 txDescrIndex[FST_MAX_PORTS]; /* transmit descriptor ring index */
313 u16 rxDescrIndex[FST_MAX_PORTS]; /* receive descriptor ring index */
314
315 u16 portMailbox[FST_MAX_PORTS][2]; /* command, modifier */
316 u16 cardMailbox[4]; /* Not used */
317
318 /* Number of times the card thinks the host has
319 * missed an interrupt by not acknowledging
320 * within 2mS (I guess NT has problems)
321 */
322 u32 interruptRetryCount;
323
324 /* Driver private data used as an ID. We'll not
325 * use this as I'd rather keep such things
326 * in main memory rather than on the PCI bus
327 */
328 u32 portHandle[FST_MAX_PORTS];
329
330 /* Count of Tx underflows for stats */
331 u32 transmitBufferUnderflow[FST_MAX_PORTS];
332
333 /* Debounced V.24 control input status */
334 u32 v24DebouncedSts[FST_MAX_PORTS];
335
336 /* Adapter debounce timers. Don't touch */
337 u32 ctsTimer[FST_MAX_PORTS];
338 u32 ctsTimerRun[FST_MAX_PORTS];
339 u32 dcdTimer[FST_MAX_PORTS];
340 u32 dcdTimerRun[FST_MAX_PORTS];
341
342 u32 numberOfPorts; /* Number of ports detected at startup */
343
344 u16 _reserved[64];
345
346 u16 cardMode; /* Bit-mask to enable features:
347 * Bit 0: 1 enables LED identify mode
348 */
349
350 u16 portScheduleOffset;
351
352 struct su_config suConfig; /* TE1 Bits */
353 struct su_status suStatus;
354
355 u32 endOfSmcSignature; /* endOfSmcSignature MUST be the last member of
356 * the structure and marks the end of shared
357 * memory. Adapter code initializes it as
358 * END_SIG.
359 */
360};
361
362/* endOfSmcSignature value */
363#define END_SIG 0x12345678
364
365/* Mailbox values. (portMailbox) */
366#define NOP 0 /* No operation */
367#define ACK 1 /* Positive acknowledgement to PC driver */
368#define NAK 2 /* Negative acknowledgement to PC driver */
369#define STARTPORT 3 /* Start an HDLC port */
370#define STOPPORT 4 /* Stop an HDLC port */
371#define ABORTTX 5 /* Abort the transmitter for a port */
372#define SETV24O 6 /* Set V24 outputs */
373
374/* PLX Chip Register Offsets */
375#define CNTRL_9052 0x50 /* Control Register */
376#define CNTRL_9054 0x6c /* Control Register */
377
378#define INTCSR_9052 0x4c /* Interrupt control/status register */
379#define INTCSR_9054 0x68 /* Interrupt control/status register */
380
381/* 9054 DMA Registers */
382/* Note that we will be using DMA Channel 0 for copying rx data
383 * and Channel 1 for copying tx data
384 */
385#define DMAMODE0 0x80
386#define DMAPADR0 0x84
387#define DMALADR0 0x88
388#define DMASIZ0 0x8c
389#define DMADPR0 0x90
390#define DMAMODE1 0x94
391#define DMAPADR1 0x98
392#define DMALADR1 0x9c
393#define DMASIZ1 0xa0
394#define DMADPR1 0xa4
395#define DMACSR0 0xa8
396#define DMACSR1 0xa9
397#define DMAARB 0xac
398#define DMATHR 0xb0
399#define DMADAC0 0xb4
400#define DMADAC1 0xb8
401#define DMAMARBR 0xac
402
403#define FST_MIN_DMA_LEN 64
404#define FST_RX_DMA_INT 0x01
405#define FST_TX_DMA_INT 0x02
406#define FST_CARD_INT 0x04
407
408/* Larger buffers are positioned in memory at offset BFM_BASE */
409struct buf_window {
410 u8 txBuffer[FST_MAX_PORTS][NUM_TX_BUFFER][LEN_TX_BUFFER];
411 u8 rxBuffer[FST_MAX_PORTS][NUM_RX_BUFFER][LEN_RX_BUFFER];
412};
413
414/* Calculate offset of a buffer object within the shared memory window */
415#define BUF_OFFSET(X) (BFM_BASE + offsetof(struct buf_window, X))
416
417#pragma pack()
418
419/* Device driver private information
420 * =================================
421 */
422/* Per port (line or channel) information
423 */
424struct fst_port_info {
425 struct net_device *dev; /* Device struct - must be first */
426 struct fst_card_info *card; /* Card we're associated with */
427 int index; /* Port index on the card */
428 int hwif; /* Line hardware (lineInterface copy) */
429 int run; /* Port is running */
430 int mode; /* Normal or FarSync raw */
431 int rxpos; /* Next Rx buffer to use */
432 int txpos; /* Next Tx buffer to use */
433 int txipos; /* Next Tx buffer to check for free */
434 int start; /* Indication of start/stop to network */
435 /* A sixteen entry transmit queue
436 */
437 int txqs; /* index to get next buffer to tx */
438 int txqe; /* index to queue next packet */
439 struct sk_buff *txq[FST_TXQ_DEPTH]; /* The queue */
440 int rxqdepth;
441};
442
443/* Per card information
444 */
445struct fst_card_info {
446 char __iomem *mem; /* Card memory mapped to kernel space */
447 char __iomem *ctlmem; /* Control memory for PCI cards */
448 unsigned int phys_mem; /* Physical memory window address */
449 unsigned int phys_ctlmem; /* Physical control memory address */
450 unsigned int irq; /* Interrupt request line number */
451 unsigned int nports; /* Number of serial ports */
452 unsigned int type; /* Type index of card */
453 unsigned int state; /* State of card */
454 spinlock_t card_lock; /* Lock for SMP access */
455 unsigned short pci_conf; /* PCI card config in I/O space */
456 /* Per port info */
457 struct fst_port_info ports[FST_MAX_PORTS];
458 struct pci_dev *device; /* Information about the pci device */
459 int card_no; /* Inst of the card on the system */
460 int family; /* TxP or TxU */
461 int dmarx_in_progress;
462 int dmatx_in_progress;
463 unsigned long int_count;
464 unsigned long int_time_ave;
465 void *rx_dma_handle_host;
466 dma_addr_t rx_dma_handle_card;
467 void *tx_dma_handle_host;
468 dma_addr_t tx_dma_handle_card;
469 struct sk_buff *dma_skb_rx;
470 struct fst_port_info *dma_port_rx;
471 struct fst_port_info *dma_port_tx;
472 int dma_len_rx;
473 int dma_len_tx;
474 int dma_txpos;
475 int dma_rxpos;
476};
477
478/* Convert an HDLC device pointer into a port info pointer and similar */
479#define dev_to_port(D) (dev_to_hdlc(D)->priv)
480#define port_to_dev(P) ((P)->dev)
481
482/* Shared memory window access macros
483 *
484 * We have a nice memory based structure above, which could be directly
485 * mapped on i386 but might not work on other architectures unless we use
486 * the readb,w,l and writeb,w,l macros. Unfortunately these macros take
487 * physical offsets so we have to convert. The only saving grace is that
488 * this should all collapse back to a simple indirection eventually.
489 */
490#define WIN_OFFSET(X) ((long)&(((struct fst_shared *)SMC_BASE)->X))
491
492#define FST_RDB(C, E) (readb((C)->mem + WIN_OFFSET(E)))
493#define FST_RDW(C, E) (readw((C)->mem + WIN_OFFSET(E)))
494#define FST_RDL(C, E) (readl((C)->mem + WIN_OFFSET(E)))
495
496#define FST_WRB(C, E, B) (writeb((B), (C)->mem + WIN_OFFSET(E)))
497#define FST_WRW(C, E, W) (writew((W), (C)->mem + WIN_OFFSET(E)))
498#define FST_WRL(C, E, L) (writel((L), (C)->mem + WIN_OFFSET(E)))
499
500/* Debug support
501 */
502#if FST_DEBUG
503
504static int fst_debug_mask = { FST_DEBUG };
505
506/* Most common debug activity is to print something if the corresponding bit
507 * is set in the debug mask. Note: this uses a non-ANSI extension in GCC to
508 * support variable numbers of macro parameters. The inverted if prevents us
509 * eating someone else's else clause.
510 */
511#define dbg(F, fmt, args...) \
512do { \
513 if (fst_debug_mask & (F)) \
514 printk(KERN_DEBUG pr_fmt(fmt), ##args); \
515} while (0)
516#else
517#define dbg(F, fmt, args...) \
518do { \
519 if (0) \
520 printk(KERN_DEBUG pr_fmt(fmt), ##args); \
521} while (0)
522#endif
523
524/* PCI ID lookup table
525 */
526static const struct pci_device_id fst_pci_dev_id[] = {
527 { PCI_VDEVICE(FARSITE, PCI_DEVICE_ID_FARSITE_T2P), .driver_data = FST_TYPE_T2P },
528
529 { PCI_VDEVICE(FARSITE, PCI_DEVICE_ID_FARSITE_T4P), .driver_data = FST_TYPE_T4P },
530
531 { PCI_VDEVICE(FARSITE, PCI_DEVICE_ID_FARSITE_T1U), .driver_data = FST_TYPE_T1U },
532
533 { PCI_VDEVICE(FARSITE, PCI_DEVICE_ID_FARSITE_T2U), .driver_data = FST_TYPE_T2U },
534
535 { PCI_VDEVICE(FARSITE, PCI_DEVICE_ID_FARSITE_T4U), .driver_data = FST_TYPE_T4U },
536
537 { PCI_VDEVICE(FARSITE, PCI_DEVICE_ID_FARSITE_TE1), .driver_data = FST_TYPE_TE1 },
538
539 { PCI_VDEVICE(FARSITE, PCI_DEVICE_ID_FARSITE_TE1C), .driver_data = FST_TYPE_TE1 },
540
541 { } /* End */
542};
543
544MODULE_DEVICE_TABLE(pci, fst_pci_dev_id);
545
546/* Device Driver Work Queues
547 *
548 * So that we don't spend too much time processing events in the
549 * Interrupt Service routine, we will declare a work queue per Card
550 * and make the ISR schedule a task in the queue for later execution.
551 * In the 2.4 Kernel we used to use the immediate queue for BH's
552 * Now that they are gone, tasklets seem to be much better than work
553 * queues.
554 */
555
556static void do_bottom_half_tx(struct fst_card_info *card);
557static void do_bottom_half_rx(struct fst_card_info *card);
558static void fst_process_tx_work_q(struct tasklet_struct *unused);
559static void fst_process_int_work_q(struct tasklet_struct *unused);
560
561static DECLARE_TASKLET(fst_tx_task, fst_process_tx_work_q);
562static DECLARE_TASKLET(fst_int_task, fst_process_int_work_q);
563
564static struct fst_card_info *fst_card_array[FST_MAX_CARDS];
565static DEFINE_SPINLOCK(fst_work_q_lock);
566static u64 fst_work_txq;
567static u64 fst_work_intq;
568
569static void
570fst_q_work_item(u64 *queue, int card_index)
571{
572 unsigned long flags;
573 u64 mask;
574
575 /* Grab the queue exclusively
576 */
577 spin_lock_irqsave(&fst_work_q_lock, flags);
578
579 /* Making an entry in the queue is simply a matter of setting
580 * a bit for the card indicating that there is work to do in the
581 * bottom half for the card. Note the limitation of 64 cards.
582 * That ought to be enough
583 */
584 mask = (u64)1 << card_index;
585 *queue |= mask;
586 spin_unlock_irqrestore(&fst_work_q_lock, flags);
587}
588
589static void
590fst_process_tx_work_q(struct tasklet_struct *unused)
591{
592 unsigned long flags;
593 u64 work_txq;
594 int i;
595
596 /* Grab the queue exclusively
597 */
598 dbg(DBG_TX, "fst_process_tx_work_q\n");
599 spin_lock_irqsave(&fst_work_q_lock, flags);
600 work_txq = fst_work_txq;
601 fst_work_txq = 0;
602 spin_unlock_irqrestore(&fst_work_q_lock, flags);
603
604 /* Call the bottom half for each card with work waiting
605 */
606 for (i = 0; i < FST_MAX_CARDS; i++) {
607 if (work_txq & 0x01) {
608 if (fst_card_array[i]) {
609 dbg(DBG_TX, "Calling tx bh for card %d\n", i);
610 do_bottom_half_tx(fst_card_array[i]);
611 }
612 }
613 work_txq = work_txq >> 1;
614 }
615}
616
617static void
618fst_process_int_work_q(struct tasklet_struct *unused)
619{
620 unsigned long flags;
621 u64 work_intq;
622 int i;
623
624 /* Grab the queue exclusively
625 */
626 dbg(DBG_INTR, "fst_process_int_work_q\n");
627 spin_lock_irqsave(&fst_work_q_lock, flags);
628 work_intq = fst_work_intq;
629 fst_work_intq = 0;
630 spin_unlock_irqrestore(&fst_work_q_lock, flags);
631
632 /* Call the bottom half for each card with work waiting
633 */
634 for (i = 0; i < FST_MAX_CARDS; i++) {
635 if (work_intq & 0x01) {
636 if (fst_card_array[i]) {
637 dbg(DBG_INTR,
638 "Calling rx & tx bh for card %d\n", i);
639 do_bottom_half_rx(fst_card_array[i]);
640 do_bottom_half_tx(fst_card_array[i]);
641 }
642 }
643 work_intq = work_intq >> 1;
644 }
645}
646
647/* Card control functions
648 * ======================
649 */
650/* Place the processor in reset state
651 *
652 * Used to be a simple write to card control space but a glitch in the latest
653 * AMD Am186CH processor means that we now have to do it by asserting and de-
654 * asserting the PLX chip PCI Adapter Software Reset. Bit 30 in CNTRL register
655 * at offset 9052_CNTRL. Note the updates for the TXU.
656 */
657static inline void
658fst_cpureset(struct fst_card_info *card)
659{
660 unsigned char interrupt_line_register;
661 unsigned int regval;
662
663 if (card->family == FST_FAMILY_TXU) {
664 if (pci_read_config_byte
665 (card->device, PCI_INTERRUPT_LINE, &interrupt_line_register)) {
666 dbg(DBG_ASS,
667 "Error in reading interrupt line register\n");
668 }
669 /* Assert PLX software reset and Am186 hardware reset
670 * and then deassert the PLX software reset but 186 still in reset
671 */
672 outw(0x440f, card->pci_conf + CNTRL_9054 + 2);
673 outw(0x040f, card->pci_conf + CNTRL_9054 + 2);
674 /* We are delaying here to allow the 9054 to reset itself
675 */
676 usleep_range(10, 20);
677 outw(0x240f, card->pci_conf + CNTRL_9054 + 2);
678 /* We are delaying here to allow the 9054 to reload its eeprom
679 */
680 usleep_range(10, 20);
681 outw(0x040f, card->pci_conf + CNTRL_9054 + 2);
682
683 if (pci_write_config_byte
684 (card->device, PCI_INTERRUPT_LINE, interrupt_line_register)) {
685 dbg(DBG_ASS,
686 "Error in writing interrupt line register\n");
687 }
688
689 } else {
690 regval = inl(card->pci_conf + CNTRL_9052);
691
692 outl(regval | 0x40000000, card->pci_conf + CNTRL_9052);
693 outl(regval & ~0x40000000, card->pci_conf + CNTRL_9052);
694 }
695}
696
697/* Release the processor from reset
698 */
699static inline void
700fst_cpurelease(struct fst_card_info *card)
701{
702 if (card->family == FST_FAMILY_TXU) {
703 /* Force posted writes to complete
704 */
705 (void)readb(card->mem);
706
707 /* Release LRESET DO = 1
708 * Then release Local Hold, DO = 1
709 */
710 outw(0x040e, card->pci_conf + CNTRL_9054 + 2);
711 outw(0x040f, card->pci_conf + CNTRL_9054 + 2);
712 } else {
713 (void)readb(card->ctlmem);
714 }
715}
716
717/* Clear the cards interrupt flag
718 */
719static inline void
720fst_clear_intr(struct fst_card_info *card)
721{
722 if (card->family == FST_FAMILY_TXU) {
723 (void)readb(card->ctlmem);
724 } else {
725 /* Poke the appropriate PLX chip register (same as enabling interrupts)
726 */
727 outw(0x0543, card->pci_conf + INTCSR_9052);
728 }
729}
730
731/* Enable card interrupts
732 */
733static inline void
734fst_enable_intr(struct fst_card_info *card)
735{
736 if (card->family == FST_FAMILY_TXU)
737 outl(0x0f0c0900, card->pci_conf + INTCSR_9054);
738 else
739 outw(0x0543, card->pci_conf + INTCSR_9052);
740}
741
742/* Disable card interrupts
743 */
744static inline void
745fst_disable_intr(struct fst_card_info *card)
746{
747 if (card->family == FST_FAMILY_TXU)
748 outl(0x00000000, card->pci_conf + INTCSR_9054);
749 else
750 outw(0x0000, card->pci_conf + INTCSR_9052);
751}
752
753/* Process the result of trying to pass a received frame up the stack
754 */
755static void
756fst_process_rx_status(int rx_status, char *name)
757{
758 switch (rx_status) {
759 case NET_RX_SUCCESS:
760 {
761 /* Nothing to do here
762 */
763 break;
764 }
765 case NET_RX_DROP:
766 {
767 dbg(DBG_ASS, "%s: Received packet dropped\n", name);
768 break;
769 }
770 }
771}
772
773/* Initilaise DMA for PLX 9054
774 */
775static inline void
776fst_init_dma(struct fst_card_info *card)
777{
778 /* This is only required for the PLX 9054
779 */
780 if (card->family == FST_FAMILY_TXU) {
781 pci_set_master(card->device);
782 outl(0x00020441, card->pci_conf + DMAMODE0);
783 outl(0x00020441, card->pci_conf + DMAMODE1);
784 outl(0x0, card->pci_conf + DMATHR);
785 }
786}
787
788/* Tx dma complete interrupt
789 */
790static void
791fst_tx_dma_complete(struct fst_card_info *card, struct fst_port_info *port,
792 int len, int txpos)
793{
794 struct net_device *dev = port_to_dev(port);
795
796 /* Everything is now set, just tell the card to go
797 */
798 dbg(DBG_TX, "fst_tx_dma_complete\n");
799 FST_WRB(card, txDescrRing[port->index][txpos].bits,
800 DMA_OWN | TX_STP | TX_ENP);
801 dev->stats.tx_packets++;
802 dev->stats.tx_bytes += len;
803 netif_trans_update(dev);
804}
805
806/* Mark it for our own raw sockets interface
807 */
808static __be16 farsync_type_trans(struct sk_buff *skb, struct net_device *dev)
809{
810 skb->dev = dev;
811 skb_reset_mac_header(skb);
812 skb->pkt_type = PACKET_HOST;
813 return htons(ETH_P_CUST);
814}
815
816/* Rx dma complete interrupt
817 */
818static void
819fst_rx_dma_complete(struct fst_card_info *card, struct fst_port_info *port,
820 int len, struct sk_buff *skb, int rxp)
821{
822 struct net_device *dev = port_to_dev(port);
823 int pi;
824 int rx_status;
825
826 dbg(DBG_TX, "fst_rx_dma_complete\n");
827 pi = port->index;
828 skb_put_data(skb, card->rx_dma_handle_host, len);
829
830 /* Reset buffer descriptor */
831 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
832
833 /* Update stats */
834 dev->stats.rx_packets++;
835 dev->stats.rx_bytes += len;
836
837 /* Push upstream */
838 dbg(DBG_RX, "Pushing the frame up the stack\n");
839 if (port->mode == FST_RAW)
840 skb->protocol = farsync_type_trans(skb, dev);
841 else
842 skb->protocol = hdlc_type_trans(skb, dev);
843 rx_status = netif_rx(skb);
844 fst_process_rx_status(rx_status, port_to_dev(port)->name);
845 if (rx_status == NET_RX_DROP)
846 dev->stats.rx_dropped++;
847}
848
849/* Receive a frame through the DMA
850 */
851static inline void
852fst_rx_dma(struct fst_card_info *card, dma_addr_t dma, u32 mem, int len)
853{
854 /* This routine will setup the DMA and start it
855 */
856
857 dbg(DBG_RX, "In fst_rx_dma %x %x %d\n", (u32)dma, mem, len);
858 if (card->dmarx_in_progress)
859 dbg(DBG_ASS, "In fst_rx_dma while dma in progress\n");
860
861 outl(dma, card->pci_conf + DMAPADR0); /* Copy to here */
862 outl(mem, card->pci_conf + DMALADR0); /* from here */
863 outl(len, card->pci_conf + DMASIZ0); /* for this length */
864 outl(0x00000000c, card->pci_conf + DMADPR0); /* In this direction */
865
866 /* We use the dmarx_in_progress flag to flag the channel as busy
867 */
868 card->dmarx_in_progress = 1;
869 outb(0x03, card->pci_conf + DMACSR0); /* Start the transfer */
870}
871
872/* Send a frame through the DMA
873 */
874static inline void
875fst_tx_dma(struct fst_card_info *card, dma_addr_t dma, u32 mem, int len)
876{
877 /* This routine will setup the DMA and start it.
878 */
879
880 dbg(DBG_TX, "In fst_tx_dma %x %x %d\n", (u32)dma, mem, len);
881 if (card->dmatx_in_progress)
882 dbg(DBG_ASS, "In fst_tx_dma while dma in progress\n");
883
884 outl(dma, card->pci_conf + DMAPADR1); /* Copy from here */
885 outl(mem, card->pci_conf + DMALADR1); /* to here */
886 outl(len, card->pci_conf + DMASIZ1); /* for this length */
887 outl(0x000000004, card->pci_conf + DMADPR1); /* In this direction */
888
889 /* We use the dmatx_in_progress to flag the channel as busy
890 */
891 card->dmatx_in_progress = 1;
892 outb(0x03, card->pci_conf + DMACSR1); /* Start the transfer */
893}
894
895/* Issue a Mailbox command for a port.
896 * Note we issue them on a fire and forget basis, not expecting to see an
897 * error and not waiting for completion.
898 */
899static void
900fst_issue_cmd(struct fst_port_info *port, unsigned short cmd)
901{
902 struct fst_card_info *card;
903 unsigned short mbval;
904 unsigned long flags;
905 int safety;
906
907 card = port->card;
908 spin_lock_irqsave(&card->card_lock, flags);
909 mbval = FST_RDW(card, portMailbox[port->index][0]);
910
911 safety = 0;
912 /* Wait for any previous command to complete */
913 while (mbval > NAK) {
914 spin_unlock_irqrestore(&card->card_lock, flags);
915 schedule_timeout_uninterruptible(1);
916 spin_lock_irqsave(&card->card_lock, flags);
917
918 if (++safety > 2000) {
919 pr_err("Mailbox safety timeout\n");
920 break;
921 }
922
923 mbval = FST_RDW(card, portMailbox[port->index][0]);
924 }
925 if (safety > 0)
926 dbg(DBG_CMD, "Mailbox clear after %d jiffies\n", safety);
927
928 if (mbval == NAK)
929 dbg(DBG_CMD, "issue_cmd: previous command was NAK'd\n");
930
931 FST_WRW(card, portMailbox[port->index][0], cmd);
932
933 if (cmd == ABORTTX || cmd == STARTPORT) {
934 port->txpos = 0;
935 port->txipos = 0;
936 port->start = 0;
937 }
938
939 spin_unlock_irqrestore(&card->card_lock, flags);
940}
941
942/* Port output signals control
943 */
944static inline void
945fst_op_raise(struct fst_port_info *port, unsigned int outputs)
946{
947 outputs |= FST_RDL(port->card, v24OpSts[port->index]);
948 FST_WRL(port->card, v24OpSts[port->index], outputs);
949
950 if (port->run)
951 fst_issue_cmd(port, SETV24O);
952}
953
954static inline void
955fst_op_lower(struct fst_port_info *port, unsigned int outputs)
956{
957 outputs = ~outputs & FST_RDL(port->card, v24OpSts[port->index]);
958 FST_WRL(port->card, v24OpSts[port->index], outputs);
959
960 if (port->run)
961 fst_issue_cmd(port, SETV24O);
962}
963
964/* Setup port Rx buffers
965 */
966static void
967fst_rx_config(struct fst_port_info *port)
968{
969 int i;
970 int pi;
971 unsigned int offset;
972 unsigned long flags;
973 struct fst_card_info *card;
974
975 pi = port->index;
976 card = port->card;
977 spin_lock_irqsave(&card->card_lock, flags);
978 for (i = 0; i < NUM_RX_BUFFER; i++) {
979 offset = BUF_OFFSET(rxBuffer[pi][i][0]);
980
981 FST_WRW(card, rxDescrRing[pi][i].ladr, (u16)offset);
982 FST_WRB(card, rxDescrRing[pi][i].hadr, (u8)(offset >> 16));
983 FST_WRW(card, rxDescrRing[pi][i].bcnt, cnv_bcnt(LEN_RX_BUFFER));
984 FST_WRW(card, rxDescrRing[pi][i].mcnt, LEN_RX_BUFFER);
985 FST_WRB(card, rxDescrRing[pi][i].bits, DMA_OWN);
986 }
987 port->rxpos = 0;
988 spin_unlock_irqrestore(&card->card_lock, flags);
989}
990
991/* Setup port Tx buffers
992 */
993static void
994fst_tx_config(struct fst_port_info *port)
995{
996 int i;
997 int pi;
998 unsigned int offset;
999 unsigned long flags;
1000 struct fst_card_info *card;
1001
1002 pi = port->index;
1003 card = port->card;
1004 spin_lock_irqsave(&card->card_lock, flags);
1005 for (i = 0; i < NUM_TX_BUFFER; i++) {
1006 offset = BUF_OFFSET(txBuffer[pi][i][0]);
1007
1008 FST_WRW(card, txDescrRing[pi][i].ladr, (u16)offset);
1009 FST_WRB(card, txDescrRing[pi][i].hadr, (u8)(offset >> 16));
1010 FST_WRW(card, txDescrRing[pi][i].bcnt, 0);
1011 FST_WRB(card, txDescrRing[pi][i].bits, 0);
1012 }
1013 port->txpos = 0;
1014 port->txipos = 0;
1015 port->start = 0;
1016 spin_unlock_irqrestore(&card->card_lock, flags);
1017}
1018
1019/* TE1 Alarm change interrupt event
1020 */
1021static void
1022fst_intr_te1_alarm(struct fst_card_info *card, struct fst_port_info *port)
1023{
1024 u8 los;
1025 u8 rra;
1026 u8 ais;
1027
1028 los = FST_RDB(card, suStatus.lossOfSignal);
1029 rra = FST_RDB(card, suStatus.receiveRemoteAlarm);
1030 ais = FST_RDB(card, suStatus.alarmIndicationSignal);
1031
1032 if (los) {
1033 /* Lost the link
1034 */
1035 if (netif_carrier_ok(port_to_dev(port))) {
1036 dbg(DBG_INTR, "Net carrier off\n");
1037 netif_carrier_off(port_to_dev(port));
1038 }
1039 } else {
1040 /* Link available
1041 */
1042 if (!netif_carrier_ok(port_to_dev(port))) {
1043 dbg(DBG_INTR, "Net carrier on\n");
1044 netif_carrier_on(port_to_dev(port));
1045 }
1046 }
1047
1048 if (los)
1049 dbg(DBG_INTR, "Assert LOS Alarm\n");
1050 else
1051 dbg(DBG_INTR, "De-assert LOS Alarm\n");
1052 if (rra)
1053 dbg(DBG_INTR, "Assert RRA Alarm\n");
1054 else
1055 dbg(DBG_INTR, "De-assert RRA Alarm\n");
1056
1057 if (ais)
1058 dbg(DBG_INTR, "Assert AIS Alarm\n");
1059 else
1060 dbg(DBG_INTR, "De-assert AIS Alarm\n");
1061}
1062
1063/* Control signal change interrupt event
1064 */
1065static void
1066fst_intr_ctlchg(struct fst_card_info *card, struct fst_port_info *port)
1067{
1068 int signals;
1069
1070 signals = FST_RDL(card, v24DebouncedSts[port->index]);
1071
1072 if (signals & ((port->hwif == X21 || port->hwif == X21D)
1073 ? IPSTS_INDICATE : IPSTS_DCD)) {
1074 if (!netif_carrier_ok(port_to_dev(port))) {
1075 dbg(DBG_INTR, "DCD active\n");
1076 netif_carrier_on(port_to_dev(port));
1077 }
1078 } else {
1079 if (netif_carrier_ok(port_to_dev(port))) {
1080 dbg(DBG_INTR, "DCD lost\n");
1081 netif_carrier_off(port_to_dev(port));
1082 }
1083 }
1084}
1085
1086/* Log Rx Errors
1087 */
1088static void
1089fst_log_rx_error(struct fst_card_info *card, struct fst_port_info *port,
1090 unsigned char dmabits, int rxp, unsigned short len)
1091{
1092 struct net_device *dev = port_to_dev(port);
1093
1094 /* Increment the appropriate error counter
1095 */
1096 dev->stats.rx_errors++;
1097 if (dmabits & RX_OFLO) {
1098 dev->stats.rx_fifo_errors++;
1099 dbg(DBG_ASS, "Rx fifo error on card %d port %d buffer %d\n",
1100 card->card_no, port->index, rxp);
1101 }
1102 if (dmabits & RX_CRC) {
1103 dev->stats.rx_crc_errors++;
1104 dbg(DBG_ASS, "Rx crc error on card %d port %d\n",
1105 card->card_no, port->index);
1106 }
1107 if (dmabits & RX_FRAM) {
1108 dev->stats.rx_frame_errors++;
1109 dbg(DBG_ASS, "Rx frame error on card %d port %d\n",
1110 card->card_no, port->index);
1111 }
1112 if (dmabits == (RX_STP | RX_ENP)) {
1113 dev->stats.rx_length_errors++;
1114 dbg(DBG_ASS, "Rx length error (%d) on card %d port %d\n",
1115 len, card->card_no, port->index);
1116 }
1117}
1118
1119/* Rx Error Recovery
1120 */
1121static void
1122fst_recover_rx_error(struct fst_card_info *card, struct fst_port_info *port,
1123 unsigned char dmabits, int rxp, unsigned short len)
1124{
1125 int i;
1126 int pi;
1127
1128 pi = port->index;
1129 /* Discard buffer descriptors until we see the start of the
1130 * next frame. Note that for long frames this could be in
1131 * a subsequent interrupt.
1132 */
1133 i = 0;
1134 while ((dmabits & (DMA_OWN | RX_STP)) == 0) {
1135 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
1136 rxp = (rxp + 1) % NUM_RX_BUFFER;
1137 if (++i > NUM_RX_BUFFER) {
1138 dbg(DBG_ASS, "intr_rx: Discarding more bufs"
1139 " than we have\n");
1140 break;
1141 }
1142 dmabits = FST_RDB(card, rxDescrRing[pi][rxp].bits);
1143 dbg(DBG_ASS, "DMA Bits of next buffer was %x\n", dmabits);
1144 }
1145 dbg(DBG_ASS, "There were %d subsequent buffers in error\n", i);
1146
1147 /* Discard the terminal buffer */
1148 if (!(dmabits & DMA_OWN)) {
1149 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
1150 rxp = (rxp + 1) % NUM_RX_BUFFER;
1151 }
1152 port->rxpos = rxp;
1153}
1154
1155/* Rx complete interrupt
1156 */
1157static void
1158fst_intr_rx(struct fst_card_info *card, struct fst_port_info *port)
1159{
1160 unsigned char dmabits;
1161 int pi;
1162 int rxp;
1163 int rx_status;
1164 unsigned short len;
1165 struct sk_buff *skb;
1166 struct net_device *dev = port_to_dev(port);
1167
1168 /* Check we have a buffer to process */
1169 pi = port->index;
1170 rxp = port->rxpos;
1171 dmabits = FST_RDB(card, rxDescrRing[pi][rxp].bits);
1172 if (dmabits & DMA_OWN) {
1173 dbg(DBG_RX | DBG_INTR, "intr_rx: No buffer port %d pos %d\n",
1174 pi, rxp);
1175 return;
1176 }
1177 if (card->dmarx_in_progress)
1178 return;
1179
1180 /* Get buffer length */
1181 len = FST_RDW(card, rxDescrRing[pi][rxp].mcnt);
1182 /* Discard the CRC */
1183 len -= 2;
1184 if (len == 0) {
1185 /* This seems to happen on the TE1 interface sometimes
1186 * so throw the frame away and log the event.
1187 */
1188 pr_err("Frame received with 0 length. Card %d Port %d\n",
1189 card->card_no, port->index);
1190 /* Return descriptor to card */
1191 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
1192
1193 rxp = (rxp + 1) % NUM_RX_BUFFER;
1194 port->rxpos = rxp;
1195 return;
1196 }
1197
1198 /* Check buffer length and for other errors. We insist on one packet
1199 * in one buffer. This simplifies things greatly and since we've
1200 * allocated 8K it shouldn't be a real world limitation
1201 */
1202 dbg(DBG_RX, "intr_rx: %d,%d: flags %x len %d\n", pi, rxp, dmabits, len);
1203 if (dmabits != (RX_STP | RX_ENP) || len > LEN_RX_BUFFER - 2) {
1204 fst_log_rx_error(card, port, dmabits, rxp, len);
1205 fst_recover_rx_error(card, port, dmabits, rxp, len);
1206 return;
1207 }
1208
1209 /* Allocate SKB */
1210 skb = dev_alloc_skb(len);
1211 if (!skb) {
1212 dbg(DBG_RX, "intr_rx: can't allocate buffer\n");
1213
1214 dev->stats.rx_dropped++;
1215
1216 /* Return descriptor to card */
1217 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
1218
1219 rxp = (rxp + 1) % NUM_RX_BUFFER;
1220 port->rxpos = rxp;
1221 return;
1222 }
1223
1224 /* We know the length we need to receive, len.
1225 * It's not worth using the DMA for reads of less than
1226 * FST_MIN_DMA_LEN
1227 */
1228
1229 if (len < FST_MIN_DMA_LEN || card->family == FST_FAMILY_TXP) {
1230 memcpy_fromio(skb_put(skb, len),
1231 card->mem + BUF_OFFSET(rxBuffer[pi][rxp][0]),
1232 len);
1233
1234 /* Reset buffer descriptor */
1235 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
1236
1237 /* Update stats */
1238 dev->stats.rx_packets++;
1239 dev->stats.rx_bytes += len;
1240
1241 /* Push upstream */
1242 dbg(DBG_RX, "Pushing frame up the stack\n");
1243 if (port->mode == FST_RAW)
1244 skb->protocol = farsync_type_trans(skb, dev);
1245 else
1246 skb->protocol = hdlc_type_trans(skb, dev);
1247 rx_status = netif_rx(skb);
1248 fst_process_rx_status(rx_status, port_to_dev(port)->name);
1249 if (rx_status == NET_RX_DROP)
1250 dev->stats.rx_dropped++;
1251 } else {
1252 card->dma_skb_rx = skb;
1253 card->dma_port_rx = port;
1254 card->dma_len_rx = len;
1255 card->dma_rxpos = rxp;
1256 fst_rx_dma(card, card->rx_dma_handle_card,
1257 BUF_OFFSET(rxBuffer[pi][rxp][0]), len);
1258 }
1259 if (rxp != port->rxpos) {
1260 dbg(DBG_ASS, "About to increment rxpos by more than 1\n");
1261 dbg(DBG_ASS, "rxp = %d rxpos = %d\n", rxp, port->rxpos);
1262 }
1263 rxp = (rxp + 1) % NUM_RX_BUFFER;
1264 port->rxpos = rxp;
1265}
1266
1267/* The bottom half to the ISR
1268 *
1269 */
1270
1271static void
1272do_bottom_half_tx(struct fst_card_info *card)
1273{
1274 struct fst_port_info *port;
1275 int pi;
1276 int txq_length;
1277 struct sk_buff *skb;
1278 unsigned long flags;
1279 struct net_device *dev;
1280
1281 /* Find a free buffer for the transmit
1282 * Step through each port on this card
1283 */
1284
1285 dbg(DBG_TX, "do_bottom_half_tx\n");
1286 for (pi = 0, port = card->ports; pi < card->nports; pi++, port++) {
1287 if (!port->run)
1288 continue;
1289
1290 dev = port_to_dev(port);
1291 while (!(FST_RDB(card, txDescrRing[pi][port->txpos].bits) &
1292 DMA_OWN) &&
1293 !(card->dmatx_in_progress)) {
1294 /* There doesn't seem to be a txdone event per-se
1295 * We seem to have to deduce it, by checking the DMA_OWN
1296 * bit on the next buffer we think we can use
1297 */
1298 spin_lock_irqsave(&card->card_lock, flags);
1299 txq_length = port->txqe - port->txqs;
1300 if (txq_length < 0) {
1301 /* This is the case where one has wrapped and the
1302 * maths gives us a negative number
1303 */
1304 txq_length = txq_length + FST_TXQ_DEPTH;
1305 }
1306 spin_unlock_irqrestore(&card->card_lock, flags);
1307 if (txq_length > 0) {
1308 /* There is something to send
1309 */
1310 spin_lock_irqsave(&card->card_lock, flags);
1311 skb = port->txq[port->txqs];
1312 port->txqs++;
1313 if (port->txqs == FST_TXQ_DEPTH)
1314 port->txqs = 0;
1315
1316 spin_unlock_irqrestore(&card->card_lock, flags);
1317 /* copy the data and set the required indicators on the
1318 * card.
1319 */
1320 FST_WRW(card, txDescrRing[pi][port->txpos].bcnt,
1321 cnv_bcnt(skb->len));
1322 if (skb->len < FST_MIN_DMA_LEN ||
1323 card->family == FST_FAMILY_TXP) {
1324 /* Enqueue the packet with normal io */
1325 memcpy_toio(card->mem +
1326 BUF_OFFSET(txBuffer[pi]
1327 [port->
1328 txpos][0]),
1329 skb->data, skb->len);
1330 FST_WRB(card,
1331 txDescrRing[pi][port->txpos].
1332 bits,
1333 DMA_OWN | TX_STP | TX_ENP);
1334 dev->stats.tx_packets++;
1335 dev->stats.tx_bytes += skb->len;
1336 netif_trans_update(dev);
1337 } else {
1338 /* Or do it through dma */
1339 memcpy(card->tx_dma_handle_host,
1340 skb->data, skb->len);
1341 card->dma_port_tx = port;
1342 card->dma_len_tx = skb->len;
1343 card->dma_txpos = port->txpos;
1344 fst_tx_dma(card,
1345 card->tx_dma_handle_card,
1346 BUF_OFFSET(txBuffer[pi]
1347 [port->txpos][0]),
1348 skb->len);
1349 }
1350 if (++port->txpos >= NUM_TX_BUFFER)
1351 port->txpos = 0;
1352 /* If we have flow control on, can we now release it?
1353 */
1354 if (port->start) {
1355 if (txq_length < fst_txq_low) {
1356 netif_wake_queue(port_to_dev
1357 (port));
1358 port->start = 0;
1359 }
1360 }
1361 dev_kfree_skb(skb);
1362 } else {
1363 /* Nothing to send so break out of the while loop
1364 */
1365 break;
1366 }
1367 }
1368 }
1369}
1370
1371static void
1372do_bottom_half_rx(struct fst_card_info *card)
1373{
1374 struct fst_port_info *port;
1375 int pi;
1376 int rx_count = 0;
1377
1378 /* Check for rx completions on all ports on this card */
1379 dbg(DBG_RX, "do_bottom_half_rx\n");
1380 for (pi = 0, port = card->ports; pi < card->nports; pi++, port++) {
1381 if (!port->run)
1382 continue;
1383
1384 while (!(FST_RDB(card, rxDescrRing[pi][port->rxpos].bits)
1385 & DMA_OWN) && !(card->dmarx_in_progress)) {
1386 if (rx_count > fst_max_reads) {
1387 /* Don't spend forever in receive processing
1388 * Schedule another event
1389 */
1390 fst_q_work_item(&fst_work_intq, card->card_no);
1391 tasklet_schedule(&fst_int_task);
1392 break; /* Leave the loop */
1393 }
1394 fst_intr_rx(card, port);
1395 rx_count++;
1396 }
1397 }
1398}
1399
1400/* The interrupt service routine
1401 * Dev_id is our fst_card_info pointer
1402 */
1403static irqreturn_t
1404fst_intr(int dummy, void *dev_id)
1405{
1406 struct fst_card_info *card = dev_id;
1407 struct fst_port_info *port;
1408 int rdidx; /* Event buffer indices */
1409 int wridx;
1410 int event; /* Actual event for processing */
1411 unsigned int dma_intcsr = 0;
1412 unsigned int do_card_interrupt;
1413 unsigned int int_retry_count;
1414
1415 /* Check to see if the interrupt was for this card
1416 * return if not
1417 * Note that the call to clear the interrupt is important
1418 */
1419 dbg(DBG_INTR, "intr: %d %p\n", card->irq, card);
1420 if (card->state != FST_RUNNING) {
1421 pr_err("Interrupt received for card %d in a non running state (%d)\n",
1422 card->card_no, card->state);
1423
1424 /* It is possible to really be running, i.e. we have re-loaded
1425 * a running card
1426 * Clear and reprime the interrupt source
1427 */
1428 fst_clear_intr(card);
1429 return IRQ_HANDLED;
1430 }
1431
1432 /* Clear and reprime the interrupt source */
1433 fst_clear_intr(card);
1434
1435 /* Is the interrupt for this card (handshake == 1)
1436 */
1437 do_card_interrupt = 0;
1438 if (FST_RDB(card, interruptHandshake) == 1) {
1439 do_card_interrupt += FST_CARD_INT;
1440 /* Set the software acknowledge */
1441 FST_WRB(card, interruptHandshake, 0xEE);
1442 }
1443 if (card->family == FST_FAMILY_TXU) {
1444 /* Is it a DMA Interrupt
1445 */
1446 dma_intcsr = inl(card->pci_conf + INTCSR_9054);
1447 if (dma_intcsr & 0x00200000) {
1448 /* DMA Channel 0 (Rx transfer complete)
1449 */
1450 dbg(DBG_RX, "DMA Rx xfer complete\n");
1451 outb(0x8, card->pci_conf + DMACSR0);
1452 fst_rx_dma_complete(card, card->dma_port_rx,
1453 card->dma_len_rx, card->dma_skb_rx,
1454 card->dma_rxpos);
1455 card->dmarx_in_progress = 0;
1456 do_card_interrupt += FST_RX_DMA_INT;
1457 }
1458 if (dma_intcsr & 0x00400000) {
1459 /* DMA Channel 1 (Tx transfer complete)
1460 */
1461 dbg(DBG_TX, "DMA Tx xfer complete\n");
1462 outb(0x8, card->pci_conf + DMACSR1);
1463 fst_tx_dma_complete(card, card->dma_port_tx,
1464 card->dma_len_tx, card->dma_txpos);
1465 card->dmatx_in_progress = 0;
1466 do_card_interrupt += FST_TX_DMA_INT;
1467 }
1468 }
1469
1470 /* Have we been missing Interrupts
1471 */
1472 int_retry_count = FST_RDL(card, interruptRetryCount);
1473 if (int_retry_count) {
1474 dbg(DBG_ASS, "Card %d int_retry_count is %d\n",
1475 card->card_no, int_retry_count);
1476 FST_WRL(card, interruptRetryCount, 0);
1477 }
1478
1479 if (!do_card_interrupt)
1480 return IRQ_HANDLED;
1481
1482 /* Scehdule the bottom half of the ISR */
1483 fst_q_work_item(&fst_work_intq, card->card_no);
1484 tasklet_schedule(&fst_int_task);
1485
1486 /* Drain the event queue */
1487 rdidx = FST_RDB(card, interruptEvent.rdindex) & 0x1f;
1488 wridx = FST_RDB(card, interruptEvent.wrindex) & 0x1f;
1489 while (rdidx != wridx) {
1490 event = FST_RDB(card, interruptEvent.evntbuff[rdidx]);
1491 port = &card->ports[event & 0x03];
1492
1493 dbg(DBG_INTR, "Processing Interrupt event: %x\n", event);
1494
1495 switch (event) {
1496 case TE1_ALMA:
1497 dbg(DBG_INTR, "TE1 Alarm intr\n");
1498 if (port->run)
1499 fst_intr_te1_alarm(card, port);
1500 break;
1501
1502 case CTLA_CHG:
1503 case CTLB_CHG:
1504 case CTLC_CHG:
1505 case CTLD_CHG:
1506 if (port->run)
1507 fst_intr_ctlchg(card, port);
1508 break;
1509
1510 case ABTA_SENT:
1511 case ABTB_SENT:
1512 case ABTC_SENT:
1513 case ABTD_SENT:
1514 dbg(DBG_TX, "Abort complete port %d\n", port->index);
1515 break;
1516
1517 case TXA_UNDF:
1518 case TXB_UNDF:
1519 case TXC_UNDF:
1520 case TXD_UNDF:
1521 /* Difficult to see how we'd get this given that we
1522 * always load up the entire packet for DMA.
1523 */
1524 dbg(DBG_TX, "Tx underflow port %d\n", port->index);
1525 port_to_dev(port)->stats.tx_errors++;
1526 port_to_dev(port)->stats.tx_fifo_errors++;
1527 dbg(DBG_ASS, "Tx underflow on card %d port %d\n",
1528 card->card_no, port->index);
1529 break;
1530
1531 case INIT_CPLT:
1532 dbg(DBG_INIT, "Card init OK intr\n");
1533 break;
1534
1535 case INIT_FAIL:
1536 dbg(DBG_INIT, "Card init FAILED intr\n");
1537 card->state = FST_IFAILED;
1538 break;
1539
1540 default:
1541 pr_err("intr: unknown card event %d. ignored\n", event);
1542 break;
1543 }
1544
1545 /* Bump and wrap the index */
1546 if (++rdidx >= MAX_CIRBUFF)
1547 rdidx = 0;
1548 }
1549 FST_WRB(card, interruptEvent.rdindex, rdidx);
1550 return IRQ_HANDLED;
1551}
1552
1553/* Check that the shared memory configuration is one that we can handle
1554 * and that some basic parameters are correct
1555 */
1556static void
1557check_started_ok(struct fst_card_info *card)
1558{
1559 int i;
1560
1561 /* Check structure version and end marker */
1562 if (FST_RDW(card, smcVersion) != SMC_VERSION) {
1563 pr_err("Bad shared memory version %d expected %d\n",
1564 FST_RDW(card, smcVersion), SMC_VERSION);
1565 card->state = FST_BADVERSION;
1566 return;
1567 }
1568 if (FST_RDL(card, endOfSmcSignature) != END_SIG) {
1569 pr_err("Missing shared memory signature\n");
1570 card->state = FST_BADVERSION;
1571 return;
1572 }
1573 /* Firmware status flag, 0x00 = initialising, 0x01 = OK, 0xFF = fail */
1574 i = FST_RDB(card, taskStatus);
1575 if (i == 0x01) {
1576 card->state = FST_RUNNING;
1577 } else if (i == 0xFF) {
1578 pr_err("Firmware initialisation failed. Card halted\n");
1579 card->state = FST_HALTED;
1580 return;
1581 } else if (i != 0x00) {
1582 pr_err("Unknown firmware status 0x%x\n", i);
1583 card->state = FST_HALTED;
1584 return;
1585 }
1586
1587 /* Finally check the number of ports reported by firmware against the
1588 * number we assumed at card detection. Should never happen with
1589 * existing firmware etc so we just report it for the moment.
1590 */
1591 if (FST_RDL(card, numberOfPorts) != card->nports) {
1592 pr_warn("Port count mismatch on card %d. Firmware thinks %d we say %d\n",
1593 card->card_no,
1594 FST_RDL(card, numberOfPorts), card->nports);
1595 }
1596}
1597
1598static int
1599set_conf_from_info(struct fst_card_info *card, struct fst_port_info *port,
1600 struct fstioc_info *info)
1601{
1602 int err;
1603 unsigned char my_framing;
1604
1605 /* Set things according to the user set valid flags
1606 * Several of the old options have been invalidated/replaced by the
1607 * generic hdlc package.
1608 */
1609 err = 0;
1610 if (info->valid & FSTVAL_PROTO) {
1611 if (info->proto == FST_RAW)
1612 port->mode = FST_RAW;
1613 else
1614 port->mode = FST_GEN_HDLC;
1615 }
1616
1617 if (info->valid & FSTVAL_CABLE)
1618 err = -EINVAL;
1619
1620 if (info->valid & FSTVAL_SPEED)
1621 err = -EINVAL;
1622
1623 if (info->valid & FSTVAL_PHASE)
1624 FST_WRB(card, portConfig[port->index].invertClock,
1625 info->invertClock);
1626 if (info->valid & FSTVAL_MODE)
1627 FST_WRW(card, cardMode, info->cardMode);
1628 if (info->valid & FSTVAL_TE1) {
1629 FST_WRL(card, suConfig.dataRate, info->lineSpeed);
1630 FST_WRB(card, suConfig.clocking, info->clockSource);
1631 my_framing = FRAMING_E1;
1632 if (info->framing == E1)
1633 my_framing = FRAMING_E1;
1634 if (info->framing == T1)
1635 my_framing = FRAMING_T1;
1636 if (info->framing == J1)
1637 my_framing = FRAMING_J1;
1638 FST_WRB(card, suConfig.framing, my_framing);
1639 FST_WRB(card, suConfig.structure, info->structure);
1640 FST_WRB(card, suConfig.interface, info->interface);
1641 FST_WRB(card, suConfig.coding, info->coding);
1642 FST_WRB(card, suConfig.lineBuildOut, info->lineBuildOut);
1643 FST_WRB(card, suConfig.equalizer, info->equalizer);
1644 FST_WRB(card, suConfig.transparentMode, info->transparentMode);
1645 FST_WRB(card, suConfig.loopMode, info->loopMode);
1646 FST_WRB(card, suConfig.range, info->range);
1647 FST_WRB(card, suConfig.txBufferMode, info->txBufferMode);
1648 FST_WRB(card, suConfig.rxBufferMode, info->rxBufferMode);
1649 FST_WRB(card, suConfig.startingSlot, info->startingSlot);
1650 FST_WRB(card, suConfig.losThreshold, info->losThreshold);
1651 if (info->idleCode)
1652 FST_WRB(card, suConfig.enableIdleCode, 1);
1653 else
1654 FST_WRB(card, suConfig.enableIdleCode, 0);
1655 FST_WRB(card, suConfig.idleCode, info->idleCode);
1656#if FST_DEBUG
1657 if (info->valid & FSTVAL_TE1) {
1658 printk("Setting TE1 data\n");
1659 printk("Line Speed = %d\n", info->lineSpeed);
1660 printk("Start slot = %d\n", info->startingSlot);
1661 printk("Clock source = %d\n", info->clockSource);
1662 printk("Framing = %d\n", my_framing);
1663 printk("Structure = %d\n", info->structure);
1664 printk("interface = %d\n", info->interface);
1665 printk("Coding = %d\n", info->coding);
1666 printk("Line build out = %d\n", info->lineBuildOut);
1667 printk("Equaliser = %d\n", info->equalizer);
1668 printk("Transparent mode = %d\n",
1669 info->transparentMode);
1670 printk("Loop mode = %d\n", info->loopMode);
1671 printk("Range = %d\n", info->range);
1672 printk("Tx Buffer mode = %d\n", info->txBufferMode);
1673 printk("Rx Buffer mode = %d\n", info->rxBufferMode);
1674 printk("LOS Threshold = %d\n", info->losThreshold);
1675 printk("Idle Code = %d\n", info->idleCode);
1676 }
1677#endif
1678 }
1679#if FST_DEBUG
1680 if (info->valid & FSTVAL_DEBUG)
1681 fst_debug_mask = info->debug;
1682#endif
1683
1684 return err;
1685}
1686
1687static void
1688gather_conf_info(struct fst_card_info *card, struct fst_port_info *port,
1689 struct fstioc_info *info)
1690{
1691 int i;
1692
1693 memset(info, 0, sizeof(struct fstioc_info));
1694
1695 i = port->index;
1696 info->kernelVersion = LINUX_VERSION_CODE;
1697 info->nports = card->nports;
1698 info->type = card->type;
1699 info->state = card->state;
1700 info->proto = FST_GEN_HDLC;
1701 info->index = i;
1702#if FST_DEBUG
1703 info->debug = fst_debug_mask;
1704#endif
1705
1706 /* Only mark information as valid if card is running.
1707 * Copy the data anyway in case it is useful for diagnostics
1708 */
1709 info->valid = ((card->state == FST_RUNNING) ? FSTVAL_ALL : FSTVAL_CARD)
1710#if FST_DEBUG
1711 | FSTVAL_DEBUG
1712#endif
1713 ;
1714
1715 info->lineInterface = FST_RDW(card, portConfig[i].lineInterface);
1716 info->internalClock = FST_RDB(card, portConfig[i].internalClock);
1717 info->lineSpeed = FST_RDL(card, portConfig[i].lineSpeed);
1718 info->invertClock = FST_RDB(card, portConfig[i].invertClock);
1719 info->v24IpSts = FST_RDL(card, v24IpSts[i]);
1720 info->v24OpSts = FST_RDL(card, v24OpSts[i]);
1721 info->clockStatus = FST_RDW(card, clockStatus[i]);
1722 info->cableStatus = FST_RDW(card, cableStatus);
1723 info->cardMode = FST_RDW(card, cardMode);
1724 info->smcFirmwareVersion = FST_RDL(card, smcFirmwareVersion);
1725
1726 /* The T2U can report cable presence for both A or B
1727 * in bits 0 and 1 of cableStatus. See which port we are and
1728 * do the mapping.
1729 */
1730 if (card->family == FST_FAMILY_TXU) {
1731 if (port->index == 0) {
1732 /* Port A
1733 */
1734 info->cableStatus = info->cableStatus & 1;
1735 } else {
1736 /* Port B
1737 */
1738 info->cableStatus = info->cableStatus >> 1;
1739 info->cableStatus = info->cableStatus & 1;
1740 }
1741 }
1742 /* Some additional bits if we are TE1
1743 */
1744 if (card->type == FST_TYPE_TE1) {
1745 info->lineSpeed = FST_RDL(card, suConfig.dataRate);
1746 info->clockSource = FST_RDB(card, suConfig.clocking);
1747 info->framing = FST_RDB(card, suConfig.framing);
1748 info->structure = FST_RDB(card, suConfig.structure);
1749 info->interface = FST_RDB(card, suConfig.interface);
1750 info->coding = FST_RDB(card, suConfig.coding);
1751 info->lineBuildOut = FST_RDB(card, suConfig.lineBuildOut);
1752 info->equalizer = FST_RDB(card, suConfig.equalizer);
1753 info->loopMode = FST_RDB(card, suConfig.loopMode);
1754 info->range = FST_RDB(card, suConfig.range);
1755 info->txBufferMode = FST_RDB(card, suConfig.txBufferMode);
1756 info->rxBufferMode = FST_RDB(card, suConfig.rxBufferMode);
1757 info->startingSlot = FST_RDB(card, suConfig.startingSlot);
1758 info->losThreshold = FST_RDB(card, suConfig.losThreshold);
1759 if (FST_RDB(card, suConfig.enableIdleCode))
1760 info->idleCode = FST_RDB(card, suConfig.idleCode);
1761 else
1762 info->idleCode = 0;
1763 info->receiveBufferDelay =
1764 FST_RDL(card, suStatus.receiveBufferDelay);
1765 info->framingErrorCount =
1766 FST_RDL(card, suStatus.framingErrorCount);
1767 info->codeViolationCount =
1768 FST_RDL(card, suStatus.codeViolationCount);
1769 info->crcErrorCount = FST_RDL(card, suStatus.crcErrorCount);
1770 info->lineAttenuation = FST_RDL(card, suStatus.lineAttenuation);
1771 info->lossOfSignal = FST_RDB(card, suStatus.lossOfSignal);
1772 info->receiveRemoteAlarm =
1773 FST_RDB(card, suStatus.receiveRemoteAlarm);
1774 info->alarmIndicationSignal =
1775 FST_RDB(card, suStatus.alarmIndicationSignal);
1776 }
1777}
1778
1779static int
1780fst_set_iface(struct fst_card_info *card, struct fst_port_info *port,
1781 struct if_settings *ifs)
1782{
1783 sync_serial_settings sync;
1784 int i;
1785
1786 if (ifs->size != sizeof(sync))
1787 return -ENOMEM;
1788
1789 if (copy_from_user(&sync, ifs->ifs_ifsu.sync, sizeof(sync)))
1790 return -EFAULT;
1791
1792 if (sync.loopback)
1793 return -EINVAL;
1794
1795 i = port->index;
1796
1797 switch (ifs->type) {
1798 case IF_IFACE_V35:
1799 FST_WRW(card, portConfig[i].lineInterface, V35);
1800 port->hwif = V35;
1801 break;
1802
1803 case IF_IFACE_V24:
1804 FST_WRW(card, portConfig[i].lineInterface, V24);
1805 port->hwif = V24;
1806 break;
1807
1808 case IF_IFACE_X21:
1809 FST_WRW(card, portConfig[i].lineInterface, X21);
1810 port->hwif = X21;
1811 break;
1812
1813 case IF_IFACE_X21D:
1814 FST_WRW(card, portConfig[i].lineInterface, X21D);
1815 port->hwif = X21D;
1816 break;
1817
1818 case IF_IFACE_T1:
1819 FST_WRW(card, portConfig[i].lineInterface, T1);
1820 port->hwif = T1;
1821 break;
1822
1823 case IF_IFACE_E1:
1824 FST_WRW(card, portConfig[i].lineInterface, E1);
1825 port->hwif = E1;
1826 break;
1827
1828 case IF_IFACE_SYNC_SERIAL:
1829 break;
1830
1831 default:
1832 return -EINVAL;
1833 }
1834
1835 switch (sync.clock_type) {
1836 case CLOCK_EXT:
1837 FST_WRB(card, portConfig[i].internalClock, EXTCLK);
1838 break;
1839
1840 case CLOCK_INT:
1841 FST_WRB(card, portConfig[i].internalClock, INTCLK);
1842 break;
1843
1844 default:
1845 return -EINVAL;
1846 }
1847 FST_WRL(card, portConfig[i].lineSpeed, sync.clock_rate);
1848 return 0;
1849}
1850
1851static int
1852fst_get_iface(struct fst_card_info *card, struct fst_port_info *port,
1853 struct if_settings *ifs)
1854{
1855 sync_serial_settings sync;
1856 int i;
1857
1858 /* First check what line type is set, we'll default to reporting X.21
1859 * if nothing is set as IF_IFACE_SYNC_SERIAL implies it can't be
1860 * changed
1861 */
1862 switch (port->hwif) {
1863 case E1:
1864 ifs->type = IF_IFACE_E1;
1865 break;
1866 case T1:
1867 ifs->type = IF_IFACE_T1;
1868 break;
1869 case V35:
1870 ifs->type = IF_IFACE_V35;
1871 break;
1872 case V24:
1873 ifs->type = IF_IFACE_V24;
1874 break;
1875 case X21D:
1876 ifs->type = IF_IFACE_X21D;
1877 break;
1878 case X21:
1879 default:
1880 ifs->type = IF_IFACE_X21;
1881 break;
1882 }
1883 if (!ifs->size)
1884 return 0; /* only type requested */
1885
1886 if (ifs->size < sizeof(sync))
1887 return -ENOMEM;
1888
1889 i = port->index;
1890 memset(&sync, 0, sizeof(sync));
1891 sync.clock_rate = FST_RDL(card, portConfig[i].lineSpeed);
1892 /* Lucky card and linux use same encoding here */
1893 sync.clock_type = FST_RDB(card, portConfig[i].internalClock) ==
1894 INTCLK ? CLOCK_INT : CLOCK_EXT;
1895 sync.loopback = 0;
1896
1897 if (copy_to_user(ifs->ifs_ifsu.sync, &sync, sizeof(sync)))
1898 return -EFAULT;
1899
1900 ifs->size = sizeof(sync);
1901 return 0;
1902}
1903
1904static int
1905fst_siocdevprivate(struct net_device *dev, struct ifreq *ifr, void __user *data, int cmd)
1906{
1907 struct fst_card_info *card;
1908 struct fst_port_info *port;
1909 struct fstioc_write wrthdr;
1910 struct fstioc_info info;
1911 unsigned long flags;
1912 void *buf;
1913
1914 dbg(DBG_IOCTL, "ioctl: %x, %p\n", cmd, data);
1915
1916 port = dev_to_port(dev);
1917 card = port->card;
1918
1919 if (!capable(CAP_NET_ADMIN))
1920 return -EPERM;
1921
1922 switch (cmd) {
1923 case FSTCPURESET:
1924 fst_cpureset(card);
1925 card->state = FST_RESET;
1926 return 0;
1927
1928 case FSTCPURELEASE:
1929 fst_cpurelease(card);
1930 card->state = FST_STARTING;
1931 return 0;
1932
1933 case FSTWRITE: /* Code write (download) */
1934
1935 /* First copy in the header with the length and offset of data
1936 * to write
1937 */
1938 if (!data)
1939 return -EINVAL;
1940
1941 if (copy_from_user(&wrthdr, data, sizeof(struct fstioc_write)))
1942 return -EFAULT;
1943
1944 /* Sanity check the parameters. We don't support partial writes
1945 * when going over the top
1946 */
1947 if (wrthdr.size > FST_MEMSIZE || wrthdr.offset > FST_MEMSIZE ||
1948 wrthdr.size + wrthdr.offset > FST_MEMSIZE)
1949 return -ENXIO;
1950
1951 /* Now copy the data to the card. */
1952
1953 buf = memdup_user(data + sizeof(struct fstioc_write),
1954 wrthdr.size);
1955 if (IS_ERR(buf))
1956 return PTR_ERR(buf);
1957
1958 memcpy_toio(card->mem + wrthdr.offset, buf, wrthdr.size);
1959 kfree(buf);
1960
1961 /* Writes to the memory of a card in the reset state constitute
1962 * a download
1963 */
1964 if (card->state == FST_RESET)
1965 card->state = FST_DOWNLOAD;
1966
1967 return 0;
1968
1969 case FSTGETCONF:
1970
1971 /* If card has just been started check the shared memory config
1972 * version and marker
1973 */
1974 if (card->state == FST_STARTING) {
1975 check_started_ok(card);
1976
1977 /* If everything checked out enable card interrupts */
1978 if (card->state == FST_RUNNING) {
1979 spin_lock_irqsave(&card->card_lock, flags);
1980 fst_enable_intr(card);
1981 FST_WRB(card, interruptHandshake, 0xEE);
1982 spin_unlock_irqrestore(&card->card_lock, flags);
1983 }
1984 }
1985
1986 if (!data)
1987 return -EINVAL;
1988
1989 gather_conf_info(card, port, &info);
1990
1991 if (copy_to_user(data, &info, sizeof(info)))
1992 return -EFAULT;
1993
1994 return 0;
1995
1996 case FSTSETCONF:
1997 /* Most of the settings have been moved to the generic ioctls
1998 * this just covers debug and board ident now
1999 */
2000
2001 if (card->state != FST_RUNNING) {
2002 pr_err("Attempt to configure card %d in non-running state (%d)\n",
2003 card->card_no, card->state);
2004 return -EIO;
2005 }
2006 if (copy_from_user(&info, data, sizeof(info)))
2007 return -EFAULT;
2008
2009 return set_conf_from_info(card, port, &info);
2010 default:
2011 return -EINVAL;
2012 }
2013}
2014
2015static int
2016fst_ioctl(struct net_device *dev, struct if_settings *ifs)
2017{
2018 struct fst_card_info *card;
2019 struct fst_port_info *port;
2020
2021 dbg(DBG_IOCTL, "SIOCDEVPRIVATE, %x\n", ifs->type);
2022
2023 port = dev_to_port(dev);
2024 card = port->card;
2025
2026 if (!capable(CAP_NET_ADMIN))
2027 return -EPERM;
2028
2029 switch (ifs->type) {
2030 case IF_GET_IFACE:
2031 return fst_get_iface(card, port, ifs);
2032
2033 case IF_IFACE_SYNC_SERIAL:
2034 case IF_IFACE_V35:
2035 case IF_IFACE_V24:
2036 case IF_IFACE_X21:
2037 case IF_IFACE_X21D:
2038 case IF_IFACE_T1:
2039 case IF_IFACE_E1:
2040 return fst_set_iface(card, port, ifs);
2041
2042 case IF_PROTO_RAW:
2043 port->mode = FST_RAW;
2044 return 0;
2045
2046 case IF_GET_PROTO:
2047 if (port->mode == FST_RAW) {
2048 ifs->type = IF_PROTO_RAW;
2049 return 0;
2050 }
2051 return hdlc_ioctl(dev, ifs);
2052
2053 default:
2054 port->mode = FST_GEN_HDLC;
2055 dbg(DBG_IOCTL, "Passing this type to hdlc %x\n",
2056 ifs->type);
2057 return hdlc_ioctl(dev, ifs);
2058 }
2059}
2060
2061static void
2062fst_openport(struct fst_port_info *port)
2063{
2064 int signals;
2065
2066 /* Only init things if card is actually running. This allows open to
2067 * succeed for downloads etc.
2068 */
2069 if (port->card->state == FST_RUNNING) {
2070 if (port->run) {
2071 dbg(DBG_OPEN, "open: found port already running\n");
2072
2073 fst_issue_cmd(port, STOPPORT);
2074 port->run = 0;
2075 }
2076
2077 fst_rx_config(port);
2078 fst_tx_config(port);
2079 fst_op_raise(port, OPSTS_RTS | OPSTS_DTR);
2080
2081 fst_issue_cmd(port, STARTPORT);
2082 port->run = 1;
2083
2084 signals = FST_RDL(port->card, v24DebouncedSts[port->index]);
2085 if (signals & ((port->hwif == X21 || port->hwif == X21D)
2086 ? IPSTS_INDICATE : IPSTS_DCD))
2087 netif_carrier_on(port_to_dev(port));
2088 else
2089 netif_carrier_off(port_to_dev(port));
2090
2091 port->txqe = 0;
2092 port->txqs = 0;
2093 }
2094}
2095
2096static void
2097fst_closeport(struct fst_port_info *port)
2098{
2099 if (port->card->state == FST_RUNNING) {
2100 if (port->run) {
2101 port->run = 0;
2102 fst_op_lower(port, OPSTS_RTS | OPSTS_DTR);
2103
2104 fst_issue_cmd(port, STOPPORT);
2105 } else {
2106 dbg(DBG_OPEN, "close: port not running\n");
2107 }
2108 }
2109}
2110
2111static int
2112fst_open(struct net_device *dev)
2113{
2114 int err;
2115 struct fst_port_info *port;
2116
2117 port = dev_to_port(dev);
2118 if (!try_module_get(THIS_MODULE))
2119 return -EBUSY;
2120
2121 if (port->mode != FST_RAW) {
2122 err = hdlc_open(dev);
2123 if (err) {
2124 module_put(THIS_MODULE);
2125 return err;
2126 }
2127 }
2128
2129 fst_openport(port);
2130 netif_wake_queue(dev);
2131 return 0;
2132}
2133
2134static int
2135fst_close(struct net_device *dev)
2136{
2137 struct fst_port_info *port;
2138 struct fst_card_info *card;
2139 unsigned char tx_dma_done;
2140 unsigned char rx_dma_done;
2141
2142 port = dev_to_port(dev);
2143 card = port->card;
2144
2145 tx_dma_done = inb(card->pci_conf + DMACSR1);
2146 rx_dma_done = inb(card->pci_conf + DMACSR0);
2147 dbg(DBG_OPEN,
2148 "Port Close: tx_dma_in_progress = %d (%x) rx_dma_in_progress = %d (%x)\n",
2149 card->dmatx_in_progress, tx_dma_done, card->dmarx_in_progress,
2150 rx_dma_done);
2151
2152 netif_stop_queue(dev);
2153 fst_closeport(dev_to_port(dev));
2154 if (port->mode != FST_RAW)
2155 hdlc_close(dev);
2156
2157 module_put(THIS_MODULE);
2158 return 0;
2159}
2160
2161static int
2162fst_attach(struct net_device *dev, unsigned short encoding, unsigned short parity)
2163{
2164 /* Setting currently fixed in FarSync card so we check and forget
2165 */
2166 if (encoding != ENCODING_NRZ || parity != PARITY_CRC16_PR1_CCITT)
2167 return -EINVAL;
2168 return 0;
2169}
2170
2171static void
2172fst_tx_timeout(struct net_device *dev, unsigned int txqueue)
2173{
2174 struct fst_port_info *port;
2175 struct fst_card_info *card;
2176
2177 port = dev_to_port(dev);
2178 card = port->card;
2179 dev->stats.tx_errors++;
2180 dev->stats.tx_aborted_errors++;
2181 dbg(DBG_ASS, "Tx timeout card %d port %d\n",
2182 card->card_no, port->index);
2183 fst_issue_cmd(port, ABORTTX);
2184
2185 netif_trans_update(dev);
2186 netif_wake_queue(dev);
2187 port->start = 0;
2188}
2189
2190static netdev_tx_t
2191fst_start_xmit(struct sk_buff *skb, struct net_device *dev)
2192{
2193 struct fst_card_info *card;
2194 struct fst_port_info *port;
2195 unsigned long flags;
2196 int txq_length;
2197
2198 port = dev_to_port(dev);
2199 card = port->card;
2200 dbg(DBG_TX, "fst_start_xmit: length = %d\n", skb->len);
2201
2202 /* Drop packet with error if we don't have carrier */
2203 if (!netif_carrier_ok(dev)) {
2204 dev_kfree_skb(skb);
2205 dev->stats.tx_errors++;
2206 dev->stats.tx_carrier_errors++;
2207 dbg(DBG_ASS,
2208 "Tried to transmit but no carrier on card %d port %d\n",
2209 card->card_no, port->index);
2210 return NETDEV_TX_OK;
2211 }
2212
2213 /* Drop it if it's too big! MTU failure ? */
2214 if (skb->len > LEN_TX_BUFFER) {
2215 dbg(DBG_ASS, "Packet too large %d vs %d\n", skb->len,
2216 LEN_TX_BUFFER);
2217 dev_kfree_skb(skb);
2218 dev->stats.tx_errors++;
2219 return NETDEV_TX_OK;
2220 }
2221
2222 /* We are always going to queue the packet
2223 * so that the bottom half is the only place we tx from
2224 * Check there is room in the port txq
2225 */
2226 spin_lock_irqsave(&card->card_lock, flags);
2227 txq_length = port->txqe - port->txqs;
2228 if (txq_length < 0) {
2229 /* This is the case where the next free has wrapped but the
2230 * last used hasn't
2231 */
2232 txq_length = txq_length + FST_TXQ_DEPTH;
2233 }
2234 spin_unlock_irqrestore(&card->card_lock, flags);
2235 if (txq_length > fst_txq_high) {
2236 /* We have got enough buffers in the pipeline. Ask the network
2237 * layer to stop sending frames down
2238 */
2239 netif_stop_queue(dev);
2240 port->start = 1; /* I'm using this to signal stop sent up */
2241 }
2242
2243 if (txq_length == FST_TXQ_DEPTH - 1) {
2244 /* This shouldn't have happened but such is life
2245 */
2246 dev_kfree_skb(skb);
2247 dev->stats.tx_errors++;
2248 dbg(DBG_ASS, "Tx queue overflow card %d port %d\n",
2249 card->card_no, port->index);
2250 return NETDEV_TX_OK;
2251 }
2252
2253 /* queue the buffer
2254 */
2255 spin_lock_irqsave(&card->card_lock, flags);
2256 port->txq[port->txqe] = skb;
2257 port->txqe++;
2258 if (port->txqe == FST_TXQ_DEPTH)
2259 port->txqe = 0;
2260 spin_unlock_irqrestore(&card->card_lock, flags);
2261
2262 /* Scehdule the bottom half which now does transmit processing */
2263 fst_q_work_item(&fst_work_txq, card->card_no);
2264 tasklet_schedule(&fst_tx_task);
2265
2266 return NETDEV_TX_OK;
2267}
2268
2269/* Card setup having checked hardware resources.
2270 * Should be pretty bizarre if we get an error here (kernel memory
2271 * exhaustion is one possibility). If we do see a problem we report it
2272 * via a printk and leave the corresponding interface and all that follow
2273 * disabled.
2274 */
2275static char *type_strings[] = {
2276 "no hardware", /* Should never be seen */
2277 "FarSync T2P",
2278 "FarSync T4P",
2279 "FarSync T1U",
2280 "FarSync T2U",
2281 "FarSync T4U",
2282 "FarSync TE1"
2283};
2284
2285static int
2286fst_init_card(struct fst_card_info *card)
2287{
2288 int i;
2289 int err;
2290
2291 /* We're working on a number of ports based on the card ID. If the
2292 * firmware detects something different later (should never happen)
2293 * we'll have to revise it in some way then.
2294 */
2295 for (i = 0; i < card->nports; i++) {
2296 err = register_hdlc_device(card->ports[i].dev);
2297 if (err < 0) {
2298 pr_err("Cannot register HDLC device for port %d (errno %d)\n",
2299 i, -err);
2300 while (i--)
2301 unregister_hdlc_device(card->ports[i].dev);
2302 return err;
2303 }
2304 }
2305
2306 pr_info("%s-%s: %s IRQ%d, %d ports\n",
2307 port_to_dev(&card->ports[0])->name,
2308 port_to_dev(&card->ports[card->nports - 1])->name,
2309 type_strings[card->type], card->irq, card->nports);
2310 return 0;
2311}
2312
2313static const struct net_device_ops fst_ops = {
2314 .ndo_open = fst_open,
2315 .ndo_stop = fst_close,
2316 .ndo_start_xmit = hdlc_start_xmit,
2317 .ndo_siocwandev = fst_ioctl,
2318 .ndo_siocdevprivate = fst_siocdevprivate,
2319 .ndo_tx_timeout = fst_tx_timeout,
2320};
2321
2322/* Initialise card when detected.
2323 * Returns 0 to indicate success, or errno otherwise.
2324 */
2325static int
2326fst_add_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2327{
2328 static int no_of_cards_added;
2329 struct fst_card_info *card;
2330 int err = 0;
2331 int i;
2332
2333 printk_once(KERN_INFO
2334 pr_fmt("FarSync WAN driver " FST_USER_VERSION
2335 " (c) 2001-2004 FarSite Communications Ltd.\n"));
2336#if FST_DEBUG
2337 dbg(DBG_ASS, "The value of debug mask is %x\n", fst_debug_mask);
2338#endif
2339 /* We are going to be clever and allow certain cards not to be
2340 * configured. An exclude list can be provided in /etc/modules.conf
2341 */
2342 if (fst_excluded_cards != 0) {
2343 /* There are cards to exclude
2344 *
2345 */
2346 for (i = 0; i < fst_excluded_cards; i++) {
2347 if (pdev->devfn >> 3 == fst_excluded_list[i]) {
2348 pr_info("FarSync PCI device %d not assigned\n",
2349 (pdev->devfn) >> 3);
2350 return -EBUSY;
2351 }
2352 }
2353 }
2354
2355 /* Allocate driver private data */
2356 card = kzalloc_obj(struct fst_card_info);
2357 if (!card)
2358 return -ENOMEM;
2359
2360 /* Try to enable the device */
2361 err = pci_enable_device(pdev);
2362 if (err) {
2363 pr_err("Failed to enable card. Err %d\n", -err);
2364 goto enable_fail;
2365 }
2366
2367 err = pci_request_regions(pdev, "FarSync");
2368 if (err) {
2369 pr_err("Failed to allocate regions. Err %d\n", -err);
2370 goto regions_fail;
2371 }
2372
2373 /* Get virtual addresses of memory regions */
2374 card->pci_conf = pci_resource_start(pdev, 1);
2375 card->phys_mem = pci_resource_start(pdev, 2);
2376 card->phys_ctlmem = pci_resource_start(pdev, 3);
2377 card->mem = ioremap(card->phys_mem, FST_MEMSIZE);
2378 if (!card->mem) {
2379 pr_err("Physical memory remap failed\n");
2380 err = -ENODEV;
2381 goto ioremap_physmem_fail;
2382 }
2383 card->ctlmem = ioremap(card->phys_ctlmem, 0x10);
2384 if (!card->ctlmem) {
2385 pr_err("Control memory remap failed\n");
2386 err = -ENODEV;
2387 goto ioremap_ctlmem_fail;
2388 }
2389 dbg(DBG_PCI, "kernel mem %p, ctlmem %p\n", card->mem, card->ctlmem);
2390
2391 /* Register the interrupt handler */
2392 if (request_irq(pdev->irq, fst_intr, IRQF_SHARED, FST_DEV_NAME, card)) {
2393 pr_err("Unable to register interrupt %d\n", card->irq);
2394 err = -ENODEV;
2395 goto irq_fail;
2396 }
2397
2398 /* Record info we need */
2399 card->irq = pdev->irq;
2400 card->type = ent->driver_data;
2401 card->family = ((ent->driver_data == FST_TYPE_T2P) ||
2402 (ent->driver_data == FST_TYPE_T4P))
2403 ? FST_FAMILY_TXP : FST_FAMILY_TXU;
2404 if (ent->driver_data == FST_TYPE_T1U ||
2405 ent->driver_data == FST_TYPE_TE1)
2406 card->nports = 1;
2407 else
2408 card->nports = ((ent->driver_data == FST_TYPE_T2P) ||
2409 (ent->driver_data == FST_TYPE_T2U)) ? 2 : 4;
2410
2411 card->state = FST_UNINIT;
2412 spin_lock_init(&card->card_lock);
2413
2414 for (i = 0; i < card->nports; i++) {
2415 struct net_device *dev = alloc_hdlcdev(&card->ports[i]);
2416 hdlc_device *hdlc;
2417
2418 if (!dev) {
2419 while (i--)
2420 free_netdev(card->ports[i].dev);
2421 pr_err("FarSync: out of memory\n");
2422 err = -ENOMEM;
2423 goto hdlcdev_fail;
2424 }
2425 card->ports[i].dev = dev;
2426 card->ports[i].card = card;
2427 card->ports[i].index = i;
2428 card->ports[i].run = 0;
2429
2430 hdlc = dev_to_hdlc(dev);
2431
2432 /* Fill in the net device info */
2433 /* Since this is a PCI setup this is purely
2434 * informational. Give them the buffer addresses
2435 * and basic card I/O.
2436 */
2437 dev->mem_start = card->phys_mem
2438 + BUF_OFFSET(txBuffer[i][0][0]);
2439 dev->mem_end = card->phys_mem
2440 + BUF_OFFSET(txBuffer[i][NUM_TX_BUFFER - 1][LEN_RX_BUFFER - 1]);
2441 dev->base_addr = card->pci_conf;
2442 dev->irq = card->irq;
2443
2444 dev->netdev_ops = &fst_ops;
2445 dev->tx_queue_len = FST_TX_QUEUE_LEN;
2446 dev->watchdog_timeo = FST_TX_TIMEOUT;
2447 hdlc->attach = fst_attach;
2448 hdlc->xmit = fst_start_xmit;
2449 }
2450
2451 card->device = pdev;
2452
2453 dbg(DBG_PCI, "type %d nports %d irq %d\n", card->type,
2454 card->nports, card->irq);
2455 dbg(DBG_PCI, "conf %04x mem %08x ctlmem %08x\n",
2456 card->pci_conf, card->phys_mem, card->phys_ctlmem);
2457
2458 /* Reset the card's processor */
2459 fst_cpureset(card);
2460 card->state = FST_RESET;
2461
2462 /* Initialise DMA (if required) */
2463 fst_init_dma(card);
2464
2465 /* Record driver data for later use */
2466 pci_set_drvdata(pdev, card);
2467
2468 /* Remainder of card setup */
2469 if (no_of_cards_added >= FST_MAX_CARDS) {
2470 pr_err("FarSync: too many cards\n");
2471 err = -ENOMEM;
2472 goto card_array_fail;
2473 }
2474 fst_card_array[no_of_cards_added] = card;
2475 card->card_no = no_of_cards_added++; /* Record instance and bump it */
2476 err = fst_init_card(card);
2477 if (err)
2478 goto init_card_fail;
2479 if (card->family == FST_FAMILY_TXU) {
2480 /* Allocate a dma buffer for transmit and receives
2481 */
2482 card->rx_dma_handle_host =
2483 dma_alloc_coherent(&card->device->dev, FST_MAX_MTU,
2484 &card->rx_dma_handle_card, GFP_KERNEL);
2485 if (!card->rx_dma_handle_host) {
2486 pr_err("Could not allocate rx dma buffer\n");
2487 err = -ENOMEM;
2488 goto rx_dma_fail;
2489 }
2490 card->tx_dma_handle_host =
2491 dma_alloc_coherent(&card->device->dev, FST_MAX_MTU,
2492 &card->tx_dma_handle_card, GFP_KERNEL);
2493 if (!card->tx_dma_handle_host) {
2494 pr_err("Could not allocate tx dma buffer\n");
2495 err = -ENOMEM;
2496 goto tx_dma_fail;
2497 }
2498 }
2499 return 0; /* Success */
2500
2501tx_dma_fail:
2502 dma_free_coherent(&card->device->dev, FST_MAX_MTU,
2503 card->rx_dma_handle_host, card->rx_dma_handle_card);
2504rx_dma_fail:
2505 fst_disable_intr(card);
2506 for (i = 0 ; i < card->nports ; i++)
2507 unregister_hdlc_device(card->ports[i].dev);
2508init_card_fail:
2509 fst_card_array[card->card_no] = NULL;
2510card_array_fail:
2511 for (i = 0 ; i < card->nports ; i++)
2512 free_netdev(card->ports[i].dev);
2513hdlcdev_fail:
2514 free_irq(card->irq, card);
2515irq_fail:
2516 iounmap(card->ctlmem);
2517ioremap_ctlmem_fail:
2518 iounmap(card->mem);
2519ioremap_physmem_fail:
2520 pci_release_regions(pdev);
2521regions_fail:
2522 pci_disable_device(pdev);
2523enable_fail:
2524 kfree(card);
2525 return err;
2526}
2527
2528/* Cleanup and close down a card
2529 */
2530static void
2531fst_remove_one(struct pci_dev *pdev)
2532{
2533 struct fst_card_info *card;
2534 int i;
2535
2536 card = pci_get_drvdata(pdev);
2537
2538 for (i = 0; i < card->nports; i++) {
2539 struct net_device *dev = port_to_dev(&card->ports[i]);
2540
2541 unregister_hdlc_device(dev);
2542 free_netdev(dev);
2543 }
2544
2545 fst_disable_intr(card);
2546 free_irq(card->irq, card);
2547 tasklet_kill(&fst_tx_task);
2548 tasklet_kill(&fst_int_task);
2549
2550 iounmap(card->ctlmem);
2551 iounmap(card->mem);
2552 pci_release_regions(pdev);
2553 if (card->family == FST_FAMILY_TXU) {
2554 /* Free dma buffers
2555 */
2556 dma_free_coherent(&card->device->dev, FST_MAX_MTU,
2557 card->rx_dma_handle_host,
2558 card->rx_dma_handle_card);
2559 dma_free_coherent(&card->device->dev, FST_MAX_MTU,
2560 card->tx_dma_handle_host,
2561 card->tx_dma_handle_card);
2562 }
2563 fst_card_array[card->card_no] = NULL;
2564 kfree(card);
2565}
2566
2567static struct pci_driver fst_driver = {
2568 .name = FST_NAME,
2569 .id_table = fst_pci_dev_id,
2570 .probe = fst_add_one,
2571 .remove = fst_remove_one,
2572};
2573
2574static int __init
2575fst_init(void)
2576{
2577 int i;
2578
2579 for (i = 0; i < FST_MAX_CARDS; i++)
2580 fst_card_array[i] = NULL;
2581 return pci_register_driver(&fst_driver);
2582}
2583
2584static void __exit
2585fst_cleanup_module(void)
2586{
2587 pr_info("FarSync WAN driver unloading\n");
2588 pci_unregister_driver(&fst_driver);
2589}
2590
2591module_init(fst_init);
2592module_exit(fst_cleanup_module);