| 1 | |
| 2 | |
| 3 |
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| 4 | #include <linux/clk.h>
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| 5 | #include <linux/delay.h>
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| 6 | #include <linux/hwspinlock.h>
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| 7 | #include <linux/io.h>
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| 8 | #include <linux/module.h>
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| 9 | #include <linux/nvmem-provider.h>
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| 10 | #include <linux/of.h>
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| 11 | #include <linux/platform_device.h>
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| 12 |
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| 13 | #define SPRD_EFUSE_ENABLE 0x20
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| 14 | #define SPRD_EFUSE_ERR_FLAG 0x24
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| 15 | #define SPRD_EFUSE_ERR_CLR 0x28
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| 16 | #define SPRD_EFUSE_MAGIC_NUM 0x2c
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| 17 | #define SPRD_EFUSE_FW_CFG 0x50
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| 18 | #define SPRD_EFUSE_PW_SWT 0x54
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| 19 | #define SPRD_EFUSE_MEM(val) (0x1000 + ((val) << 2))
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| 20 |
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| 21 | #define SPRD_EFUSE_VDD_EN BIT(0)
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| 22 | #define SPRD_EFUSE_AUTO_CHECK_EN BIT(1)
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| 23 | #define SPRD_EFUSE_DOUBLE_EN BIT(2)
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| 24 | #define SPRD_EFUSE_MARGIN_RD_EN BIT(3)
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| 25 | #define SPRD_EFUSE_LOCK_WR_EN BIT(4)
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| 26 |
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| 27 | #define SPRD_EFUSE_ERR_CLR_MASK GENMASK(13, 0)
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| 28 |
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| 29 | #define SPRD_EFUSE_ENK1_ON BIT(0)
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| 30 | #define SPRD_EFUSE_ENK2_ON BIT(1)
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| 31 | #define SPRD_EFUSE_PROG_EN BIT(2)
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| 32 |
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| 33 | #define SPRD_EFUSE_MAGIC_NUMBER 0x8810
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| 34 |
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| 35 |
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| 36 | #define SPRD_EFUSE_BLOCK_WIDTH 4
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| 37 |
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| 38 | |
| 39 | * The Spreadtrum AP efuse contains 2 parts: normal efuse and secure efuse,
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| 40 | * and we can only access the normal efuse in kernel. So define the normal
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| 41 | * block offset index and normal block numbers.
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| 42 |
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| 43 | #define SPRD_EFUSE_NORMAL_BLOCK_NUMS 24
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| 44 | #define SPRD_EFUSE_NORMAL_BLOCK_OFFSET 72
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| 45 |
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| 46 |
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| 47 | #define SPRD_EFUSE_HWLOCK_TIMEOUT 5000
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| 48 |
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| 49 | |
| 50 | * Since different Spreadtrum SoC chip can have different normal block numbers
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| 51 | * and offset. And some SoC can support block double feature, which means
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| 52 | * when reading or writing data to efuse memory, the controller can save double
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| 53 | * data in case one data become incorrect after a long period.
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| 54 | *
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| 55 | * Thus we should save them in the device data structure.
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| 56 |
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| 57 | struct sprd_efuse_variant_data {
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| 58 | u32 blk_nums;
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| 59 | u32 blk_offset;
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| 60 | bool blk_double;
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| 61 | };
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| 62 |
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| 63 | struct sprd_efuse {
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| 64 | struct device *dev;
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| 65 | struct clk *clk;
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| 66 | struct hwspinlock *hwlock;
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| 67 | struct mutex mutex;
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| 68 | void __iomem *base;
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| 69 | const struct sprd_efuse_variant_data *data;
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| 70 | };
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| 71 |
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| 72 | static const struct sprd_efuse_variant_data ums312_data = {
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| 73 | .blk_nums = SPRD_EFUSE_NORMAL_BLOCK_NUMS,
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| 74 | .blk_offset = SPRD_EFUSE_NORMAL_BLOCK_OFFSET,
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| 75 | .blk_double = false,
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| 76 | };
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| 77 |
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| 78 | |
| 79 | * On Spreadtrum platform, we have multi-subsystems will access the unique
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| 80 | * efuse controller, so we need one hardware spinlock to synchronize between
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| 81 | * the multiple subsystems.
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| 82 |
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| 83 | static int sprd_efuse_lock(struct sprd_efuse *efuse)
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| 84 | {
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| 85 | int ret;
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| 86 |
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| 87 | mutex_lock(&efuse->mutex);
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| 88 |
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| 89 | ret = hwspin_lock_timeout_raw(efuse->hwlock,
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| 90 | SPRD_EFUSE_HWLOCK_TIMEOUT);
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| 91 | if (ret) {
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| 92 | dev_err(efuse->dev, "timeout get the hwspinlock\n");
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| 93 | mutex_unlock(&efuse->mutex);
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| 94 | return ret;
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| 95 | }
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| 96 |
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| 97 | return 0;
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| 98 | }
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| 99 |
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| 100 | static void sprd_efuse_unlock(struct sprd_efuse *efuse)
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| 101 | {
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| 102 | hwspin_unlock_raw(efuse->hwlock);
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| 103 | mutex_unlock(&efuse->mutex);
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| 104 | }
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| 105 |
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| 106 | static void sprd_efuse_set_prog_power(struct sprd_efuse *efuse, bool en)
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| 107 | {
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| 108 | u32 val = readl(efuse->base + SPRD_EFUSE_PW_SWT);
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| 109 |
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| 110 | if (en)
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| 111 | val &= ~SPRD_EFUSE_ENK2_ON;
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| 112 | else
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| 113 | val &= ~SPRD_EFUSE_ENK1_ON;
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| 114 |
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| 115 | writel(val, efuse->base + SPRD_EFUSE_PW_SWT);
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| 116 |
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| 117 |
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| 118 | usleep_range(1000, 1200);
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| 119 |
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| 120 | if (en)
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| 121 | val |= SPRD_EFUSE_ENK1_ON;
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| 122 | else
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| 123 | val |= SPRD_EFUSE_ENK2_ON;
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| 124 |
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| 125 | writel(val, efuse->base + SPRD_EFUSE_PW_SWT);
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| 126 |
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| 127 |
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| 128 | usleep_range(1000, 1200);
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| 129 | }
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| 130 |
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| 131 | static void sprd_efuse_set_read_power(struct sprd_efuse *efuse, bool en)
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| 132 | {
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| 133 | u32 val = readl(efuse->base + SPRD_EFUSE_ENABLE);
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| 134 |
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| 135 | if (en)
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| 136 | val |= SPRD_EFUSE_VDD_EN;
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| 137 | else
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| 138 | val &= ~SPRD_EFUSE_VDD_EN;
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| 139 |
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| 140 | writel(val, efuse->base + SPRD_EFUSE_ENABLE);
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| 141 |
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| 142 |
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| 143 | usleep_range(1000, 1200);
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| 144 | }
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| 145 |
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| 146 | static void sprd_efuse_set_prog_lock(struct sprd_efuse *efuse, bool en)
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| 147 | {
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| 148 | u32 val = readl(efuse->base + SPRD_EFUSE_ENABLE);
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| 149 |
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| 150 | if (en)
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| 151 | val |= SPRD_EFUSE_LOCK_WR_EN;
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| 152 | else
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| 153 | val &= ~SPRD_EFUSE_LOCK_WR_EN;
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| 154 |
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| 155 | writel(val, efuse->base + SPRD_EFUSE_ENABLE);
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| 156 | }
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| 157 |
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| 158 | static void sprd_efuse_set_auto_check(struct sprd_efuse *efuse, bool en)
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| 159 | {
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| 160 | u32 val = readl(efuse->base + SPRD_EFUSE_ENABLE);
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| 161 |
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| 162 | if (en)
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| 163 | val |= SPRD_EFUSE_AUTO_CHECK_EN;
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| 164 | else
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| 165 | val &= ~SPRD_EFUSE_AUTO_CHECK_EN;
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| 166 |
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| 167 | writel(val, efuse->base + SPRD_EFUSE_ENABLE);
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| 168 | }
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| 169 |
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| 170 | static void sprd_efuse_set_data_double(struct sprd_efuse *efuse, bool en)
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| 171 | {
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| 172 | u32 val = readl(efuse->base + SPRD_EFUSE_ENABLE);
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| 173 |
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| 174 | if (en)
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| 175 | val |= SPRD_EFUSE_DOUBLE_EN;
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| 176 | else
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| 177 | val &= ~SPRD_EFUSE_DOUBLE_EN;
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| 178 |
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| 179 | writel(val, efuse->base + SPRD_EFUSE_ENABLE);
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| 180 | }
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| 181 |
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| 182 | static void sprd_efuse_set_prog_en(struct sprd_efuse *efuse, bool en)
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| 183 | {
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| 184 | u32 val = readl(efuse->base + SPRD_EFUSE_PW_SWT);
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| 185 |
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| 186 | if (en)
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| 187 | val |= SPRD_EFUSE_PROG_EN;
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| 188 | else
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| 189 | val &= ~SPRD_EFUSE_PROG_EN;
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| 190 |
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| 191 | writel(val, efuse->base + SPRD_EFUSE_PW_SWT);
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| 192 | }
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| 193 |
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| 194 | static int sprd_efuse_raw_prog(struct sprd_efuse *efuse, u32 blk, bool doub,
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| 195 | bool lock, u32 *data)
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| 196 | {
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| 197 | u32 status;
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| 198 | int ret = 0;
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| 199 |
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| 200 | |
| 201 | * We need set the correct magic number before writing the efuse to
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| 202 | * allow programming, and block other programming until we clear the
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| 203 | * magic number.
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| 204 |
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| 205 | writel(SPRD_EFUSE_MAGIC_NUMBER,
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| 206 | efuse->base + SPRD_EFUSE_MAGIC_NUM);
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| 207 |
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| 208 | |
| 209 | * Power on the efuse, enable programme and enable double data
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| 210 | * if asked.
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| 211 |
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| 212 | sprd_efuse_set_prog_power(efuse, true);
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| 213 | sprd_efuse_set_prog_en(efuse, true);
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| 214 | sprd_efuse_set_data_double(efuse, doub);
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| 215 |
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| 216 | |
| 217 | * Enable the auto-check function to validate if the programming is
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| 218 | * successful.
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| 219 |
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| 220 | if (lock)
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| 221 | sprd_efuse_set_auto_check(efuse, true);
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| 222 |
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| 223 | writel(*data, efuse->base + SPRD_EFUSE_MEM(blk));
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| 224 |
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| 225 |
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| 226 | if (lock)
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| 227 | sprd_efuse_set_auto_check(efuse, false);
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| 228 | sprd_efuse_set_data_double(efuse, false);
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| 229 |
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| 230 | |
| 231 | * Check the efuse error status, if the programming is successful,
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| 232 | * we should lock this efuse block to avoid programming again.
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| 233 |
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| 234 | status = readl(efuse->base + SPRD_EFUSE_ERR_FLAG);
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| 235 | if (status) {
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| 236 | dev_err(efuse->dev,
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| 237 | "write error status %u of block %d\n", status, blk);
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| 238 |
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| 239 | writel(SPRD_EFUSE_ERR_CLR_MASK,
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| 240 | efuse->base + SPRD_EFUSE_ERR_CLR);
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| 241 | ret = -EBUSY;
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| 242 | } else if (lock) {
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| 243 | sprd_efuse_set_prog_lock(efuse, lock);
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| 244 | writel(0, efuse->base + SPRD_EFUSE_MEM(blk));
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| 245 | sprd_efuse_set_prog_lock(efuse, false);
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| 246 | }
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| 247 |
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| 248 | sprd_efuse_set_prog_power(efuse, false);
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| 249 | writel(0, efuse->base + SPRD_EFUSE_MAGIC_NUM);
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| 250 |
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| 251 | return ret;
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| 252 | }
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| 253 |
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| 254 | static int sprd_efuse_raw_read(struct sprd_efuse *efuse, int blk, u32 *val,
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| 255 | bool doub)
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| 256 | {
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| 257 | u32 status;
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| 258 |
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| 259 | |
| 260 | * Need power on the efuse before reading data from efuse, and will
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| 261 | * power off the efuse after reading process.
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| 262 |
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| 263 | sprd_efuse_set_read_power(efuse, true);
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| 264 |
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| 265 |
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| 266 | sprd_efuse_set_data_double(efuse, doub);
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| 267 |
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| 268 |
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| 269 | *val = readl(efuse->base + SPRD_EFUSE_MEM(blk));
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| 270 |
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| 271 |
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| 272 | sprd_efuse_set_data_double(efuse, false);
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| 273 |
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| 274 |
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| 275 | sprd_efuse_set_read_power(efuse, false);
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| 276 |
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| 277 | |
| 278 | * Check the efuse error status and clear them if there are some
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| 279 | * errors occurred.
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| 280 |
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| 281 | status = readl(efuse->base + SPRD_EFUSE_ERR_FLAG);
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| 282 | if (status) {
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| 283 | dev_err(efuse->dev,
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| 284 | "read error status %d of block %d\n", status, blk);
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| 285 |
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| 286 | writel(SPRD_EFUSE_ERR_CLR_MASK,
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| 287 | efuse->base + SPRD_EFUSE_ERR_CLR);
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| 288 | return -EBUSY;
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| 289 | }
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| 290 |
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| 291 | return 0;
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| 292 | }
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| 293 |
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| 294 | static int sprd_efuse_read(void *context, u32 offset, void *val, size_t bytes)
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| 295 | {
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| 296 | struct sprd_efuse *efuse = context;
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| 297 | bool blk_double = efuse->data->blk_double;
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| 298 | u32 index = offset / SPRD_EFUSE_BLOCK_WIDTH + efuse->data->blk_offset;
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| 299 | u32 blk_offset = (offset % SPRD_EFUSE_BLOCK_WIDTH) * BITS_PER_BYTE;
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| 300 | u32 data;
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| 301 | int ret;
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| 302 |
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| 303 | ret = sprd_efuse_lock(efuse);
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| 304 | if (ret)
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| 305 | return ret;
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| 306 |
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| 307 | ret = clk_prepare_enable(efuse->clk);
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| 308 | if (ret)
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| 309 | goto unlock;
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| 310 |
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| 311 | ret = sprd_efuse_raw_read(efuse, index, &data, blk_double);
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| 312 | if (!ret) {
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| 313 | data >>= blk_offset;
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| 314 | memcpy(val, &data, bytes);
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| 315 | }
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| 316 |
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| 317 | clk_disable_unprepare(efuse->clk);
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| 318 |
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| 319 | unlock:
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| 320 | sprd_efuse_unlock(efuse);
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| 321 | return ret;
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| 322 | }
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| 323 |
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| 324 | static int sprd_efuse_write(void *context, u32 offset, void *val, size_t bytes)
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| 325 | {
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| 326 | struct sprd_efuse *efuse = context;
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| 327 | bool blk_double = efuse->data->blk_double;
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| 328 | bool lock;
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| 329 | int ret;
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| 330 |
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| 331 | ret = sprd_efuse_lock(efuse);
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| 332 | if (ret)
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| 333 | return ret;
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| 334 |
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| 335 | ret = clk_prepare_enable(efuse->clk);
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| 336 | if (ret)
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| 337 | goto unlock;
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| 338 |
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| 339 | |
| 340 | * If the writing bytes are equal with the block width, which means the
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| 341 | * whole block will be programmed. For this case, we should not allow
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| 342 | * this block to be programmed again by locking this block.
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| 343 | *
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| 344 | * If the block was programmed partially, we should allow this block to
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| 345 | * be programmed again.
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| 346 |
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| 347 | if (bytes < SPRD_EFUSE_BLOCK_WIDTH)
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| 348 | lock = false;
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| 349 | else
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| 350 | lock = true;
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| 351 |
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| 352 | ret = sprd_efuse_raw_prog(efuse, offset, blk_double, lock, val);
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| 353 |
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| 354 | clk_disable_unprepare(efuse->clk);
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| 355 |
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| 356 | unlock:
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| 357 | sprd_efuse_unlock(efuse);
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| 358 | return ret;
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| 359 | }
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| 360 |
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| 361 | static int sprd_efuse_probe(struct platform_device *pdev)
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| 362 | {
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| 363 | struct device_node *np = pdev->dev.of_node;
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| 364 | struct nvmem_device *nvmem;
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| 365 | struct nvmem_config econfig = { };
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| 366 | struct sprd_efuse *efuse;
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| 367 | const struct sprd_efuse_variant_data *pdata;
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| 368 | int ret;
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| 369 |
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| 370 | pdata = of_device_get_match_data(&pdev->dev);
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| 371 | if (!pdata) {
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| 372 | dev_err(&pdev->dev, "No matching driver data found\n");
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| 373 | return -EINVAL;
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| 374 | }
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| 375 |
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| 376 | efuse = devm_kzalloc(&pdev->dev, sizeof(*efuse), GFP_KERNEL);
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| 377 | if (!efuse)
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| 378 | return -ENOMEM;
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| 379 |
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| 380 | efuse->base = devm_platform_ioremap_resource(pdev, 0);
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| 381 | if (IS_ERR(efuse->base))
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| 382 | return PTR_ERR(efuse->base);
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| 383 |
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| 384 | ret = of_hwspin_lock_get_id(np, 0);
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| 385 | if (ret < 0) {
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| 386 | dev_err(&pdev->dev, "failed to get hwlock id\n");
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| 387 | return ret;
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| 388 | }
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| 389 |
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| 390 | efuse->hwlock = devm_hwspin_lock_request_specific(&pdev->dev, ret);
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| 391 | if (!efuse->hwlock) {
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| 392 | dev_err(&pdev->dev, "failed to request hwlock\n");
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| 393 | return -ENXIO;
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| 394 | }
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| 395 |
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| 396 | efuse->clk = devm_clk_get(&pdev->dev, "enable");
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| 397 | if (IS_ERR(efuse->clk)) {
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| 398 | dev_err(&pdev->dev, "failed to get enable clock\n");
|
| 399 | return PTR_ERR(efuse->clk);
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| 400 | }
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| 401 |
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| 402 | mutex_init(&efuse->mutex);
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| 403 | efuse->dev = &pdev->dev;
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| 404 | efuse->data = pdata;
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| 405 |
|
| 406 | econfig.stride = 1;
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| 407 | econfig.word_size = 1;
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| 408 | econfig.read_only = false;
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| 409 | econfig.name = "sprd-efuse";
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| 410 | econfig.size = efuse->data->blk_nums * SPRD_EFUSE_BLOCK_WIDTH;
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| 411 | econfig.add_legacy_fixed_of_cells = true;
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| 412 | econfig.reg_read = sprd_efuse_read;
|
| 413 | econfig.reg_write = sprd_efuse_write;
|
| 414 | econfig.priv = efuse;
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| 415 | econfig.dev = &pdev->dev;
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| 416 | nvmem = devm_nvmem_register(&pdev->dev, &econfig);
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| 417 | if (IS_ERR(nvmem)) {
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| 418 | dev_err(&pdev->dev, "failed to register nvmem\n");
|
| 419 | return PTR_ERR(nvmem);
|
| 420 | }
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| 421 |
|
| 422 | return 0;
|
| 423 | }
|
| 424 |
|
| 425 | static const struct of_device_id sprd_efuse_of_match[] = {
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| 426 | { .compatible = "sprd,ums312-efuse", .data = &ums312_data },
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| 427 | { }
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| 428 | };
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| 429 | MODULE_DEVICE_TABLE(of, sprd_efuse_of_match);
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| 430 |
|
| 431 | static struct platform_driver sprd_efuse_driver = {
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| 432 | .probe = sprd_efuse_probe,
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| 433 | .driver = {
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| 434 | .name = "sprd-efuse",
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| 435 | .of_match_table = sprd_efuse_of_match,
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| 436 | },
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| 437 | };
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| 438 |
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| 439 | module_platform_driver(sprd_efuse_driver);
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| 440 |
|
| 441 | MODULE_AUTHOR("Freeman Liu <[email protected]>");
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| 442 | MODULE_DESCRIPTION("Spreadtrum AP efuse driver");
|
| 443 | MODULE_LICENSE("GPL v2");
|