| 1 | |
| 2 | |
| 3 | * Interrupt management for most GSC and related devices.
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| 4 | *
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| 5 | * (c) Copyright 1999 Alex deVries for The Puffin Group
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| 6 | * (c) Copyright 1999 Grant Grundler for Hewlett-Packard
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| 7 | * (c) Copyright 1999 Matthew Wilcox
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| 8 | * (c) Copyright 2000 Helge Deller
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| 9 | * (c) Copyright 2001 Matthew Wilcox for Hewlett-Packard
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| 10 |
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| 11 |
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| 12 | #include <linux/bitops.h>
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| 13 | #include <linux/errno.h>
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| 14 | #include <linux/init.h>
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| 15 | #include <linux/interrupt.h>
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| 16 | #include <linux/ioport.h>
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| 17 | #include <linux/module.h>
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| 18 | #include <linux/types.h>
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| 19 |
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| 20 | #include <asm/hardware.h>
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| 21 | #include <asm/io.h>
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| 22 |
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| 23 | #include "gsc.h"
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| 24 |
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| 25 | #undef DEBUG
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| 26 |
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| 27 | #ifdef DEBUG
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| 28 | #define DEBPRINTK printk
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| 29 | #else
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| 30 | #define DEBPRINTK(x,...)
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| 31 | #endif
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| 32 |
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| 33 | int gsc_alloc_irq(struct gsc_irq *i)
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| 34 | {
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| 35 | int irq = txn_alloc_irq(GSC_EIM_WIDTH);
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| 36 | if (irq < 0) {
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| 37 | printk("cannot get irq\n");
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| 38 | return irq;
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| 39 | }
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| 40 |
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| 41 | i->txn_addr = txn_alloc_addr(irq);
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| 42 | i->txn_data = txn_alloc_data(irq);
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| 43 | i->irq = irq;
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| 44 |
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| 45 | return irq;
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| 46 | }
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| 47 |
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| 48 | int gsc_claim_irq(struct gsc_irq *i, int irq)
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| 49 | {
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| 50 | int c = irq;
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| 51 |
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| 52 | irq += CPU_IRQ_BASE;
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| 53 |
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| 54 | irq = txn_claim_irq(irq);
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| 55 | if (irq < 0) {
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| 56 | printk("cannot claim irq %d\n", c);
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| 57 | return irq;
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| 58 | }
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| 59 |
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| 60 | i->txn_addr = txn_alloc_addr(irq);
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| 61 | i->txn_data = txn_alloc_data(irq);
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| 62 | i->irq = irq;
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| 63 |
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| 64 | return irq;
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| 65 | }
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| 66 |
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| 67 | EXPORT_SYMBOL(gsc_alloc_irq);
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| 68 | EXPORT_SYMBOL(gsc_claim_irq);
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| 69 |
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| 70 |
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| 71 | irqreturn_t gsc_asic_intr(int gsc_asic_irq, void *dev)
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| 72 | {
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| 73 | unsigned long irr;
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| 74 | struct gsc_asic *gsc_asic = dev;
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| 75 |
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| 76 | irr = gsc_readl(gsc_asic->hpa + OFFSET_IRR);
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| 77 | if (irr == 0)
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| 78 | return IRQ_NONE;
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| 79 |
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| 80 | DEBPRINTK("%s intr, mask=0x%x\n", gsc_asic->name, irr);
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| 81 |
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| 82 | do {
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| 83 | int local_irq = __ffs(irr);
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| 84 | unsigned int irq = gsc_asic->global_irq[local_irq];
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| 85 | generic_handle_irq(irq);
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| 86 | irr &= ~(1 << local_irq);
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| 87 | } while (irr);
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| 88 |
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| 89 | return IRQ_HANDLED;
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| 90 | }
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| 91 |
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| 92 | int gsc_find_local_irq(unsigned int irq, int *global_irqs, int limit)
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| 93 | {
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| 94 | int local_irq;
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| 95 |
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| 96 | for (local_irq = 0; local_irq < limit; local_irq++) {
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| 97 | if (global_irqs[local_irq] == irq)
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| 98 | return local_irq;
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| 99 | }
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| 100 |
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| 101 | return NO_IRQ;
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| 102 | }
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| 103 |
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| 104 | static void gsc_asic_mask_irq(struct irq_data *d)
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| 105 | {
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| 106 | struct gsc_asic *irq_dev = irq_data_get_irq_chip_data(d);
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| 107 | int local_irq = gsc_find_local_irq(d->irq, irq_dev->global_irq, 32);
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| 108 | u32 imr;
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| 109 |
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| 110 | DEBPRINTK(KERN_DEBUG "%s(%d) %s: IMR 0x%x\n", __func__, d->irq,
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| 111 | irq_dev->name, imr);
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| 112 |
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| 113 |
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| 114 | imr = gsc_readl(irq_dev->hpa + OFFSET_IMR);
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| 115 | imr &= ~(1 << local_irq);
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| 116 | gsc_writel(imr, irq_dev->hpa + OFFSET_IMR);
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| 117 | }
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| 118 |
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| 119 | static void gsc_asic_unmask_irq(struct irq_data *d)
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| 120 | {
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| 121 | struct gsc_asic *irq_dev = irq_data_get_irq_chip_data(d);
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| 122 | int local_irq = gsc_find_local_irq(d->irq, irq_dev->global_irq, 32);
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| 123 | u32 imr;
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| 124 |
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| 125 | DEBPRINTK(KERN_DEBUG "%s(%d) %s: IMR 0x%x\n", __func__, d->irq,
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| 126 | irq_dev->name, imr);
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| 127 |
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| 128 |
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| 129 | imr = gsc_readl(irq_dev->hpa + OFFSET_IMR);
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| 130 | imr |= 1 << local_irq;
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| 131 | gsc_writel(imr, irq_dev->hpa + OFFSET_IMR);
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| 132 | |
| 133 | * FIXME: read IPR to make sure the IRQ isn't already pending.
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| 134 | * If so, we need to read IRR and manually call do_irq().
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| 135 |
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| 136 | }
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| 137 |
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| 138 | #ifdef CONFIG_SMP
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| 139 | static int gsc_set_affinity_irq(struct irq_data *d, const struct cpumask *dest,
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| 140 | bool force)
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| 141 | {
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| 142 | struct gsc_asic *gsc_dev = irq_data_get_irq_chip_data(d);
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| 143 | struct cpumask tmask;
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| 144 | int cpu_irq;
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| 145 |
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| 146 | if (!cpumask_and(&tmask, dest, cpu_online_mask))
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| 147 | return -EINVAL;
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| 148 |
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| 149 | cpu_irq = cpu_check_affinity(d, &tmask);
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| 150 | if (cpu_irq < 0)
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| 151 | return cpu_irq;
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| 152 |
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| 153 | gsc_dev->gsc_irq.txn_addr = txn_affinity_addr(d->irq, cpu_irq);
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| 154 | gsc_dev->eim = ((u32) gsc_dev->gsc_irq.txn_addr) | gsc_dev->gsc_irq.txn_data;
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| 155 |
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| 156 |
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| 157 |
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| 158 | if (gsc_dev->gsc->id.sversion != 0x70)
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| 159 | gsc_writel(gsc_dev->eim, gsc_dev->hpa + OFFSET_IAR);
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| 160 |
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| 161 | irq_data_update_effective_affinity(d, &tmask);
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| 162 |
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| 163 | return IRQ_SET_MASK_OK;
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| 164 | }
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| 165 | #endif
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| 166 |
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| 167 |
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| 168 | static struct irq_chip gsc_asic_interrupt_type = {
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| 169 | .name = "GSC-ASIC",
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| 170 | .irq_unmask = gsc_asic_unmask_irq,
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| 171 | .irq_mask = gsc_asic_mask_irq,
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| 172 | #ifdef CONFIG_SMP
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| 173 | .irq_set_affinity = gsc_set_affinity_irq,
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| 174 | #endif
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| 175 | };
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| 176 |
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| 177 | int gsc_assign_irq(struct irq_chip *type, void *data)
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| 178 | {
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| 179 | static int irq = GSC_IRQ_BASE;
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| 180 |
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| 181 | if (irq > GSC_IRQ_MAX)
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| 182 | return NO_IRQ;
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| 183 |
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| 184 | irq_set_chip_and_handler(irq, type, handle_simple_irq);
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| 185 | irq_set_chip_data(irq, data);
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| 186 |
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| 187 | return irq++;
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| 188 | }
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| 189 |
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| 190 | void gsc_asic_assign_irq(struct gsc_asic *asic, int local_irq, int *irqp)
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| 191 | {
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| 192 | int irq = asic->global_irq[local_irq];
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| 193 |
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| 194 | if (irq <= 0) {
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| 195 | irq = gsc_assign_irq(&gsc_asic_interrupt_type, asic);
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| 196 | if (irq == NO_IRQ)
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| 197 | return;
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| 198 |
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| 199 | asic->global_irq[local_irq] = irq;
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| 200 | }
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| 201 | *irqp = irq;
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| 202 | }
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| 203 |
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| 204 | struct gsc_fixup_struct {
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| 205 | void (*choose_irq)(struct parisc_device *, void *);
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| 206 | void *ctrl;
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| 207 | };
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| 208 |
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| 209 | static int gsc_fixup_irqs_callback(struct device *dev, void *data)
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| 210 | {
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| 211 | struct parisc_device *padev = to_parisc_device(dev);
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| 212 | struct gsc_fixup_struct *gf = data;
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| 213 |
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| 214 | |
| 215 | at path [5] and children at path [5/0/x]
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| 216 | if (padev->id.hw_type == HPHW_FAULTY)
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| 217 | gsc_fixup_irqs(padev, gf->ctrl, gf->choose_irq);
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| 218 | gf->choose_irq(padev, gf->ctrl);
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| 219 |
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| 220 | return 0;
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| 221 | }
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| 222 |
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| 223 | void gsc_fixup_irqs(struct parisc_device *parent, void *ctrl,
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| 224 | void (*choose_irq)(struct parisc_device *, void *))
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| 225 | {
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| 226 | struct gsc_fixup_struct data = {
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| 227 | .choose_irq = choose_irq,
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| 228 | .ctrl = ctrl,
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| 229 | };
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| 230 |
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| 231 | device_for_each_child(&parent->dev, &data, gsc_fixup_irqs_callback);
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| 232 | }
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| 233 |
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| 234 | int gsc_common_setup(struct parisc_device *parent, struct gsc_asic *gsc_asic)
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| 235 | {
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| 236 | struct resource *res;
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| 237 | int i;
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| 238 |
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| 239 | gsc_asic->gsc = parent;
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| 240 |
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| 241 |
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| 242 | for (i = 0; i < 32; i++) {
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| 243 | gsc_asic->global_irq[i] = NO_IRQ;
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| 244 | }
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| 245 |
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| 246 |
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| 247 | res = request_mem_region(gsc_asic->hpa, 0x100000, gsc_asic->name);
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| 248 | if (res) {
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| 249 | res->flags = IORESOURCE_MEM;
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| 250 | }
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| 251 |
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| 252 | #if 0 |
| 253 | printk(KERN_WARNING "%s IRQ %d EIM 0x%x", gsc_asic->name,
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| 254 | parent->irq, gsc_asic->eim);
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| 255 | if (gsc_readl(gsc_asic->hpa + OFFSET_IMR))
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| 256 | printk(" IMR is non-zero! (0x%x)",
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| 257 | gsc_readl(gsc_asic->hpa + OFFSET_IMR));
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| 258 | printk("\n");
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| 259 | #endif
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| 260 |
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| 261 | return 0;
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| 262 | }
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