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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 *
4 * Copyright (C) 2014 ARM Limited
5 */
6
7#include <linux/ctype.h>
8#include <linux/hrtimer.h>
9#include <linux/idr.h>
10#include <linux/interrupt.h>
11#include <linux/io.h>
12#include <linux/module.h>
13#include <linux/perf_event.h>
14#include <linux/platform_device.h>
15#include <linux/slab.h>
16
17#define CCN_NUM_XP_PORTS 2
18#define CCN_NUM_VCS 4
19#define CCN_NUM_REGIONS 256
20#define CCN_REGION_SIZE 0x10000
21
22#define CCN_ALL_OLY_ID 0xff00
23#define CCN_ALL_OLY_ID__OLY_ID__SHIFT 0
24#define CCN_ALL_OLY_ID__OLY_ID__MASK 0x1f
25#define CCN_ALL_OLY_ID__NODE_ID__SHIFT 8
26#define CCN_ALL_OLY_ID__NODE_ID__MASK 0x3f
27
28#define CCN_MN_ERRINT_STATUS 0x0008
29#define CCN_MN_ERRINT_STATUS__INTREQ__DESSERT 0x11
30#define CCN_MN_ERRINT_STATUS__ALL_ERRORS__ENABLE 0x02
31#define CCN_MN_ERRINT_STATUS__ALL_ERRORS__DISABLED 0x20
32#define CCN_MN_ERRINT_STATUS__ALL_ERRORS__DISABLE 0x22
33#define CCN_MN_ERRINT_STATUS__CORRECTED_ERRORS_ENABLE 0x04
34#define CCN_MN_ERRINT_STATUS__CORRECTED_ERRORS_DISABLED 0x40
35#define CCN_MN_ERRINT_STATUS__CORRECTED_ERRORS_DISABLE 0x44
36#define CCN_MN_ERRINT_STATUS__PMU_EVENTS__ENABLE 0x08
37#define CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLED 0x80
38#define CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLE 0x88
39#define CCN_MN_OLY_COMP_LIST_63_0 0x01e0
40#define CCN_MN_ERR_SIG_VAL_63_0 0x0300
41#define CCN_MN_ERR_SIG_VAL_63_0__DT (1 << 1)
42
43#define CCN_DT_ACTIVE_DSM 0x0000
44#define CCN_DT_ACTIVE_DSM__DSM_ID__SHIFT(n) ((n) * 8)
45#define CCN_DT_ACTIVE_DSM__DSM_ID__MASK 0xff
46#define CCN_DT_CTL 0x0028
47#define CCN_DT_CTL__DT_EN (1 << 0)
48#define CCN_DT_PMEVCNT(n) (0x0100 + (n) * 0x8)
49#define CCN_DT_PMCCNTR 0x0140
50#define CCN_DT_PMCCNTRSR 0x0190
51#define CCN_DT_PMOVSR 0x0198
52#define CCN_DT_PMOVSR_CLR 0x01a0
53#define CCN_DT_PMOVSR_CLR__MASK 0x1f
54#define CCN_DT_PMCR 0x01a8
55#define CCN_DT_PMCR__OVFL_INTR_EN (1 << 6)
56#define CCN_DT_PMCR__PMU_EN (1 << 0)
57#define CCN_DT_PMSR 0x01b0
58#define CCN_DT_PMSR_REQ 0x01b8
59#define CCN_DT_PMSR_CLR 0x01c0
60
61#define CCN_HNF_PMU_EVENT_SEL 0x0600
62#define CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(n) ((n) * 4)
63#define CCN_HNF_PMU_EVENT_SEL__ID__MASK 0xf
64
65#define CCN_XP_DT_CONFIG 0x0300
66#define CCN_XP_DT_CONFIG__DT_CFG__SHIFT(n) ((n) * 4)
67#define CCN_XP_DT_CONFIG__DT_CFG__MASK 0xf
68#define CCN_XP_DT_CONFIG__DT_CFG__PASS_THROUGH 0x0
69#define CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT_0_OR_1 0x1
70#define CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT(n) (0x2 + (n))
71#define CCN_XP_DT_CONFIG__DT_CFG__XP_PMU_EVENT(n) (0x4 + (n))
72#define CCN_XP_DT_CONFIG__DT_CFG__DEVICE_PMU_EVENT(d, n) (0x8 + (d) * 4 + (n))
73#define CCN_XP_DT_INTERFACE_SEL 0x0308
74#define CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__SHIFT(n) (0 + (n) * 8)
75#define CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__MASK 0x1
76#define CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__SHIFT(n) (1 + (n) * 8)
77#define CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__MASK 0x1
78#define CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__SHIFT(n) (2 + (n) * 8)
79#define CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__MASK 0x3
80#define CCN_XP_DT_CMP_VAL_L(n) (0x0310 + (n) * 0x40)
81#define CCN_XP_DT_CMP_VAL_H(n) (0x0318 + (n) * 0x40)
82#define CCN_XP_DT_CMP_MASK_L(n) (0x0320 + (n) * 0x40)
83#define CCN_XP_DT_CMP_MASK_H(n) (0x0328 + (n) * 0x40)
84#define CCN_XP_DT_CONTROL 0x0370
85#define CCN_XP_DT_CONTROL__DT_ENABLE (1 << 0)
86#define CCN_XP_DT_CONTROL__WP_ARM_SEL__SHIFT(n) (12 + (n) * 4)
87#define CCN_XP_DT_CONTROL__WP_ARM_SEL__MASK 0xf
88#define CCN_XP_DT_CONTROL__WP_ARM_SEL__ALWAYS 0xf
89#define CCN_XP_PMU_EVENT_SEL 0x0600
90#define CCN_XP_PMU_EVENT_SEL__ID__SHIFT(n) ((n) * 7)
91#define CCN_XP_PMU_EVENT_SEL__ID__MASK 0x3f
92
93#define CCN_SBAS_PMU_EVENT_SEL 0x0600
94#define CCN_SBAS_PMU_EVENT_SEL__ID__SHIFT(n) ((n) * 4)
95#define CCN_SBAS_PMU_EVENT_SEL__ID__MASK 0xf
96
97#define CCN_RNI_PMU_EVENT_SEL 0x0600
98#define CCN_RNI_PMU_EVENT_SEL__ID__SHIFT(n) ((n) * 4)
99#define CCN_RNI_PMU_EVENT_SEL__ID__MASK 0xf
100
101#define CCN_TYPE_MN 0x01
102#define CCN_TYPE_DT 0x02
103#define CCN_TYPE_HNF 0x04
104#define CCN_TYPE_HNI 0x05
105#define CCN_TYPE_XP 0x08
106#define CCN_TYPE_SBSX 0x0c
107#define CCN_TYPE_SBAS 0x10
108#define CCN_TYPE_RNI_1P 0x14
109#define CCN_TYPE_RNI_2P 0x15
110#define CCN_TYPE_RNI_3P 0x16
111#define CCN_TYPE_RND_1P 0x18 /* RN-D = RN-I + DVM */
112#define CCN_TYPE_RND_2P 0x19
113#define CCN_TYPE_RND_3P 0x1a
114#define CCN_TYPE_CYCLES 0xff /* Pseudotype */
115
116#define CCN_EVENT_WATCHPOINT 0xfe /* Pseudoevent */
117
118#define CCN_NUM_PMU_EVENTS 4
119#define CCN_NUM_XP_WATCHPOINTS 2 /* See DT.dbg_id.num_watchpoints */
120#define CCN_NUM_PMU_EVENT_COUNTERS 8 /* See DT.dbg_id.num_pmucntr */
121#define CCN_IDX_PMU_CYCLE_COUNTER CCN_NUM_PMU_EVENT_COUNTERS
122
123#define CCN_NUM_PREDEFINED_MASKS 4
124#define CCN_IDX_MASK_ANY (CCN_NUM_PMU_EVENT_COUNTERS + 0)
125#define CCN_IDX_MASK_EXACT (CCN_NUM_PMU_EVENT_COUNTERS + 1)
126#define CCN_IDX_MASK_ORDER (CCN_NUM_PMU_EVENT_COUNTERS + 2)
127#define CCN_IDX_MASK_OPCODE (CCN_NUM_PMU_EVENT_COUNTERS + 3)
128
129struct arm_ccn_component {
130 void __iomem *base;
131 u32 type;
132
133 DECLARE_BITMAP(pmu_events_mask, CCN_NUM_PMU_EVENTS);
134 union {
135 struct {
136 DECLARE_BITMAP(dt_cmp_mask, CCN_NUM_XP_WATCHPOINTS);
137 } xp;
138 };
139};
140
141#define pmu_to_arm_ccn(_pmu) container_of(container_of(_pmu, \
142 struct arm_ccn_dt, pmu), struct arm_ccn, dt)
143
144struct arm_ccn_dt {
145 int id;
146 void __iomem *base;
147
148 spinlock_t config_lock;
149
150 DECLARE_BITMAP(pmu_counters_mask, CCN_NUM_PMU_EVENT_COUNTERS + 1);
151 struct {
152 struct arm_ccn_component *source;
153 struct perf_event *event;
154 } pmu_counters[CCN_NUM_PMU_EVENT_COUNTERS + 1];
155
156 struct {
157 u64 l, h;
158 } cmp_mask[CCN_NUM_PMU_EVENT_COUNTERS + CCN_NUM_PREDEFINED_MASKS];
159
160 struct hrtimer hrtimer;
161
162 unsigned int cpu;
163 struct hlist_node node;
164
165 struct pmu pmu;
166};
167
168struct arm_ccn {
169 struct device *dev;
170 void __iomem *base;
171 unsigned int irq;
172
173 unsigned sbas_present:1;
174 unsigned sbsx_present:1;
175
176 int num_nodes;
177 struct arm_ccn_component *node;
178
179 int num_xps;
180 struct arm_ccn_component *xp;
181
182 struct arm_ccn_dt dt;
183 int mn_id;
184};
185
186static int arm_ccn_node_to_xp(int node)
187{
188 return node / CCN_NUM_XP_PORTS;
189}
190
191static int arm_ccn_node_to_xp_port(int node)
192{
193 return node % CCN_NUM_XP_PORTS;
194}
195
196
197/*
198 * Bit shifts and masks in these defines must be kept in sync with
199 * arm_ccn_pmu_config_set() and CCN_FORMAT_ATTRs below!
200 */
201#define CCN_CONFIG_NODE(_config) (((_config) >> 0) & 0xff)
202#define CCN_CONFIG_XP(_config) (((_config) >> 0) & 0xff)
203#define CCN_CONFIG_TYPE(_config) (((_config) >> 8) & 0xff)
204#define CCN_CONFIG_EVENT(_config) (((_config) >> 16) & 0xff)
205#define CCN_CONFIG_PORT(_config) (((_config) >> 24) & 0x3)
206#define CCN_CONFIG_BUS(_config) (((_config) >> 24) & 0x3)
207#define CCN_CONFIG_VC(_config) (((_config) >> 26) & 0x7)
208#define CCN_CONFIG_DIR(_config) (((_config) >> 29) & 0x1)
209#define CCN_CONFIG_MASK(_config) (((_config) >> 30) & 0xf)
210
211static void arm_ccn_pmu_config_set(u64 *config, u32 node_xp, u32 type, u32 port)
212{
213 *config &= ~((0xff << 0) | (0xff << 8) | (0x3 << 24));
214 *config |= (node_xp << 0) | (type << 8) | (port << 24);
215}
216
217#define CCN_FORMAT_ATTR(_name, _config) \
218 struct dev_ext_attribute arm_ccn_pmu_format_attr_##_name = \
219 { __ATTR(_name, S_IRUGO, device_show_string, \
220 NULL), _config }
221
222static CCN_FORMAT_ATTR(node, "config:0-7");
223static CCN_FORMAT_ATTR(xp, "config:0-7");
224static CCN_FORMAT_ATTR(type, "config:8-15");
225static CCN_FORMAT_ATTR(event, "config:16-23");
226static CCN_FORMAT_ATTR(port, "config:24-25");
227static CCN_FORMAT_ATTR(bus, "config:24-25");
228static CCN_FORMAT_ATTR(vc, "config:26-28");
229static CCN_FORMAT_ATTR(dir, "config:29-29");
230static CCN_FORMAT_ATTR(mask, "config:30-33");
231static CCN_FORMAT_ATTR(cmp_l, "config1:0-62");
232static CCN_FORMAT_ATTR(cmp_h, "config2:0-59");
233
234static struct attribute *arm_ccn_pmu_format_attrs[] = {
235 &arm_ccn_pmu_format_attr_node.attr.attr,
236 &arm_ccn_pmu_format_attr_xp.attr.attr,
237 &arm_ccn_pmu_format_attr_type.attr.attr,
238 &arm_ccn_pmu_format_attr_event.attr.attr,
239 &arm_ccn_pmu_format_attr_port.attr.attr,
240 &arm_ccn_pmu_format_attr_bus.attr.attr,
241 &arm_ccn_pmu_format_attr_vc.attr.attr,
242 &arm_ccn_pmu_format_attr_dir.attr.attr,
243 &arm_ccn_pmu_format_attr_mask.attr.attr,
244 &arm_ccn_pmu_format_attr_cmp_l.attr.attr,
245 &arm_ccn_pmu_format_attr_cmp_h.attr.attr,
246 NULL
247};
248
249static const struct attribute_group arm_ccn_pmu_format_attr_group = {
250 .name = "format",
251 .attrs = arm_ccn_pmu_format_attrs,
252};
253
254
255struct arm_ccn_pmu_event {
256 struct device_attribute attr;
257 u32 type;
258 u32 event;
259 int num_ports;
260 int num_vcs;
261 const char *def;
262 int mask;
263};
264
265#define CCN_EVENT_ATTR(_name) \
266 __ATTR(_name, S_IRUGO, arm_ccn_pmu_event_show, NULL)
267
268/*
269 * Events defined in TRM for MN, HN-I and SBSX are actually watchpoints set on
270 * their ports in XP they are connected to. For the sake of usability they are
271 * explicitly defined here (and translated into a relevant watchpoint in
272 * arm_ccn_pmu_event_init()) so the user can easily request them without deep
273 * knowledge of the flit format.
274 */
275
276#define CCN_EVENT_MN(_name, _def, _mask) { .attr = CCN_EVENT_ATTR(mn_##_name), \
277 .type = CCN_TYPE_MN, .event = CCN_EVENT_WATCHPOINT, \
278 .num_ports = CCN_NUM_XP_PORTS, .num_vcs = CCN_NUM_VCS, \
279 .def = _def, .mask = _mask, }
280
281#define CCN_EVENT_HNI(_name, _def, _mask) { \
282 .attr = CCN_EVENT_ATTR(hni_##_name), .type = CCN_TYPE_HNI, \
283 .event = CCN_EVENT_WATCHPOINT, .num_ports = CCN_NUM_XP_PORTS, \
284 .num_vcs = CCN_NUM_VCS, .def = _def, .mask = _mask, }
285
286#define CCN_EVENT_SBSX(_name, _def, _mask) { \
287 .attr = CCN_EVENT_ATTR(sbsx_##_name), .type = CCN_TYPE_SBSX, \
288 .event = CCN_EVENT_WATCHPOINT, .num_ports = CCN_NUM_XP_PORTS, \
289 .num_vcs = CCN_NUM_VCS, .def = _def, .mask = _mask, }
290
291#define CCN_EVENT_HNF(_name, _event) { .attr = CCN_EVENT_ATTR(hnf_##_name), \
292 .type = CCN_TYPE_HNF, .event = _event, }
293
294#define CCN_EVENT_XP(_name, _event) { .attr = CCN_EVENT_ATTR(xp_##_name), \
295 .type = CCN_TYPE_XP, .event = _event, \
296 .num_ports = CCN_NUM_XP_PORTS, .num_vcs = CCN_NUM_VCS, }
297
298/*
299 * RN-I & RN-D (RN-D = RN-I + DVM) nodes have different type ID depending
300 * on configuration. One of them is picked to represent the whole group,
301 * as they all share the same event types.
302 */
303#define CCN_EVENT_RNI(_name, _event) { .attr = CCN_EVENT_ATTR(rni_##_name), \
304 .type = CCN_TYPE_RNI_3P, .event = _event, }
305
306#define CCN_EVENT_SBAS(_name, _event) { .attr = CCN_EVENT_ATTR(sbas_##_name), \
307 .type = CCN_TYPE_SBAS, .event = _event, }
308
309#define CCN_EVENT_CYCLES(_name) { .attr = CCN_EVENT_ATTR(_name), \
310 .type = CCN_TYPE_CYCLES }
311
312
313static ssize_t arm_ccn_pmu_event_show(struct device *dev,
314 struct device_attribute *attr, char *buf)
315{
316 struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
317 struct arm_ccn_pmu_event *event = container_of(attr,
318 struct arm_ccn_pmu_event, attr);
319 int res;
320
321 res = sysfs_emit(buf, "type=0x%x", event->type);
322 if (event->event)
323 res += sysfs_emit_at(buf, res, ",event=0x%x", event->event);
324 if (event->def)
325 res += sysfs_emit_at(buf, res, ",%s", event->def);
326 if (event->mask)
327 res += sysfs_emit_at(buf, res, ",mask=0x%x", event->mask);
328
329 /* Arguments required by an event */
330 switch (event->type) {
331 case CCN_TYPE_CYCLES:
332 break;
333 case CCN_TYPE_XP:
334 res += sysfs_emit_at(buf, res, ",xp=?,vc=?");
335 if (event->event == CCN_EVENT_WATCHPOINT)
336 res += sysfs_emit_at(buf, res,
337 ",port=?,dir=?,cmp_l=?,cmp_h=?,mask=?");
338 else
339 res += sysfs_emit_at(buf, res, ",bus=?");
340
341 break;
342 case CCN_TYPE_MN:
343 res += sysfs_emit_at(buf, res, ",node=%d", ccn->mn_id);
344 break;
345 default:
346 res += sysfs_emit_at(buf, res, ",node=?");
347 break;
348 }
349
350 res += sysfs_emit_at(buf, res, "\n");
351
352 return res;
353}
354
355static umode_t arm_ccn_pmu_events_is_visible(struct kobject *kobj,
356 struct attribute *attr, int index)
357{
358 struct device *dev = kobj_to_dev(kobj);
359 struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
360 struct device_attribute *dev_attr = container_of(attr,
361 struct device_attribute, attr);
362 struct arm_ccn_pmu_event *event = container_of(dev_attr,
363 struct arm_ccn_pmu_event, attr);
364
365 if (event->type == CCN_TYPE_SBAS && !ccn->sbas_present)
366 return 0;
367 if (event->type == CCN_TYPE_SBSX && !ccn->sbsx_present)
368 return 0;
369
370 return attr->mode;
371}
372
373static struct arm_ccn_pmu_event arm_ccn_pmu_events[] = {
374 CCN_EVENT_MN(eobarrier, "dir=1,vc=0,cmp_h=0x1c00", CCN_IDX_MASK_OPCODE),
375 CCN_EVENT_MN(ecbarrier, "dir=1,vc=0,cmp_h=0x1e00", CCN_IDX_MASK_OPCODE),
376 CCN_EVENT_MN(dvmop, "dir=1,vc=0,cmp_h=0x2800", CCN_IDX_MASK_OPCODE),
377 CCN_EVENT_HNI(txdatflits, "dir=1,vc=3", CCN_IDX_MASK_ANY),
378 CCN_EVENT_HNI(rxdatflits, "dir=0,vc=3", CCN_IDX_MASK_ANY),
379 CCN_EVENT_HNI(txreqflits, "dir=1,vc=0", CCN_IDX_MASK_ANY),
380 CCN_EVENT_HNI(rxreqflits, "dir=0,vc=0", CCN_IDX_MASK_ANY),
381 CCN_EVENT_HNI(rxreqflits_order, "dir=0,vc=0,cmp_h=0x8000",
382 CCN_IDX_MASK_ORDER),
383 CCN_EVENT_SBSX(txdatflits, "dir=1,vc=3", CCN_IDX_MASK_ANY),
384 CCN_EVENT_SBSX(rxdatflits, "dir=0,vc=3", CCN_IDX_MASK_ANY),
385 CCN_EVENT_SBSX(txreqflits, "dir=1,vc=0", CCN_IDX_MASK_ANY),
386 CCN_EVENT_SBSX(rxreqflits, "dir=0,vc=0", CCN_IDX_MASK_ANY),
387 CCN_EVENT_SBSX(rxreqflits_order, "dir=0,vc=0,cmp_h=0x8000",
388 CCN_IDX_MASK_ORDER),
389 CCN_EVENT_HNF(cache_miss, 0x1),
390 CCN_EVENT_HNF(l3_sf_cache_access, 0x02),
391 CCN_EVENT_HNF(cache_fill, 0x3),
392 CCN_EVENT_HNF(pocq_retry, 0x4),
393 CCN_EVENT_HNF(pocq_reqs_recvd, 0x5),
394 CCN_EVENT_HNF(sf_hit, 0x6),
395 CCN_EVENT_HNF(sf_evictions, 0x7),
396 CCN_EVENT_HNF(snoops_sent, 0x8),
397 CCN_EVENT_HNF(snoops_broadcast, 0x9),
398 CCN_EVENT_HNF(l3_eviction, 0xa),
399 CCN_EVENT_HNF(l3_fill_invalid_way, 0xb),
400 CCN_EVENT_HNF(mc_retries, 0xc),
401 CCN_EVENT_HNF(mc_reqs, 0xd),
402 CCN_EVENT_HNF(qos_hh_retry, 0xe),
403 CCN_EVENT_RNI(rdata_beats_p0, 0x1),
404 CCN_EVENT_RNI(rdata_beats_p1, 0x2),
405 CCN_EVENT_RNI(rdata_beats_p2, 0x3),
406 CCN_EVENT_RNI(rxdat_flits, 0x4),
407 CCN_EVENT_RNI(txdat_flits, 0x5),
408 CCN_EVENT_RNI(txreq_flits, 0x6),
409 CCN_EVENT_RNI(txreq_flits_retried, 0x7),
410 CCN_EVENT_RNI(rrt_full, 0x8),
411 CCN_EVENT_RNI(wrt_full, 0x9),
412 CCN_EVENT_RNI(txreq_flits_replayed, 0xa),
413 CCN_EVENT_XP(upload_starvation, 0x1),
414 CCN_EVENT_XP(download_starvation, 0x2),
415 CCN_EVENT_XP(respin, 0x3),
416 CCN_EVENT_XP(valid_flit, 0x4),
417 CCN_EVENT_XP(watchpoint, CCN_EVENT_WATCHPOINT),
418 CCN_EVENT_SBAS(rdata_beats_p0, 0x1),
419 CCN_EVENT_SBAS(rxdat_flits, 0x4),
420 CCN_EVENT_SBAS(txdat_flits, 0x5),
421 CCN_EVENT_SBAS(txreq_flits, 0x6),
422 CCN_EVENT_SBAS(txreq_flits_retried, 0x7),
423 CCN_EVENT_SBAS(rrt_full, 0x8),
424 CCN_EVENT_SBAS(wrt_full, 0x9),
425 CCN_EVENT_SBAS(txreq_flits_replayed, 0xa),
426 CCN_EVENT_CYCLES(cycles),
427};
428
429/* Populated in arm_ccn_init() */
430static struct attribute
431 *arm_ccn_pmu_events_attrs[ARRAY_SIZE(arm_ccn_pmu_events) + 1];
432
433static const struct attribute_group arm_ccn_pmu_events_attr_group = {
434 .name = "events",
435 .is_visible = arm_ccn_pmu_events_is_visible,
436 .attrs = arm_ccn_pmu_events_attrs,
437};
438
439
440static u64 *arm_ccn_pmu_get_cmp_mask(struct arm_ccn *ccn, const char *name)
441{
442 unsigned long i;
443
444 if (WARN_ON(!name || !name[0] || !isxdigit(name[0]) || !name[1]))
445 return NULL;
446 i = isdigit(name[0]) ? name[0] - '0' : 0xa + tolower(name[0]) - 'a';
447
448 switch (name[1]) {
449 case 'l':
450 return &ccn->dt.cmp_mask[i].l;
451 case 'h':
452 return &ccn->dt.cmp_mask[i].h;
453 default:
454 return NULL;
455 }
456}
457
458static ssize_t arm_ccn_pmu_cmp_mask_show(struct device *dev,
459 struct device_attribute *attr, char *buf)
460{
461 struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
462 u64 *mask = arm_ccn_pmu_get_cmp_mask(ccn, attr->attr.name);
463
464 return mask ? sysfs_emit(buf, "0x%016llx\n", *mask) : -EINVAL;
465}
466
467static ssize_t arm_ccn_pmu_cmp_mask_store(struct device *dev,
468 struct device_attribute *attr, const char *buf, size_t count)
469{
470 struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
471 u64 *mask = arm_ccn_pmu_get_cmp_mask(ccn, attr->attr.name);
472 int err = -EINVAL;
473
474 if (mask)
475 err = kstrtoull(buf, 0, mask);
476
477 return err ? err : count;
478}
479
480#define CCN_CMP_MASK_ATTR(_name) \
481 struct device_attribute arm_ccn_pmu_cmp_mask_attr_##_name = \
482 __ATTR(_name, S_IRUGO | S_IWUSR, \
483 arm_ccn_pmu_cmp_mask_show, arm_ccn_pmu_cmp_mask_store)
484
485#define CCN_CMP_MASK_ATTR_RO(_name) \
486 struct device_attribute arm_ccn_pmu_cmp_mask_attr_##_name = \
487 __ATTR(_name, S_IRUGO, arm_ccn_pmu_cmp_mask_show, NULL)
488
489static CCN_CMP_MASK_ATTR(0l);
490static CCN_CMP_MASK_ATTR(0h);
491static CCN_CMP_MASK_ATTR(1l);
492static CCN_CMP_MASK_ATTR(1h);
493static CCN_CMP_MASK_ATTR(2l);
494static CCN_CMP_MASK_ATTR(2h);
495static CCN_CMP_MASK_ATTR(3l);
496static CCN_CMP_MASK_ATTR(3h);
497static CCN_CMP_MASK_ATTR(4l);
498static CCN_CMP_MASK_ATTR(4h);
499static CCN_CMP_MASK_ATTR(5l);
500static CCN_CMP_MASK_ATTR(5h);
501static CCN_CMP_MASK_ATTR(6l);
502static CCN_CMP_MASK_ATTR(6h);
503static CCN_CMP_MASK_ATTR(7l);
504static CCN_CMP_MASK_ATTR(7h);
505static CCN_CMP_MASK_ATTR_RO(8l);
506static CCN_CMP_MASK_ATTR_RO(8h);
507static CCN_CMP_MASK_ATTR_RO(9l);
508static CCN_CMP_MASK_ATTR_RO(9h);
509static CCN_CMP_MASK_ATTR_RO(al);
510static CCN_CMP_MASK_ATTR_RO(ah);
511static CCN_CMP_MASK_ATTR_RO(bl);
512static CCN_CMP_MASK_ATTR_RO(bh);
513
514static struct attribute *arm_ccn_pmu_cmp_mask_attrs[] = {
515 &arm_ccn_pmu_cmp_mask_attr_0l.attr, &arm_ccn_pmu_cmp_mask_attr_0h.attr,
516 &arm_ccn_pmu_cmp_mask_attr_1l.attr, &arm_ccn_pmu_cmp_mask_attr_1h.attr,
517 &arm_ccn_pmu_cmp_mask_attr_2l.attr, &arm_ccn_pmu_cmp_mask_attr_2h.attr,
518 &arm_ccn_pmu_cmp_mask_attr_3l.attr, &arm_ccn_pmu_cmp_mask_attr_3h.attr,
519 &arm_ccn_pmu_cmp_mask_attr_4l.attr, &arm_ccn_pmu_cmp_mask_attr_4h.attr,
520 &arm_ccn_pmu_cmp_mask_attr_5l.attr, &arm_ccn_pmu_cmp_mask_attr_5h.attr,
521 &arm_ccn_pmu_cmp_mask_attr_6l.attr, &arm_ccn_pmu_cmp_mask_attr_6h.attr,
522 &arm_ccn_pmu_cmp_mask_attr_7l.attr, &arm_ccn_pmu_cmp_mask_attr_7h.attr,
523 &arm_ccn_pmu_cmp_mask_attr_8l.attr, &arm_ccn_pmu_cmp_mask_attr_8h.attr,
524 &arm_ccn_pmu_cmp_mask_attr_9l.attr, &arm_ccn_pmu_cmp_mask_attr_9h.attr,
525 &arm_ccn_pmu_cmp_mask_attr_al.attr, &arm_ccn_pmu_cmp_mask_attr_ah.attr,
526 &arm_ccn_pmu_cmp_mask_attr_bl.attr, &arm_ccn_pmu_cmp_mask_attr_bh.attr,
527 NULL
528};
529
530static const struct attribute_group arm_ccn_pmu_cmp_mask_attr_group = {
531 .name = "cmp_mask",
532 .attrs = arm_ccn_pmu_cmp_mask_attrs,
533};
534
535static ssize_t arm_ccn_pmu_cpumask_show(struct device *dev,
536 struct device_attribute *attr, char *buf)
537{
538 struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
539
540 return sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(cpumask_of(ccn->dt.cpu)));
541}
542
543static struct device_attribute arm_ccn_pmu_cpumask_attr =
544 __ATTR(cpumask, S_IRUGO, arm_ccn_pmu_cpumask_show, NULL);
545
546static struct attribute *arm_ccn_pmu_cpumask_attrs[] = {
547 &arm_ccn_pmu_cpumask_attr.attr,
548 NULL,
549};
550
551static const struct attribute_group arm_ccn_pmu_cpumask_attr_group = {
552 .attrs = arm_ccn_pmu_cpumask_attrs,
553};
554
555/*
556 * Default poll period is 10ms, which is way over the top anyway,
557 * as in the worst case scenario (an event every cycle), with 1GHz
558 * clocked bus, the smallest, 32 bit counter will overflow in
559 * more than 4s.
560 */
561static unsigned int arm_ccn_pmu_poll_period_us = 10000;
562module_param_named(pmu_poll_period_us, arm_ccn_pmu_poll_period_us, uint,
563 S_IRUGO | S_IWUSR);
564
565static ktime_t arm_ccn_pmu_timer_period(void)
566{
567 return us_to_ktime((u64)arm_ccn_pmu_poll_period_us);
568}
569
570
571static const struct attribute_group *arm_ccn_pmu_attr_groups[] = {
572 &arm_ccn_pmu_events_attr_group,
573 &arm_ccn_pmu_format_attr_group,
574 &arm_ccn_pmu_cmp_mask_attr_group,
575 &arm_ccn_pmu_cpumask_attr_group,
576 NULL
577};
578
579
580static int arm_ccn_pmu_alloc_bit(unsigned long *bitmap, unsigned long size)
581{
582 int bit;
583
584 do {
585 bit = find_first_zero_bit(bitmap, size);
586 if (bit >= size)
587 return -EAGAIN;
588 } while (test_and_set_bit(bit, bitmap));
589
590 return bit;
591}
592
593/* All RN-I and RN-D nodes have identical PMUs */
594static int arm_ccn_pmu_type_eq(u32 a, u32 b)
595{
596 if (a == b)
597 return 1;
598
599 switch (a) {
600 case CCN_TYPE_RNI_1P:
601 case CCN_TYPE_RNI_2P:
602 case CCN_TYPE_RNI_3P:
603 case CCN_TYPE_RND_1P:
604 case CCN_TYPE_RND_2P:
605 case CCN_TYPE_RND_3P:
606 switch (b) {
607 case CCN_TYPE_RNI_1P:
608 case CCN_TYPE_RNI_2P:
609 case CCN_TYPE_RNI_3P:
610 case CCN_TYPE_RND_1P:
611 case CCN_TYPE_RND_2P:
612 case CCN_TYPE_RND_3P:
613 return 1;
614 }
615 break;
616 }
617
618 return 0;
619}
620
621static int arm_ccn_pmu_event_alloc(struct perf_event *event)
622{
623 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
624 struct hw_perf_event *hw = &event->hw;
625 u32 node_xp, type, event_id;
626 struct arm_ccn_component *source;
627 int bit;
628
629 node_xp = CCN_CONFIG_NODE(event->attr.config);
630 type = CCN_CONFIG_TYPE(event->attr.config);
631 event_id = CCN_CONFIG_EVENT(event->attr.config);
632
633 /* Allocate the cycle counter */
634 if (type == CCN_TYPE_CYCLES) {
635 if (test_and_set_bit(CCN_IDX_PMU_CYCLE_COUNTER,
636 ccn->dt.pmu_counters_mask))
637 return -EAGAIN;
638
639 hw->idx = CCN_IDX_PMU_CYCLE_COUNTER;
640 ccn->dt.pmu_counters[CCN_IDX_PMU_CYCLE_COUNTER].event = event;
641
642 return 0;
643 }
644
645 /* Allocate an event counter */
646 hw->idx = arm_ccn_pmu_alloc_bit(ccn->dt.pmu_counters_mask,
647 CCN_NUM_PMU_EVENT_COUNTERS);
648 if (hw->idx < 0) {
649 dev_dbg(ccn->dev, "No more counters available!\n");
650 return -EAGAIN;
651 }
652
653 if (type == CCN_TYPE_XP)
654 source = &ccn->xp[node_xp];
655 else
656 source = &ccn->node[node_xp];
657 ccn->dt.pmu_counters[hw->idx].source = source;
658
659 /* Allocate an event source or a watchpoint */
660 if (type == CCN_TYPE_XP && event_id == CCN_EVENT_WATCHPOINT)
661 bit = arm_ccn_pmu_alloc_bit(source->xp.dt_cmp_mask,
662 CCN_NUM_XP_WATCHPOINTS);
663 else
664 bit = arm_ccn_pmu_alloc_bit(source->pmu_events_mask,
665 CCN_NUM_PMU_EVENTS);
666 if (bit < 0) {
667 dev_dbg(ccn->dev, "No more event sources/watchpoints on node/XP %d!\n",
668 node_xp);
669 clear_bit(hw->idx, ccn->dt.pmu_counters_mask);
670 return -EAGAIN;
671 }
672 hw->config_base = bit;
673
674 ccn->dt.pmu_counters[hw->idx].event = event;
675
676 return 0;
677}
678
679static void arm_ccn_pmu_event_release(struct perf_event *event)
680{
681 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
682 struct hw_perf_event *hw = &event->hw;
683
684 if (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER) {
685 clear_bit(CCN_IDX_PMU_CYCLE_COUNTER, ccn->dt.pmu_counters_mask);
686 } else {
687 struct arm_ccn_component *source =
688 ccn->dt.pmu_counters[hw->idx].source;
689
690 if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP &&
691 CCN_CONFIG_EVENT(event->attr.config) ==
692 CCN_EVENT_WATCHPOINT)
693 clear_bit(hw->config_base, source->xp.dt_cmp_mask);
694 else
695 clear_bit(hw->config_base, source->pmu_events_mask);
696 clear_bit(hw->idx, ccn->dt.pmu_counters_mask);
697 }
698
699 ccn->dt.pmu_counters[hw->idx].source = NULL;
700 ccn->dt.pmu_counters[hw->idx].event = NULL;
701}
702
703static int arm_ccn_pmu_event_init(struct perf_event *event)
704{
705 struct arm_ccn *ccn;
706 struct hw_perf_event *hw = &event->hw;
707 u32 node_xp, type, event_id;
708 int valid;
709 int i;
710 struct perf_event *sibling;
711
712 if (event->attr.type != event->pmu->type)
713 return -ENOENT;
714
715 ccn = pmu_to_arm_ccn(event->pmu);
716
717 if (hw->sample_period) {
718 dev_dbg(ccn->dev, "Sampling not supported!\n");
719 return -EOPNOTSUPP;
720 }
721
722 if (has_branch_stack(event)) {
723 dev_dbg(ccn->dev, "Can't exclude execution levels!\n");
724 return -EINVAL;
725 }
726
727 if (event->cpu < 0) {
728 dev_dbg(ccn->dev, "Can't provide per-task data!\n");
729 return -EOPNOTSUPP;
730 }
731 /*
732 * Many perf core operations (eg. events rotation) operate on a
733 * single CPU context. This is obvious for CPU PMUs, where one
734 * expects the same sets of events being observed on all CPUs,
735 * but can lead to issues for off-core PMUs, like CCN, where each
736 * event could be theoretically assigned to a different CPU. To
737 * mitigate this, we enforce CPU assignment to one, selected
738 * processor (the one described in the "cpumask" attribute).
739 */
740 event->cpu = ccn->dt.cpu;
741
742 node_xp = CCN_CONFIG_NODE(event->attr.config);
743 type = CCN_CONFIG_TYPE(event->attr.config);
744 event_id = CCN_CONFIG_EVENT(event->attr.config);
745
746 /* Validate node/xp vs topology */
747 switch (type) {
748 case CCN_TYPE_MN:
749 if (node_xp != ccn->mn_id) {
750 dev_dbg(ccn->dev, "Invalid MN ID %d!\n", node_xp);
751 return -EINVAL;
752 }
753 break;
754 case CCN_TYPE_XP:
755 if (node_xp >= ccn->num_xps) {
756 dev_dbg(ccn->dev, "Invalid XP ID %d!\n", node_xp);
757 return -EINVAL;
758 }
759 break;
760 case CCN_TYPE_CYCLES:
761 break;
762 default:
763 if (node_xp >= ccn->num_nodes) {
764 dev_dbg(ccn->dev, "Invalid node ID %d!\n", node_xp);
765 return -EINVAL;
766 }
767 if (!arm_ccn_pmu_type_eq(type, ccn->node[node_xp].type)) {
768 dev_dbg(ccn->dev, "Invalid type 0x%x for node %d!\n",
769 type, node_xp);
770 return -EINVAL;
771 }
772 break;
773 }
774
775 /* Validate event ID vs available for the type */
776 for (i = 0, valid = 0; i < ARRAY_SIZE(arm_ccn_pmu_events) && !valid;
777 i++) {
778 struct arm_ccn_pmu_event *e = &arm_ccn_pmu_events[i];
779 u32 port = CCN_CONFIG_PORT(event->attr.config);
780 u32 vc = CCN_CONFIG_VC(event->attr.config);
781
782 if (!arm_ccn_pmu_type_eq(type, e->type))
783 continue;
784 if (event_id != e->event)
785 continue;
786 if (e->num_ports && port >= e->num_ports) {
787 dev_dbg(ccn->dev, "Invalid port %d for node/XP %d!\n",
788 port, node_xp);
789 return -EINVAL;
790 }
791 if (e->num_vcs && vc >= e->num_vcs) {
792 dev_dbg(ccn->dev, "Invalid vc %d for node/XP %d!\n",
793 vc, node_xp);
794 return -EINVAL;
795 }
796 valid = 1;
797 }
798 if (!valid) {
799 dev_dbg(ccn->dev, "Invalid event 0x%x for node/XP %d!\n",
800 event_id, node_xp);
801 return -EINVAL;
802 }
803
804 /* Watchpoint-based event for a node is actually set on XP */
805 if (event_id == CCN_EVENT_WATCHPOINT && type != CCN_TYPE_XP) {
806 u32 port;
807
808 type = CCN_TYPE_XP;
809 port = arm_ccn_node_to_xp_port(node_xp);
810 node_xp = arm_ccn_node_to_xp(node_xp);
811
812 arm_ccn_pmu_config_set(&event->attr.config,
813 node_xp, type, port);
814 }
815
816 /*
817 * We must NOT create groups containing mixed PMUs, although software
818 * events are acceptable (for example to create a CCN group
819 * periodically read when a hrtimer aka cpu-clock leader triggers).
820 */
821 if (event->group_leader->pmu != event->pmu &&
822 !is_software_event(event->group_leader))
823 return -EINVAL;
824
825 for_each_sibling_event(sibling, event->group_leader) {
826 if (sibling->pmu != event->pmu &&
827 !is_software_event(sibling))
828 return -EINVAL;
829 }
830
831 return 0;
832}
833
834static u64 arm_ccn_pmu_read_counter(struct arm_ccn *ccn, int idx)
835{
836 u64 res;
837
838 if (idx == CCN_IDX_PMU_CYCLE_COUNTER) {
839#ifdef readq
840 res = readq(ccn->dt.base + CCN_DT_PMCCNTR);
841#else
842 /* 40 bit counter, can do snapshot and read in two parts */
843 writel(0x1, ccn->dt.base + CCN_DT_PMSR_REQ);
844 while (!(readl(ccn->dt.base + CCN_DT_PMSR) & 0x1))
845 ;
846 writel(0x1, ccn->dt.base + CCN_DT_PMSR_CLR);
847 res = readl(ccn->dt.base + CCN_DT_PMCCNTRSR + 4) & 0xff;
848 res <<= 32;
849 res |= readl(ccn->dt.base + CCN_DT_PMCCNTRSR);
850#endif
851 } else {
852 res = readl(ccn->dt.base + CCN_DT_PMEVCNT(idx));
853 }
854
855 return res;
856}
857
858static void arm_ccn_pmu_event_update(struct perf_event *event)
859{
860 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
861 struct hw_perf_event *hw = &event->hw;
862 u64 prev_count, new_count, mask;
863
864 do {
865 prev_count = local64_read(&hw->prev_count);
866 new_count = arm_ccn_pmu_read_counter(ccn, hw->idx);
867 } while (local64_xchg(&hw->prev_count, new_count) != prev_count);
868
869 mask = (1LLU << (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER ? 40 : 32)) - 1;
870
871 local64_add((new_count - prev_count) & mask, &event->count);
872}
873
874static void arm_ccn_pmu_xp_dt_config(struct perf_event *event, int enable)
875{
876 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
877 struct hw_perf_event *hw = &event->hw;
878 struct arm_ccn_component *xp;
879 u32 val, dt_cfg;
880
881 /* Nothing to do for cycle counter */
882 if (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER)
883 return;
884
885 if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP)
886 xp = &ccn->xp[CCN_CONFIG_XP(event->attr.config)];
887 else
888 xp = &ccn->xp[arm_ccn_node_to_xp(
889 CCN_CONFIG_NODE(event->attr.config))];
890
891 if (enable)
892 dt_cfg = hw->event_base;
893 else
894 dt_cfg = CCN_XP_DT_CONFIG__DT_CFG__PASS_THROUGH;
895
896 spin_lock(&ccn->dt.config_lock);
897
898 val = readl(xp->base + CCN_XP_DT_CONFIG);
899 val &= ~(CCN_XP_DT_CONFIG__DT_CFG__MASK <<
900 CCN_XP_DT_CONFIG__DT_CFG__SHIFT(hw->idx));
901 val |= dt_cfg << CCN_XP_DT_CONFIG__DT_CFG__SHIFT(hw->idx);
902 writel(val, xp->base + CCN_XP_DT_CONFIG);
903
904 spin_unlock(&ccn->dt.config_lock);
905}
906
907static void arm_ccn_pmu_event_start(struct perf_event *event, int flags)
908{
909 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
910 struct hw_perf_event *hw = &event->hw;
911
912 local64_set(&event->hw.prev_count,
913 arm_ccn_pmu_read_counter(ccn, hw->idx));
914 hw->state = 0;
915
916 /* Set the DT bus input, engaging the counter */
917 arm_ccn_pmu_xp_dt_config(event, 1);
918}
919
920static void arm_ccn_pmu_event_stop(struct perf_event *event, int flags)
921{
922 struct hw_perf_event *hw = &event->hw;
923
924 /* Disable counting, setting the DT bus to pass-through mode */
925 arm_ccn_pmu_xp_dt_config(event, 0);
926
927 if (flags & PERF_EF_UPDATE)
928 arm_ccn_pmu_event_update(event);
929
930 hw->state |= PERF_HES_STOPPED;
931}
932
933static void arm_ccn_pmu_xp_watchpoint_config(struct perf_event *event)
934{
935 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
936 struct hw_perf_event *hw = &event->hw;
937 struct arm_ccn_component *source =
938 ccn->dt.pmu_counters[hw->idx].source;
939 unsigned long wp = hw->config_base;
940 u32 val;
941 u64 cmp_l = event->attr.config1;
942 u64 cmp_h = event->attr.config2;
943 u64 mask_l = ccn->dt.cmp_mask[CCN_CONFIG_MASK(event->attr.config)].l;
944 u64 mask_h = ccn->dt.cmp_mask[CCN_CONFIG_MASK(event->attr.config)].h;
945
946 hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT(wp);
947
948 /* Direction (RX/TX), device (port) & virtual channel */
949 val = readl(source->base + CCN_XP_DT_INTERFACE_SEL);
950 val &= ~(CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__MASK <<
951 CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__SHIFT(wp));
952 val |= CCN_CONFIG_DIR(event->attr.config) <<
953 CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__SHIFT(wp);
954 val &= ~(CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__MASK <<
955 CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__SHIFT(wp));
956 val |= CCN_CONFIG_PORT(event->attr.config) <<
957 CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__SHIFT(wp);
958 val &= ~(CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__MASK <<
959 CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__SHIFT(wp));
960 val |= CCN_CONFIG_VC(event->attr.config) <<
961 CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__SHIFT(wp);
962 writel(val, source->base + CCN_XP_DT_INTERFACE_SEL);
963
964 /* Comparison values */
965 writel(cmp_l & 0xffffffff, source->base + CCN_XP_DT_CMP_VAL_L(wp));
966 writel((cmp_l >> 32) & 0x7fffffff,
967 source->base + CCN_XP_DT_CMP_VAL_L(wp) + 4);
968 writel(cmp_h & 0xffffffff, source->base + CCN_XP_DT_CMP_VAL_H(wp));
969 writel((cmp_h >> 32) & 0x0fffffff,
970 source->base + CCN_XP_DT_CMP_VAL_H(wp) + 4);
971
972 /* Mask */
973 writel(mask_l & 0xffffffff, source->base + CCN_XP_DT_CMP_MASK_L(wp));
974 writel((mask_l >> 32) & 0x7fffffff,
975 source->base + CCN_XP_DT_CMP_MASK_L(wp) + 4);
976 writel(mask_h & 0xffffffff, source->base + CCN_XP_DT_CMP_MASK_H(wp));
977 writel((mask_h >> 32) & 0x0fffffff,
978 source->base + CCN_XP_DT_CMP_MASK_H(wp) + 4);
979}
980
981static void arm_ccn_pmu_xp_event_config(struct perf_event *event)
982{
983 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
984 struct hw_perf_event *hw = &event->hw;
985 struct arm_ccn_component *source =
986 ccn->dt.pmu_counters[hw->idx].source;
987 u32 val, id;
988
989 hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__XP_PMU_EVENT(hw->config_base);
990
991 id = (CCN_CONFIG_VC(event->attr.config) << 4) |
992 (CCN_CONFIG_BUS(event->attr.config) << 3) |
993 (CCN_CONFIG_EVENT(event->attr.config) << 0);
994
995 val = readl(source->base + CCN_XP_PMU_EVENT_SEL);
996 val &= ~(CCN_XP_PMU_EVENT_SEL__ID__MASK <<
997 CCN_XP_PMU_EVENT_SEL__ID__SHIFT(hw->config_base));
998 val |= id << CCN_XP_PMU_EVENT_SEL__ID__SHIFT(hw->config_base);
999 writel(val, source->base + CCN_XP_PMU_EVENT_SEL);
1000}
1001
1002static void arm_ccn_pmu_node_event_config(struct perf_event *event)
1003{
1004 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
1005 struct hw_perf_event *hw = &event->hw;
1006 struct arm_ccn_component *source =
1007 ccn->dt.pmu_counters[hw->idx].source;
1008 u32 type = CCN_CONFIG_TYPE(event->attr.config);
1009 u32 val, port;
1010
1011 port = arm_ccn_node_to_xp_port(CCN_CONFIG_NODE(event->attr.config));
1012 hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__DEVICE_PMU_EVENT(port,
1013 hw->config_base);
1014
1015 /* These *_event_sel regs should be identical, but let's make sure... */
1016 BUILD_BUG_ON(CCN_HNF_PMU_EVENT_SEL != CCN_SBAS_PMU_EVENT_SEL);
1017 BUILD_BUG_ON(CCN_SBAS_PMU_EVENT_SEL != CCN_RNI_PMU_EVENT_SEL);
1018 BUILD_BUG_ON(CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(1) !=
1019 CCN_SBAS_PMU_EVENT_SEL__ID__SHIFT(1));
1020 BUILD_BUG_ON(CCN_SBAS_PMU_EVENT_SEL__ID__SHIFT(1) !=
1021 CCN_RNI_PMU_EVENT_SEL__ID__SHIFT(1));
1022 BUILD_BUG_ON(CCN_HNF_PMU_EVENT_SEL__ID__MASK !=
1023 CCN_SBAS_PMU_EVENT_SEL__ID__MASK);
1024 BUILD_BUG_ON(CCN_SBAS_PMU_EVENT_SEL__ID__MASK !=
1025 CCN_RNI_PMU_EVENT_SEL__ID__MASK);
1026 if (WARN_ON(type != CCN_TYPE_HNF && type != CCN_TYPE_SBAS &&
1027 !arm_ccn_pmu_type_eq(type, CCN_TYPE_RNI_3P)))
1028 return;
1029
1030 /* Set the event id for the pre-allocated counter */
1031 val = readl(source->base + CCN_HNF_PMU_EVENT_SEL);
1032 val &= ~(CCN_HNF_PMU_EVENT_SEL__ID__MASK <<
1033 CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(hw->config_base));
1034 val |= CCN_CONFIG_EVENT(event->attr.config) <<
1035 CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(hw->config_base);
1036 writel(val, source->base + CCN_HNF_PMU_EVENT_SEL);
1037}
1038
1039static void arm_ccn_pmu_event_config(struct perf_event *event)
1040{
1041 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
1042 struct hw_perf_event *hw = &event->hw;
1043 u32 xp, offset, val;
1044
1045 /* Cycle counter requires no setup */
1046 if (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER)
1047 return;
1048
1049 if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP)
1050 xp = CCN_CONFIG_XP(event->attr.config);
1051 else
1052 xp = arm_ccn_node_to_xp(CCN_CONFIG_NODE(event->attr.config));
1053
1054 spin_lock(&ccn->dt.config_lock);
1055
1056 /* Set the DT bus "distance" register */
1057 offset = (hw->idx / 4) * 4;
1058 val = readl(ccn->dt.base + CCN_DT_ACTIVE_DSM + offset);
1059 val &= ~(CCN_DT_ACTIVE_DSM__DSM_ID__MASK <<
1060 CCN_DT_ACTIVE_DSM__DSM_ID__SHIFT(hw->idx % 4));
1061 val |= xp << CCN_DT_ACTIVE_DSM__DSM_ID__SHIFT(hw->idx % 4);
1062 writel(val, ccn->dt.base + CCN_DT_ACTIVE_DSM + offset);
1063
1064 if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP) {
1065 if (CCN_CONFIG_EVENT(event->attr.config) ==
1066 CCN_EVENT_WATCHPOINT)
1067 arm_ccn_pmu_xp_watchpoint_config(event);
1068 else
1069 arm_ccn_pmu_xp_event_config(event);
1070 } else {
1071 arm_ccn_pmu_node_event_config(event);
1072 }
1073
1074 spin_unlock(&ccn->dt.config_lock);
1075}
1076
1077static int arm_ccn_pmu_active_counters(struct arm_ccn *ccn)
1078{
1079 return bitmap_weight(ccn->dt.pmu_counters_mask,
1080 CCN_NUM_PMU_EVENT_COUNTERS + 1);
1081}
1082
1083static int arm_ccn_pmu_event_add(struct perf_event *event, int flags)
1084{
1085 int err;
1086 struct hw_perf_event *hw = &event->hw;
1087 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
1088
1089 err = arm_ccn_pmu_event_alloc(event);
1090 if (err)
1091 return err;
1092
1093 /*
1094 * Pin the timer, so that the overflows are handled by the chosen
1095 * event->cpu (this is the same one as presented in "cpumask"
1096 * attribute).
1097 */
1098 if (!ccn->irq && arm_ccn_pmu_active_counters(ccn) == 1)
1099 hrtimer_start(&ccn->dt.hrtimer, arm_ccn_pmu_timer_period(),
1100 HRTIMER_MODE_REL_PINNED);
1101
1102 arm_ccn_pmu_event_config(event);
1103
1104 hw->state = PERF_HES_STOPPED;
1105
1106 if (flags & PERF_EF_START)
1107 arm_ccn_pmu_event_start(event, PERF_EF_UPDATE);
1108
1109 return 0;
1110}
1111
1112static void arm_ccn_pmu_event_del(struct perf_event *event, int flags)
1113{
1114 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
1115
1116 arm_ccn_pmu_event_stop(event, PERF_EF_UPDATE);
1117
1118 arm_ccn_pmu_event_release(event);
1119
1120 if (!ccn->irq && arm_ccn_pmu_active_counters(ccn) == 0)
1121 hrtimer_cancel(&ccn->dt.hrtimer);
1122}
1123
1124static void arm_ccn_pmu_event_read(struct perf_event *event)
1125{
1126 arm_ccn_pmu_event_update(event);
1127}
1128
1129static void arm_ccn_pmu_enable(struct pmu *pmu)
1130{
1131 struct arm_ccn *ccn = pmu_to_arm_ccn(pmu);
1132
1133 u32 val = readl(ccn->dt.base + CCN_DT_PMCR);
1134 val |= CCN_DT_PMCR__PMU_EN;
1135 writel(val, ccn->dt.base + CCN_DT_PMCR);
1136}
1137
1138static void arm_ccn_pmu_disable(struct pmu *pmu)
1139{
1140 struct arm_ccn *ccn = pmu_to_arm_ccn(pmu);
1141
1142 u32 val = readl(ccn->dt.base + CCN_DT_PMCR);
1143 val &= ~CCN_DT_PMCR__PMU_EN;
1144 writel(val, ccn->dt.base + CCN_DT_PMCR);
1145}
1146
1147static irqreturn_t arm_ccn_pmu_overflow_handler(struct arm_ccn_dt *dt)
1148{
1149 u32 pmovsr = readl(dt->base + CCN_DT_PMOVSR);
1150 int idx;
1151
1152 if (!pmovsr)
1153 return IRQ_NONE;
1154
1155 writel(pmovsr, dt->base + CCN_DT_PMOVSR_CLR);
1156
1157 BUILD_BUG_ON(CCN_IDX_PMU_CYCLE_COUNTER != CCN_NUM_PMU_EVENT_COUNTERS);
1158
1159 for (idx = 0; idx < CCN_NUM_PMU_EVENT_COUNTERS + 1; idx++) {
1160 struct perf_event *event = dt->pmu_counters[idx].event;
1161 int overflowed = pmovsr & BIT(idx);
1162
1163 WARN_ON_ONCE(overflowed && !event &&
1164 idx != CCN_IDX_PMU_CYCLE_COUNTER);
1165
1166 if (!event || !overflowed)
1167 continue;
1168
1169 arm_ccn_pmu_event_update(event);
1170 }
1171
1172 return IRQ_HANDLED;
1173}
1174
1175static enum hrtimer_restart arm_ccn_pmu_timer_handler(struct hrtimer *hrtimer)
1176{
1177 struct arm_ccn_dt *dt = container_of(hrtimer, struct arm_ccn_dt,
1178 hrtimer);
1179 unsigned long flags;
1180
1181 local_irq_save(flags);
1182 arm_ccn_pmu_overflow_handler(dt);
1183 local_irq_restore(flags);
1184
1185 hrtimer_forward_now(hrtimer, arm_ccn_pmu_timer_period());
1186 return HRTIMER_RESTART;
1187}
1188
1189
1190static int arm_ccn_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node)
1191{
1192 struct arm_ccn_dt *dt = hlist_entry_safe(node, struct arm_ccn_dt, node);
1193 struct arm_ccn *ccn = container_of(dt, struct arm_ccn, dt);
1194 unsigned int target;
1195
1196 if (cpu != dt->cpu)
1197 return 0;
1198 target = cpumask_any_but(cpu_online_mask, cpu);
1199 if (target >= nr_cpu_ids)
1200 return 0;
1201 perf_pmu_migrate_context(&dt->pmu, cpu, target);
1202 dt->cpu = target;
1203 if (ccn->irq)
1204 WARN_ON(irq_set_affinity(ccn->irq, cpumask_of(dt->cpu)));
1205 return 0;
1206}
1207
1208static DEFINE_IDA(arm_ccn_pmu_ida);
1209
1210static int arm_ccn_pmu_init(struct arm_ccn *ccn)
1211{
1212 int i;
1213 char *name;
1214 int err;
1215
1216 /* Initialize DT subsystem */
1217 ccn->dt.base = ccn->base + CCN_REGION_SIZE;
1218 spin_lock_init(&ccn->dt.config_lock);
1219 writel(CCN_DT_PMOVSR_CLR__MASK, ccn->dt.base + CCN_DT_PMOVSR_CLR);
1220 writel(CCN_DT_CTL__DT_EN, ccn->dt.base + CCN_DT_CTL);
1221 writel(CCN_DT_PMCR__OVFL_INTR_EN | CCN_DT_PMCR__PMU_EN,
1222 ccn->dt.base + CCN_DT_PMCR);
1223 writel(0x1, ccn->dt.base + CCN_DT_PMSR_CLR);
1224 for (i = 0; i < ccn->num_xps; i++) {
1225 writel(0, ccn->xp[i].base + CCN_XP_DT_CONFIG);
1226 writel((CCN_XP_DT_CONTROL__WP_ARM_SEL__ALWAYS <<
1227 CCN_XP_DT_CONTROL__WP_ARM_SEL__SHIFT(0)) |
1228 (CCN_XP_DT_CONTROL__WP_ARM_SEL__ALWAYS <<
1229 CCN_XP_DT_CONTROL__WP_ARM_SEL__SHIFT(1)) |
1230 CCN_XP_DT_CONTROL__DT_ENABLE,
1231 ccn->xp[i].base + CCN_XP_DT_CONTROL);
1232 }
1233 ccn->dt.cmp_mask[CCN_IDX_MASK_ANY].l = ~0;
1234 ccn->dt.cmp_mask[CCN_IDX_MASK_ANY].h = ~0;
1235 ccn->dt.cmp_mask[CCN_IDX_MASK_EXACT].l = 0;
1236 ccn->dt.cmp_mask[CCN_IDX_MASK_EXACT].h = 0;
1237 ccn->dt.cmp_mask[CCN_IDX_MASK_ORDER].l = ~0;
1238 ccn->dt.cmp_mask[CCN_IDX_MASK_ORDER].h = ~(0x1 << 15);
1239 ccn->dt.cmp_mask[CCN_IDX_MASK_OPCODE].l = ~0;
1240 ccn->dt.cmp_mask[CCN_IDX_MASK_OPCODE].h = ~(0x1f << 9);
1241
1242 /* Get a convenient /sys/event_source/devices/ name */
1243 ccn->dt.id = ida_alloc(&arm_ccn_pmu_ida, GFP_KERNEL);
1244 if (ccn->dt.id == 0) {
1245 name = "ccn";
1246 } else {
1247 name = devm_kasprintf(ccn->dev, GFP_KERNEL, "ccn_%d",
1248 ccn->dt.id);
1249 if (!name) {
1250 err = -ENOMEM;
1251 goto error_choose_name;
1252 }
1253 }
1254
1255 /* Perf driver registration */
1256 ccn->dt.pmu = (struct pmu) {
1257 .module = THIS_MODULE,
1258 .parent = ccn->dev,
1259 .attr_groups = arm_ccn_pmu_attr_groups,
1260 .task_ctx_nr = perf_invalid_context,
1261 .event_init = arm_ccn_pmu_event_init,
1262 .add = arm_ccn_pmu_event_add,
1263 .del = arm_ccn_pmu_event_del,
1264 .start = arm_ccn_pmu_event_start,
1265 .stop = arm_ccn_pmu_event_stop,
1266 .read = arm_ccn_pmu_event_read,
1267 .pmu_enable = arm_ccn_pmu_enable,
1268 .pmu_disable = arm_ccn_pmu_disable,
1269 .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
1270 };
1271
1272 /* No overflow interrupt? Have to use a timer instead. */
1273 if (!ccn->irq) {
1274 dev_info(ccn->dev, "No access to interrupts, using timer.\n");
1275 hrtimer_setup(&ccn->dt.hrtimer, arm_ccn_pmu_timer_handler, CLOCK_MONOTONIC,
1276 HRTIMER_MODE_REL);
1277 }
1278
1279 /* Pick one CPU which we will use to collect data from CCN... */
1280 ccn->dt.cpu = raw_smp_processor_id();
1281
1282 /* Also make sure that the overflow interrupt is handled by this CPU */
1283 if (ccn->irq) {
1284 err = irq_set_affinity(ccn->irq, cpumask_of(ccn->dt.cpu));
1285 if (err) {
1286 dev_err(ccn->dev, "Failed to set interrupt affinity!\n");
1287 goto error_set_affinity;
1288 }
1289 }
1290
1291 cpuhp_state_add_instance_nocalls(CPUHP_AP_PERF_ARM_CCN_ONLINE,
1292 &ccn->dt.node);
1293
1294 err = perf_pmu_register(&ccn->dt.pmu, name, -1);
1295 if (err)
1296 goto error_pmu_register;
1297
1298 return 0;
1299
1300error_pmu_register:
1301 cpuhp_state_remove_instance_nocalls(CPUHP_AP_PERF_ARM_CCN_ONLINE,
1302 &ccn->dt.node);
1303error_set_affinity:
1304error_choose_name:
1305 ida_free(&arm_ccn_pmu_ida, ccn->dt.id);
1306 for (i = 0; i < ccn->num_xps; i++)
1307 writel(0, ccn->xp[i].base + CCN_XP_DT_CONTROL);
1308 writel(0, ccn->dt.base + CCN_DT_PMCR);
1309 return err;
1310}
1311
1312static void arm_ccn_pmu_cleanup(struct arm_ccn *ccn)
1313{
1314 int i;
1315
1316 cpuhp_state_remove_instance_nocalls(CPUHP_AP_PERF_ARM_CCN_ONLINE,
1317 &ccn->dt.node);
1318 for (i = 0; i < ccn->num_xps; i++)
1319 writel(0, ccn->xp[i].base + CCN_XP_DT_CONTROL);
1320 writel(0, ccn->dt.base + CCN_DT_PMCR);
1321 perf_pmu_unregister(&ccn->dt.pmu);
1322 ida_free(&arm_ccn_pmu_ida, ccn->dt.id);
1323}
1324
1325static int arm_ccn_for_each_valid_region(struct arm_ccn *ccn,
1326 int (*callback)(struct arm_ccn *ccn, int region,
1327 void __iomem *base, u32 type, u32 id))
1328{
1329 int region;
1330
1331 for (region = 0; region < CCN_NUM_REGIONS; region++) {
1332 u32 val, type, id;
1333 void __iomem *base;
1334 int err;
1335
1336 val = readl(ccn->base + CCN_MN_OLY_COMP_LIST_63_0 +
1337 4 * (region / 32));
1338 if (!(val & (1 << (region % 32))))
1339 continue;
1340
1341 base = ccn->base + region * CCN_REGION_SIZE;
1342 val = readl(base + CCN_ALL_OLY_ID);
1343 type = (val >> CCN_ALL_OLY_ID__OLY_ID__SHIFT) &
1344 CCN_ALL_OLY_ID__OLY_ID__MASK;
1345 id = (val >> CCN_ALL_OLY_ID__NODE_ID__SHIFT) &
1346 CCN_ALL_OLY_ID__NODE_ID__MASK;
1347
1348 err = callback(ccn, region, base, type, id);
1349 if (err)
1350 return err;
1351 }
1352
1353 return 0;
1354}
1355
1356static int arm_ccn_get_nodes_num(struct arm_ccn *ccn, int region,
1357 void __iomem *base, u32 type, u32 id)
1358{
1359
1360 if (type == CCN_TYPE_XP && id >= ccn->num_xps)
1361 ccn->num_xps = id + 1;
1362 else if (id >= ccn->num_nodes)
1363 ccn->num_nodes = id + 1;
1364
1365 return 0;
1366}
1367
1368static int arm_ccn_init_nodes(struct arm_ccn *ccn, int region,
1369 void __iomem *base, u32 type, u32 id)
1370{
1371 struct arm_ccn_component *component;
1372
1373 dev_dbg(ccn->dev, "Region %d: id=%u, type=0x%02x\n", region, id, type);
1374
1375 switch (type) {
1376 case CCN_TYPE_MN:
1377 ccn->mn_id = id;
1378 return 0;
1379 case CCN_TYPE_DT:
1380 return 0;
1381 case CCN_TYPE_XP:
1382 component = &ccn->xp[id];
1383 break;
1384 case CCN_TYPE_SBSX:
1385 ccn->sbsx_present = 1;
1386 component = &ccn->node[id];
1387 break;
1388 case CCN_TYPE_SBAS:
1389 ccn->sbas_present = 1;
1390 fallthrough;
1391 default:
1392 component = &ccn->node[id];
1393 break;
1394 }
1395
1396 component->base = base;
1397 component->type = type;
1398
1399 return 0;
1400}
1401
1402
1403static irqreturn_t arm_ccn_error_handler(struct arm_ccn *ccn,
1404 const u32 *err_sig_val)
1405{
1406 /* This should be really handled by firmware... */
1407 dev_err(ccn->dev, "Error reported in %08x%08x%08x%08x%08x%08x.\n",
1408 err_sig_val[5], err_sig_val[4], err_sig_val[3],
1409 err_sig_val[2], err_sig_val[1], err_sig_val[0]);
1410 dev_err(ccn->dev, "Disabling interrupt generation for all errors.\n");
1411 writel(CCN_MN_ERRINT_STATUS__ALL_ERRORS__DISABLE,
1412 ccn->base + CCN_MN_ERRINT_STATUS);
1413
1414 return IRQ_HANDLED;
1415}
1416
1417
1418static irqreturn_t arm_ccn_irq_handler(int irq, void *dev_id)
1419{
1420 irqreturn_t res = IRQ_NONE;
1421 struct arm_ccn *ccn = dev_id;
1422 u32 err_sig_val[6];
1423 u32 err_or;
1424 int i;
1425
1426 /* PMU overflow is a special case */
1427 err_or = err_sig_val[0] = readl(ccn->base + CCN_MN_ERR_SIG_VAL_63_0);
1428 if (err_or & CCN_MN_ERR_SIG_VAL_63_0__DT) {
1429 err_or &= ~CCN_MN_ERR_SIG_VAL_63_0__DT;
1430 res = arm_ccn_pmu_overflow_handler(&ccn->dt);
1431 }
1432
1433 /* Have to read all err_sig_vals to clear them */
1434 for (i = 1; i < ARRAY_SIZE(err_sig_val); i++) {
1435 err_sig_val[i] = readl(ccn->base +
1436 CCN_MN_ERR_SIG_VAL_63_0 + i * 4);
1437 err_or |= err_sig_val[i];
1438 }
1439 if (err_or)
1440 res |= arm_ccn_error_handler(ccn, err_sig_val);
1441
1442 if (res != IRQ_NONE)
1443 writel(CCN_MN_ERRINT_STATUS__INTREQ__DESSERT,
1444 ccn->base + CCN_MN_ERRINT_STATUS);
1445
1446 return res;
1447}
1448
1449
1450static int arm_ccn_probe(struct platform_device *pdev)
1451{
1452 struct arm_ccn *ccn;
1453 int irq;
1454 int err;
1455
1456 ccn = devm_kzalloc(&pdev->dev, sizeof(*ccn), GFP_KERNEL);
1457 if (!ccn)
1458 return -ENOMEM;
1459 ccn->dev = &pdev->dev;
1460 platform_set_drvdata(pdev, ccn);
1461
1462 ccn->base = devm_platform_ioremap_resource(pdev, 0);
1463 if (IS_ERR(ccn->base))
1464 return PTR_ERR(ccn->base);
1465
1466 irq = platform_get_irq(pdev, 0);
1467 if (irq < 0)
1468 return irq;
1469
1470 /* Check if we can use the interrupt */
1471 writel(CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLE,
1472 ccn->base + CCN_MN_ERRINT_STATUS);
1473 if (readl(ccn->base + CCN_MN_ERRINT_STATUS) &
1474 CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLED) {
1475 /* Can set 'disable' bits, so can acknowledge interrupts */
1476 writel(CCN_MN_ERRINT_STATUS__PMU_EVENTS__ENABLE,
1477 ccn->base + CCN_MN_ERRINT_STATUS);
1478 err = devm_request_irq(ccn->dev, irq, arm_ccn_irq_handler,
1479 IRQF_NOBALANCING | IRQF_NO_THREAD,
1480 dev_name(ccn->dev), ccn);
1481 if (err)
1482 return err;
1483
1484 ccn->irq = irq;
1485 }
1486
1487
1488 /* Build topology */
1489
1490 err = arm_ccn_for_each_valid_region(ccn, arm_ccn_get_nodes_num);
1491 if (err)
1492 return err;
1493
1494 ccn->node = devm_kcalloc(ccn->dev, ccn->num_nodes, sizeof(*ccn->node),
1495 GFP_KERNEL);
1496 ccn->xp = devm_kcalloc(ccn->dev, ccn->num_xps, sizeof(*ccn->node),
1497 GFP_KERNEL);
1498 if (!ccn->node || !ccn->xp)
1499 return -ENOMEM;
1500
1501 err = arm_ccn_for_each_valid_region(ccn, arm_ccn_init_nodes);
1502 if (err)
1503 return err;
1504
1505 return arm_ccn_pmu_init(ccn);
1506}
1507
1508static void arm_ccn_remove(struct platform_device *pdev)
1509{
1510 struct arm_ccn *ccn = platform_get_drvdata(pdev);
1511
1512 arm_ccn_pmu_cleanup(ccn);
1513}
1514
1515static const struct of_device_id arm_ccn_match[] = {
1516 { .compatible = "arm,ccn-502", },
1517 { .compatible = "arm,ccn-504", },
1518 { .compatible = "arm,ccn-512", },
1519 {},
1520};
1521MODULE_DEVICE_TABLE(of, arm_ccn_match);
1522
1523static struct platform_driver arm_ccn_driver = {
1524 .driver = {
1525 .name = "arm-ccn",
1526 .of_match_table = arm_ccn_match,
1527 .suppress_bind_attrs = true,
1528 },
1529 .probe = arm_ccn_probe,
1530 .remove = arm_ccn_remove,
1531};
1532
1533static int __init arm_ccn_init(void)
1534{
1535 int i, ret;
1536
1537 ret = cpuhp_setup_state_multi(CPUHP_AP_PERF_ARM_CCN_ONLINE,
1538 "perf/arm/ccn:online", NULL,
1539 arm_ccn_pmu_offline_cpu);
1540 if (ret)
1541 return ret;
1542
1543 for (i = 0; i < ARRAY_SIZE(arm_ccn_pmu_events); i++)
1544 arm_ccn_pmu_events_attrs[i] = &arm_ccn_pmu_events[i].attr.attr;
1545
1546 ret = platform_driver_register(&arm_ccn_driver);
1547 if (ret)
1548 cpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_CCN_ONLINE);
1549 return ret;
1550}
1551
1552static void __exit arm_ccn_exit(void)
1553{
1554 platform_driver_unregister(&arm_ccn_driver);
1555 cpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_CCN_ONLINE);
1556}
1557
1558module_init(arm_ccn_init);
1559module_exit(arm_ccn_exit);
1560
1561MODULE_AUTHOR("Pawel Moll <[email protected]>");
1562MODULE_DESCRIPTION("ARM CCN (Cache Coherent Network) Performance Monitor Driver");
1563MODULE_LICENSE("GPL v2");