| 1 | |
| 2 | |
| 3 | * Copyright (c) 2024 AIROHA Inc
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| 4 | * Author: Lorenzo Bianconi <[email protected]>
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| 5 |
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| 6 |
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| 7 | #include <linux/bitfield.h>
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| 8 | #include <linux/delay.h>
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| 9 | #include <linux/io.h>
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| 10 | #include <linux/module.h>
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| 11 | #include <linux/of.h>
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| 12 | #include <linux/phy/phy.h>
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| 13 | #include <linux/platform_device.h>
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| 14 | #include <linux/slab.h>
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| 15 |
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| 16 | #include "phy-airoha-pcie-regs.h"
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| 17 |
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| 18 | #define LEQ_LEN_CTRL_MAX_VAL 7
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| 19 | #define FREQ_LOCK_MAX_ATTEMPT 10
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| 20 |
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| 21 |
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| 22 | #define PHY_HW_INIT_TIME_MS 30
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| 23 |
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| 24 | enum airoha_pcie_port_gen {
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| 25 | PCIE_PORT_GEN1 = 1,
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| 26 | PCIE_PORT_GEN2,
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| 27 | PCIE_PORT_GEN3,
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| 28 | };
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| 29 |
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| 30 | |
| 31 | * struct airoha_pcie_phy - PCIe phy driver main structure
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| 32 | * @dev: pointer to device
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| 33 | * @phy: pointer to generic phy
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| 34 | * @csr_2l: Analogic lane IO mapped register base address
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| 35 | * @pma0: IO mapped register base address of PMA0-PCIe
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| 36 | * @pma1: IO mapped register base address of PMA1-PCIe
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| 37 | * @p0_xr_dtime: IO mapped register base address of port0 Tx-Rx detection time
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| 38 | * @p1_xr_dtime: IO mapped register base address of port1 Tx-Rx detection time
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| 39 | * @rx_aeq: IO mapped register base address of Rx AEQ training
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| 40 |
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| 41 | struct airoha_pcie_phy {
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| 42 | struct device *dev;
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| 43 | struct phy *phy;
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| 44 | void __iomem *csr_2l;
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| 45 | void __iomem *pma0;
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| 46 | void __iomem *pma1;
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| 47 | void __iomem *p0_xr_dtime;
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| 48 | void __iomem *p1_xr_dtime;
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| 49 | void __iomem *rx_aeq;
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| 50 | };
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| 51 |
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| 52 | static void airoha_phy_clear_bits(void __iomem *reg, u32 mask)
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| 53 | {
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| 54 | u32 val = readl(reg) & ~mask;
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| 55 |
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| 56 | writel(val, reg);
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| 57 | }
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| 58 |
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| 59 | static void airoha_phy_set_bits(void __iomem *reg, u32 mask)
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| 60 | {
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| 61 | u32 val = readl(reg) | mask;
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| 62 |
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| 63 | writel(val, reg);
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| 64 | }
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| 65 |
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| 66 | static void airoha_phy_update_bits(void __iomem *reg, u32 mask, u32 val)
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| 67 | {
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| 68 | u32 tmp = readl(reg);
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| 69 |
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| 70 | tmp &= ~mask;
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| 71 | tmp |= val & mask;
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| 72 | writel(tmp, reg);
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| 73 | }
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| 74 |
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| 75 | #define airoha_phy_update_field(reg, mask, val) \
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| 76 | do { \
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| 77 | BUILD_BUG_ON_MSG(!__builtin_constant_p((mask)), \
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| 78 | "mask is not constant"); \
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| 79 | airoha_phy_update_bits((reg), (mask), \
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| 80 | FIELD_PREP((mask), (val))); \
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| 81 | } while (0)
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| 82 |
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| 83 | #define airoha_phy_csr_2l_clear_bits(pcie_phy, reg, mask) \
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| 84 | airoha_phy_clear_bits((pcie_phy)->csr_2l + (reg), (mask))
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| 85 | #define airoha_phy_csr_2l_set_bits(pcie_phy, reg, mask) \
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| 86 | airoha_phy_set_bits((pcie_phy)->csr_2l + (reg), (mask))
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| 87 | #define airoha_phy_csr_2l_update_field(pcie_phy, reg, mask, val) \
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| 88 | airoha_phy_update_field((pcie_phy)->csr_2l + (reg), (mask), (val))
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| 89 | #define airoha_phy_pma0_clear_bits(pcie_phy, reg, mask) \
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| 90 | airoha_phy_clear_bits((pcie_phy)->pma0 + (reg), (mask))
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| 91 | #define airoha_phy_pma1_clear_bits(pcie_phy, reg, mask) \
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| 92 | airoha_phy_clear_bits((pcie_phy)->pma1 + (reg), (mask))
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| 93 | #define airoha_phy_pma0_set_bits(pcie_phy, reg, mask) \
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| 94 | airoha_phy_set_bits((pcie_phy)->pma0 + (reg), (mask))
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| 95 | #define airoha_phy_pma1_set_bits(pcie_phy, reg, mask) \
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| 96 | airoha_phy_set_bits((pcie_phy)->pma1 + (reg), (mask))
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| 97 | #define airoha_phy_pma0_update_field(pcie_phy, reg, mask, val) \
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| 98 | airoha_phy_update_field((pcie_phy)->pma0 + (reg), (mask), (val))
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| 99 | #define airoha_phy_pma1_update_field(pcie_phy, reg, mask, val) \
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| 100 | airoha_phy_update_field((pcie_phy)->pma1 + (reg), (mask), (val))
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| 101 |
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| 102 | static void
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| 103 | airoha_phy_init_lane0_rx_fw_pre_calib(struct airoha_pcie_phy *pcie_phy,
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| 104 | enum airoha_pcie_port_gen gen)
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| 105 | {
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| 106 | u32 fl_out_target = gen == PCIE_PORT_GEN3 ? 41600 : 41941;
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| 107 | u32 lock_cyclecnt = gen == PCIE_PORT_GEN3 ? 26000 : 32767;
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| 108 | u32 pr_idac, val, cdr_pr_idac_tmp = 0;
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| 109 | int i;
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| 110 |
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| 111 | airoha_phy_pma0_set_bits(pcie_phy,
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| 112 | REG_PCIE_PMA_SS_LCPLL_PWCTL_SETTING_1,
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| 113 | PCIE_LCPLL_MAN_PWDB);
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| 114 | airoha_phy_pma0_update_field(pcie_phy, REG_PCIE_PMA_SS_RX_FREQ_DET2,
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| 115 | PCIE_LOCK_TARGET_BEG,
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| 116 | fl_out_target - 100);
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| 117 | airoha_phy_pma0_update_field(pcie_phy, REG_PCIE_PMA_SS_RX_FREQ_DET2,
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| 118 | PCIE_LOCK_TARGET_END,
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| 119 | fl_out_target + 100);
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| 120 | airoha_phy_pma0_update_field(pcie_phy, REG_PCIE_PMA_SS_RX_FREQ_DET1,
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| 121 | PCIE_PLL_FT_LOCK_CYCLECNT, lock_cyclecnt);
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| 122 | airoha_phy_pma0_update_field(pcie_phy, REG_PCIE_PMA_SS_RX_FREQ_DET4,
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| 123 | PCIE_LOCK_LOCKTH, 0x3);
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| 124 | airoha_phy_pma0_update_field(pcie_phy, REG_PCIE_PMA_SS_RX_FREQ_DET3,
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| 125 | PCIE_UNLOCK_TARGET_BEG,
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| 126 | fl_out_target - 100);
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| 127 | airoha_phy_pma0_update_field(pcie_phy, REG_PCIE_PMA_SS_RX_FREQ_DET3,
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| 128 | PCIE_UNLOCK_TARGET_END,
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| 129 | fl_out_target + 100);
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| 130 | airoha_phy_pma0_update_field(pcie_phy, REG_PCIE_PMA_SS_RX_FREQ_DET1,
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| 131 | PCIE_PLL_FT_UNLOCK_CYCLECNT,
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| 132 | lock_cyclecnt);
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| 133 | airoha_phy_pma0_update_field(pcie_phy, REG_PCIE_PMA_SS_RX_FREQ_DET4,
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| 134 | PCIE_UNLOCK_LOCKTH, 0x3);
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| 135 |
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| 136 | airoha_phy_csr_2l_set_bits(pcie_phy, REG_CSR_2L_CDR0_PR_INJ_MODE,
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| 137 | CSR_2L_PXP_CDR0_INJ_FORCE_OFF);
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| 138 |
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| 139 | airoha_phy_pma0_set_bits(pcie_phy,
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| 140 | REG_PCIE_PMA_FORCE_DA_PXP_CDR_PR_LPF_C,
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| 141 | PCIE_FORCE_SEL_DA_PXP_CDR_PR_LPF_R_EN);
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| 142 | airoha_phy_pma0_set_bits(pcie_phy,
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| 143 | REG_PCIE_PMA_FORCE_DA_PXP_CDR_PR_LPF_C,
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| 144 | PCIE_FORCE_DA_PXP_CDR_PR_LPF_R_EN);
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| 145 | airoha_phy_pma0_set_bits(pcie_phy,
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| 146 | REG_PCIE_PMA_FORCE_DA_PXP_CDR_PR_LPF_C,
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| 147 | PCIE_FORCE_SEL_DA_PXP_CDR_PR_LPF_C_EN);
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| 148 | airoha_phy_pma0_clear_bits(pcie_phy,
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| 149 | REG_PCIE_PMA_FORCE_DA_PXP_CDR_PR_LPF_C,
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| 150 | PCIE_FORCE_DA_PXP_CDR_PR_LPF_C_EN);
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| 151 | airoha_phy_pma0_set_bits(pcie_phy,
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| 152 | REG_PCIE_PMA_FORCE_DA_PXP_CDR_PR_IDAC,
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| 153 | PCIE_FORCE_SEL_DA_PXP_CDR_PR_IDAC);
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| 154 |
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| 155 | airoha_phy_pma0_set_bits(pcie_phy,
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| 156 | REG_PCIE_PMA_FORCE_DA_PXP_CDR_PR_PIEYE_PWDB,
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| 157 | PCIE_FORCE_SEL_DA_PXP_CDR_PR_PWDB);
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| 158 | airoha_phy_pma0_clear_bits(pcie_phy,
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| 159 | REG_PCIE_PMA_FORCE_DA_PXP_CDR_PR_PIEYE_PWDB,
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| 160 | PCIE_FORCE_DA_PXP_CDR_PR_PWDB);
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| 161 | airoha_phy_pma0_set_bits(pcie_phy,
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| 162 | REG_PCIE_PMA_FORCE_DA_PXP_CDR_PR_PIEYE_PWDB,
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| 163 | PCIE_FORCE_DA_PXP_CDR_PR_PWDB);
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| 164 |
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| 165 | for (i = 0; i < LEQ_LEN_CTRL_MAX_VAL; i++) {
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| 166 | airoha_phy_pma0_update_field(pcie_phy,
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| 167 | REG_PCIE_PMA_FORCE_DA_PXP_CDR_PR_IDAC,
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| 168 | PCIE_FORCE_DA_PXP_CDR_PR_IDAC, i << 8);
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| 169 | airoha_phy_pma0_clear_bits(pcie_phy,
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| 170 | REG_PCIE_PMA_SS_RX_FREQ_DET4,
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| 171 | PCIE_FREQLOCK_DET_EN);
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| 172 | airoha_phy_pma0_update_field(pcie_phy,
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| 173 | REG_PCIE_PMA_SS_RX_FREQ_DET4,
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| 174 | PCIE_FREQLOCK_DET_EN, 0x3);
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| 175 |
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| 176 | usleep_range(10000, 15000);
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| 177 |
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| 178 | val = FIELD_GET(PCIE_RO_FL_OUT,
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| 179 | readl(pcie_phy->pma0 +
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| 180 | REG_PCIE_PMA_RO_RX_FREQDET));
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| 181 | if (val > fl_out_target)
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| 182 | cdr_pr_idac_tmp = i << 8;
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| 183 | }
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| 184 |
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| 185 | for (i = LEQ_LEN_CTRL_MAX_VAL; i >= 0; i--) {
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| 186 | pr_idac = cdr_pr_idac_tmp | (0x1 << i);
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| 187 | airoha_phy_pma0_update_field(pcie_phy,
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| 188 | REG_PCIE_PMA_FORCE_DA_PXP_CDR_PR_IDAC,
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| 189 | PCIE_FORCE_DA_PXP_CDR_PR_IDAC, pr_idac);
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| 190 | airoha_phy_pma0_clear_bits(pcie_phy,
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| 191 | REG_PCIE_PMA_SS_RX_FREQ_DET4,
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| 192 | PCIE_FREQLOCK_DET_EN);
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| 193 | airoha_phy_pma0_update_field(pcie_phy,
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| 194 | REG_PCIE_PMA_SS_RX_FREQ_DET4,
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| 195 | PCIE_FREQLOCK_DET_EN, 0x3);
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| 196 |
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| 197 | usleep_range(10000, 15000);
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| 198 |
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| 199 | val = FIELD_GET(PCIE_RO_FL_OUT,
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| 200 | readl(pcie_phy->pma0 +
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| 201 | REG_PCIE_PMA_RO_RX_FREQDET));
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| 202 | if (val < fl_out_target)
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| 203 | pr_idac &= ~(0x1 << i);
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| 204 |
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| 205 | cdr_pr_idac_tmp = pr_idac;
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| 206 | }
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| 207 |
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| 208 | airoha_phy_pma0_update_field(pcie_phy,
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| 209 | REG_PCIE_PMA_FORCE_DA_PXP_CDR_PR_IDAC,
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| 210 | PCIE_FORCE_DA_PXP_CDR_PR_IDAC,
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| 211 | cdr_pr_idac_tmp);
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| 212 |
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| 213 | for (i = 0; i < FREQ_LOCK_MAX_ATTEMPT; i++) {
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| 214 | u32 val;
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| 215 |
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| 216 | airoha_phy_pma0_clear_bits(pcie_phy,
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| 217 | REG_PCIE_PMA_SS_RX_FREQ_DET4,
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| 218 | PCIE_FREQLOCK_DET_EN);
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| 219 | airoha_phy_pma0_update_field(pcie_phy,
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| 220 | REG_PCIE_PMA_SS_RX_FREQ_DET4,
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| 221 | PCIE_FREQLOCK_DET_EN, 0x3);
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| 222 |
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| 223 | usleep_range(10000, 15000);
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| 224 |
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| 225 | val = readl(pcie_phy->pma0 + REG_PCIE_PMA_RO_RX_FREQDET);
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| 226 | if (val & PCIE_RO_FBCK_LOCK)
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| 227 | break;
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| 228 | }
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| 229 |
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| 230 |
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| 231 | airoha_phy_csr_2l_clear_bits(pcie_phy, REG_CSR_2L_CDR0_PR_INJ_MODE,
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| 232 | CSR_2L_PXP_CDR0_INJ_FORCE_OFF);
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| 233 |
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| 234 | airoha_phy_pma0_clear_bits(pcie_phy,
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| 235 | REG_PCIE_PMA_FORCE_DA_PXP_CDR_PR_LPF_C,
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| 236 | PCIE_FORCE_SEL_DA_PXP_CDR_PR_LPF_R_EN);
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| 237 | airoha_phy_pma0_clear_bits(pcie_phy,
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| 238 | REG_PCIE_PMA_FORCE_DA_PXP_CDR_PR_LPF_C,
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| 239 | PCIE_FORCE_SEL_DA_PXP_CDR_PR_LPF_C_EN);
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| 240 | airoha_phy_pma0_clear_bits(pcie_phy,
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| 241 | REG_PCIE_PMA_FORCE_DA_PXP_CDR_PR_PIEYE_PWDB,
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| 242 | PCIE_FORCE_SEL_DA_PXP_CDR_PR_PWDB);
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| 243 | airoha_phy_pma0_clear_bits(pcie_phy,
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| 244 | REG_PCIE_PMA_FORCE_DA_PXP_CDR_PR_IDAC,
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| 245 | PCIE_FORCE_SEL_DA_PXP_CDR_PR_IDAC);
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| 246 | if (gen == PCIE_PORT_GEN3) {
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| 247 | airoha_phy_pma0_update_field(pcie_phy,
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| 248 | REG_PCIE_PMA_DIG_RESERVE_14,
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| 249 | PCIE_FLL_IDAC_PCIEG3,
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| 250 | cdr_pr_idac_tmp);
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| 251 | } else {
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| 252 | airoha_phy_pma0_update_field(pcie_phy,
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| 253 | REG_PCIE_PMA_DIG_RESERVE_13,
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| 254 | PCIE_FLL_IDAC_PCIEG1,
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| 255 | cdr_pr_idac_tmp);
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| 256 | airoha_phy_pma0_update_field(pcie_phy,
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| 257 | REG_PCIE_PMA_DIG_RESERVE_13,
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| 258 | PCIE_FLL_IDAC_PCIEG2,
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| 259 | cdr_pr_idac_tmp);
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| 260 | }
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| 261 | }
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| 262 |
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| 263 | static void
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| 264 | airoha_phy_init_lane1_rx_fw_pre_calib(struct airoha_pcie_phy *pcie_phy,
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| 265 | enum airoha_pcie_port_gen gen)
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| 266 | {
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| 267 | u32 fl_out_target = gen == PCIE_PORT_GEN3 ? 41600 : 41941;
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| 268 | u32 lock_cyclecnt = gen == PCIE_PORT_GEN3 ? 26000 : 32767;
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| 269 | u32 pr_idac, val, cdr_pr_idac_tmp = 0;
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| 270 | int i;
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| 271 |
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| 272 | airoha_phy_pma1_set_bits(pcie_phy,
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| 273 | REG_PCIE_PMA_SS_LCPLL_PWCTL_SETTING_1,
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| 274 | PCIE_LCPLL_MAN_PWDB);
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| 275 | airoha_phy_pma1_update_field(pcie_phy, REG_PCIE_PMA_SS_RX_FREQ_DET2,
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| 276 | PCIE_LOCK_TARGET_BEG,
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| 277 | fl_out_target - 100);
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| 278 | airoha_phy_pma1_update_field(pcie_phy, REG_PCIE_PMA_SS_RX_FREQ_DET2,
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| 279 | PCIE_LOCK_TARGET_END,
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| 280 | fl_out_target + 100);
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| 281 | airoha_phy_pma1_update_field(pcie_phy, REG_PCIE_PMA_SS_RX_FREQ_DET1,
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| 282 | PCIE_PLL_FT_LOCK_CYCLECNT, lock_cyclecnt);
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| 283 | airoha_phy_pma1_update_field(pcie_phy, REG_PCIE_PMA_SS_RX_FREQ_DET4,
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| 284 | PCIE_LOCK_LOCKTH, 0x3);
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| 285 | airoha_phy_pma1_update_field(pcie_phy, REG_PCIE_PMA_SS_RX_FREQ_DET3,
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| 286 | PCIE_UNLOCK_TARGET_BEG,
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| 287 | fl_out_target - 100);
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| 288 | airoha_phy_pma1_update_field(pcie_phy, REG_PCIE_PMA_SS_RX_FREQ_DET3,
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| 289 | PCIE_UNLOCK_TARGET_END,
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| 290 | fl_out_target + 100);
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| 291 | airoha_phy_pma1_update_field(pcie_phy, REG_PCIE_PMA_SS_RX_FREQ_DET1,
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| 292 | PCIE_PLL_FT_UNLOCK_CYCLECNT,
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| 293 | lock_cyclecnt);
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| 294 | airoha_phy_pma1_update_field(pcie_phy, REG_PCIE_PMA_SS_RX_FREQ_DET4,
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| 295 | PCIE_UNLOCK_LOCKTH, 0x3);
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| 296 |
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| 297 | airoha_phy_csr_2l_set_bits(pcie_phy, REG_CSR_2L_CDR1_PR_INJ_MODE,
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| 298 | CSR_2L_PXP_CDR1_INJ_FORCE_OFF);
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| 299 |
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| 300 | airoha_phy_pma1_set_bits(pcie_phy,
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| 301 | REG_PCIE_PMA_FORCE_DA_PXP_CDR_PR_LPF_C,
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| 302 | PCIE_FORCE_SEL_DA_PXP_CDR_PR_LPF_R_EN);
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| 303 | airoha_phy_pma1_set_bits(pcie_phy,
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| 304 | REG_PCIE_PMA_FORCE_DA_PXP_CDR_PR_LPF_C,
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| 305 | PCIE_FORCE_DA_PXP_CDR_PR_LPF_R_EN);
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| 306 | airoha_phy_pma1_set_bits(pcie_phy,
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| 307 | REG_PCIE_PMA_FORCE_DA_PXP_CDR_PR_LPF_C,
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| 308 | PCIE_FORCE_SEL_DA_PXP_CDR_PR_LPF_C_EN);
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| 309 | airoha_phy_pma1_clear_bits(pcie_phy,
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| 310 | REG_PCIE_PMA_FORCE_DA_PXP_CDR_PR_LPF_C,
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| 311 | PCIE_FORCE_DA_PXP_CDR_PR_LPF_C_EN);
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| 312 | airoha_phy_pma1_set_bits(pcie_phy,
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| 313 | REG_PCIE_PMA_FORCE_DA_PXP_CDR_PR_IDAC,
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| 314 | PCIE_FORCE_SEL_DA_PXP_CDR_PR_IDAC);
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| 315 | airoha_phy_pma1_set_bits(pcie_phy,
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| 316 | REG_PCIE_PMA_FORCE_DA_PXP_CDR_PR_PIEYE_PWDB,
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| 317 | PCIE_FORCE_SEL_DA_PXP_CDR_PR_PWDB);
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| 318 | airoha_phy_pma1_clear_bits(pcie_phy,
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| 319 | REG_PCIE_PMA_FORCE_DA_PXP_CDR_PR_PIEYE_PWDB,
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| 320 | PCIE_FORCE_DA_PXP_CDR_PR_PWDB);
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| 321 | airoha_phy_pma1_set_bits(pcie_phy,
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| 322 | REG_PCIE_PMA_FORCE_DA_PXP_CDR_PR_PIEYE_PWDB,
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| 323 | PCIE_FORCE_DA_PXP_CDR_PR_PWDB);
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| 324 |
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| 325 | for (i = 0; i < LEQ_LEN_CTRL_MAX_VAL; i++) {
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| 326 | airoha_phy_pma1_update_field(pcie_phy,
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| 327 | REG_PCIE_PMA_FORCE_DA_PXP_CDR_PR_IDAC,
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| 328 | PCIE_FORCE_DA_PXP_CDR_PR_IDAC, i << 8);
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| 329 | airoha_phy_pma1_clear_bits(pcie_phy,
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| 330 | REG_PCIE_PMA_SS_RX_FREQ_DET4,
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| 331 | PCIE_FREQLOCK_DET_EN);
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| 332 | airoha_phy_pma1_update_field(pcie_phy,
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| 333 | REG_PCIE_PMA_SS_RX_FREQ_DET4,
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| 334 | PCIE_FREQLOCK_DET_EN, 0x3);
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| 335 |
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| 336 | usleep_range(10000, 15000);
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| 337 |
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| 338 | val = FIELD_GET(PCIE_RO_FL_OUT,
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| 339 | readl(pcie_phy->pma1 +
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| 340 | REG_PCIE_PMA_RO_RX_FREQDET));
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| 341 | if (val > fl_out_target)
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| 342 | cdr_pr_idac_tmp = i << 8;
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| 343 | }
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| 344 |
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| 345 | for (i = LEQ_LEN_CTRL_MAX_VAL; i >= 0; i--) {
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| 346 | pr_idac = cdr_pr_idac_tmp | (0x1 << i);
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| 347 | airoha_phy_pma1_update_field(pcie_phy,
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| 348 | REG_PCIE_PMA_FORCE_DA_PXP_CDR_PR_IDAC,
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| 349 | PCIE_FORCE_DA_PXP_CDR_PR_IDAC, pr_idac);
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| 350 | airoha_phy_pma1_clear_bits(pcie_phy,
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| 351 | REG_PCIE_PMA_SS_RX_FREQ_DET4,
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| 352 | PCIE_FREQLOCK_DET_EN);
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| 353 | airoha_phy_pma1_update_field(pcie_phy,
|
| 354 | REG_PCIE_PMA_SS_RX_FREQ_DET4,
|
| 355 | PCIE_FREQLOCK_DET_EN, 0x3);
|
| 356 |
|
| 357 | usleep_range(10000, 15000);
|
| 358 |
|
| 359 | val = FIELD_GET(PCIE_RO_FL_OUT,
|
| 360 | readl(pcie_phy->pma1 +
|
| 361 | REG_PCIE_PMA_RO_RX_FREQDET));
|
| 362 | if (val < fl_out_target)
|
| 363 | pr_idac &= ~(0x1 << i);
|
| 364 |
|
| 365 | cdr_pr_idac_tmp = pr_idac;
|
| 366 | }
|
| 367 |
|
| 368 | airoha_phy_pma1_update_field(pcie_phy,
|
| 369 | REG_PCIE_PMA_FORCE_DA_PXP_CDR_PR_IDAC,
|
| 370 | PCIE_FORCE_DA_PXP_CDR_PR_IDAC,
|
| 371 | cdr_pr_idac_tmp);
|
| 372 |
|
| 373 | for (i = 0; i < FREQ_LOCK_MAX_ATTEMPT; i++) {
|
| 374 | u32 val;
|
| 375 |
|
| 376 | airoha_phy_pma1_clear_bits(pcie_phy,
|
| 377 | REG_PCIE_PMA_SS_RX_FREQ_DET4,
|
| 378 | PCIE_FREQLOCK_DET_EN);
|
| 379 | airoha_phy_pma1_update_field(pcie_phy,
|
| 380 | REG_PCIE_PMA_SS_RX_FREQ_DET4,
|
| 381 | PCIE_FREQLOCK_DET_EN, 0x3);
|
| 382 |
|
| 383 | usleep_range(10000, 15000);
|
| 384 |
|
| 385 | val = readl(pcie_phy->pma1 + REG_PCIE_PMA_RO_RX_FREQDET);
|
| 386 | if (val & PCIE_RO_FBCK_LOCK)
|
| 387 | break;
|
| 388 | }
|
| 389 |
|
| 390 |
|
| 391 | airoha_phy_csr_2l_clear_bits(pcie_phy, REG_CSR_2L_CDR1_PR_INJ_MODE,
|
| 392 | CSR_2L_PXP_CDR1_INJ_FORCE_OFF);
|
| 393 |
|
| 394 | airoha_phy_pma1_clear_bits(pcie_phy,
|
| 395 | REG_PCIE_PMA_FORCE_DA_PXP_CDR_PR_LPF_C,
|
| 396 | PCIE_FORCE_SEL_DA_PXP_CDR_PR_LPF_R_EN);
|
| 397 | airoha_phy_pma1_clear_bits(pcie_phy,
|
| 398 | REG_PCIE_PMA_FORCE_DA_PXP_CDR_PR_LPF_C,
|
| 399 | PCIE_FORCE_SEL_DA_PXP_CDR_PR_LPF_C_EN);
|
| 400 | airoha_phy_pma1_clear_bits(pcie_phy,
|
| 401 | REG_PCIE_PMA_FORCE_DA_PXP_CDR_PR_PIEYE_PWDB,
|
| 402 | PCIE_FORCE_SEL_DA_PXP_CDR_PR_PWDB);
|
| 403 | airoha_phy_pma1_clear_bits(pcie_phy,
|
| 404 | REG_PCIE_PMA_FORCE_DA_PXP_CDR_PR_IDAC,
|
| 405 | PCIE_FORCE_SEL_DA_PXP_CDR_PR_IDAC);
|
| 406 | if (gen == PCIE_PORT_GEN3) {
|
| 407 | airoha_phy_pma1_update_field(pcie_phy,
|
| 408 | REG_PCIE_PMA_DIG_RESERVE_14,
|
| 409 | PCIE_FLL_IDAC_PCIEG3,
|
| 410 | cdr_pr_idac_tmp);
|
| 411 | } else {
|
| 412 | airoha_phy_pma1_update_field(pcie_phy,
|
| 413 | REG_PCIE_PMA_DIG_RESERVE_13,
|
| 414 | PCIE_FLL_IDAC_PCIEG1,
|
| 415 | cdr_pr_idac_tmp);
|
| 416 | airoha_phy_pma1_update_field(pcie_phy,
|
| 417 | REG_PCIE_PMA_DIG_RESERVE_13,
|
| 418 | PCIE_FLL_IDAC_PCIEG2,
|
| 419 | cdr_pr_idac_tmp);
|
| 420 | }
|
| 421 | }
|
| 422 |
|
| 423 | static void airoha_pcie_phy_init_default(struct airoha_pcie_phy *pcie_phy)
|
| 424 | {
|
| 425 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_CMN,
|
| 426 | CSR_2L_PXP_CMN_TRIM_MASK, 0x10);
|
| 427 | writel(0xcccbcccb, pcie_phy->pma0 + REG_PCIE_PMA_DIG_RESERVE_21);
|
| 428 | writel(0xcccb, pcie_phy->pma0 + REG_PCIE_PMA_DIG_RESERVE_22);
|
| 429 | writel(0xcccbcccb, pcie_phy->pma1 + REG_PCIE_PMA_DIG_RESERVE_21);
|
| 430 | writel(0xcccb, pcie_phy->pma1 + REG_PCIE_PMA_DIG_RESERVE_22);
|
| 431 | airoha_phy_csr_2l_set_bits(pcie_phy, REG_CSR_2L_CMN,
|
| 432 | CSR_2L_PXP_CMN_LANE_EN);
|
| 433 | }
|
| 434 |
|
| 435 | static void airoha_pcie_phy_init_clk_out(struct airoha_pcie_phy *pcie_phy)
|
| 436 | {
|
| 437 | airoha_phy_csr_2l_update_field(pcie_phy,
|
| 438 | REG_CSR_2L_TXPLL_POSTDIV_D256,
|
| 439 | CSR_2L_PXP_CLKTX0_AMP, 0x5);
|
| 440 | airoha_phy_csr_2l_update_field(pcie_phy,
|
| 441 | REG_CSR_2L_CLKTX0_FORCE_OUT1,
|
| 442 | CSR_2L_PXP_CLKTX1_AMP, 0x5);
|
| 443 | airoha_phy_csr_2l_update_field(pcie_phy,
|
| 444 | REG_CSR_2L_TXPLL_POSTDIV_D256,
|
| 445 | CSR_2L_PXP_CLKTX0_OFFSET, 0x2);
|
| 446 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_CLKTX1_OFFSET,
|
| 447 | CSR_2L_PXP_CLKTX1_OFFSET, 0x2);
|
| 448 | airoha_phy_csr_2l_clear_bits(pcie_phy, REG_CSR_2L_CLKTX0_FORCE_OUT1,
|
| 449 | CSR_2L_PXP_CLKTX0_HZ);
|
| 450 | airoha_phy_csr_2l_clear_bits(pcie_phy, REG_CSR_2L_CLKTX1_OFFSET,
|
| 451 | CSR_2L_PXP_CLKTX1_HZ);
|
| 452 | airoha_phy_csr_2l_update_field(pcie_phy,
|
| 453 | REG_CSR_2L_CLKTX0_FORCE_OUT1,
|
| 454 | CSR_2L_PXP_CLKTX0_IMP_SEL, 0x12);
|
| 455 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_CLKTX1_IMP_SEL,
|
| 456 | CSR_2L_PXP_CLKTX1_IMP_SEL, 0x12);
|
| 457 | airoha_phy_csr_2l_clear_bits(pcie_phy, REG_CSR_2L_TXPLL_POSTDIV_D256,
|
| 458 | CSR_2L_PXP_CLKTX0_SR);
|
| 459 | airoha_phy_csr_2l_clear_bits(pcie_phy, REG_CSR_2L_CLKTX1_OFFSET,
|
| 460 | CSR_2L_PXP_CLKTX1_SR);
|
| 461 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_PLL_CMN_RESERVE0,
|
| 462 | CSR_2L_PXP_PLL_RESERVE_MASK, 0xd0d);
|
| 463 | }
|
| 464 |
|
| 465 | static void airoha_pcie_phy_init_csr_2l(struct airoha_pcie_phy *pcie_phy)
|
| 466 | {
|
| 467 | airoha_phy_pma0_set_bits(pcie_phy, REG_PCIE_PMA_SW_RESET,
|
| 468 | PCIE_SW_XFI_RXPCS_RST | PCIE_SW_REF_RST |
|
| 469 | PCIE_SW_RX_RST);
|
| 470 | airoha_phy_pma1_set_bits(pcie_phy, REG_PCIE_PMA_SW_RESET,
|
| 471 | PCIE_SW_XFI_RXPCS_RST | PCIE_SW_REF_RST |
|
| 472 | PCIE_SW_RX_RST);
|
| 473 | airoha_phy_pma0_set_bits(pcie_phy, REG_PCIE_PMA_TX_RESET,
|
| 474 | PCIE_TX_TOP_RST | PCIE_TX_CAL_RST);
|
| 475 | airoha_phy_pma1_set_bits(pcie_phy, REG_PCIE_PMA_TX_RESET,
|
| 476 | PCIE_TX_TOP_RST | PCIE_TX_CAL_RST);
|
| 477 | }
|
| 478 |
|
| 479 | static void airoha_pcie_phy_init_rx(struct airoha_pcie_phy *pcie_phy)
|
| 480 | {
|
| 481 | writel(0x2a00090b, pcie_phy->pma0 + REG_PCIE_PMA_DIG_RESERVE_17);
|
| 482 | writel(0x2a00090b, pcie_phy->pma1 + REG_PCIE_PMA_DIG_RESERVE_17);
|
| 483 | airoha_phy_csr_2l_set_bits(pcie_phy, REG_CSR_2L_CDR0_PR_MONPI,
|
| 484 | CSR_2L_PXP_CDR0_PR_XFICK_EN);
|
| 485 | airoha_phy_csr_2l_set_bits(pcie_phy, REG_CSR_2L_CDR1_PR_MONPI,
|
| 486 | CSR_2L_PXP_CDR1_PR_XFICK_EN);
|
| 487 | airoha_phy_csr_2l_clear_bits(pcie_phy,
|
| 488 | REG_CSR_2L_CDR0_PD_PICAL_CKD8_INV,
|
| 489 | CSR_2L_PXP_CDR0_PD_EDGE_DISABLE);
|
| 490 | airoha_phy_csr_2l_clear_bits(pcie_phy,
|
| 491 | REG_CSR_2L_CDR1_PD_PICAL_CKD8_INV,
|
| 492 | CSR_2L_PXP_CDR1_PD_EDGE_DISABLE);
|
| 493 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_RX0_PHYCK_DIV,
|
| 494 | CSR_2L_PXP_RX0_PHYCK_SEL, 0x1);
|
| 495 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_RX1_PHYCK_DIV,
|
| 496 | CSR_2L_PXP_RX1_PHYCK_SEL, 0x1);
|
| 497 | }
|
| 498 |
|
| 499 | static void airoha_pcie_phy_init_jcpll(struct airoha_pcie_phy *pcie_phy)
|
| 500 | {
|
| 501 | airoha_phy_pma0_set_bits(pcie_phy, REG_PCIE_PMA_FORCE_PXP_JCPLL_CKOUT,
|
| 502 | PCIE_FORCE_SEL_DA_PXP_JCPLL_EN);
|
| 503 | airoha_phy_pma0_clear_bits(pcie_phy,
|
| 504 | REG_PCIE_PMA_FORCE_PXP_JCPLL_CKOUT,
|
| 505 | PCIE_FORCE_DA_PXP_JCPLL_EN);
|
| 506 | airoha_phy_pma1_set_bits(pcie_phy, REG_PCIE_PMA_FORCE_PXP_JCPLL_CKOUT,
|
| 507 | PCIE_FORCE_SEL_DA_PXP_JCPLL_EN);
|
| 508 | airoha_phy_pma1_clear_bits(pcie_phy,
|
| 509 | REG_PCIE_PMA_FORCE_PXP_JCPLL_CKOUT,
|
| 510 | PCIE_FORCE_DA_PXP_JCPLL_EN);
|
| 511 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_JCPLL_TCL_VTP_EN,
|
| 512 | CSR_2L_PXP_JCPLL_SPARE_LOW, 0x20);
|
| 513 | airoha_phy_csr_2l_set_bits(pcie_phy, REG_CSR_2L_JCPLL_RST_DLY,
|
| 514 | CSR_2L_PXP_JCPLL_RST);
|
| 515 | writel(0x0, pcie_phy->csr_2l + REG_CSR_2L_JCPLL_SSC_DELTA1);
|
| 516 | airoha_phy_csr_2l_clear_bits(pcie_phy, REG_CSR_2L_JCPLL_SSC_PERIOD,
|
| 517 | CSR_2L_PXP_JCPLL_SSC_PERIOD);
|
| 518 | airoha_phy_csr_2l_clear_bits(pcie_phy, REG_CSR_2L_JCPLL_SSC,
|
| 519 | CSR_2L_PXP_JCPLL_SSC_PHASE_INI);
|
| 520 | airoha_phy_csr_2l_clear_bits(pcie_phy, REG_CSR_2L_JCPLL_SSC,
|
| 521 | CSR_2L_PXP_JCPLL_SSC_TRI_EN);
|
| 522 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_JCPLL_LPF_BR,
|
| 523 | CSR_2L_PXP_JCPLL_LPF_BR, 0xa);
|
| 524 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_JCPLL_LPF_BR,
|
| 525 | CSR_2L_PXP_JCPLL_LPF_BP, 0xc);
|
| 526 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_JCPLL_LPF_BR,
|
| 527 | CSR_2L_PXP_JCPLL_LPF_BC, 0x1f);
|
| 528 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_JCPLL_LPF_BWC,
|
| 529 | CSR_2L_PXP_JCPLL_LPF_BWC, 0x1e);
|
| 530 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_JCPLL_LPF_BR,
|
| 531 | CSR_2L_PXP_JCPLL_LPF_BWR, 0xa);
|
| 532 | airoha_phy_csr_2l_update_field(pcie_phy,
|
| 533 | REG_CSR_2L_JCPLL_MMD_PREDIV_MODE,
|
| 534 | CSR_2L_PXP_JCPLL_MMD_PREDIV_MODE,
|
| 535 | 0x1);
|
| 536 | airoha_phy_csr_2l_clear_bits(pcie_phy, CSR_2L_PXP_JCPLL_MONCK,
|
| 537 | CSR_2L_PXP_JCPLL_REFIN_DIV);
|
| 538 |
|
| 539 | airoha_phy_pma0_set_bits(pcie_phy, REG_PCIE_PMA_FORCE_DA_PXP_RX_FE_VOS,
|
| 540 | PCIE_FORCE_SEL_DA_PXP_JCPLL_SDM_PCW);
|
| 541 | airoha_phy_pma1_set_bits(pcie_phy, REG_PCIE_PMA_FORCE_DA_PXP_RX_FE_VOS,
|
| 542 | PCIE_FORCE_SEL_DA_PXP_JCPLL_SDM_PCW);
|
| 543 | airoha_phy_pma0_update_field(pcie_phy,
|
| 544 | REG_PCIE_PMA_FORCE_DA_PXP_JCPLL_SDM_PCW,
|
| 545 | PCIE_FORCE_DA_PXP_JCPLL_SDM_PCW,
|
| 546 | 0x50000000);
|
| 547 | airoha_phy_pma1_update_field(pcie_phy,
|
| 548 | REG_PCIE_PMA_FORCE_DA_PXP_JCPLL_SDM_PCW,
|
| 549 | PCIE_FORCE_DA_PXP_JCPLL_SDM_PCW,
|
| 550 | 0x50000000);
|
| 551 |
|
| 552 | airoha_phy_csr_2l_set_bits(pcie_phy,
|
| 553 | REG_CSR_2L_JCPLL_MMD_PREDIV_MODE,
|
| 554 | CSR_2L_PXP_JCPLL_POSTDIV_D5);
|
| 555 | airoha_phy_csr_2l_set_bits(pcie_phy,
|
| 556 | REG_CSR_2L_JCPLL_MMD_PREDIV_MODE,
|
| 557 | CSR_2L_PXP_JCPLL_POSTDIV_D2);
|
| 558 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_JCPLL_RST_DLY,
|
| 559 | CSR_2L_PXP_JCPLL_RST_DLY, 0x4);
|
| 560 | airoha_phy_csr_2l_clear_bits(pcie_phy, REG_CSR_2L_JCPLL_RST_DLY,
|
| 561 | CSR_2L_PXP_JCPLL_SDM_DI_LS);
|
| 562 | airoha_phy_csr_2l_clear_bits(pcie_phy, REG_CSR_2L_JCPLL_TCL_KBAND_VREF,
|
| 563 | CSR_2L_PXP_JCPLL_VCO_KBAND_MEAS_EN);
|
| 564 | airoha_phy_csr_2l_clear_bits(pcie_phy, REG_CSR_2L_JCPLL_IB_EXT,
|
| 565 | CSR_2L_PXP_JCPLL_CHP_IOFST);
|
| 566 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_JCPLL_IB_EXT,
|
| 567 | CSR_2L_PXP_JCPLL_CHP_IBIAS, 0xc);
|
| 568 | airoha_phy_csr_2l_update_field(pcie_phy,
|
| 569 | REG_CSR_2L_JCPLL_MMD_PREDIV_MODE,
|
| 570 | CSR_2L_PXP_JCPLL_MMD_PREDIV_MODE,
|
| 571 | 0x1);
|
| 572 | airoha_phy_csr_2l_set_bits(pcie_phy, REG_CSR_2L_JCPLL_VCODIV,
|
| 573 | CSR_2L_PXP_JCPLL_VCO_HALFLSB_EN);
|
| 574 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_JCPLL_VCODIV,
|
| 575 | CSR_2L_PXP_JCPLL_VCO_CFIX, 0x1);
|
| 576 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_JCPLL_VCODIV,
|
| 577 | CSR_2L_PXP_JCPLL_VCO_SCAPWR, 0x4);
|
| 578 | airoha_phy_csr_2l_clear_bits(pcie_phy, REG_CSR_2L_JCPLL_IB_EXT,
|
| 579 | REG_CSR_2L_JCPLL_LPF_SHCK_EN);
|
| 580 | airoha_phy_csr_2l_set_bits(pcie_phy, REG_CSR_2L_JCPLL_KBAND_KFC,
|
| 581 | CSR_2L_PXP_JCPLL_POSTDIV_EN);
|
| 582 | airoha_phy_csr_2l_clear_bits(pcie_phy, REG_CSR_2L_JCPLL_KBAND_KFC,
|
| 583 | CSR_2L_PXP_JCPLL_KBAND_KFC);
|
| 584 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_JCPLL_KBAND_KFC,
|
| 585 | CSR_2L_PXP_JCPLL_KBAND_KF, 0x3);
|
| 586 | airoha_phy_csr_2l_clear_bits(pcie_phy, REG_CSR_2L_JCPLL_KBAND_KFC,
|
| 587 | CSR_2L_PXP_JCPLL_KBAND_KS);
|
| 588 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_JCPLL_LPF_BWC,
|
| 589 | CSR_2L_PXP_JCPLL_KBAND_DIV, 0x1);
|
| 590 |
|
| 591 | airoha_phy_pma0_set_bits(pcie_phy, REG_PCIE_PMA_SCAN_MODE,
|
| 592 | PCIE_FORCE_SEL_DA_PXP_JCPLL_KBAND_LOAD_EN);
|
| 593 | airoha_phy_pma0_clear_bits(pcie_phy, REG_PCIE_PMA_SCAN_MODE,
|
| 594 | PCIE_FORCE_DA_PXP_JCPLL_KBAND_LOAD_EN);
|
| 595 |
|
| 596 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_JCPLL_LPF_BWC,
|
| 597 | CSR_2L_PXP_JCPLL_KBAND_CODE, 0xe4);
|
| 598 | airoha_phy_csr_2l_set_bits(pcie_phy, REG_CSR_2L_JCPLL_SDM_HREN,
|
| 599 | CSR_2L_PXP_JCPLL_TCL_AMP_EN);
|
| 600 | airoha_phy_csr_2l_set_bits(pcie_phy, REG_CSR_2L_JCPLL_TCL_CMP,
|
| 601 | CSR_2L_PXP_JCPLL_TCL_LPF_EN);
|
| 602 | airoha_phy_csr_2l_update_field(pcie_phy,
|
| 603 | REG_CSR_2L_JCPLL_TCL_KBAND_VREF,
|
| 604 | CSR_2L_PXP_JCPLL_TCL_KBAND_VREF, 0xf);
|
| 605 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_JCPLL_SDM_HREN,
|
| 606 | CSR_2L_PXP_JCPLL_TCL_AMP_GAIN, 0x1);
|
| 607 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_JCPLL_SDM_HREN,
|
| 608 | CSR_2L_PXP_JCPLL_TCL_AMP_VREF, 0x5);
|
| 609 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_JCPLL_TCL_CMP,
|
| 610 | CSR_2L_PXP_JCPLL_TCL_LPF_BW, 0x1);
|
| 611 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_JCPLL_VCO_TCLVAR,
|
| 612 | CSR_2L_PXP_JCPLL_VCO_TCLVAR, 0x3);
|
| 613 |
|
| 614 | airoha_phy_pma0_set_bits(pcie_phy, REG_PCIE_PMA_FORCE_PXP_JCPLL_CKOUT,
|
| 615 | PCIE_FORCE_SEL_DA_PXP_JCPLL_CKOUT_EN);
|
| 616 | airoha_phy_pma0_set_bits(pcie_phy, REG_PCIE_PMA_FORCE_PXP_JCPLL_CKOUT,
|
| 617 | PCIE_FORCE_DA_PXP_JCPLL_CKOUT_EN);
|
| 618 | airoha_phy_pma1_set_bits(pcie_phy, REG_PCIE_PMA_FORCE_PXP_JCPLL_CKOUT,
|
| 619 | PCIE_FORCE_SEL_DA_PXP_JCPLL_CKOUT_EN);
|
| 620 | airoha_phy_pma1_set_bits(pcie_phy, REG_PCIE_PMA_FORCE_PXP_JCPLL_CKOUT,
|
| 621 | PCIE_FORCE_DA_PXP_JCPLL_CKOUT_EN);
|
| 622 | airoha_phy_pma0_set_bits(pcie_phy, REG_PCIE_PMA_FORCE_PXP_JCPLL_CKOUT,
|
| 623 | PCIE_FORCE_SEL_DA_PXP_JCPLL_EN);
|
| 624 | airoha_phy_pma0_set_bits(pcie_phy, REG_PCIE_PMA_FORCE_PXP_JCPLL_CKOUT,
|
| 625 | PCIE_FORCE_DA_PXP_JCPLL_EN);
|
| 626 | airoha_phy_pma1_set_bits(pcie_phy, REG_PCIE_PMA_FORCE_PXP_JCPLL_CKOUT,
|
| 627 | PCIE_FORCE_SEL_DA_PXP_JCPLL_EN);
|
| 628 | airoha_phy_pma1_set_bits(pcie_phy, REG_PCIE_PMA_FORCE_PXP_JCPLL_CKOUT,
|
| 629 | PCIE_FORCE_DA_PXP_JCPLL_EN);
|
| 630 | }
|
| 631 |
|
| 632 | static void airoha_pcie_phy_txpll(struct airoha_pcie_phy *pcie_phy)
|
| 633 | {
|
| 634 | airoha_phy_pma0_set_bits(pcie_phy,
|
| 635 | REG_PCIE_PMA_FORCE_DA_PXP_TXPLL_CKOUT,
|
| 636 | PCIE_FORCE_SEL_DA_PXP_TXPLL_EN);
|
| 637 | airoha_phy_pma0_clear_bits(pcie_phy,
|
| 638 | REG_PCIE_PMA_FORCE_DA_PXP_TXPLL_CKOUT,
|
| 639 | PCIE_FORCE_DA_PXP_TXPLL_EN);
|
| 640 | airoha_phy_pma1_set_bits(pcie_phy,
|
| 641 | REG_PCIE_PMA_FORCE_DA_PXP_TXPLL_CKOUT,
|
| 642 | PCIE_FORCE_SEL_DA_PXP_TXPLL_EN);
|
| 643 | airoha_phy_pma1_clear_bits(pcie_phy,
|
| 644 | REG_PCIE_PMA_FORCE_DA_PXP_TXPLL_CKOUT,
|
| 645 | PCIE_FORCE_DA_PXP_TXPLL_EN);
|
| 646 |
|
| 647 | airoha_phy_csr_2l_set_bits(pcie_phy, REG_CSR_2L_TXPLL_REFIN_DIV,
|
| 648 | CSR_2L_PXP_TXPLL_PLL_RSTB);
|
| 649 | writel(0x0, pcie_phy->csr_2l + REG_CSR_2L_TXPLL_SSC_DELTA1);
|
| 650 | airoha_phy_csr_2l_clear_bits(pcie_phy, REG_CSR_2L_TXPLL_SSC_PERIOD,
|
| 651 | CSR_2L_PXP_txpll_SSC_PERIOD);
|
| 652 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_TXPLL_CHP_IOFST,
|
| 653 | CSR_2L_PXP_TXPLL_CHP_IOFST, 0x1);
|
| 654 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_750M_SYS_CK,
|
| 655 | CSR_2L_PXP_TXPLL_CHP_IBIAS, 0x2d);
|
| 656 | airoha_phy_csr_2l_clear_bits(pcie_phy, REG_CSR_2L_TXPLL_REFIN_DIV,
|
| 657 | CSR_2L_PXP_TXPLL_REFIN_DIV);
|
| 658 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_TXPLL_TCL_LPF_BW,
|
| 659 | CSR_2L_PXP_TXPLL_VCO_CFIX, 0x3);
|
| 660 |
|
| 661 | airoha_phy_pma0_set_bits(pcie_phy, REG_PCIE_PMA_FORCE_DA_PXP_CDR_PR_IDAC,
|
| 662 | PCIE_FORCE_SEL_DA_PXP_TXPLL_SDM_PCW);
|
| 663 | airoha_phy_pma1_set_bits(pcie_phy, REG_PCIE_PMA_FORCE_DA_PXP_CDR_PR_IDAC,
|
| 664 | PCIE_FORCE_SEL_DA_PXP_TXPLL_SDM_PCW);
|
| 665 | airoha_phy_pma0_update_field(pcie_phy,
|
| 666 | REG_PCIE_PMA_FORCE_DA_PXP_TXPLL_SDM_PCW,
|
| 667 | PCIE_FORCE_DA_PXP_TXPLL_SDM_PCW,
|
| 668 | 0xc800000);
|
| 669 | airoha_phy_pma1_update_field(pcie_phy,
|
| 670 | REG_PCIE_PMA_FORCE_DA_PXP_TXPLL_SDM_PCW,
|
| 671 | PCIE_FORCE_DA_PXP_TXPLL_SDM_PCW,
|
| 672 | 0xc800000);
|
| 673 |
|
| 674 | airoha_phy_csr_2l_clear_bits(pcie_phy, REG_CSR_2L_TXPLL_SDM_DI_LS,
|
| 675 | CSR_2L_PXP_TXPLL_SDM_IFM);
|
| 676 | airoha_phy_csr_2l_clear_bits(pcie_phy, REG_CSR_2L_TXPLL_SSC,
|
| 677 | CSR_2L_PXP_TXPLL_SSC_PHASE_INI);
|
| 678 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_TXPLL_REFIN_DIV,
|
| 679 | CSR_2L_PXP_TXPLL_RST_DLY, 0x4);
|
| 680 | airoha_phy_csr_2l_clear_bits(pcie_phy, REG_CSR_2L_TXPLL_SDM_DI_LS,
|
| 681 | CSR_2L_PXP_TXPLL_SDM_DI_LS);
|
| 682 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_TXPLL_SDM_DI_LS,
|
| 683 | CSR_2L_PXP_TXPLL_SDM_ORD, 0x3);
|
| 684 | airoha_phy_csr_2l_clear_bits(pcie_phy, REG_CSR_2L_TXPLL_TCL_KBAND_VREF,
|
| 685 | CSR_2L_PXP_TXPLL_VCO_KBAND_MEAS_EN);
|
| 686 | writel(0x0, pcie_phy->csr_2l + REG_CSR_2L_TXPLL_SSC_DELTA1);
|
| 687 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_TXPLL_CHP_IOFST,
|
| 688 | CSR_2L_PXP_TXPLL_LPF_BP, 0x1);
|
| 689 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_TXPLL_CHP_IOFST,
|
| 690 | CSR_2L_PXP_TXPLL_LPF_BC, 0x18);
|
| 691 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_TXPLL_CHP_IOFST,
|
| 692 | CSR_2L_PXP_TXPLL_LPF_BR, 0x5);
|
| 693 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_TXPLL_CHP_IOFST,
|
| 694 | CSR_2L_PXP_TXPLL_CHP_IOFST, 0x1);
|
| 695 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_750M_SYS_CK,
|
| 696 | CSR_2L_PXP_TXPLL_CHP_IBIAS, 0x2d);
|
| 697 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_TXPLL_TCL_VTP,
|
| 698 | CSR_2L_PXP_TXPLL_SPARE_L, 0x1);
|
| 699 | airoha_phy_csr_2l_clear_bits(pcie_phy, REG_CSR_2L_TXPLL_LPF_BWR,
|
| 700 | CSR_2L_PXP_TXPLL_LPF_BWC);
|
| 701 | airoha_phy_csr_2l_clear_bits(pcie_phy, REG_CSR_2L_TXPLL_POSTDIV,
|
| 702 | CSR_2L_PXP_TXPLL_MMD_PREDIV_MODE);
|
| 703 | airoha_phy_csr_2l_clear_bits(pcie_phy, REG_CSR_2L_TXPLL_REFIN_DIV,
|
| 704 | CSR_2L_PXP_TXPLL_REFIN_DIV);
|
| 705 | airoha_phy_csr_2l_set_bits(pcie_phy, REG_CSR_2L_TXPLL_TCL_LPF_BW,
|
| 706 | CSR_2L_PXP_TXPLL_VCO_HALFLSB_EN);
|
| 707 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_TXPLL_VCO_SCAPWR,
|
| 708 | CSR_2L_PXP_TXPLL_VCO_SCAPWR, 0x7);
|
| 709 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_TXPLL_TCL_LPF_BW,
|
| 710 | CSR_2L_PXP_TXPLL_VCO_CFIX, 0x3);
|
| 711 |
|
| 712 | airoha_phy_pma0_set_bits(pcie_phy,
|
| 713 | REG_PCIE_PMA_FORCE_DA_PXP_CDR_PR_IDAC,
|
| 714 | PCIE_FORCE_SEL_DA_PXP_TXPLL_SDM_PCW);
|
| 715 | airoha_phy_pma1_set_bits(pcie_phy,
|
| 716 | REG_PCIE_PMA_FORCE_DA_PXP_CDR_PR_IDAC,
|
| 717 | PCIE_FORCE_SEL_DA_PXP_TXPLL_SDM_PCW);
|
| 718 |
|
| 719 | airoha_phy_csr_2l_clear_bits(pcie_phy, REG_CSR_2L_TXPLL_SSC,
|
| 720 | CSR_2L_PXP_TXPLL_SSC_PHASE_INI);
|
| 721 | airoha_phy_csr_2l_clear_bits(pcie_phy, REG_CSR_2L_TXPLL_LPF_BWR,
|
| 722 | CSR_2L_PXP_TXPLL_LPF_BWR);
|
| 723 | airoha_phy_csr_2l_set_bits(pcie_phy, REG_CSR_2L_TXPLL_PHY_CK2,
|
| 724 | CSR_2L_PXP_TXPLL_REFIN_INTERNAL);
|
| 725 | airoha_phy_csr_2l_clear_bits(pcie_phy, REG_CSR_2L_TXPLL_TCL_KBAND_VREF,
|
| 726 | CSR_2L_PXP_TXPLL_VCO_KBAND_MEAS_EN);
|
| 727 | airoha_phy_csr_2l_clear_bits(pcie_phy, REG_CSR_2L_TXPLL_VTP,
|
| 728 | CSR_2L_PXP_TXPLL_VTP_EN);
|
| 729 | airoha_phy_csr_2l_clear_bits(pcie_phy, REG_CSR_2L_TXPLL_POSTDIV,
|
| 730 | CSR_2L_PXP_TXPLL_PHY_CK1_EN);
|
| 731 | airoha_phy_csr_2l_set_bits(pcie_phy, REG_CSR_2L_TXPLL_PHY_CK2,
|
| 732 | CSR_2L_PXP_TXPLL_REFIN_INTERNAL);
|
| 733 | airoha_phy_csr_2l_clear_bits(pcie_phy, REG_CSR_2L_TXPLL_SSC,
|
| 734 | CSR_2L_PXP_TXPLL_SSC_EN);
|
| 735 | airoha_phy_csr_2l_clear_bits(pcie_phy, REG_CSR_2L_750M_SYS_CK,
|
| 736 | CSR_2L_PXP_TXPLL_LPF_SHCK_EN);
|
| 737 | airoha_phy_csr_2l_clear_bits(pcie_phy, REG_CSR_2L_TXPLL_POSTDIV,
|
| 738 | CSR_2L_PXP_TXPLL_POSTDIV_EN);
|
| 739 | airoha_phy_csr_2l_clear_bits(pcie_phy, REG_CSR_2L_TXPLL_KBAND_DIV,
|
| 740 | CSR_2L_PXP_TXPLL_KBAND_KFC);
|
| 741 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_TXPLL_KBAND_DIV,
|
| 742 | CSR_2L_PXP_TXPLL_KBAND_KF, 0x3);
|
| 743 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_TXPLL_KBAND_DIV,
|
| 744 | CSR_2L_PXP_txpll_KBAND_KS, 0x1);
|
| 745 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_TXPLL_KBAND_DIV,
|
| 746 | CSR_2L_PXP_TXPLL_KBAND_DIV, 0x4);
|
| 747 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_TXPLL_LPF_BWR,
|
| 748 | CSR_2L_PXP_TXPLL_KBAND_CODE, 0xe4);
|
| 749 | airoha_phy_csr_2l_set_bits(pcie_phy, REG_CSR_2L_TXPLL_SDM_OUT,
|
| 750 | CSR_2L_PXP_TXPLL_TCL_AMP_EN);
|
| 751 | airoha_phy_csr_2l_set_bits(pcie_phy, REG_CSR_2L_TXPLL_TCL_AMP_VREF,
|
| 752 | CSR_2L_PXP_TXPLL_TCL_LPF_EN);
|
| 753 | airoha_phy_csr_2l_update_field(pcie_phy,
|
| 754 | REG_CSR_2L_TXPLL_TCL_KBAND_VREF,
|
| 755 | CSR_2L_PXP_TXPLL_TCL_KBAND_VREF, 0xf);
|
| 756 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_TXPLL_SDM_OUT,
|
| 757 | CSR_2L_PXP_TXPLL_TCL_AMP_GAIN, 0x3);
|
| 758 | airoha_phy_csr_2l_update_field(pcie_phy,
|
| 759 | REG_CSR_2L_TXPLL_TCL_AMP_VREF,
|
| 760 | CSR_2L_PXP_TXPLL_TCL_AMP_VREF, 0xb);
|
| 761 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_TXPLL_TCL_LPF_BW,
|
| 762 | CSR_2L_PXP_TXPLL_TCL_LPF_BW, 0x3);
|
| 763 |
|
| 764 | airoha_phy_pma0_set_bits(pcie_phy,
|
| 765 | REG_PCIE_PMA_FORCE_DA_PXP_TXPLL_CKOUT,
|
| 766 | PCIE_FORCE_SEL_DA_PXP_TXPLL_CKOUT_EN);
|
| 767 | airoha_phy_pma0_set_bits(pcie_phy,
|
| 768 | REG_PCIE_PMA_FORCE_DA_PXP_TXPLL_CKOUT,
|
| 769 | PCIE_FORCE_DA_PXP_TXPLL_CKOUT_EN);
|
| 770 | airoha_phy_pma1_set_bits(pcie_phy,
|
| 771 | REG_PCIE_PMA_FORCE_DA_PXP_TXPLL_CKOUT,
|
| 772 | PCIE_FORCE_SEL_DA_PXP_TXPLL_CKOUT_EN);
|
| 773 | airoha_phy_pma1_set_bits(pcie_phy,
|
| 774 | REG_PCIE_PMA_FORCE_DA_PXP_TXPLL_CKOUT,
|
| 775 | PCIE_FORCE_DA_PXP_TXPLL_CKOUT_EN);
|
| 776 | airoha_phy_pma0_set_bits(pcie_phy,
|
| 777 | REG_PCIE_PMA_FORCE_DA_PXP_TXPLL_CKOUT,
|
| 778 | PCIE_FORCE_SEL_DA_PXP_TXPLL_EN);
|
| 779 | airoha_phy_pma0_set_bits(pcie_phy,
|
| 780 | REG_PCIE_PMA_FORCE_DA_PXP_TXPLL_CKOUT,
|
| 781 | PCIE_FORCE_DA_PXP_TXPLL_EN);
|
| 782 | airoha_phy_pma1_set_bits(pcie_phy,
|
| 783 | REG_PCIE_PMA_FORCE_DA_PXP_TXPLL_CKOUT,
|
| 784 | PCIE_FORCE_SEL_DA_PXP_TXPLL_EN);
|
| 785 | airoha_phy_pma1_set_bits(pcie_phy,
|
| 786 | REG_PCIE_PMA_FORCE_DA_PXP_TXPLL_CKOUT,
|
| 787 | PCIE_FORCE_DA_PXP_TXPLL_EN);
|
| 788 | }
|
| 789 |
|
| 790 | static void airoha_pcie_phy_init_ssc_jcpll(struct airoha_pcie_phy *pcie_phy)
|
| 791 | {
|
| 792 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_JCPLL_SSC_DELTA1,
|
| 793 | CSR_2L_PXP_JCPLL_SSC_DELTA1, 0x106);
|
| 794 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_JCPLL_SSC_DELTA1,
|
| 795 | CSR_2L_PXP_JCPLL_SSC_DELTA, 0x106);
|
| 796 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_JCPLL_SSC_PERIOD,
|
| 797 | CSR_2L_PXP_JCPLL_SSC_PERIOD, 0x31b);
|
| 798 | airoha_phy_csr_2l_set_bits(pcie_phy, REG_CSR_2L_JCPLL_SSC,
|
| 799 | CSR_2L_PXP_JCPLL_SSC_PHASE_INI);
|
| 800 | airoha_phy_csr_2l_set_bits(pcie_phy, REG_CSR_2L_JCPLL_SSC,
|
| 801 | CSR_2L_PXP_JCPLL_SSC_EN);
|
| 802 | airoha_phy_csr_2l_set_bits(pcie_phy, REG_CSR_2L_JCPLL_SDM_IFM,
|
| 803 | CSR_2L_PXP_JCPLL_SDM_IFM);
|
| 804 | airoha_phy_csr_2l_set_bits(pcie_phy, REG_CSR_2L_JCPLL_SDM_HREN,
|
| 805 | CSR_2L_PXP_JCPLL_SDM_HREN);
|
| 806 | airoha_phy_csr_2l_clear_bits(pcie_phy, REG_CSR_2L_JCPLL_RST_DLY,
|
| 807 | CSR_2L_PXP_JCPLL_SDM_DI_EN);
|
| 808 | airoha_phy_csr_2l_set_bits(pcie_phy, REG_CSR_2L_JCPLL_SSC,
|
| 809 | CSR_2L_PXP_JCPLL_SSC_TRI_EN);
|
| 810 | }
|
| 811 |
|
| 812 | static void
|
| 813 | airoha_pcie_phy_set_rxlan0_signal_detect(struct airoha_pcie_phy *pcie_phy)
|
| 814 | {
|
| 815 | airoha_phy_csr_2l_set_bits(pcie_phy, REG_CSR_2L_CDR0_PR_COR_HBW,
|
| 816 | CSR_2L_PXP_CDR0_PR_LDO_FORCE_ON);
|
| 817 |
|
| 818 | usleep_range(100, 200);
|
| 819 |
|
| 820 | airoha_phy_pma0_update_field(pcie_phy, REG_PCIE_PMA_DIG_RESERVE_19,
|
| 821 | PCIE_PCP_RX_REV0_PCIE_GEN1, 0x18b0);
|
| 822 | airoha_phy_pma0_update_field(pcie_phy, REG_PCIE_PMA_DIG_RESERVE_20,
|
| 823 | PCIE_PCP_RX_REV0_PCIE_GEN2, 0x18b0);
|
| 824 | airoha_phy_pma0_update_field(pcie_phy, REG_PCIE_PMA_DIG_RESERVE_20,
|
| 825 | PCIE_PCP_RX_REV0_PCIE_GEN3, 0x1030);
|
| 826 |
|
| 827 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_RX0_SIGDET_DCTEST,
|
| 828 | CSR_2L_PXP_RX0_SIGDET_PEAK, 0x2);
|
| 829 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_RX0_SIGDET_VTH_SEL,
|
| 830 | CSR_2L_PXP_RX0_SIGDET_VTH_SEL, 0x5);
|
| 831 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_RX0_REV0,
|
| 832 | CSR_2L_PXP_VOS_PNINV, 0x2);
|
| 833 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_RX0_SIGDET_DCTEST,
|
| 834 | CSR_2L_PXP_RX0_SIGDET_LPF_CTRL, 0x1);
|
| 835 |
|
| 836 | airoha_phy_pma0_update_field(pcie_phy, REG_PCIE_PMA_SS_RX_CAL2,
|
| 837 | PCIE_CAL_OUT_OS, 0x0);
|
| 838 |
|
| 839 | airoha_phy_csr_2l_set_bits(pcie_phy, REG_CSR_2L_PXP_RX0_FE_VB_EQ2,
|
| 840 | CSR_2L_PXP_RX0_FE_VCM_GEN_PWDB);
|
| 841 |
|
| 842 | airoha_phy_pma0_set_bits(pcie_phy,
|
| 843 | REG_PCIE_PMA_FORCE_DA_PXP_RX_FE_GAIN_CTRL,
|
| 844 | PCIE_FORCE_SEL_DA_PXP_RX_FE_PWDB);
|
| 845 | airoha_phy_pma0_update_field(pcie_phy,
|
| 846 | REG_PCIE_PMA_FORCE_DA_PXP_RX_FE_GAIN_CTRL,
|
| 847 | PCIE_FORCE_DA_PXP_RX_FE_GAIN_CTRL, 0x3);
|
| 848 | airoha_phy_pma0_update_field(pcie_phy, REG_PCIE_PMA_RX_FORCE_MODE0,
|
| 849 | PCIE_FORCE_DA_XPON_RX_FE_GAIN_CTRL, 0x1);
|
| 850 | airoha_phy_pma0_update_field(pcie_phy, REG_PCIE_PMA_SS_RX_SIGDET0,
|
| 851 | PCIE_SIGDET_WIN_NONVLD_TIMES, 0x3);
|
| 852 | airoha_phy_pma0_clear_bits(pcie_phy, REG_PCIE_PMA_SEQUENCE_DISB_CTRL1,
|
| 853 | PCIE_DISB_RX_SDCAL_EN);
|
| 854 |
|
| 855 | airoha_phy_pma0_set_bits(pcie_phy,
|
| 856 | REG_PCIE_PMA_CTRL_SEQUENCE_FORCE_CTRL1,
|
| 857 | PCIE_FORCE_RX_SDCAL_EN);
|
| 858 | usleep_range(150, 200);
|
| 859 | airoha_phy_pma0_clear_bits(pcie_phy,
|
| 860 | REG_PCIE_PMA_CTRL_SEQUENCE_FORCE_CTRL1,
|
| 861 | PCIE_FORCE_RX_SDCAL_EN);
|
| 862 | }
|
| 863 |
|
| 864 | static void
|
| 865 | airoha_pcie_phy_set_rxlan1_signal_detect(struct airoha_pcie_phy *pcie_phy)
|
| 866 | {
|
| 867 | airoha_phy_csr_2l_set_bits(pcie_phy, REG_CSR_2L_CDR1_PR_COR_HBW,
|
| 868 | CSR_2L_PXP_CDR1_PR_LDO_FORCE_ON);
|
| 869 |
|
| 870 | usleep_range(100, 200);
|
| 871 |
|
| 872 | airoha_phy_pma1_update_field(pcie_phy, REG_PCIE_PMA_DIG_RESERVE_19,
|
| 873 | PCIE_PCP_RX_REV0_PCIE_GEN1, 0x18b0);
|
| 874 | airoha_phy_pma1_update_field(pcie_phy, REG_PCIE_PMA_DIG_RESERVE_20,
|
| 875 | PCIE_PCP_RX_REV0_PCIE_GEN2, 0x18b0);
|
| 876 | airoha_phy_pma1_update_field(pcie_phy, REG_PCIE_PMA_DIG_RESERVE_20,
|
| 877 | PCIE_PCP_RX_REV0_PCIE_GEN3, 0x1030);
|
| 878 |
|
| 879 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_RX1_SIGDET_NOVTH,
|
| 880 | CSR_2L_PXP_RX1_SIGDET_PEAK, 0x2);
|
| 881 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_RX1_SIGDET_NOVTH,
|
| 882 | CSR_2L_PXP_RX1_SIGDET_VTH_SEL, 0x5);
|
| 883 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_RX1_REV0,
|
| 884 | CSR_2L_PXP_VOS_PNINV, 0x2);
|
| 885 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_RX1_DAC_RANGE_EYE,
|
| 886 | CSR_2L_PXP_RX1_SIGDET_LPF_CTRL, 0x1);
|
| 887 |
|
| 888 | airoha_phy_pma1_update_field(pcie_phy, REG_PCIE_PMA_SS_RX_CAL2,
|
| 889 | PCIE_CAL_OUT_OS, 0x0);
|
| 890 |
|
| 891 | airoha_phy_csr_2l_set_bits(pcie_phy, REG_CSR_2L_RX1_FE_VB_EQ1,
|
| 892 | CSR_2L_PXP_RX1_FE_VCM_GEN_PWDB);
|
| 893 |
|
| 894 | airoha_phy_pma1_set_bits(pcie_phy,
|
| 895 | REG_PCIE_PMA_FORCE_DA_PXP_RX_FE_GAIN_CTRL,
|
| 896 | PCIE_FORCE_SEL_DA_PXP_RX_FE_PWDB);
|
| 897 | airoha_phy_pma1_update_field(pcie_phy,
|
| 898 | REG_PCIE_PMA_FORCE_DA_PXP_RX_FE_GAIN_CTRL,
|
| 899 | PCIE_FORCE_DA_PXP_RX_FE_GAIN_CTRL, 0x3);
|
| 900 | airoha_phy_pma1_update_field(pcie_phy, REG_PCIE_PMA_RX_FORCE_MODE0,
|
| 901 | PCIE_FORCE_DA_XPON_RX_FE_GAIN_CTRL, 0x1);
|
| 902 | airoha_phy_pma1_update_field(pcie_phy, REG_PCIE_PMA_SS_RX_SIGDET0,
|
| 903 | PCIE_SIGDET_WIN_NONVLD_TIMES, 0x3);
|
| 904 | airoha_phy_pma1_clear_bits(pcie_phy, REG_PCIE_PMA_SEQUENCE_DISB_CTRL1,
|
| 905 | PCIE_DISB_RX_SDCAL_EN);
|
| 906 |
|
| 907 | airoha_phy_pma1_set_bits(pcie_phy,
|
| 908 | REG_PCIE_PMA_CTRL_SEQUENCE_FORCE_CTRL1,
|
| 909 | PCIE_FORCE_RX_SDCAL_EN);
|
| 910 | usleep_range(150, 200);
|
| 911 | airoha_phy_pma1_clear_bits(pcie_phy,
|
| 912 | REG_PCIE_PMA_CTRL_SEQUENCE_FORCE_CTRL1,
|
| 913 | PCIE_FORCE_RX_SDCAL_EN);
|
| 914 | }
|
| 915 |
|
| 916 | static void airoha_pcie_phy_set_rxflow(struct airoha_pcie_phy *pcie_phy)
|
| 917 | {
|
| 918 | airoha_phy_pma0_set_bits(pcie_phy,
|
| 919 | REG_PCIE_PMA_FORCE_DA_PXP_RX_SCAN_RST,
|
| 920 | PCIE_FORCE_DA_PXP_RX_SIGDET_PWDB |
|
| 921 | PCIE_FORCE_SEL_DA_PXP_RX_SIGDET_PWDB);
|
| 922 | airoha_phy_pma1_set_bits(pcie_phy,
|
| 923 | REG_PCIE_PMA_FORCE_DA_PXP_RX_SCAN_RST,
|
| 924 | PCIE_FORCE_DA_PXP_RX_SIGDET_PWDB |
|
| 925 | PCIE_FORCE_SEL_DA_PXP_RX_SIGDET_PWDB);
|
| 926 |
|
| 927 | airoha_phy_pma0_set_bits(pcie_phy,
|
| 928 | REG_PCIE_PMA_FORCE_DA_PXP_CDR_PD_PWDB,
|
| 929 | PCIE_FORCE_DA_PXP_CDR_PD_PWDB |
|
| 930 | PCIE_FORCE_SEL_DA_PXP_CDR_PD_PWDB);
|
| 931 | airoha_phy_pma0_set_bits(pcie_phy,
|
| 932 | REG_PCIE_PMA_FORCE_DA_PXP_RX_FE_PWDB,
|
| 933 | PCIE_FORCE_DA_PXP_RX_FE_PWDB |
|
| 934 | PCIE_FORCE_SEL_DA_PXP_RX_FE_PWDB);
|
| 935 | airoha_phy_pma1_set_bits(pcie_phy,
|
| 936 | REG_PCIE_PMA_FORCE_DA_PXP_CDR_PD_PWDB,
|
| 937 | PCIE_FORCE_DA_PXP_CDR_PD_PWDB |
|
| 938 | PCIE_FORCE_SEL_DA_PXP_CDR_PD_PWDB);
|
| 939 | airoha_phy_pma1_set_bits(pcie_phy,
|
| 940 | REG_PCIE_PMA_FORCE_DA_PXP_RX_FE_PWDB,
|
| 941 | PCIE_FORCE_DA_PXP_RX_FE_PWDB |
|
| 942 | PCIE_FORCE_SEL_DA_PXP_RX_FE_PWDB);
|
| 943 |
|
| 944 | airoha_phy_csr_2l_set_bits(pcie_phy, REG_CSR_2L_RX0_PHYCK_DIV,
|
| 945 | CSR_2L_PXP_RX0_PHYCK_RSTB |
|
| 946 | CSR_2L_PXP_RX0_TDC_CK_SEL);
|
| 947 | airoha_phy_csr_2l_set_bits(pcie_phy, REG_CSR_2L_RX1_PHYCK_DIV,
|
| 948 | CSR_2L_PXP_RX1_PHYCK_RSTB |
|
| 949 | CSR_2L_PXP_RX1_TDC_CK_SEL);
|
| 950 |
|
| 951 | airoha_phy_pma0_set_bits(pcie_phy, REG_PCIE_PMA_SW_RESET,
|
| 952 | PCIE_SW_RX_FIFO_RST | PCIE_SW_TX_RST |
|
| 953 | PCIE_SW_PMA_RST | PCIE_SW_ALLPCS_RST |
|
| 954 | PCIE_SW_TX_FIFO_RST);
|
| 955 | airoha_phy_pma1_set_bits(pcie_phy, REG_PCIE_PMA_SW_RESET,
|
| 956 | PCIE_SW_RX_FIFO_RST | PCIE_SW_TX_RST |
|
| 957 | PCIE_SW_PMA_RST | PCIE_SW_ALLPCS_RST |
|
| 958 | PCIE_SW_TX_FIFO_RST);
|
| 959 |
|
| 960 | airoha_phy_csr_2l_set_bits(pcie_phy, REG_CSR_2L_PXP_RX0_FE_VB_EQ2,
|
| 961 | CSR_2L_PXP_RX0_FE_VB_EQ2_EN |
|
| 962 | CSR_2L_PXP_RX0_FE_VB_EQ3_EN);
|
| 963 | airoha_phy_csr_2l_set_bits(pcie_phy, REG_CSR_2L_RX0_SIGDET_VTH_SEL,
|
| 964 | CSR_2L_PXP_RX0_FE_VB_EQ1_EN);
|
| 965 | airoha_phy_csr_2l_set_bits(pcie_phy, REG_CSR_2L_RX1_FE_VB_EQ1,
|
| 966 | CSR_2L_PXP_RX1_FE_VB_EQ1_EN |
|
| 967 | CSR_2L_PXP_RX1_FE_VB_EQ2_EN |
|
| 968 | CSR_2L_PXP_RX1_FE_VB_EQ3_EN);
|
| 969 |
|
| 970 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_RX0_REV0,
|
| 971 | CSR_2L_PXP_FE_GAIN_NORMAL_MODE, 0x4);
|
| 972 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_RX0_REV0,
|
| 973 | CSR_2L_PXP_FE_GAIN_TRAIN_MODE, 0x4);
|
| 974 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_RX1_REV0,
|
| 975 | CSR_2L_PXP_FE_GAIN_NORMAL_MODE, 0x4);
|
| 976 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_RX1_REV0,
|
| 977 | CSR_2L_PXP_FE_GAIN_TRAIN_MODE, 0x4);
|
| 978 | }
|
| 979 |
|
| 980 | static void airoha_pcie_phy_set_pr(struct airoha_pcie_phy *pcie_phy)
|
| 981 | {
|
| 982 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_CDR0_PR_VREG_IBAND,
|
| 983 | CSR_2L_PXP_CDR0_PR_VREG_IBAND, 0x5);
|
| 984 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_CDR0_PR_VREG_IBAND,
|
| 985 | CSR_2L_PXP_CDR0_PR_VREG_CKBUF, 0x5);
|
| 986 |
|
| 987 | airoha_phy_csr_2l_clear_bits(pcie_phy, REG_CSR_2L_CDR0_PR_CKREF_DIV,
|
| 988 | CSR_2L_PXP_CDR0_PR_CKREF_DIV);
|
| 989 | airoha_phy_csr_2l_clear_bits(pcie_phy, REG_CSR_2L_CDR0_PR_COR_HBW,
|
| 990 | CSR_2L_PXP_CDR0_PR_CKREF_DIV1);
|
| 991 |
|
| 992 | airoha_phy_csr_2l_update_field(pcie_phy,
|
| 993 | REG_CSR_2L_CDR1_PR_VREG_IBAND_VAL,
|
| 994 | CSR_2L_PXP_CDR1_PR_VREG_IBAND, 0x5);
|
| 995 | airoha_phy_csr_2l_update_field(pcie_phy,
|
| 996 | REG_CSR_2L_CDR1_PR_VREG_IBAND_VAL,
|
| 997 | CSR_2L_PXP_CDR1_PR_VREG_CKBUF, 0x5);
|
| 998 |
|
| 999 | airoha_phy_csr_2l_clear_bits(pcie_phy, REG_CSR_2L_CDR1_PR_CKREF_DIV,
|
| 1000 | CSR_2L_PXP_CDR1_PR_CKREF_DIV);
|
| 1001 | airoha_phy_csr_2l_clear_bits(pcie_phy, REG_CSR_2L_CDR1_PR_COR_HBW,
|
| 1002 | CSR_2L_PXP_CDR1_PR_CKREF_DIV1);
|
| 1003 |
|
| 1004 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_CDR0_LPF_RATIO,
|
| 1005 | CSR_2L_PXP_CDR0_LPF_TOP_LIM, 0x20000);
|
| 1006 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_CDR1_LPF_RATIO,
|
| 1007 | CSR_2L_PXP_CDR1_LPF_TOP_LIM, 0x20000);
|
| 1008 |
|
| 1009 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_CDR0_PR_BETA_DAC,
|
| 1010 | CSR_2L_PXP_CDR0_PR_BETA_SEL, 0x2);
|
| 1011 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_CDR1_PR_BETA_DAC,
|
| 1012 | CSR_2L_PXP_CDR1_PR_BETA_SEL, 0x2);
|
| 1013 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_CDR0_PR_BETA_DAC,
|
| 1014 | CSR_2L_PXP_CDR0_PR_KBAND_DIV, 0x4);
|
| 1015 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_CDR1_PR_BETA_DAC,
|
| 1016 | CSR_2L_PXP_CDR1_PR_KBAND_DIV, 0x4);
|
| 1017 | }
|
| 1018 |
|
| 1019 | static void airoha_pcie_phy_set_txflow(struct airoha_pcie_phy *pcie_phy)
|
| 1020 | {
|
| 1021 | airoha_phy_csr_2l_set_bits(pcie_phy, REG_CSR_2L_TX0_CKLDO,
|
| 1022 | CSR_2L_PXP_TX0_CKLDO_EN);
|
| 1023 | airoha_phy_csr_2l_set_bits(pcie_phy, REG_CSR_2L_TX1_CKLDO,
|
| 1024 | CSR_2L_PXP_TX1_CKLDO_EN);
|
| 1025 |
|
| 1026 | airoha_phy_csr_2l_set_bits(pcie_phy, REG_CSR_2L_TX0_CKLDO,
|
| 1027 | CSR_2L_PXP_TX0_DMEDGEGEN_EN);
|
| 1028 | airoha_phy_csr_2l_set_bits(pcie_phy, REG_CSR_2L_TX1_CKLDO,
|
| 1029 | CSR_2L_PXP_TX1_DMEDGEGEN_EN);
|
| 1030 | airoha_phy_csr_2l_clear_bits(pcie_phy, REG_CSR_2L_TX1_MULTLANE,
|
| 1031 | CSR_2L_PXP_TX1_MULTLANE_EN);
|
| 1032 | }
|
| 1033 |
|
| 1034 | static void airoha_pcie_phy_set_rx_mode(struct airoha_pcie_phy *pcie_phy)
|
| 1035 | {
|
| 1036 | writel(0x804000, pcie_phy->pma0 + REG_PCIE_PMA_DIG_RESERVE_27);
|
| 1037 | airoha_phy_pma0_update_field(pcie_phy, REG_PCIE_PMA_DIG_RESERVE_18,
|
| 1038 | PCIE_PXP_RX_VTH_SEL_PCIE_G1, 0x5);
|
| 1039 | airoha_phy_pma0_update_field(pcie_phy, REG_PCIE_PMA_DIG_RESERVE_18,
|
| 1040 | PCIE_PXP_RX_VTH_SEL_PCIE_G2, 0x5);
|
| 1041 | airoha_phy_pma0_update_field(pcie_phy, REG_PCIE_PMA_DIG_RESERVE_18,
|
| 1042 | PCIE_PXP_RX_VTH_SEL_PCIE_G3, 0x5);
|
| 1043 | airoha_phy_pma0_set_bits(pcie_phy, REG_PCIE_PMA_DIG_RESERVE_30,
|
| 1044 | 0x77700);
|
| 1045 |
|
| 1046 | airoha_phy_csr_2l_clear_bits(pcie_phy, REG_CSR_2L_CDR0_PR_MONCK,
|
| 1047 | CSR_2L_PXP_CDR0_PR_MONCK_ENABLE);
|
| 1048 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_CDR0_PR_MONCK,
|
| 1049 | CSR_2L_PXP_CDR0_PR_RESERVE0, 0x2);
|
| 1050 | airoha_phy_csr_2l_update_field(pcie_phy,
|
| 1051 | REG_CSR_2L_PXP_RX0_OSCAL_CTLE1IOS,
|
| 1052 | CSR_2L_PXP_RX0_PR_OSCAL_VGA1IOS, 0x19);
|
| 1053 | airoha_phy_csr_2l_update_field(pcie_phy,
|
| 1054 | REG_CSR_2L_PXP_RX0_OSCA_VGA1VOS,
|
| 1055 | CSR_2L_PXP_RX0_PR_OSCAL_VGA1VOS, 0x19);
|
| 1056 | airoha_phy_csr_2l_update_field(pcie_phy,
|
| 1057 | REG_CSR_2L_PXP_RX0_OSCA_VGA1VOS,
|
| 1058 | CSR_2L_PXP_RX0_PR_OSCAL_VGA2IOS, 0x14);
|
| 1059 |
|
| 1060 | writel(0x804000, pcie_phy->pma1 + REG_PCIE_PMA_DIG_RESERVE_27);
|
| 1061 | airoha_phy_pma1_update_field(pcie_phy, REG_PCIE_PMA_DIG_RESERVE_18,
|
| 1062 | PCIE_PXP_RX_VTH_SEL_PCIE_G1, 0x5);
|
| 1063 | airoha_phy_pma1_update_field(pcie_phy, REG_PCIE_PMA_DIG_RESERVE_18,
|
| 1064 | PCIE_PXP_RX_VTH_SEL_PCIE_G2, 0x5);
|
| 1065 | airoha_phy_pma1_update_field(pcie_phy, REG_PCIE_PMA_DIG_RESERVE_18,
|
| 1066 | PCIE_PXP_RX_VTH_SEL_PCIE_G3, 0x5);
|
| 1067 |
|
| 1068 | airoha_phy_pma1_set_bits(pcie_phy, REG_PCIE_PMA_DIG_RESERVE_30,
|
| 1069 | 0x77700);
|
| 1070 |
|
| 1071 | airoha_phy_csr_2l_clear_bits(pcie_phy, REG_CSR_2L_CDR1_PR_MONCK,
|
| 1072 | CSR_2L_PXP_CDR1_PR_MONCK_ENABLE);
|
| 1073 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_CDR1_PR_MONCK,
|
| 1074 | CSR_2L_PXP_CDR1_PR_RESERVE0, 0x2);
|
| 1075 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_RX1_OSCAL_VGA1IOS,
|
| 1076 | CSR_2L_PXP_RX1_PR_OSCAL_VGA1IOS, 0x19);
|
| 1077 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_RX1_OSCAL_VGA1IOS,
|
| 1078 | CSR_2L_PXP_RX1_PR_OSCAL_VGA1VOS, 0x19);
|
| 1079 | airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_RX1_OSCAL_VGA1IOS,
|
| 1080 | CSR_2L_PXP_RX1_PR_OSCAL_VGA2IOS, 0x14);
|
| 1081 | }
|
| 1082 |
|
| 1083 | static void airoha_pcie_phy_load_kflow(struct airoha_pcie_phy *pcie_phy)
|
| 1084 | {
|
| 1085 | airoha_phy_pma0_update_field(pcie_phy, REG_PCIE_PMA_DIG_RESERVE_12,
|
| 1086 | PCIE_FORCE_PMA_RX_SPEED, 0xa);
|
| 1087 | airoha_phy_pma1_update_field(pcie_phy, REG_PCIE_PMA_DIG_RESERVE_12,
|
| 1088 | PCIE_FORCE_PMA_RX_SPEED, 0xa);
|
| 1089 | airoha_phy_init_lane0_rx_fw_pre_calib(pcie_phy, PCIE_PORT_GEN3);
|
| 1090 | airoha_phy_init_lane1_rx_fw_pre_calib(pcie_phy, PCIE_PORT_GEN3);
|
| 1091 |
|
| 1092 | airoha_phy_pma0_clear_bits(pcie_phy, REG_PCIE_PMA_DIG_RESERVE_12,
|
| 1093 | PCIE_FORCE_PMA_RX_SPEED);
|
| 1094 | airoha_phy_pma1_clear_bits(pcie_phy, REG_PCIE_PMA_DIG_RESERVE_12,
|
| 1095 | PCIE_FORCE_PMA_RX_SPEED);
|
| 1096 | usleep_range(100, 200);
|
| 1097 |
|
| 1098 | airoha_phy_init_lane0_rx_fw_pre_calib(pcie_phy, PCIE_PORT_GEN2);
|
| 1099 | airoha_phy_init_lane1_rx_fw_pre_calib(pcie_phy, PCIE_PORT_GEN2);
|
| 1100 | }
|
| 1101 |
|
| 1102 | |
| 1103 | * airoha_pcie_phy_init() - Initialize the phy
|
| 1104 | * @phy: the phy to be initialized
|
| 1105 | *
|
| 1106 | * Initialize the phy registers.
|
| 1107 | * The hardware settings will be reset during suspend, it should be
|
| 1108 | * reinitialized when the consumer calls phy_init() again on resume.
|
| 1109 |
|
| 1110 | static int airoha_pcie_phy_init(struct phy *phy)
|
| 1111 | {
|
| 1112 | struct airoha_pcie_phy *pcie_phy = phy_get_drvdata(phy);
|
| 1113 | u32 val;
|
| 1114 |
|
| 1115 |
|
| 1116 | val = FIELD_PREP(PCIE_XTP_RXDET_VCM_OFF_STB_T_SEL, 0x33) |
|
| 1117 | FIELD_PREP(PCIE_XTP_RXDET_EN_STB_T_SEL, 0x1) |
|
| 1118 | FIELD_PREP(PCIE_XTP_RXDET_FINISH_STB_T_SEL, 0x2) |
|
| 1119 | FIELD_PREP(PCIE_XTP_TXPD_TX_DATA_EN_DLY, 0x3) |
|
| 1120 | FIELD_PREP(PCIE_XTP_RXDET_LATCH_STB_T_SEL, 0x1);
|
| 1121 | writel(val, pcie_phy->p0_xr_dtime + REG_PCIE_PEXTP_DIG_GLB44);
|
| 1122 | writel(val, pcie_phy->p1_xr_dtime + REG_PCIE_PEXTP_DIG_GLB44);
|
| 1123 |
|
| 1124 | val = FIELD_PREP(PCIE_XTP_LN_RX_PDOWN_L1P2_EXIT_WAIT, 0x32) |
|
| 1125 | FIELD_PREP(PCIE_XTP_LN_RX_PDOWN_E0_AEQEN_WAIT, 0x5050);
|
| 1126 | writel(val, pcie_phy->rx_aeq + REG_PCIE_PEXTP_DIG_LN_RX30_P0);
|
| 1127 | writel(val, pcie_phy->rx_aeq + REG_PCIE_PEXTP_DIG_LN_RX30_P1);
|
| 1128 |
|
| 1129 |
|
| 1130 | airoha_phy_pma0_set_bits(pcie_phy, REG_PCIE_PMA_DIG_RESERVE_14,
|
| 1131 | PCIE_FLL_LOAD_EN);
|
| 1132 | airoha_phy_pma1_set_bits(pcie_phy, REG_PCIE_PMA_DIG_RESERVE_14,
|
| 1133 | PCIE_FLL_LOAD_EN);
|
| 1134 |
|
| 1135 | airoha_pcie_phy_init_default(pcie_phy);
|
| 1136 | airoha_pcie_phy_init_clk_out(pcie_phy);
|
| 1137 | airoha_pcie_phy_init_csr_2l(pcie_phy);
|
| 1138 |
|
| 1139 | usleep_range(100, 200);
|
| 1140 |
|
| 1141 | airoha_pcie_phy_init_rx(pcie_phy);
|
| 1142 |
|
| 1143 | airoha_pcie_phy_init_jcpll(pcie_phy);
|
| 1144 |
|
| 1145 | usleep_range(500, 600);
|
| 1146 |
|
| 1147 |
|
| 1148 | airoha_pcie_phy_txpll(pcie_phy);
|
| 1149 |
|
| 1150 | usleep_range(200, 300);
|
| 1151 |
|
| 1152 |
|
| 1153 | airoha_pcie_phy_init_ssc_jcpll(pcie_phy);
|
| 1154 |
|
| 1155 | usleep_range(100, 200);
|
| 1156 |
|
| 1157 |
|
| 1158 | airoha_pcie_phy_set_rxlan0_signal_detect(pcie_phy);
|
| 1159 |
|
| 1160 | airoha_pcie_phy_set_rxlan1_signal_detect(pcie_phy);
|
| 1161 |
|
| 1162 | airoha_pcie_phy_set_rxflow(pcie_phy);
|
| 1163 |
|
| 1164 | usleep_range(100, 200);
|
| 1165 |
|
| 1166 | airoha_pcie_phy_set_pr(pcie_phy);
|
| 1167 |
|
| 1168 | airoha_pcie_phy_set_txflow(pcie_phy);
|
| 1169 |
|
| 1170 | usleep_range(100, 200);
|
| 1171 |
|
| 1172 | airoha_pcie_phy_set_rx_mode(pcie_phy);
|
| 1173 |
|
| 1174 | airoha_pcie_phy_load_kflow(pcie_phy);
|
| 1175 | airoha_phy_pma0_clear_bits(pcie_phy, REG_PCIE_PMA_SS_DA_XPON_PWDB0,
|
| 1176 | PCIE_DA_XPON_CDR_PR_PWDB);
|
| 1177 | airoha_phy_pma1_clear_bits(pcie_phy, REG_PCIE_PMA_SS_DA_XPON_PWDB0,
|
| 1178 | PCIE_DA_XPON_CDR_PR_PWDB);
|
| 1179 |
|
| 1180 | usleep_range(100, 200);
|
| 1181 |
|
| 1182 | airoha_phy_pma0_set_bits(pcie_phy, REG_PCIE_PMA_SS_DA_XPON_PWDB0,
|
| 1183 | PCIE_DA_XPON_CDR_PR_PWDB);
|
| 1184 | airoha_phy_pma1_set_bits(pcie_phy, REG_PCIE_PMA_SS_DA_XPON_PWDB0,
|
| 1185 | PCIE_DA_XPON_CDR_PR_PWDB);
|
| 1186 |
|
| 1187 |
|
| 1188 | msleep(PHY_HW_INIT_TIME_MS);
|
| 1189 |
|
| 1190 | return 0;
|
| 1191 | }
|
| 1192 |
|
| 1193 | static int airoha_pcie_phy_exit(struct phy *phy)
|
| 1194 | {
|
| 1195 | struct airoha_pcie_phy *pcie_phy = phy_get_drvdata(phy);
|
| 1196 |
|
| 1197 | airoha_phy_pma0_clear_bits(pcie_phy, REG_PCIE_PMA_SW_RESET,
|
| 1198 | PCIE_PMA_SW_RST);
|
| 1199 | airoha_phy_pma1_clear_bits(pcie_phy, REG_PCIE_PMA_SW_RESET,
|
| 1200 | PCIE_PMA_SW_RST);
|
| 1201 | airoha_phy_csr_2l_clear_bits(pcie_phy, REG_CSR_2L_JCPLL_SSC,
|
| 1202 | CSR_2L_PXP_JCPLL_SSC_PHASE_INI |
|
| 1203 | CSR_2L_PXP_JCPLL_SSC_TRI_EN |
|
| 1204 | CSR_2L_PXP_JCPLL_SSC_EN);
|
| 1205 |
|
| 1206 | return 0;
|
| 1207 | }
|
| 1208 |
|
| 1209 | static const struct phy_ops airoha_pcie_phy_ops = {
|
| 1210 | .init = airoha_pcie_phy_init,
|
| 1211 | .exit = airoha_pcie_phy_exit,
|
| 1212 | .owner = THIS_MODULE,
|
| 1213 | };
|
| 1214 |
|
| 1215 | static int airoha_pcie_phy_probe(struct platform_device *pdev)
|
| 1216 | {
|
| 1217 | struct airoha_pcie_phy *pcie_phy;
|
| 1218 | struct device *dev = &pdev->dev;
|
| 1219 | struct phy_provider *provider;
|
| 1220 |
|
| 1221 | pcie_phy = devm_kzalloc(dev, sizeof(*pcie_phy), GFP_KERNEL);
|
| 1222 | if (!pcie_phy)
|
| 1223 | return -ENOMEM;
|
| 1224 |
|
| 1225 | pcie_phy->csr_2l = devm_platform_ioremap_resource_byname(pdev, "csr-2l");
|
| 1226 | if (IS_ERR(pcie_phy->csr_2l))
|
| 1227 | return dev_err_probe(dev, PTR_ERR(pcie_phy->csr_2l),
|
| 1228 | "Failed to map phy-csr-2l base\n");
|
| 1229 |
|
| 1230 | pcie_phy->pma0 = devm_platform_ioremap_resource_byname(pdev, "pma0");
|
| 1231 | if (IS_ERR(pcie_phy->pma0))
|
| 1232 | return dev_err_probe(dev, PTR_ERR(pcie_phy->pma0),
|
| 1233 | "Failed to map phy-pma0 base\n");
|
| 1234 |
|
| 1235 | pcie_phy->pma1 = devm_platform_ioremap_resource_byname(pdev, "pma1");
|
| 1236 | if (IS_ERR(pcie_phy->pma1))
|
| 1237 | return dev_err_probe(dev, PTR_ERR(pcie_phy->pma1),
|
| 1238 | "Failed to map phy-pma1 base\n");
|
| 1239 |
|
| 1240 | pcie_phy->phy = devm_phy_create(dev, dev->of_node, &airoha_pcie_phy_ops);
|
| 1241 | if (IS_ERR(pcie_phy->phy))
|
| 1242 | return dev_err_probe(dev, PTR_ERR(pcie_phy->phy),
|
| 1243 | "Failed to create PCIe phy\n");
|
| 1244 |
|
| 1245 | pcie_phy->p0_xr_dtime =
|
| 1246 | devm_platform_ioremap_resource_byname(pdev, "p0-xr-dtime");
|
| 1247 | if (IS_ERR(pcie_phy->p0_xr_dtime))
|
| 1248 | return dev_err_probe(dev, PTR_ERR(pcie_phy->p0_xr_dtime),
|
| 1249 | "Failed to map P0 Tx-Rx dtime base\n");
|
| 1250 |
|
| 1251 | pcie_phy->p1_xr_dtime =
|
| 1252 | devm_platform_ioremap_resource_byname(pdev, "p1-xr-dtime");
|
| 1253 | if (IS_ERR(pcie_phy->p1_xr_dtime))
|
| 1254 | return dev_err_probe(dev, PTR_ERR(pcie_phy->p1_xr_dtime),
|
| 1255 | "Failed to map P1 Tx-Rx dtime base\n");
|
| 1256 |
|
| 1257 | pcie_phy->rx_aeq = devm_platform_ioremap_resource_byname(pdev, "rx-aeq");
|
| 1258 | if (IS_ERR(pcie_phy->rx_aeq))
|
| 1259 | return dev_err_probe(dev, PTR_ERR(pcie_phy->rx_aeq),
|
| 1260 | "Failed to map Rx AEQ base\n");
|
| 1261 |
|
| 1262 | pcie_phy->dev = dev;
|
| 1263 | phy_set_drvdata(pcie_phy->phy, pcie_phy);
|
| 1264 |
|
| 1265 | provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
|
| 1266 | if (IS_ERR(provider))
|
| 1267 | return dev_err_probe(dev, PTR_ERR(provider),
|
| 1268 | "PCIe phy probe failed\n");
|
| 1269 |
|
| 1270 | return 0;
|
| 1271 | }
|
| 1272 |
|
| 1273 | static const struct of_device_id airoha_pcie_phy_of_match[] = {
|
| 1274 | { .compatible = "airoha,en7581-pcie-phy" },
|
| 1275 | { }
|
| 1276 | };
|
| 1277 | MODULE_DEVICE_TABLE(of, airoha_pcie_phy_of_match);
|
| 1278 |
|
| 1279 | static struct platform_driver airoha_pcie_phy_driver = {
|
| 1280 | .probe = airoha_pcie_phy_probe,
|
| 1281 | .driver = {
|
| 1282 | .name = "airoha-pcie-phy",
|
| 1283 | .of_match_table = airoha_pcie_phy_of_match,
|
| 1284 | },
|
| 1285 | };
|
| 1286 | module_platform_driver(airoha_pcie_phy_driver);
|
| 1287 |
|
| 1288 | MODULE_DESCRIPTION("Airoha PCIe PHY driver");
|
| 1289 | MODULE_AUTHOR("Lorenzo Bianconi <[email protected]>");
|
| 1290 | MODULE_LICENSE("GPL");
|