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182 lines · 4.3 KiB

1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Author: Caleb James DeLisle <[email protected]>
4 * Ahmed Naseef <[email protected]>
5 */
6
7#include <linux/bitfield.h>
8#include <linux/module.h>
9#include <linux/of.h>
10#include <linux/phy/phy.h>
11#include <linux/platform_device.h>
12#include <linux/regmap.h>
13#include <linux/bits.h>
14#include <linux/delay.h>
15
16/* Rx detection timing for EN751221: 16*8 clock cycles */
17#define EN751221_RXDET_VAL 16
18
19/* Rx detection timing when in power mode 3 */
20#define EN75_RXDET_P3_REG 0xa28
21#define EN75_RXDET_P3_MASK GENMASK(17, 9)
22
23/* Rx detection timing when in power mode 2 */
24#define EN75_RXDET_P2_REG 0xa2c
25#define EN75_RXDET_P2_MASK GENMASK(8, 0)
26
27/* Rx impedance */
28#define EN75_RX_IMPEDANCE_REG 0xb2c
29#define EN75_RX_IMPEDANCE_MASK GENMASK(13, 12)
30enum en75_rx_impedance {
31 EN75_RX_IMPEDANCE_100_OHM = 0,
32 EN75_RX_IMPEDANCE_95_OHM = 1,
33 EN75_RX_IMPEDANCE_90_OHM = 2,
34};
35
36/* PLL Invert clock */
37#define EN75_PLL_PH_INV_REG 0x4a0
38#define EN75_PLL_PH_INV_MASK BIT(5)
39
40struct en75_phy_op {
41 u32 reg;
42 u32 mask;
43 u32 val;
44};
45
46struct en7528_pcie_phy {
47 struct regmap *regmap;
48 const struct en75_phy_op *data;
49};
50
51/* Port 0 PHY: set LCDDS_CLK_PH_INV for PLL operation */
52static const struct en75_phy_op en7528_phy_gen1[] = {
53 {
54 .reg = EN75_PLL_PH_INV_REG,
55 .mask = EN75_PLL_PH_INV_MASK,
56 .val = 1,
57 },
58 { /* sentinel */ }
59};
60
61/* EN7528 Port 1 PHY: Rx impedance tuning, target R -5 Ohm */
62static const struct en75_phy_op en7528_phy_gen2[] = {
63 {
64 .reg = EN75_RX_IMPEDANCE_REG,
65 .mask = EN75_RX_IMPEDANCE_MASK,
66 .val = EN75_RX_IMPEDANCE_95_OHM,
67 },
68 { /* sentinel */ }
69};
70
71/* EN751221 Port 1 PHY, set RX detect to 16*8 clock cycles */
72static const struct en75_phy_op en751221_phy_gen2[] = {
73 {
74 .reg = EN75_RXDET_P3_REG,
75 .mask = EN75_RXDET_P3_MASK,
76 .val = EN751221_RXDET_VAL,
77 },
78 {
79 .reg = EN75_RXDET_P2_REG,
80 .mask = EN75_RXDET_P2_MASK,
81 .val = EN751221_RXDET_VAL,
82 },
83 { /* sentinel */ }
84};
85
86static int en75_pcie_phy_init(struct phy *phy)
87{
88 struct en7528_pcie_phy *ephy = phy_get_drvdata(phy);
89 const struct en75_phy_op *data = ephy->data;
90 int i, ret;
91 u32 val;
92
93 for (i = 0; data[i].mask || data[i].val; i++) {
94 if (i)
95 usleep_range(1000, 2000);
96
97 val = field_prep(data[i].mask, data[i].val);
98
99 ret = regmap_update_bits(ephy->regmap, data[i].reg,
100 data[i].mask, val);
101 if (ret)
102 return ret;
103 }
104
105 return 0;
106}
107
108static const struct phy_ops en75_pcie_phy_ops = {
109 .init = en75_pcie_phy_init,
110 .owner = THIS_MODULE,
111};
112
113static int en75_pcie_phy_probe(struct platform_device *pdev)
114{
115 struct regmap_config regmap_config = {
116 .reg_bits = 32,
117 .val_bits = 32,
118 .reg_stride = 4,
119 };
120 struct device *dev = &pdev->dev;
121 const struct en75_phy_op *data;
122 struct phy_provider *provider;
123 struct en7528_pcie_phy *ephy;
124 void __iomem *base;
125 struct phy *phy;
126 int i;
127
128 data = of_device_get_match_data(dev);
129 if (!data)
130 return -EINVAL;
131
132 ephy = devm_kzalloc(dev, sizeof(*ephy), GFP_KERNEL);
133 if (!ephy)
134 return -ENOMEM;
135
136 ephy->data = data;
137
138 base = devm_platform_ioremap_resource(pdev, 0);
139 if (IS_ERR(base))
140 return PTR_ERR(base);
141
142 /* Set max_register to highest used register */
143 for (i = 0; data[i].mask || data[i].val; i++)
144 if (data[i].reg > regmap_config.max_register)
145 regmap_config.max_register = data[i].reg;
146
147 ephy->regmap = devm_regmap_init_mmio(dev, base, &regmap_config);
148 if (IS_ERR(ephy->regmap))
149 return PTR_ERR(ephy->regmap);
150
151 phy = devm_phy_create(dev, dev->of_node, &en75_pcie_phy_ops);
152 if (IS_ERR(phy))
153 return PTR_ERR(phy);
154
155 phy_set_drvdata(phy, ephy);
156
157 provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
158
159 return PTR_ERR_OR_ZERO(provider);
160}
161
162static const struct of_device_id en75_pcie_phy_ids[] = {
163 { .compatible = "econet,en7528-pcie-gen1", .data = en7528_phy_gen1 },
164 { .compatible = "econet,en7528-pcie-gen2", .data = en7528_phy_gen2 },
165 { .compatible = "econet,en751221-pcie-gen1", .data = en7528_phy_gen1 },
166 { .compatible = "econet,en751221-pcie-gen2", .data = en751221_phy_gen2 },
167 { /* sentinel */ }
168};
169MODULE_DEVICE_TABLE(of, en75_pcie_phy_ids);
170
171static struct platform_driver en75_pcie_phy_driver = {
172 .probe = en75_pcie_phy_probe,
173 .driver = {
174 .name = "econet-pcie-phy",
175 .of_match_table = en75_pcie_phy_ids,
176 },
177};
178module_platform_driver(en75_pcie_phy_driver);
179
180MODULE_AUTHOR("Caleb James DeLisle <[email protected]>");
181MODULE_DESCRIPTION("EcoNet PCIe PHY driver");
182MODULE_LICENSE("GPL");