| 1 | # SPDX-License-Identifier: GPL-2.0-only |
| 2 | config PINCTRL_ASPEED |
| 3 | bool |
| 4 | depends on (ARCH_ASPEED || COMPILE_TEST) && OF |
| 5 | select MFD_SYSCON |
| 6 | select PINMUX |
| 7 | select PINCONF |
| 8 | select GENERIC_PINCONF |
| 9 | select REGMAP_MMIO |
| 10 | |
| 11 | config PINCTRL_ASPEED_G4 |
| 12 | bool "Aspeed G4 SoC pin control" |
| 13 | depends on (MACH_ASPEED_G4 || COMPILE_TEST) && OF |
| 14 | select PINCTRL_ASPEED |
| 15 | help |
| 16 | Say Y here to enable pin controller support for Aspeed's 4th |
| 17 | generation SoCs. GPIO is provided by a separate GPIO driver. |
| 18 | |
| 19 | config PINCTRL_ASPEED_G5 |
| 20 | bool "Aspeed G5 SoC pin control" |
| 21 | depends on (MACH_ASPEED_G5 || COMPILE_TEST) && OF |
| 22 | select PINCTRL_ASPEED |
| 23 | help |
| 24 | Say Y here to enable pin controller support for Aspeed's 5th |
| 25 | generation SoCs. GPIO is provided by a separate GPIO driver. |
| 26 | |
| 27 | config PINCTRL_ASPEED_G6 |
| 28 | bool "Aspeed G6 SoC pin control" |
| 29 | depends on (MACH_ASPEED_G6 || COMPILE_TEST) && OF |
| 30 | select PINCTRL_ASPEED |
| 31 | help |
| 32 | Say Y here to enable pin controller support for Aspeed's 6th |
| 33 | generation SoCs. GPIO is provided by a separate GPIO driver. |
| 34 | |
| 35 | config PINCTRL_ASPEED_G7_SOC0 |
| 36 | bool "Aspeed G7 SoC pin control" |
| 37 | depends on (ARCH_ASPEED || COMPILE_TEST) && OF |
| 38 | select PINCTRL_ASPEED |
| 39 | help |
| 40 | Say Y here to enable pin controller support for the SoC0 instance |
| 41 | of Aspeed's 7th generation SoCs. GPIO is provided by a separate |
| 42 | GPIO driver. |
| 43 | |
| 44 | config PINCTRL_ASPEED_G7_SOC1 |
| 45 | bool "Aspeed G7 SoC1 pin control" |
| 46 | depends on (ARCH_ASPEED || COMPILE_TEST) && OF |
| 47 | select MFD_SYSCON |
| 48 | select PINMUX |
| 49 | select GENERIC_PINCTRL_GROUPS |
| 50 | select GENERIC_PINMUX_FUNCTIONS |
| 51 | select GENERIC_PINCONF |
| 52 | select REGMAP_MMIO |
| 53 | help |
| 54 | Say Y here to enable pin controller support for the SoC1 instance |
| 55 | of Aspeed's 7th generation SoCs. GPIO is provided by a separate |
| 56 | GPIO driver. |