projects/linux·blob master · refs

292 lines · 9.5 KiB

1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Core pinctrl/GPIO driver for Intel GPIO controllers
4 *
5 * Copyright (C) 2015 Intel Corporation
6 * Authors: Mathias Nyman <[email protected]>
7 * Mika Westerberg <[email protected]>
8 */
9
10#ifndef PINCTRL_INTEL_H
11#define PINCTRL_INTEL_H
12
13#include <linux/array_size.h>
14#include <linux/bits.h>
15#include <linux/compiler_types.h>
16#include <linux/gpio/driver.h>
17#include <linux/irq.h>
18#include <linux/pm.h>
19#include <linux/pinctrl/pinctrl.h>
20#include <linux/spinlock_types.h>
21
22struct platform_device;
23struct device;
24
25/**
26 * struct intel_pingroup - Description about group of pins
27 * @grp: Generic data of the pin group (name and pins)
28 * @mode: Native mode in which the group is muxed out @pins. Used if @modes is %NULL.
29 * @modes: If not %NULL this will hold mode for each pin in @pins
30 */
31struct intel_pingroup {
32 struct pingroup grp;
33 unsigned short mode;
34 const unsigned int *modes;
35};
36
37/**
38 * struct intel_function - Description about a function
39 * @func: Generic data of the pin function (name and groups of pins)
40 */
41struct intel_function {
42 struct pinfunction func;
43};
44
45#define INTEL_PINCTRL_MAX_GPP_SIZE 32
46
47/**
48 * struct intel_padgroup - Hardware pad group information
49 * @reg_num: GPI_IS register number
50 * @base: Starting pin of this group
51 * @size: Size of this group (maximum is %INTEL_PINCTRL_MAX_GPP_SIZE).
52 * @gpio_base: Starting GPIO base of this group
53 * @padown_num: PAD_OWN register number (assigned by the core driver)
54 *
55 * If pad groups of a community are not the same size, use this structure
56 * to specify them.
57 */
58struct intel_padgroup {
59 unsigned int reg_num;
60 unsigned int base;
61 unsigned int size;
62 int gpio_base;
63 unsigned int padown_num;
64};
65
66/**
67 * enum - Special treatment for GPIO base in pad group
68 *
69 * @INTEL_GPIO_BASE_ZERO: force GPIO base to be 0
70 * @INTEL_GPIO_BASE_NOMAP: no GPIO mapping should be created
71 * @INTEL_GPIO_BASE_MATCH: matches with starting pin number
72 */
73enum {
74 INTEL_GPIO_BASE_ZERO = -2,
75 INTEL_GPIO_BASE_NOMAP = -1,
76 INTEL_GPIO_BASE_MATCH = 0,
77};
78
79/* Initialise struct intel_padgroup */
80#define INTEL_GPP(r, s, e, g) \
81 { \
82 .reg_num = (r), \
83 .base = (s), \
84 .size = ((e) - (s) + 1), \
85 .gpio_base = (g), \
86 }
87
88/**
89 * struct intel_community - Intel pin community description
90 * @barno: MMIO BAR number where registers for this community reside
91 * @padown_offset: Register offset of PAD_OWN register from @regs. If %0
92 * then there is no support for owner.
93 * @padcfglock_offset: Register offset of PADCFGLOCK from @regs. If %0 then
94 * locking is not supported.
95 * @hostown_offset: Register offset of HOSTSW_OWN from @regs. If %0 then it
96 * is assumed that the host owns the pin (rather than
97 * ACPI).
98 * @is_offset: Register offset of GPI_IS from @regs.
99 * @ie_offset: Register offset of GPI_IE from @regs.
100 * @features: Additional features supported by the hardware
101 * @pin_base: Starting pin of pins in this community
102 * @npins: Number of pins in this community
103 * @gpp_size: Maximum number of pads in each group, such as PADCFGLOCK,
104 * HOSTSW_OWN, GPI_IS, GPI_IE. Used when @gpps is %NULL.
105 * @gpp_num_padown_regs: Number of pad registers each pad group consumes at
106 * minimum. Used when @gpps is %NULL.
107 * @gpps: Pad groups if the controller has variable size pad groups
108 * @ngpps: Number of pad groups in this community
109 * @pad_map: Optional non-linear mapping of the pads
110 * @nirqs: Optional total number of IRQs this community can generate
111 * @acpi_space_id: Optional address space ID for ACPI OpRegion handler
112 * @regs: Community specific common registers (reserved for core driver)
113 * @pad_regs: Community specific pad registers (reserved for core driver)
114 *
115 * In older Intel GPIO host controllers, this driver supports, each pad group
116 * is of equal size (except the last one). In that case the driver can just
117 * fill in @gpp_size and @gpp_num_padown_regs fields and let the core driver
118 * to handle the rest.
119 *
120 * In newer Intel GPIO host controllers each pad group is of variable size,
121 * so the client driver can pass custom @gpps and @ngpps instead.
122 */
123struct intel_community {
124 unsigned int barno;
125 unsigned int padown_offset;
126 unsigned int padcfglock_offset;
127 unsigned int hostown_offset;
128 unsigned int is_offset;
129 unsigned int ie_offset;
130 unsigned int features;
131 unsigned int pin_base;
132 size_t npins;
133 unsigned int gpp_size;
134 unsigned int gpp_num_padown_regs;
135 const struct intel_padgroup *gpps;
136 size_t ngpps;
137 const unsigned int *pad_map;
138 unsigned short nirqs;
139 unsigned short acpi_space_id;
140
141 /* Reserved for the core driver */
142 void __iomem *regs;
143 void __iomem *pad_regs;
144};
145
146/* Additional features supported by the hardware */
147#define PINCTRL_FEATURE_DEBOUNCE BIT(0)
148#define PINCTRL_FEATURE_1K_PD BIT(1)
149#define PINCTRL_FEATURE_GPIO_HW_INFO BIT(2)
150#define PINCTRL_FEATURE_PWM BIT(3)
151#define PINCTRL_FEATURE_BLINK BIT(4)
152#define PINCTRL_FEATURE_EXP BIT(5)
153#define PINCTRL_FEATURE_3BIT_PAD_OWN BIT(6)
154
155#define __INTEL_COMMUNITY(b, s, e, g, n, gs, gn, soc) \
156 { \
157 .barno = (b), \
158 .padown_offset = soc ## _PAD_OWN, \
159 .padcfglock_offset = soc ## _PADCFGLOCK, \
160 .hostown_offset = soc ## _HOSTSW_OWN, \
161 .is_offset = soc ## _GPI_IS, \
162 .ie_offset = soc ## _GPI_IE, \
163 .gpp_size = (gs), \
164 .gpp_num_padown_regs = (gn), \
165 .pin_base = (s), \
166 .npins = ((e) - (s) + 1), \
167 .gpps = (g), \
168 .ngpps = (n), \
169 }
170
171#define INTEL_COMMUNITY_GPPS(b, s, e, g, soc) \
172 __INTEL_COMMUNITY(b, s, e, g, ARRAY_SIZE(g), 0, 0, soc)
173
174#define INTEL_COMMUNITY_SIZE(b, s, e, gs, gn, soc) \
175 __INTEL_COMMUNITY(b, s, e, NULL, 0, gs, gn, soc)
176
177/**
178 * PIN_GROUP - Declare a pin group
179 * @n: Name of the group
180 * @p: An array of pins this group consists
181 * @m: Mode which the pins are put when this group is active. Can be either
182 * a single integer or an array of integers in which case mode is per
183 * pin.
184 */
185#define PIN_GROUP(n, p, m) \
186 { \
187 .grp = PINCTRL_PINGROUP((n), (p), ARRAY_SIZE((p))), \
188 .mode = __builtin_choose_expr(__builtin_constant_p((m)), (m), 0), \
189 .modes = __builtin_choose_expr(__builtin_constant_p((m)), NULL, (m)), \
190 }
191
192#define PIN_GROUP_GPIO(n, p, m) \
193 PIN_GROUP(n, p, m), \
194 PIN_GROUP(n "_gpio", p, 0)
195
196#define FUNCTION(n, g) \
197 { \
198 .func = PINCTRL_PINFUNCTION((n), (g), ARRAY_SIZE(g)), \
199 }
200
201/**
202 * struct intel_pinctrl_soc_data - Intel pin controller per-SoC configuration
203 * @uid: ACPI _UID for the probe driver use if needed
204 * @pins: Array if pins this pinctrl controls
205 * @npins: Number of pins in the array
206 * @groups: Array of pin groups
207 * @ngroups: Number of groups in the array
208 * @functions: Array of functions
209 * @nfunctions: Number of functions in the array
210 * @communities: Array of communities this pinctrl handles
211 * @ncommunities: Number of communities in the array
212 *
213 * The @communities is used as a template by the core driver. It will make
214 * copy of all communities and fill in rest of the information.
215 */
216struct intel_pinctrl_soc_data {
217 const char *uid;
218 const struct pinctrl_pin_desc *pins;
219 size_t npins;
220 const struct intel_pingroup *groups;
221 size_t ngroups;
222 const struct intel_function *functions;
223 size_t nfunctions;
224 const struct intel_community *communities;
225 size_t ncommunities;
226};
227
228const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(struct platform_device *pdev);
229
230struct intel_pad_context;
231struct intel_community_context;
232
233/**
234 * struct intel_pinctrl_context - context to be saved during suspend-resume
235 * @pads: Opaque context per pad (driver dependent)
236 * @communities: Opaque context per community (driver dependent)
237 */
238struct intel_pinctrl_context {
239 struct intel_pad_context *pads;
240 struct intel_community_context *communities;
241};
242
243/**
244 * struct intel_pinctrl - Intel pinctrl private structure
245 * @dev: Pointer to the device structure
246 * @lock: Lock to serialize register access
247 * @pctldesc: Pin controller description
248 * @pctldev: Pointer to the pin controller device
249 * @chip: GPIO chip in this pin controller
250 * @soc: SoC/PCH specific pin configuration data
251 * @communities: All communities in this pin controller
252 * @ncommunities: Number of communities in this pin controller
253 * @context: Configuration saved over system sleep
254 * @irq: pinctrl/GPIO chip irq number
255 */
256struct intel_pinctrl {
257 struct device *dev;
258 raw_spinlock_t lock;
259 struct pinctrl_desc pctldesc;
260 struct pinctrl_dev *pctldev;
261 struct gpio_chip chip;
262 const struct intel_pinctrl_soc_data *soc;
263 struct intel_community *communities;
264 size_t ncommunities;
265 struct intel_pinctrl_context context;
266 int irq;
267};
268
269int intel_pinctrl_probe(struct platform_device *pdev,
270 const struct intel_pinctrl_soc_data *soc_data);
271
272int intel_pinctrl_probe_by_hid(struct platform_device *pdev);
273int intel_pinctrl_probe_by_uid(struct platform_device *pdev);
274
275extern const struct dev_pm_ops intel_pinctrl_pm_ops;
276
277const struct intel_community *intel_get_community(const struct intel_pinctrl *pctrl,
278 unsigned int pin);
279
280int intel_gpio_add_pin_ranges(struct gpio_chip *gc);
281
282int intel_get_groups_count(struct pinctrl_dev *pctldev);
283const char *intel_get_group_name(struct pinctrl_dev *pctldev, unsigned int group);
284int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
285 const unsigned int **pins, unsigned int *npins);
286
287int intel_get_functions_count(struct pinctrl_dev *pctldev);
288const char *intel_get_function_name(struct pinctrl_dev *pctldev, unsigned int function);
289int intel_get_function_groups(struct pinctrl_dev *pctldev, unsigned int function,
290 const char * const **groups, unsigned int * const ngroups);
291
292#endif /* PINCTRL_INTEL_H */