projects/linux·blob master · refs

142 lines · 3.6 KiB

1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * PTP hardware clock driver for the IDT ClockMatrix(TM) family of timing and
4 * synchronization devices.
5 *
6 * Copyright (C) 2019 Integrated Device Technology, Inc., a Renesas Company.
7 */
8#ifndef PTP_IDTCLOCKMATRIX_H
9#define PTP_IDTCLOCKMATRIX_H
10
11#include <linux/ktime.h>
12#include <linux/mfd/idt8a340_reg.h>
13#include <linux/ptp_clock.h>
14#include <linux/regmap.h>
15
16#define FW_FILENAME "idtcm.bin"
17#define MAX_TOD (4)
18#define MAX_PLL (8)
19#define MAX_REF_CLK (16)
20
21#define MAX_ABS_WRITE_PHASE_NANOSECONDS (107374182L)
22
23#define TOD_MASK_ADDR (0xFFA5)
24#define DEFAULT_TOD_MASK (0x04)
25
26#define SET_U16_LSB(orig, val8) (orig = (0xff00 & (orig)) | (val8))
27#define SET_U16_MSB(orig, val8) (orig = (0x00ff & (orig)) | (val8 << 8))
28
29#define TOD0_PTP_PLL_ADDR (0xFFA8)
30#define TOD1_PTP_PLL_ADDR (0xFFA9)
31#define TOD2_PTP_PLL_ADDR (0xFFAA)
32#define TOD3_PTP_PLL_ADDR (0xFFAB)
33
34#define TOD0_OUT_ALIGN_MASK_ADDR (0xFFB0)
35#define TOD1_OUT_ALIGN_MASK_ADDR (0xFFB2)
36#define TOD2_OUT_ALIGN_MASK_ADDR (0xFFB4)
37#define TOD3_OUT_ALIGN_MASK_ADDR (0xFFB6)
38
39#define DEFAULT_OUTPUT_MASK_PLL0 (0x003)
40#define DEFAULT_OUTPUT_MASK_PLL1 (0x00c)
41#define DEFAULT_OUTPUT_MASK_PLL2 (0x030)
42#define DEFAULT_OUTPUT_MASK_PLL3 (0x0c0)
43
44#define DEFAULT_TOD0_PTP_PLL (0)
45#define DEFAULT_TOD1_PTP_PLL (1)
46#define DEFAULT_TOD2_PTP_PLL (2)
47#define DEFAULT_TOD3_PTP_PLL (3)
48
49#define PHASE_PULL_IN_THRESHOLD_NS_DEPRECATED (150000)
50#define PHASE_PULL_IN_THRESHOLD_NS (15000)
51#define TOD_WRITE_OVERHEAD_COUNT_MAX (2)
52#define TOD_BYTE_COUNT (11)
53
54#define LOCK_TIMEOUT_MS (2000)
55#define LOCK_POLL_INTERVAL_MS (10)
56
57#define IDTCM_MAX_WRITE_COUNT (512)
58
59#define PHASE_PULL_IN_MAX_PPB (144000)
60#define PHASE_PULL_IN_MIN_THRESHOLD_NS (2)
61
62/*
63 * Return register address based on passed in firmware version
64 */
65#define IDTCM_FW_REG(FW, VER, REG) (((FW) < (VER)) ? (REG) : (REG##_##VER))
66enum fw_version {
67 V_DEFAULT = 0,
68 V487 = 1,
69 V520 = 2,
70};
71
72/* PTP PLL Mode */
73enum ptp_pll_mode {
74 PTP_PLL_MODE_MIN = 0,
75 PTP_PLL_MODE_WRITE_FREQUENCY = PTP_PLL_MODE_MIN,
76 PTP_PLL_MODE_WRITE_PHASE,
77 PTP_PLL_MODE_UNSUPPORTED,
78 PTP_PLL_MODE_MAX = PTP_PLL_MODE_UNSUPPORTED,
79};
80
81struct idtcm;
82
83struct idtcm_channel {
84 struct ptp_clock_info caps;
85 struct ptp_clock *ptp_clock;
86 struct idtcm *idtcm;
87 u16 dpll_phase;
88 u16 dpll_freq;
89 u16 dpll_n;
90 u16 dpll_ctrl_n;
91 u16 dpll_phase_pull_in;
92 u16 tod_read_primary;
93 u16 tod_read_secondary;
94 u16 tod_write;
95 u16 tod_n;
96 u16 hw_dpll_n;
97 u8 sync_src;
98 enum ptp_pll_mode mode;
99 int (*configure_write_frequency)(struct idtcm_channel *channel);
100 int (*configure_write_phase)(struct idtcm_channel *channel);
101 int (*do_phase_pull_in)(struct idtcm_channel *channel,
102 s32 offset_ns, u32 max_ffo_ppb);
103 s32 current_freq_scaled_ppm;
104 bool phase_pull_in;
105 u32 dco_delay;
106 /* last input trigger for extts */
107 u8 refn;
108 u8 pll;
109 u8 tod;
110 u16 output_mask;
111};
112
113struct idtcm {
114 struct idtcm_channel channel[MAX_TOD];
115 struct device *dev;
116 u8 tod_mask;
117 char version[16];
118 enum fw_version fw_ver;
119 /* Polls for external time stamps */
120 u8 extts_mask;
121 bool extts_single_shot;
122 struct delayed_work extts_work;
123 /* Remember the ptp channel to report extts */
124 struct idtcm_channel *event_channel[MAX_TOD];
125 /* Mutex to protect operations from being interrupted */
126 struct mutex *lock;
127 struct device *mfd;
128 struct regmap *regmap;
129 /* Overhead calculation for adjtime */
130 u8 calculate_overhead_flag;
131 s64 tod_write_overhead_ns;
132 ktime_t start_time;
133};
134
135struct idtcm_fwrc {
136 u8 hiaddr;
137 u8 loaddr;
138 u8 value;
139 u8 reserved;
140} __packed;
141
142#endif /* PTP_IDTCLOCKMATRIX_H */