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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * PTP 1588 clock using the EG20T PCH
4 *
5 * Copyright (C) 2010 OMICRON electronics GmbH
6 * Copyright (C) 2011-2012 LAPIS SEMICONDUCTOR Co., LTD.
7 *
8 * This code was derived from the IXP46X driver.
9 */
10
11#include <linux/device.h>
12#include <linux/err.h>
13#include <linux/hex.h>
14#include <linux/interrupt.h>
15#include <linux/io.h>
16#include <linux/io-64-nonatomic-lo-hi.h>
17#include <linux/io-64-nonatomic-hi-lo.h>
18#include <linux/irq.h>
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/pci.h>
22#include <linux/ptp_clock_kernel.h>
23#include <linux/ptp_pch.h>
24#include <linux/slab.h>
25
26#define STATION_ADDR_LEN 20
27#define PCI_DEVICE_ID_PCH_1588 0x8819
28#define IO_MEM_BAR 1
29
30#define DEFAULT_ADDEND 0xA0000000
31#define TICKS_NS_SHIFT 5
32#define N_EXT_TS 2
33
34enum pch_status {
35 PCH_SUCCESS,
36 PCH_INVALIDPARAM,
37 PCH_NOTIMESTAMP,
38 PCH_INTERRUPTMODEINUSE,
39 PCH_FAILED,
40 PCH_UNSUPPORTED,
41};
42
43/*
44 * struct pch_ts_regs - IEEE 1588 registers
45 */
46struct pch_ts_regs {
47 u32 control;
48 u32 event;
49 u32 addend;
50 u32 accum;
51 u32 test;
52 u32 ts_compare;
53 u32 rsystime_lo;
54 u32 rsystime_hi;
55 u32 systime_lo;
56 u32 systime_hi;
57 u32 trgt_lo;
58 u32 trgt_hi;
59 u32 asms_lo;
60 u32 asms_hi;
61 u32 amms_lo;
62 u32 amms_hi;
63 u32 ch_control;
64 u32 ch_event;
65 u32 tx_snap_lo;
66 u32 tx_snap_hi;
67 u32 rx_snap_lo;
68 u32 rx_snap_hi;
69 u32 src_uuid_lo;
70 u32 src_uuid_hi;
71 u32 can_status;
72 u32 can_snap_lo;
73 u32 can_snap_hi;
74 u32 ts_sel;
75 u32 ts_st[6];
76 u32 reserve1[14];
77 u32 stl_max_set_en;
78 u32 stl_max_set;
79 u32 reserve2[13];
80 u32 srst;
81};
82
83#define PCH_TSC_RESET (1 << 0)
84#define PCH_TSC_TTM_MASK (1 << 1)
85#define PCH_TSC_ASMS_MASK (1 << 2)
86#define PCH_TSC_AMMS_MASK (1 << 3)
87#define PCH_TSC_PPSM_MASK (1 << 4)
88#define PCH_TSE_TTIPEND (1 << 1)
89#define PCH_TSE_SNS (1 << 2)
90#define PCH_TSE_SNM (1 << 3)
91#define PCH_TSE_PPS (1 << 4)
92#define PCH_CC_MM (1 << 0)
93#define PCH_CC_TA (1 << 1)
94
95#define PCH_CC_MODE_SHIFT 16
96#define PCH_CC_MODE_MASK 0x001F0000
97#define PCH_CC_VERSION (1 << 31)
98#define PCH_CE_TXS (1 << 0)
99#define PCH_CE_RXS (1 << 1)
100#define PCH_CE_OVR (1 << 0)
101#define PCH_CE_VAL (1 << 1)
102#define PCH_ECS_ETH (1 << 0)
103
104#define PCH_ECS_CAN (1 << 1)
105
106#define PCH_IEEE1588_ETH (1 << 0)
107#define PCH_IEEE1588_CAN (1 << 1)
108
109/*
110 * struct pch_dev - Driver private data
111 */
112struct pch_dev {
113 struct pch_ts_regs __iomem *regs;
114 struct ptp_clock *ptp_clock;
115 struct ptp_clock_info caps;
116 int exts0_enabled;
117 int exts1_enabled;
118
119 u32 irq;
120 struct pci_dev *pdev;
121 spinlock_t register_lock;
122};
123
124/*
125 * struct pch_params - 1588 module parameter
126 */
127struct pch_params {
128 u8 station[STATION_ADDR_LEN];
129};
130
131/* structure to hold the module parameters */
132static struct pch_params pch_param = {
133 "00:00:00:00:00:00"
134};
135
136/*
137 * Register access functions
138 */
139static inline void pch_eth_enable_set(struct pch_dev *chip)
140{
141 u32 val;
142 /* SET the eth_enable bit */
143 val = ioread32(&chip->regs->ts_sel) | (PCH_ECS_ETH);
144 iowrite32(val, (&chip->regs->ts_sel));
145}
146
147static u64 pch_systime_read(struct pch_ts_regs __iomem *regs)
148{
149 u64 ns;
150
151 ns = ioread64_lo_hi(&regs->systime_lo);
152
153 return ns << TICKS_NS_SHIFT;
154}
155
156static void pch_systime_write(struct pch_ts_regs __iomem *regs, u64 ns)
157{
158 iowrite64_lo_hi(ns >> TICKS_NS_SHIFT, &regs->systime_lo);
159}
160
161static inline void pch_block_reset(struct pch_dev *chip)
162{
163 u32 val;
164 /* Reset Hardware Assist block */
165 val = ioread32(&chip->regs->control) | PCH_TSC_RESET;
166 iowrite32(val, (&chip->regs->control));
167 val = val & ~PCH_TSC_RESET;
168 iowrite32(val, (&chip->regs->control));
169}
170
171void pch_ch_control_write(struct pci_dev *pdev, u32 val)
172{
173 struct pch_dev *chip = pci_get_drvdata(pdev);
174
175 iowrite32(val, (&chip->regs->ch_control));
176}
177EXPORT_SYMBOL(pch_ch_control_write);
178
179u32 pch_ch_event_read(struct pci_dev *pdev)
180{
181 struct pch_dev *chip = pci_get_drvdata(pdev);
182 u32 val;
183
184 val = ioread32(&chip->regs->ch_event);
185
186 return val;
187}
188EXPORT_SYMBOL(pch_ch_event_read);
189
190void pch_ch_event_write(struct pci_dev *pdev, u32 val)
191{
192 struct pch_dev *chip = pci_get_drvdata(pdev);
193
194 iowrite32(val, (&chip->regs->ch_event));
195}
196EXPORT_SYMBOL(pch_ch_event_write);
197
198u32 pch_src_uuid_lo_read(struct pci_dev *pdev)
199{
200 struct pch_dev *chip = pci_get_drvdata(pdev);
201 u32 val;
202
203 val = ioread32(&chip->regs->src_uuid_lo);
204
205 return val;
206}
207EXPORT_SYMBOL(pch_src_uuid_lo_read);
208
209u32 pch_src_uuid_hi_read(struct pci_dev *pdev)
210{
211 struct pch_dev *chip = pci_get_drvdata(pdev);
212 u32 val;
213
214 val = ioread32(&chip->regs->src_uuid_hi);
215
216 return val;
217}
218EXPORT_SYMBOL(pch_src_uuid_hi_read);
219
220u64 pch_rx_snap_read(struct pci_dev *pdev)
221{
222 struct pch_dev *chip = pci_get_drvdata(pdev);
223 u64 ns;
224
225 ns = ioread64_lo_hi(&chip->regs->rx_snap_lo);
226
227 return ns << TICKS_NS_SHIFT;
228}
229EXPORT_SYMBOL(pch_rx_snap_read);
230
231u64 pch_tx_snap_read(struct pci_dev *pdev)
232{
233 struct pch_dev *chip = pci_get_drvdata(pdev);
234 u64 ns;
235
236 ns = ioread64_lo_hi(&chip->regs->tx_snap_lo);
237
238 return ns << TICKS_NS_SHIFT;
239}
240EXPORT_SYMBOL(pch_tx_snap_read);
241
242/* This function enables all 64 bits in system time registers [high & low].
243This is a work-around for non continuous value in the SystemTime Register*/
244static void pch_set_system_time_count(struct pch_dev *chip)
245{
246 iowrite32(0x01, &chip->regs->stl_max_set_en);
247 iowrite32(0xFFFFFFFF, &chip->regs->stl_max_set);
248 iowrite32(0x00, &chip->regs->stl_max_set_en);
249}
250
251static void pch_reset(struct pch_dev *chip)
252{
253 /* Reset Hardware Assist */
254 pch_block_reset(chip);
255
256 /* enable all 32 bits in system time registers */
257 pch_set_system_time_count(chip);
258}
259
260/**
261 * pch_set_station_address() - This API sets the station address used by
262 * IEEE 1588 hardware when looking at PTP
263 * traffic on the ethernet interface
264 * @addr: dress which contain the column separated address to be used.
265 * @pdev: PCI device.
266 */
267int pch_set_station_address(u8 *addr, struct pci_dev *pdev)
268{
269 struct pch_dev *chip = pci_get_drvdata(pdev);
270 bool valid;
271 u64 mac;
272
273 /* Verify the parameter */
274 if ((chip->regs == NULL) || addr == (u8 *)NULL) {
275 dev_err(&pdev->dev,
276 "invalid params returning PCH_INVALIDPARAM\n");
277 return PCH_INVALIDPARAM;
278 }
279
280 valid = mac_pton(addr, (u8 *)&mac);
281 if (!valid) {
282 dev_err(&pdev->dev, "invalid params returning PCH_INVALIDPARAM\n");
283 return PCH_INVALIDPARAM;
284 }
285
286 dev_dbg(&pdev->dev, "invoking pch_station_set\n");
287 iowrite64_lo_hi(mac, &chip->regs->ts_st);
288 return 0;
289}
290EXPORT_SYMBOL(pch_set_station_address);
291
292/*
293 * Interrupt service routine
294 */
295static irqreturn_t isr(int irq, void *priv)
296{
297 struct pch_dev *pch_dev = priv;
298 struct pch_ts_regs __iomem *regs = pch_dev->regs;
299 struct ptp_clock_event event;
300 u32 ack = 0, val;
301
302 val = ioread32(&regs->event);
303
304 if (val & PCH_TSE_SNS) {
305 ack |= PCH_TSE_SNS;
306 if (pch_dev->exts0_enabled) {
307 event.type = PTP_CLOCK_EXTTS;
308 event.index = 0;
309 event.timestamp = ioread64_hi_lo(&regs->asms_hi);
310 event.timestamp <<= TICKS_NS_SHIFT;
311 ptp_clock_event(pch_dev->ptp_clock, &event);
312 }
313 }
314
315 if (val & PCH_TSE_SNM) {
316 ack |= PCH_TSE_SNM;
317 if (pch_dev->exts1_enabled) {
318 event.type = PTP_CLOCK_EXTTS;
319 event.index = 1;
320 event.timestamp = ioread64_hi_lo(&regs->asms_hi);
321 event.timestamp <<= TICKS_NS_SHIFT;
322 ptp_clock_event(pch_dev->ptp_clock, &event);
323 }
324 }
325
326 if (val & PCH_TSE_TTIPEND)
327 ack |= PCH_TSE_TTIPEND; /* this bit seems to be always set */
328
329 if (ack) {
330 iowrite32(ack, &regs->event);
331 return IRQ_HANDLED;
332 } else
333 return IRQ_NONE;
334}
335
336/*
337 * PTP clock operations
338 */
339
340static int ptp_pch_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
341{
342 u32 addend;
343 struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps);
344 struct pch_ts_regs __iomem *regs = pch_dev->regs;
345
346 addend = adjust_by_scaled_ppm(DEFAULT_ADDEND, scaled_ppm);
347
348 iowrite32(addend, &regs->addend);
349
350 return 0;
351}
352
353static int ptp_pch_adjtime(struct ptp_clock_info *ptp, s64 delta)
354{
355 s64 now;
356 unsigned long flags;
357 struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps);
358 struct pch_ts_regs __iomem *regs = pch_dev->regs;
359
360 spin_lock_irqsave(&pch_dev->register_lock, flags);
361 now = pch_systime_read(regs);
362 now += delta;
363 pch_systime_write(regs, now);
364 spin_unlock_irqrestore(&pch_dev->register_lock, flags);
365
366 return 0;
367}
368
369static int ptp_pch_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
370{
371 u64 ns;
372 unsigned long flags;
373 struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps);
374 struct pch_ts_regs __iomem *regs = pch_dev->regs;
375
376 spin_lock_irqsave(&pch_dev->register_lock, flags);
377 ns = pch_systime_read(regs);
378 spin_unlock_irqrestore(&pch_dev->register_lock, flags);
379
380 *ts = ns_to_timespec64(ns);
381 return 0;
382}
383
384static int ptp_pch_settime(struct ptp_clock_info *ptp,
385 const struct timespec64 *ts)
386{
387 u64 ns;
388 unsigned long flags;
389 struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps);
390 struct pch_ts_regs __iomem *regs = pch_dev->regs;
391
392 ns = timespec64_to_ns(ts);
393
394 spin_lock_irqsave(&pch_dev->register_lock, flags);
395 pch_systime_write(regs, ns);
396 spin_unlock_irqrestore(&pch_dev->register_lock, flags);
397
398 return 0;
399}
400
401static int ptp_pch_enable(struct ptp_clock_info *ptp,
402 struct ptp_clock_request *rq, int on)
403{
404 struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps);
405
406 switch (rq->type) {
407 case PTP_CLK_REQ_EXTTS:
408 switch (rq->extts.index) {
409 case 0:
410 pch_dev->exts0_enabled = on ? 1 : 0;
411 break;
412 case 1:
413 pch_dev->exts1_enabled = on ? 1 : 0;
414 break;
415 default:
416 return -EINVAL;
417 }
418 return 0;
419 default:
420 break;
421 }
422
423 return -EOPNOTSUPP;
424}
425
426static const struct ptp_clock_info ptp_pch_caps = {
427 .owner = THIS_MODULE,
428 .name = "PCH timer",
429 .max_adj = 50000000,
430 .n_ext_ts = N_EXT_TS,
431 .n_pins = 0,
432 .pps = 0,
433 .adjfine = ptp_pch_adjfine,
434 .adjtime = ptp_pch_adjtime,
435 .gettime64 = ptp_pch_gettime,
436 .settime64 = ptp_pch_settime,
437 .enable = ptp_pch_enable,
438};
439
440static void pch_remove(struct pci_dev *pdev)
441{
442 struct pch_dev *chip = pci_get_drvdata(pdev);
443
444 free_irq(pdev->irq, chip);
445 ptp_clock_unregister(chip->ptp_clock);
446}
447
448static s32
449pch_probe(struct pci_dev *pdev, const struct pci_device_id *id)
450{
451 s32 ret;
452 unsigned long flags;
453 struct pch_dev *chip;
454
455 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
456 if (chip == NULL)
457 return -ENOMEM;
458
459 /* enable the 1588 pci device */
460 ret = pcim_enable_device(pdev);
461 if (ret != 0) {
462 dev_err(&pdev->dev, "could not enable the pci device\n");
463 return ret;
464 }
465
466 /* get the virtual address to the 1588 registers */
467 chip->regs = pcim_iomap_region(pdev, IO_MEM_BAR, KBUILD_MODNAME);
468 ret = PTR_ERR_OR_ZERO(chip->regs);
469 if (ret) {
470 dev_err(&pdev->dev, "could not locate IO memory address\n");
471 return ret;
472 }
473
474 chip->caps = ptp_pch_caps;
475 chip->ptp_clock = ptp_clock_register(&chip->caps, &pdev->dev);
476 if (IS_ERR(chip->ptp_clock))
477 return PTR_ERR(chip->ptp_clock);
478
479 spin_lock_init(&chip->register_lock);
480
481 ret = request_irq(pdev->irq, &isr, IRQF_SHARED, KBUILD_MODNAME, chip);
482 if (ret != 0) {
483 dev_err(&pdev->dev, "failed to get irq %d\n", pdev->irq);
484 goto err_req_irq;
485 }
486
487 /* indicate success */
488 chip->irq = pdev->irq;
489 chip->pdev = pdev;
490 pci_set_drvdata(pdev, chip);
491
492 spin_lock_irqsave(&chip->register_lock, flags);
493 /* reset the ieee1588 h/w */
494 pch_reset(chip);
495
496 iowrite32(DEFAULT_ADDEND, &chip->regs->addend);
497 iowrite64_lo_hi(1, &chip->regs->trgt_lo);
498 iowrite32(PCH_TSE_TTIPEND, &chip->regs->event);
499
500 pch_eth_enable_set(chip);
501
502 if (strcmp(pch_param.station, "00:00:00:00:00:00") != 0) {
503 if (pch_set_station_address(pch_param.station, pdev) != 0) {
504 dev_err(&pdev->dev,
505 "Invalid station address parameter\n"
506 "Module loaded but station address not set correctly\n"
507 );
508 }
509 }
510 spin_unlock_irqrestore(&chip->register_lock, flags);
511 return 0;
512
513err_req_irq:
514 ptp_clock_unregister(chip->ptp_clock);
515
516 dev_err(&pdev->dev, "probe failed(ret=0x%x)\n", ret);
517
518 return ret;
519}
520
521static const struct pci_device_id pch_ieee1588_pcidev_id[] = {
522 {
523 .vendor = PCI_VENDOR_ID_INTEL,
524 .device = PCI_DEVICE_ID_PCH_1588
525 },
526 {0}
527};
528MODULE_DEVICE_TABLE(pci, pch_ieee1588_pcidev_id);
529
530static struct pci_driver pch_driver = {
531 .name = KBUILD_MODNAME,
532 .id_table = pch_ieee1588_pcidev_id,
533 .probe = pch_probe,
534 .remove = pch_remove,
535};
536module_pci_driver(pch_driver);
537
538module_param_string(station,
539 pch_param.station, sizeof(pch_param.station), 0444);
540MODULE_PARM_DESC(station,
541 "IEEE 1588 station address to use - colon separated hex values");
542
543MODULE_AUTHOR("LAPIS SEMICONDUCTOR, <[email protected]>");
544MODULE_DESCRIPTION("PTP clock using the EG20T timer");
545MODULE_LICENSE("GPL");