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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * drivers/pwm/pwm-pxa.c
4 *
5 * simple driver for PWM (Pulse Width Modulator) controller
6 *
7 * 2008-02-13 initial version
8 * eric miao <[email protected]>
9 *
10 * Links to reference manuals for some of the supported PWM chips can be found
11 * in Documentation/arch/arm/marvell.rst.
12 *
13 * Limitations:
14 * - When PWM is stopped, the current PWM period stops abruptly at the next
15 * input clock (PWMCR_SD is set) and the output is driven to inactive.
16 */
17
18#include <linux/module.h>
19#include <linux/kernel.h>
20#include <linux/platform_device.h>
21#include <linux/slab.h>
22#include <linux/err.h>
23#include <linux/clk.h>
24#include <linux/io.h>
25#include <linux/pwm.h>
26#include <linux/of.h>
27#include <linux/reset.h>
28
29#include <asm/div64.h>
30
31#define HAS_SECONDARY_PWM 0x10
32
33static const struct platform_device_id pwm_id_table[] = {
34 /* PWM has_secondary_pwm? */
35 { .name = "pxa25x-pwm", .driver_data = 0 },
36 { .name = "pxa27x-pwm", .driver_data = HAS_SECONDARY_PWM },
37 { .name = "pxa168-pwm", .driver_data = 0 },
38 { .name = "pxa910-pwm", .driver_data = 0 },
39 { }
40};
41MODULE_DEVICE_TABLE(platform, pwm_id_table);
42
43/* PWM registers and bits definitions */
44#define PWMCR (0x00)
45#define PWMDCR (0x04)
46#define PWMPCR (0x08)
47
48#define PWMCR_SD (1 << 6)
49#define PWMDCR_FD (1 << 10)
50
51struct pxa_pwm_chip {
52 struct device *dev;
53
54 struct clk *clk;
55 void __iomem *mmio_base;
56};
57
58static inline struct pxa_pwm_chip *to_pxa_pwm_chip(struct pwm_chip *chip)
59{
60 return pwmchip_get_drvdata(chip);
61}
62
63/*
64 * period_ns = 10^9 * (PRESCALE + 1) * (PV + 1) / PWM_CLK_RATE
65 * duty_ns = 10^9 * (PRESCALE + 1) * DC / PWM_CLK_RATE
66 */
67static int pxa_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
68 u64 duty_ns, u64 period_ns)
69{
70 struct pxa_pwm_chip *pc = to_pxa_pwm_chip(chip);
71 unsigned long long c;
72 unsigned long period_cycles, prescale, pv, dc;
73 unsigned long offset;
74
75 offset = pwm->hwpwm ? 0x10 : 0;
76
77 c = clk_get_rate(pc->clk);
78 c = c * period_ns;
79 do_div(c, 1000000000);
80 period_cycles = c;
81
82 if (period_cycles < 1)
83 period_cycles = 1;
84 prescale = (period_cycles - 1) / 1024;
85 pv = period_cycles / (prescale + 1) - 1;
86
87 if (prescale > 63)
88 return -EINVAL;
89
90 if (duty_ns == period_ns)
91 dc = PWMDCR_FD;
92 else
93 dc = mul_u64_u64_div_u64(pv + 1, duty_ns, period_ns);
94
95 writel(prescale | PWMCR_SD, pc->mmio_base + offset + PWMCR);
96 writel(dc, pc->mmio_base + offset + PWMDCR);
97 writel(pv, pc->mmio_base + offset + PWMPCR);
98
99 return 0;
100}
101
102static int pxa_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
103 const struct pwm_state *state)
104{
105 struct pxa_pwm_chip *pc = to_pxa_pwm_chip(chip);
106 u64 duty_cycle;
107 int err;
108
109 if (state->polarity != PWM_POLARITY_NORMAL)
110 return -EINVAL;
111
112 err = clk_prepare_enable(pc->clk);
113 if (err)
114 return err;
115
116 duty_cycle = state->enabled ? state->duty_cycle : 0;
117
118 err = pxa_pwm_config(chip, pwm, duty_cycle, state->period);
119 if (err) {
120 clk_disable_unprepare(pc->clk);
121 return err;
122 }
123
124 if (state->enabled && !pwm->state.enabled)
125 return 0;
126
127 clk_disable_unprepare(pc->clk);
128
129 if (!state->enabled && pwm->state.enabled)
130 clk_disable_unprepare(pc->clk);
131
132 return 0;
133}
134
135static const struct pwm_ops pxa_pwm_ops = {
136 .apply = pxa_pwm_apply,
137};
138
139/*
140 * Device tree users must create one device instance for each PWM channel.
141 * Hence we dispense with the HAS_SECONDARY_PWM and "tell" the original driver
142 * code that this is a single channel pxa25x-pwm. Currently all devices are
143 * supported identically.
144 */
145static const struct of_device_id pwm_of_match[] = {
146 { .compatible = "marvell,pxa250-pwm", .data = &pwm_id_table[0] },
147 { .compatible = "marvell,pxa270-pwm", .data = &pwm_id_table[0] },
148 { .compatible = "marvell,pxa168-pwm", .data = &pwm_id_table[0] },
149 { .compatible = "marvell,pxa910-pwm", .data = &pwm_id_table[0] },
150 { }
151};
152MODULE_DEVICE_TABLE(of, pwm_of_match);
153
154static int pwm_probe(struct platform_device *pdev)
155{
156 const struct platform_device_id *id = platform_get_device_id(pdev);
157 struct pwm_chip *chip;
158 struct pxa_pwm_chip *pc;
159 struct clk *bus_clk;
160 struct device *dev = &pdev->dev;
161 struct reset_control *rst;
162 int ret = 0;
163
164 if (id == NULL)
165 id = of_device_get_match_data(dev);
166
167 if (id == NULL)
168 return -EINVAL;
169
170 chip = devm_pwmchip_alloc(dev, (id->driver_data & HAS_SECONDARY_PWM) ? 2 : 1,
171 sizeof(*pc));
172 if (IS_ERR(chip))
173 return PTR_ERR(chip);
174 pc = to_pxa_pwm_chip(chip);
175
176 bus_clk = devm_clk_get_optional_enabled(dev, "bus");
177 if (IS_ERR(bus_clk))
178 return dev_err_probe(dev, PTR_ERR(bus_clk), "Failed to get bus clock\n");
179
180 /* Get named func clk if bus clock is valid */
181 pc->clk = devm_clk_get(dev, bus_clk ? "func" : NULL);
182 if (IS_ERR(pc->clk))
183 return dev_err_probe(dev, PTR_ERR(pc->clk), "Failed to get clock\n");
184
185 rst = devm_reset_control_get_optional_exclusive_deasserted(dev, NULL);
186 if (IS_ERR(rst))
187 return PTR_ERR(rst);
188
189 chip->ops = &pxa_pwm_ops;
190 chip->of_xlate = of_pwm_single_xlate;
191
192 pc->mmio_base = devm_platform_ioremap_resource(pdev, 0);
193 if (IS_ERR(pc->mmio_base))
194 return PTR_ERR(pc->mmio_base);
195
196 ret = devm_pwmchip_add(dev, chip);
197 if (ret < 0)
198 return dev_err_probe(dev, ret, "pwmchip_add() failed\n");
199
200 return 0;
201}
202
203static struct platform_driver pwm_driver = {
204 .driver = {
205 .name = "pxa25x-pwm",
206 .of_match_table = pwm_of_match,
207 },
208 .probe = pwm_probe,
209 .id_table = pwm_id_table,
210};
211
212module_platform_driver(pwm_driver);
213
214MODULE_DESCRIPTION("PXA Pulse Width Modulator driver");
215MODULE_LICENSE("GPL v2");