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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2017-2018 SiFive
4 * For SiFive's PWM IP block documentation please refer Chapter 14 of
5 * Reference Manual : https://static.dev.sifive.com/FU540-C000-v1.0.pdf
6 *
7 * PWM output inversion: According to the SiFive Reference manual
8 * the output of each comparator is high whenever the value of pwms is
9 * greater than or equal to the corresponding pwmcmpX[Reference Manual].
10 *
11 * Figure 29 in the same manual shows that the pwmcmpXcenter bit is
12 * hard-tied to 0 (XNOR), which effectively inverts the comparison so that
13 * the output goes HIGH when `pwms < pwmcmpX`.
14 *
15 * In other words, each pwmcmp register actually defines the **inactive**
16 * (low) period of the pulse, not the active time exactly opposite to what
17 * the documentation text implies.
18 *
19 * To compensate, this driver always **inverts** the duty value when reading
20 * or writing pwmcmp registers , so that users interact with a conventional
21 * **active-high** PWM interface.
22 *
23 *
24 * Limitations:
25 * - When changing both duty cycle and period, we cannot prevent in
26 * software that the output might produce a period with mixed
27 * settings (new period length and old duty cycle).
28 * - The hardware cannot generate a 0% duty cycle.
29 * - The hardware generates only inverted output.
30 */
31#include <linux/clk.h>
32#include <linux/io.h>
33#include <linux/module.h>
34#include <linux/platform_device.h>
35#include <linux/pwm.h>
36#include <linux/slab.h>
37#include <linux/bitfield.h>
38
39/* Register offsets */
40#define PWM_SIFIVE_PWMCFG 0x0
41#define PWM_SIFIVE_PWMCOUNT 0x8
42#define PWM_SIFIVE_PWMS 0x10
43#define PWM_SIFIVE_PWMCMP(i) (0x20 + 4 * (i))
44
45/* PWMCFG fields */
46#define PWM_SIFIVE_PWMCFG_SCALE GENMASK(3, 0)
47#define PWM_SIFIVE_PWMCFG_STICKY BIT(8)
48#define PWM_SIFIVE_PWMCFG_ZERO_CMP BIT(9)
49#define PWM_SIFIVE_PWMCFG_DEGLITCH BIT(10)
50#define PWM_SIFIVE_PWMCFG_EN_ALWAYS BIT(12)
51#define PWM_SIFIVE_PWMCFG_EN_ONCE BIT(13)
52#define PWM_SIFIVE_PWMCFG_CENTER BIT(16)
53#define PWM_SIFIVE_PWMCFG_GANG BIT(24)
54#define PWM_SIFIVE_PWMCFG_IP BIT(28)
55
56#define PWM_SIFIVE_CMPWIDTH 16
57#define PWM_SIFIVE_DEFAULT_PERIOD 10000000
58
59struct pwm_sifive_ddata {
60 struct device *parent;
61 struct mutex lock; /* lock to protect user_count and approx_period */
62 struct notifier_block notifier;
63 struct clk *clk;
64 void __iomem *regs;
65 unsigned int real_period;
66 unsigned int approx_period;
67 int user_count;
68};
69
70static inline
71struct pwm_sifive_ddata *pwm_sifive_chip_to_ddata(struct pwm_chip *chip)
72{
73 return pwmchip_get_drvdata(chip);
74}
75
76static int pwm_sifive_request(struct pwm_chip *chip, struct pwm_device *pwm)
77{
78 struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
79
80 mutex_lock(&ddata->lock);
81 ddata->user_count++;
82 mutex_unlock(&ddata->lock);
83
84 return 0;
85}
86
87static void pwm_sifive_free(struct pwm_chip *chip, struct pwm_device *pwm)
88{
89 struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
90
91 mutex_lock(&ddata->lock);
92 ddata->user_count--;
93 mutex_unlock(&ddata->lock);
94}
95
96/* Called holding ddata->lock */
97static void pwm_sifive_update_clock(struct pwm_sifive_ddata *ddata,
98 unsigned long rate)
99{
100 unsigned long long num;
101 unsigned long scale_pow;
102 int scale;
103 u32 val;
104 /*
105 * The PWM unit is used with pwmzerocmp=0, so the only way to modify the
106 * period length is using pwmscale which provides the number of bits the
107 * counter is shifted before being feed to the comparators. A period
108 * lasts (1 << (PWM_SIFIVE_CMPWIDTH + pwmscale)) clock ticks.
109 * (1 << (PWM_SIFIVE_CMPWIDTH + scale)) * 10^9/rate = period
110 */
111 scale_pow = div64_ul(ddata->approx_period * (u64)rate, NSEC_PER_SEC);
112 scale = clamp(ilog2(scale_pow) - PWM_SIFIVE_CMPWIDTH, 0, 0xf);
113
114 val = PWM_SIFIVE_PWMCFG_EN_ALWAYS |
115 FIELD_PREP(PWM_SIFIVE_PWMCFG_SCALE, scale);
116 writel(val, ddata->regs + PWM_SIFIVE_PWMCFG);
117
118 /* As scale <= 15 the shift operation cannot overflow. */
119 num = (unsigned long long)NSEC_PER_SEC << (PWM_SIFIVE_CMPWIDTH + scale);
120 ddata->real_period = DIV_ROUND_UP_ULL(num, rate);
121 dev_dbg(ddata->parent,
122 "New real_period = %u ns\n", ddata->real_period);
123}
124
125static int pwm_sifive_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
126 struct pwm_state *state)
127{
128 struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
129 u32 duty, val, inactive;
130
131 inactive = readl(ddata->regs + PWM_SIFIVE_PWMCMP(pwm->hwpwm));
132 /*
133 * PWM hardware uses 'inactive' counts in pwmcmp, so invert to get actual duty.
134 * Here, 'inactive' is the low time and we compute duty as max_count - inactive.
135 */
136 duty = (1U << PWM_SIFIVE_CMPWIDTH) - 1 - inactive;
137
138 state->enabled = duty > 0;
139
140 val = readl(ddata->regs + PWM_SIFIVE_PWMCFG);
141 if (!(val & PWM_SIFIVE_PWMCFG_EN_ALWAYS))
142 state->enabled = false;
143
144 state->period = ddata->real_period;
145 state->duty_cycle = DIV_ROUND_UP_ULL((u64)duty * ddata->real_period,
146 (1U << PWM_SIFIVE_CMPWIDTH));
147 state->polarity = PWM_POLARITY_NORMAL;
148
149 return 0;
150}
151
152static int pwm_sifive_apply(struct pwm_chip *chip, struct pwm_device *pwm,
153 const struct pwm_state *state)
154{
155 struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
156 struct pwm_state cur_state;
157 unsigned int duty_cycle;
158 unsigned long long num;
159 bool enabled;
160 int ret = 0;
161 u64 frac;
162 u32 inactive;
163
164 if (state->polarity != PWM_POLARITY_NORMAL)
165 return -EINVAL;
166
167 cur_state = pwm->state;
168 enabled = cur_state.enabled;
169
170 duty_cycle = state->duty_cycle;
171 if (!state->enabled)
172 duty_cycle = 0;
173
174 /*
175 * The problem of output producing mixed setting as mentioned at top,
176 * occurs here. To minimize the window for this problem, we are
177 * calculating the register values first and then writing them
178 * consecutively
179 */
180 num = (u64)duty_cycle * (1U << PWM_SIFIVE_CMPWIDTH);
181 frac = num;
182 do_div(frac, state->period);
183 /* The hardware cannot generate a 0% duty cycle */
184 frac = min(frac, (u64)(1U << PWM_SIFIVE_CMPWIDTH) - 1);
185 /* pwmcmp register must be loaded with the inactive(invert the duty) */
186 inactive = (1U << PWM_SIFIVE_CMPWIDTH) - 1 - frac;
187
188 mutex_lock(&ddata->lock);
189 if (state->period != ddata->approx_period) {
190 /*
191 * Don't let a 2nd user change the period underneath the 1st user.
192 * However if ddate->approx_period == 0 this is the first time we set
193 * any period, so let whoever gets here first set the period so other
194 * users who agree on the period won't fail.
195 */
196 if (ddata->user_count != 1 && ddata->approx_period) {
197 mutex_unlock(&ddata->lock);
198 return -EBUSY;
199 }
200 ddata->approx_period = state->period;
201 pwm_sifive_update_clock(ddata, clk_get_rate(ddata->clk));
202 }
203 mutex_unlock(&ddata->lock);
204
205 /*
206 * If the PWM is enabled the clk is already on. So only enable it
207 * conditionally to have it on exactly once afterwards independent of
208 * the PWM state.
209 */
210 if (!enabled) {
211 ret = clk_enable(ddata->clk);
212 if (ret) {
213 dev_err(pwmchip_parent(chip), "Enable clk failed\n");
214 return ret;
215 }
216 }
217
218 writel(inactive, ddata->regs + PWM_SIFIVE_PWMCMP(pwm->hwpwm));
219
220 if (!state->enabled)
221 clk_disable(ddata->clk);
222
223 return 0;
224}
225
226static const struct pwm_ops pwm_sifive_ops = {
227 .request = pwm_sifive_request,
228 .free = pwm_sifive_free,
229 .get_state = pwm_sifive_get_state,
230 .apply = pwm_sifive_apply,
231};
232
233static int pwm_sifive_clock_notifier(struct notifier_block *nb,
234 unsigned long event, void *data)
235{
236 struct clk_notifier_data *ndata = data;
237 struct pwm_sifive_ddata *ddata =
238 container_of(nb, struct pwm_sifive_ddata, notifier);
239
240 if (event == POST_RATE_CHANGE) {
241 mutex_lock(&ddata->lock);
242 pwm_sifive_update_clock(ddata, ndata->new_rate);
243 mutex_unlock(&ddata->lock);
244 }
245
246 return NOTIFY_OK;
247}
248
249static int pwm_sifive_probe(struct platform_device *pdev)
250{
251 struct device *dev = &pdev->dev;
252 struct pwm_sifive_ddata *ddata;
253 struct pwm_chip *chip;
254 int ret;
255 u32 val;
256 unsigned int enabled_pwms = 0, enabled_clks = 1;
257
258 chip = devm_pwmchip_alloc(dev, 4, sizeof(*ddata));
259 if (IS_ERR(chip))
260 return PTR_ERR(chip);
261
262 ddata = pwm_sifive_chip_to_ddata(chip);
263 ddata->parent = dev;
264 mutex_init(&ddata->lock);
265 chip->ops = &pwm_sifive_ops;
266
267 ddata->regs = devm_platform_ioremap_resource(pdev, 0);
268 if (IS_ERR(ddata->regs))
269 return PTR_ERR(ddata->regs);
270
271 ddata->clk = devm_clk_get_prepared(dev, NULL);
272 if (IS_ERR(ddata->clk))
273 return dev_err_probe(dev, PTR_ERR(ddata->clk),
274 "Unable to find controller clock\n");
275
276 ret = clk_enable(ddata->clk);
277 if (ret) {
278 dev_err(dev, "failed to enable clock for pwm: %d\n", ret);
279 return ret;
280 }
281
282 val = readl(ddata->regs + PWM_SIFIVE_PWMCFG);
283 if (val & PWM_SIFIVE_PWMCFG_EN_ALWAYS) {
284 unsigned int i;
285
286 for (i = 0; i < chip->npwm; ++i) {
287 val = readl(ddata->regs + PWM_SIFIVE_PWMCMP(i));
288 if (val > 0)
289 ++enabled_pwms;
290 }
291 }
292
293 /* The clk should be on once for each running PWM. */
294 if (enabled_pwms) {
295 while (enabled_clks < enabled_pwms) {
296 /* This is not expected to fail as the clk is already on */
297 ret = clk_enable(ddata->clk);
298 if (unlikely(ret)) {
299 dev_err_probe(dev, ret, "Failed to enable clk\n");
300 goto disable_clk;
301 }
302 ++enabled_clks;
303 }
304 } else {
305 clk_disable(ddata->clk);
306 enabled_clks = 0;
307 }
308
309 /* Watch for changes to underlying clock frequency */
310 ddata->notifier.notifier_call = pwm_sifive_clock_notifier;
311 ret = clk_notifier_register(ddata->clk, &ddata->notifier);
312 if (ret) {
313 dev_err(dev, "failed to register clock notifier: %d\n", ret);
314 goto disable_clk;
315 }
316
317 ret = pwmchip_add(chip);
318 if (ret < 0) {
319 dev_err(dev, "cannot register PWM: %d\n", ret);
320 goto unregister_clk;
321 }
322
323 platform_set_drvdata(pdev, chip);
324 dev_dbg(dev, "SiFive PWM chip registered %d PWMs\n", chip->npwm);
325
326 return 0;
327
328unregister_clk:
329 clk_notifier_unregister(ddata->clk, &ddata->notifier);
330disable_clk:
331 while (enabled_clks) {
332 clk_disable(ddata->clk);
333 --enabled_clks;
334 }
335
336 return ret;
337}
338
339static void pwm_sifive_remove(struct platform_device *dev)
340{
341 struct pwm_chip *chip = platform_get_drvdata(dev);
342 struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
343 struct pwm_device *pwm;
344 int ch;
345
346 pwmchip_remove(chip);
347 clk_notifier_unregister(ddata->clk, &ddata->notifier);
348
349 for (ch = 0; ch < chip->npwm; ch++) {
350 pwm = &chip->pwms[ch];
351 if (pwm->state.enabled)
352 clk_disable(ddata->clk);
353 }
354}
355
356static const struct of_device_id pwm_sifive_of_match[] = {
357 { .compatible = "sifive,pwm0" },
358 { }
359};
360MODULE_DEVICE_TABLE(of, pwm_sifive_of_match);
361
362static struct platform_driver pwm_sifive_driver = {
363 .probe = pwm_sifive_probe,
364 .remove = pwm_sifive_remove,
365 .driver = {
366 .name = "pwm-sifive",
367 .of_match_table = pwm_sifive_of_match,
368 },
369};
370module_platform_driver(pwm_sifive_driver);
371
372MODULE_DESCRIPTION("SiFive PWM driver");
373MODULE_LICENSE("GPL v2");