projects/linux·blob master · refs

295 lines · 7.7 KiB

1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2019 Spreadtrum Communications Inc.
4 */
5
6#include <linux/clk.h>
7#include <linux/err.h>
8#include <linux/io.h>
9#include <linux/math64.h>
10#include <linux/module.h>
11#include <linux/platform_device.h>
12#include <linux/pwm.h>
13
14#define SPRD_PWM_PRESCALE 0x0
15#define SPRD_PWM_MOD 0x4
16#define SPRD_PWM_DUTY 0x8
17#define SPRD_PWM_ENABLE 0x18
18
19#define SPRD_PWM_MOD_MAX GENMASK(7, 0)
20#define SPRD_PWM_DUTY_MSK GENMASK(15, 0)
21#define SPRD_PWM_PRESCALE_MSK GENMASK(7, 0)
22#define SPRD_PWM_ENABLE_BIT BIT(0)
23
24#define SPRD_PWM_CHN_NUM 4
25#define SPRD_PWM_REGS_SHIFT 5
26#define SPRD_PWM_CHN_CLKS_NUM 2
27#define SPRD_PWM_CHN_OUTPUT_CLK 1
28
29struct sprd_pwm_chn {
30 struct clk_bulk_data clks[SPRD_PWM_CHN_CLKS_NUM];
31 u32 clk_rate;
32};
33
34struct sprd_pwm_chip {
35 void __iomem *base;
36 struct sprd_pwm_chn chn[SPRD_PWM_CHN_NUM];
37};
38
39static inline struct sprd_pwm_chip* sprd_pwm_from_chip(struct pwm_chip *chip)
40{
41 return pwmchip_get_drvdata(chip);
42}
43
44/*
45 * The list of clocks required by PWM channels, and each channel has 2 clocks:
46 * enable clock and pwm clock.
47 */
48static const char * const sprd_pwm_clks[] = {
49 "enable0", "pwm0",
50 "enable1", "pwm1",
51 "enable2", "pwm2",
52 "enable3", "pwm3",
53};
54
55static u32 sprd_pwm_read(struct sprd_pwm_chip *spc, u32 hwid, u32 reg)
56{
57 u32 offset = reg + (hwid << SPRD_PWM_REGS_SHIFT);
58
59 return readl_relaxed(spc->base + offset);
60}
61
62static void sprd_pwm_write(struct sprd_pwm_chip *spc, u32 hwid,
63 u32 reg, u32 val)
64{
65 u32 offset = reg + (hwid << SPRD_PWM_REGS_SHIFT);
66
67 writel_relaxed(val, spc->base + offset);
68}
69
70static int sprd_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
71 struct pwm_state *state)
72{
73 struct sprd_pwm_chip *spc = sprd_pwm_from_chip(chip);
74 struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm];
75 u32 val, duty, prescale;
76 u64 tmp;
77 int ret;
78
79 /*
80 * The clocks to PWM channel has to be enabled first before
81 * reading to the registers.
82 */
83 ret = clk_bulk_prepare_enable(SPRD_PWM_CHN_CLKS_NUM, chn->clks);
84 if (ret) {
85 dev_err(pwmchip_parent(chip), "failed to enable pwm%u clocks\n",
86 pwm->hwpwm);
87 return ret;
88 }
89
90 val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_ENABLE);
91 if (val & SPRD_PWM_ENABLE_BIT)
92 state->enabled = true;
93 else
94 state->enabled = false;
95
96 /*
97 * The hardware provides a counter that is feed by the source clock.
98 * The period length is (PRESCALE + 1) * MOD counter steps.
99 * The duty cycle length is (PRESCALE + 1) * DUTY counter steps.
100 * Thus the period_ns and duty_ns calculation formula should be:
101 * period_ns = NSEC_PER_SEC * (prescale + 1) * mod / clk_rate
102 * duty_ns = NSEC_PER_SEC * (prescale + 1) * duty / clk_rate
103 */
104 val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_PRESCALE);
105 prescale = val & SPRD_PWM_PRESCALE_MSK;
106 tmp = (prescale + 1) * NSEC_PER_SEC * SPRD_PWM_MOD_MAX;
107 state->period = DIV_ROUND_CLOSEST_ULL(tmp, chn->clk_rate);
108
109 val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_DUTY);
110 duty = val & SPRD_PWM_DUTY_MSK;
111 tmp = (prescale + 1) * NSEC_PER_SEC * duty;
112 state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, chn->clk_rate);
113 state->polarity = PWM_POLARITY_NORMAL;
114
115 /* Disable PWM clocks if the PWM channel is not in enable state. */
116 if (!state->enabled)
117 clk_bulk_disable_unprepare(SPRD_PWM_CHN_CLKS_NUM, chn->clks);
118
119 return 0;
120}
121
122static int sprd_pwm_config(struct sprd_pwm_chip *spc, struct pwm_device *pwm,
123 int duty_ns, int period_ns)
124{
125 struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm];
126 u32 prescale, duty;
127 u64 tmp;
128
129 /*
130 * The hardware provides a counter that is feed by the source clock.
131 * The period length is (PRESCALE + 1) * MOD counter steps.
132 * The duty cycle length is (PRESCALE + 1) * DUTY counter steps.
133 *
134 * To keep the maths simple we're always using MOD = SPRD_PWM_MOD_MAX.
135 * The value for PRESCALE is selected such that the resulting period
136 * gets the maximal length not bigger than the requested one with the
137 * given settings (MOD = SPRD_PWM_MOD_MAX and input clock).
138 */
139 duty = duty_ns * SPRD_PWM_MOD_MAX / period_ns;
140
141 tmp = (u64)chn->clk_rate * period_ns;
142 do_div(tmp, NSEC_PER_SEC);
143 prescale = DIV_ROUND_CLOSEST_ULL(tmp, SPRD_PWM_MOD_MAX) - 1;
144 if (prescale > SPRD_PWM_PRESCALE_MSK)
145 prescale = SPRD_PWM_PRESCALE_MSK;
146
147 /*
148 * Note: Writing DUTY triggers the hardware to actually apply the
149 * values written to MOD and DUTY to the output, so must keep writing
150 * DUTY last.
151 *
152 * The hardware can ensures that current running period is completed
153 * before changing a new configuration to avoid mixed settings.
154 */
155 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_PRESCALE, prescale);
156 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_MOD, SPRD_PWM_MOD_MAX);
157 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_DUTY, duty);
158
159 return 0;
160}
161
162static int sprd_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
163 const struct pwm_state *state)
164{
165 struct sprd_pwm_chip *spc = sprd_pwm_from_chip(chip);
166 struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm];
167 struct pwm_state *cstate = &pwm->state;
168 int ret;
169
170 if (state->polarity != PWM_POLARITY_NORMAL)
171 return -EINVAL;
172
173 if (state->enabled) {
174 if (!cstate->enabled) {
175 /*
176 * The clocks to PWM channel has to be enabled first
177 * before writing to the registers.
178 */
179 ret = clk_bulk_prepare_enable(SPRD_PWM_CHN_CLKS_NUM,
180 chn->clks);
181 if (ret) {
182 dev_err(pwmchip_parent(chip),
183 "failed to enable pwm%u clocks\n",
184 pwm->hwpwm);
185 return ret;
186 }
187 }
188
189 ret = sprd_pwm_config(spc, pwm, state->duty_cycle,
190 state->period);
191 if (ret)
192 return ret;
193
194 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_ENABLE, 1);
195 } else if (cstate->enabled) {
196 /*
197 * Note: After setting SPRD_PWM_ENABLE to zero, the controller
198 * will not wait for current period to be completed, instead it
199 * will stop the PWM channel immediately.
200 */
201 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_ENABLE, 0);
202
203 clk_bulk_disable_unprepare(SPRD_PWM_CHN_CLKS_NUM, chn->clks);
204 }
205
206 return 0;
207}
208
209static const struct pwm_ops sprd_pwm_ops = {
210 .apply = sprd_pwm_apply,
211 .get_state = sprd_pwm_get_state,
212};
213
214static int sprd_pwm_clk_init(struct device *dev,
215 struct sprd_pwm_chn chn[SPRD_PWM_CHN_NUM])
216{
217 struct clk *clk_pwm;
218 int ret, i;
219
220 for (i = 0; i < SPRD_PWM_CHN_NUM; i++) {
221 int j;
222
223 for (j = 0; j < SPRD_PWM_CHN_CLKS_NUM; ++j)
224 chn[i].clks[j].id =
225 sprd_pwm_clks[i * SPRD_PWM_CHN_CLKS_NUM + j];
226
227 ret = devm_clk_bulk_get(dev, SPRD_PWM_CHN_CLKS_NUM,
228 chn[i].clks);
229 if (ret) {
230 if (ret == -ENOENT)
231 break;
232
233 return dev_err_probe(dev, ret,
234 "failed to get channel clocks\n");
235 }
236
237 clk_pwm = chn[i].clks[SPRD_PWM_CHN_OUTPUT_CLK].clk;
238 chn[i].clk_rate = clk_get_rate(clk_pwm);
239 }
240
241 if (!i)
242 return dev_err_probe(dev, -ENODEV, "no available PWM channels\n");
243
244 return i;
245}
246
247static int sprd_pwm_probe(struct platform_device *pdev)
248{
249 struct pwm_chip *chip;
250 struct sprd_pwm_chip *spc;
251 struct sprd_pwm_chn chn[SPRD_PWM_CHN_NUM];
252 int ret, npwm;
253
254 npwm = sprd_pwm_clk_init(&pdev->dev, chn);
255 if (npwm < 0)
256 return npwm;
257
258 chip = devm_pwmchip_alloc(&pdev->dev, npwm, sizeof(*spc));
259 if (IS_ERR(chip))
260 return PTR_ERR(chip);
261 spc = sprd_pwm_from_chip(chip);
262
263 spc->base = devm_platform_ioremap_resource(pdev, 0);
264 if (IS_ERR(spc->base))
265 return PTR_ERR(spc->base);
266
267 memcpy(spc->chn, chn, sizeof(chn));
268
269 chip->ops = &sprd_pwm_ops;
270
271 ret = devm_pwmchip_add(&pdev->dev, chip);
272 if (ret)
273 dev_err(&pdev->dev, "failed to add PWM chip\n");
274
275 return ret;
276}
277
278static const struct of_device_id sprd_pwm_of_match[] = {
279 { .compatible = "sprd,ums512-pwm" },
280 { }
281};
282MODULE_DEVICE_TABLE(of, sprd_pwm_of_match);
283
284static struct platform_driver sprd_pwm_driver = {
285 .driver = {
286 .name = "sprd-pwm",
287 .of_match_table = sprd_pwm_of_match,
288 },
289 .probe = sprd_pwm_probe,
290};
291
292module_platform_driver(sprd_pwm_driver);
293
294MODULE_DESCRIPTION("Spreadtrum PWM Driver");
295MODULE_LICENSE("GPL v2");