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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) STMicroelectronics 2016
4 *
5 * Author: Gerald Baeza <[email protected]>
6 *
7 * Inspired by timer-stm32.c from Maxime Coquelin
8 * pwm-atmel.c from Bo Shen
9 */
10
11#include <linux/bitfield.h>
12#include <linux/mfd/stm32-timers.h>
13#include <linux/module.h>
14#include <linux/of.h>
15#include <linux/pinctrl/consumer.h>
16#include <linux/platform_device.h>
17#include <linux/pwm.h>
18
19#define CCMR_CHANNEL_SHIFT 8
20#define CCMR_CHANNEL_MASK 0xFF
21#define MAX_BREAKINPUT 2
22#define STM32_MAX_PWM_OUTPUT 4
23
24struct stm32_breakinput {
25 u32 index;
26 u32 level;
27 u32 filter;
28};
29
30struct stm32_pwm {
31 struct mutex lock; /* protect pwm config/enable */
32 struct clk *clk;
33 struct regmap *regmap;
34 u32 max_arr;
35 bool have_complementary_output;
36 struct stm32_breakinput breakinputs[MAX_BREAKINPUT];
37 unsigned int num_breakinputs;
38 u32 capture[4] ____cacheline_aligned; /* DMA'able buffer */
39};
40
41static inline struct stm32_pwm *to_stm32_pwm_dev(struct pwm_chip *chip)
42{
43 return pwmchip_get_drvdata(chip);
44}
45
46static u32 active_channels(struct stm32_pwm *dev)
47{
48 u32 ccer;
49
50 regmap_read(dev->regmap, TIM_CCER, &ccer);
51
52 return ccer & TIM_CCER_CCXE;
53}
54
55struct stm32_pwm_waveform {
56 u32 ccer;
57 u32 psc;
58 u32 arr;
59 u32 ccr;
60};
61
62static int stm32_pwm_round_waveform_tohw(struct pwm_chip *chip,
63 struct pwm_device *pwm,
64 const struct pwm_waveform *wf,
65 void *_wfhw)
66{
67 struct stm32_pwm_waveform *wfhw = _wfhw;
68 struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
69 unsigned int ch = pwm->hwpwm;
70 unsigned long rate;
71 u64 duty_ticks, offset_ticks;
72 int ret;
73
74 if (wf->period_length_ns == 0) {
75 *wfhw = (struct stm32_pwm_waveform){
76 .ccer = 0,
77 };
78
79 return 0;
80 }
81
82 ret = clk_enable(priv->clk);
83 if (ret)
84 return ret;
85
86 wfhw->ccer = TIM_CCER_CCxE(ch + 1);
87 if (priv->have_complementary_output)
88 wfhw->ccer |= TIM_CCER_CCxNE(ch + 1);
89
90 rate = clk_get_rate(priv->clk);
91
92 if (active_channels(priv) & ~TIM_CCER_CCxE(ch + 1)) {
93 u64 arr;
94
95 /*
96 * Other channels are already enabled, so the configured PSC and
97 * ARR must be used for this channel, too.
98 */
99 ret = regmap_read(priv->regmap, TIM_PSC, &wfhw->psc);
100 if (ret)
101 goto out;
102
103 ret = regmap_read(priv->regmap, TIM_ARR, &wfhw->arr);
104 if (ret)
105 goto out;
106
107 arr = mul_u64_u64_div_u64(wf->period_length_ns, rate,
108 (u64)NSEC_PER_SEC * (wfhw->psc + 1));
109 if (arr <= wfhw->arr) {
110 /*
111 * requested period is smaller than the currently
112 * configured and unchangable period, report back the smallest
113 * possible period, i.e. the current state and return 1
114 * to indicate the wrong rounding direction.
115 */
116 ret = 1;
117 }
118
119 } else {
120 /*
121 * .probe() asserted that clk_get_rate() is not bigger than 1 GHz, so
122 * the calculations here won't overflow.
123 * First we need to find the minimal value for prescaler such that
124 *
125 * period_ns * clkrate
126 * ------------------------------ < max_arr + 1
127 * NSEC_PER_SEC * (prescaler + 1)
128 *
129 * This equation is equivalent to
130 *
131 * period_ns * clkrate
132 * ---------------------------- < prescaler + 1
133 * NSEC_PER_SEC * (max_arr + 1)
134 *
135 * Using integer division and knowing that the right hand side is
136 * integer, this is further equivalent to
137 *
138 * (period_ns * clkrate) // (NSEC_PER_SEC * (max_arr + 1)) ≤ prescaler
139 */
140 u64 psc = mul_u64_u64_div_u64(wf->period_length_ns, rate,
141 (u64)NSEC_PER_SEC * ((u64)priv->max_arr + 1));
142 u64 arr;
143
144 wfhw->psc = min_t(u64, psc, MAX_TIM_PSC);
145
146 arr = mul_u64_u64_div_u64(wf->period_length_ns, rate,
147 (u64)NSEC_PER_SEC * (wfhw->psc + 1));
148 if (!arr) {
149 /*
150 * requested period is too small, report back the smallest
151 * possible period, i.e. ARR = 0. The only valid CCR
152 * value is then zero, too.
153 */
154 wfhw->arr = 0;
155 wfhw->ccr = 0;
156 ret = 1;
157 goto out;
158 }
159
160 /*
161 * ARR is limited intentionally to values less than
162 * priv->max_arr to allow 100% duty cycle.
163 */
164 wfhw->arr = min_t(u64, arr, priv->max_arr) - 1;
165 }
166
167 duty_ticks = mul_u64_u64_div_u64(wf->duty_length_ns, rate,
168 (u64)NSEC_PER_SEC * (wfhw->psc + 1));
169 duty_ticks = min_t(u64, duty_ticks, wfhw->arr + 1);
170
171 offset_ticks = mul_u64_u64_div_u64(wf->duty_offset_ns, rate,
172 (u64)NSEC_PER_SEC * (wfhw->psc + 1));
173 offset_ticks = min_t(u64, offset_ticks, wfhw->arr + 1);
174
175 if (duty_ticks && offset_ticks &&
176 duty_ticks + offset_ticks >= wfhw->arr + 1) {
177 wfhw->ccer |= TIM_CCER_CCxP(ch + 1);
178 if (priv->have_complementary_output)
179 wfhw->ccer |= TIM_CCER_CCxNP(ch + 1);
180
181 wfhw->ccr = wfhw->arr + 1 - duty_ticks;
182 } else {
183 wfhw->ccr = duty_ticks;
184 }
185
186out:
187 dev_dbg(&chip->dev, "pwm#%u: %lld/%lld [+%lld] @%lu -> CCER: %08x, PSC: %08x, ARR: %08x, CCR: %08x\n",
188 pwm->hwpwm, wf->duty_length_ns, wf->period_length_ns, wf->duty_offset_ns,
189 rate, wfhw->ccer, wfhw->psc, wfhw->arr, wfhw->ccr);
190
191 clk_disable(priv->clk);
192
193 return ret;
194}
195
196static int stm32_pwm_round_waveform_fromhw(struct pwm_chip *chip,
197 struct pwm_device *pwm,
198 const void *_wfhw,
199 struct pwm_waveform *wf)
200{
201 const struct stm32_pwm_waveform *wfhw = _wfhw;
202 struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
203 unsigned long rate = clk_get_rate(priv->clk);
204 unsigned int ch = pwm->hwpwm;
205
206 if (wfhw->ccer & TIM_CCER_CCxE(ch + 1)) {
207 u64 ccr_ns;
208
209 /* The result doesn't overflow for rate >= 15259 */
210 wf->period_length_ns = mul_u64_u64_div_u64_roundup(((u64)wfhw->psc + 1) * (wfhw->arr + 1),
211 NSEC_PER_SEC, rate);
212
213 ccr_ns = mul_u64_u64_div_u64_roundup(((u64)wfhw->psc + 1) * wfhw->ccr, NSEC_PER_SEC, rate);
214
215 if (wfhw->ccer & TIM_CCER_CCxP(ch + 1)) {
216 wf->duty_length_ns =
217 mul_u64_u64_div_u64_roundup(((u64)wfhw->psc + 1) * (wfhw->arr + 1 - wfhw->ccr),
218 NSEC_PER_SEC, rate);
219
220 wf->duty_offset_ns = ccr_ns;
221 } else {
222 wf->duty_length_ns = ccr_ns;
223 wf->duty_offset_ns = 0;
224 }
225 } else {
226 *wf = (struct pwm_waveform){
227 .period_length_ns = 0,
228 };
229 }
230
231 dev_dbg(&chip->dev, "pwm#%u: CCER: %08x, PSC: %08x, ARR: %08x, CCR: %08x @%lu -> %lld/%lld [+%lld]\n",
232 pwm->hwpwm, wfhw->ccer, wfhw->psc, wfhw->arr, wfhw->ccr, rate,
233 wf->duty_length_ns, wf->period_length_ns, wf->duty_offset_ns);
234
235 return 0;
236}
237
238static int stm32_pwm_read_waveform(struct pwm_chip *chip,
239 struct pwm_device *pwm,
240 void *_wfhw)
241{
242 struct stm32_pwm_waveform *wfhw = _wfhw;
243 struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
244 unsigned int ch = pwm->hwpwm;
245 int ret;
246
247 ret = clk_enable(priv->clk);
248 if (ret)
249 return ret;
250
251 ret = regmap_read(priv->regmap, TIM_CCER, &wfhw->ccer);
252 if (ret)
253 goto out;
254
255 if (wfhw->ccer & TIM_CCER_CCxE(ch + 1)) {
256 ret = regmap_read(priv->regmap, TIM_PSC, &wfhw->psc);
257 if (ret)
258 goto out;
259
260 ret = regmap_read(priv->regmap, TIM_ARR, &wfhw->arr);
261 if (ret)
262 goto out;
263
264 if (wfhw->arr == U32_MAX)
265 wfhw->arr -= 1;
266
267 ret = regmap_read(priv->regmap, TIM_CCRx(ch + 1), &wfhw->ccr);
268 if (ret)
269 goto out;
270
271 if (wfhw->ccr > wfhw->arr + 1)
272 wfhw->ccr = wfhw->arr + 1;
273 }
274
275out:
276 clk_disable(priv->clk);
277
278 return ret;
279}
280
281static int stm32_pwm_write_waveform(struct pwm_chip *chip,
282 struct pwm_device *pwm,
283 const void *_wfhw)
284{
285 const struct stm32_pwm_waveform *wfhw = _wfhw;
286 struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
287 unsigned int ch = pwm->hwpwm;
288 int ret;
289
290 ret = clk_enable(priv->clk);
291 if (ret)
292 return ret;
293
294 if (wfhw->ccer & TIM_CCER_CCxE(ch + 1)) {
295 u32 ccer, mask;
296 unsigned int shift;
297 u32 ccmr;
298
299 ret = regmap_read(priv->regmap, TIM_CCER, &ccer);
300 if (ret)
301 goto out;
302
303 /* If there are other channels enabled, don't update PSC and ARR */
304 if (ccer & ~TIM_CCER_CCxE(ch + 1) & TIM_CCER_CCXE) {
305 u32 psc, arr;
306
307 ret = regmap_read(priv->regmap, TIM_PSC, &psc);
308 if (ret)
309 goto out;
310
311 if (psc != wfhw->psc) {
312 ret = -EBUSY;
313 goto out;
314 }
315
316 ret = regmap_read(priv->regmap, TIM_ARR, &arr);
317 if (ret)
318 goto out;
319
320 if (arr != wfhw->arr) {
321 ret = -EBUSY;
322 goto out;
323 }
324 } else {
325 ret = regmap_write(priv->regmap, TIM_PSC, wfhw->psc);
326 if (ret)
327 goto out;
328
329 ret = regmap_write(priv->regmap, TIM_ARR, wfhw->arr);
330 if (ret)
331 goto out;
332
333 ret = regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE);
334 if (ret)
335 goto out;
336
337 }
338
339 /* set polarity */
340 mask = TIM_CCER_CCxP(ch + 1) | TIM_CCER_CCxNP(ch + 1);
341 ret = regmap_update_bits(priv->regmap, TIM_CCER, mask, wfhw->ccer);
342 if (ret)
343 goto out;
344
345 ret = regmap_write(priv->regmap, TIM_CCRx(ch + 1), wfhw->ccr);
346 if (ret)
347 goto out;
348
349 /* Configure output mode */
350 shift = (ch & 0x1) * CCMR_CHANNEL_SHIFT;
351 ccmr = (TIM_CCMR_PE | TIM_CCMR_M1) << shift;
352 mask = CCMR_CHANNEL_MASK << shift;
353
354 if (ch < 2)
355 ret = regmap_update_bits(priv->regmap, TIM_CCMR1, mask, ccmr);
356 else
357 ret = regmap_update_bits(priv->regmap, TIM_CCMR2, mask, ccmr);
358 if (ret)
359 goto out;
360
361 ret = regmap_set_bits(priv->regmap, TIM_BDTR, TIM_BDTR_MOE);
362 if (ret)
363 goto out;
364
365 if (!(ccer & TIM_CCER_CCxE(ch + 1))) {
366 mask = TIM_CCER_CCxE(ch + 1) | TIM_CCER_CCxNE(ch + 1);
367
368 ret = clk_enable(priv->clk);
369 if (ret)
370 goto out;
371
372 ccer = (ccer & ~mask) | (wfhw->ccer & mask);
373 regmap_write(priv->regmap, TIM_CCER, ccer);
374
375 /* Make sure that registers are updated */
376 regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG);
377
378 /* Enable controller */
379 regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
380 }
381
382 } else {
383 /* disable channel */
384 u32 mask, ccer;
385
386 mask = TIM_CCER_CCxE(ch + 1);
387 if (priv->have_complementary_output)
388 mask |= TIM_CCER_CCxNE(ch + 1);
389
390 ret = regmap_read(priv->regmap, TIM_CCER, &ccer);
391 if (ret)
392 goto out;
393
394 if (ccer & mask) {
395 ccer = ccer & ~mask;
396
397 ret = regmap_write(priv->regmap, TIM_CCER, ccer);
398 if (ret)
399 goto out;
400
401 if (!(ccer & TIM_CCER_CCXE)) {
402 /* When all channels are disabled, we can disable the controller */
403 ret = regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
404 if (ret)
405 goto out;
406 }
407
408 clk_disable(priv->clk);
409 }
410 }
411
412out:
413 clk_disable(priv->clk);
414
415 return ret;
416}
417
418#define TIM_CCER_CC12P (TIM_CCER_CC1P | TIM_CCER_CC2P)
419#define TIM_CCER_CC12E (TIM_CCER_CC1E | TIM_CCER_CC2E)
420#define TIM_CCER_CC34P (TIM_CCER_CC3P | TIM_CCER_CC4P)
421#define TIM_CCER_CC34E (TIM_CCER_CC3E | TIM_CCER_CC4E)
422
423/*
424 * Capture using PWM input mode:
425 * ___ ___
426 * TI[1, 2, 3 or 4]: ........._| |________|
427 * ^0 ^1 ^2
428 * . . .
429 * . . XXXXX
430 * . . XXXXX |
431 * . XXXXX . |
432 * XXXXX . . |
433 * COUNTER: ______XXXXX . . . |_XXX
434 * start^ . . . ^stop
435 * . . . .
436 * v v . v
437 * v
438 * CCR1/CCR3: tx..........t0...........t2
439 * CCR2/CCR4: tx..............t1.........
440 *
441 * DMA burst transfer: | |
442 * v v
443 * DMA buffer: { t0, tx } { t2, t1 }
444 * DMA done: ^
445 *
446 * 0: IC1/3 snapchot on rising edge: counter value -> CCR1/CCR3
447 * + DMA transfer CCR[1/3] & CCR[2/4] values (t0, tx: doesn't care)
448 * 1: IC2/4 snapchot on falling edge: counter value -> CCR2/CCR4
449 * 2: IC1/3 snapchot on rising edge: counter value -> CCR1/CCR3
450 * + DMA transfer CCR[1/3] & CCR[2/4] values (t2, t1)
451 *
452 * DMA done, compute:
453 * - Period = t2 - t0
454 * - Duty cycle = t1 - t0
455 */
456static int stm32_pwm_raw_capture(struct pwm_chip *chip, struct pwm_device *pwm,
457 unsigned long tmo_ms, u32 *raw_prd,
458 u32 *raw_dty)
459{
460 struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
461 struct device *parent = pwmchip_parent(chip)->parent;
462 enum stm32_timers_dmas dma_id;
463 u32 ccen, ccr;
464 int ret;
465
466 /* Ensure registers have been updated, enable counter and capture */
467 regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG);
468 regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
469
470 /* Use cc1 or cc3 DMA resp for PWM input channels 1 & 2 or 3 & 4 */
471 dma_id = pwm->hwpwm < 2 ? STM32_TIMERS_DMA_CH1 : STM32_TIMERS_DMA_CH3;
472 ccen = pwm->hwpwm < 2 ? TIM_CCER_CC12E : TIM_CCER_CC34E;
473 ccr = pwm->hwpwm < 2 ? TIM_CCR1 : TIM_CCR3;
474 regmap_set_bits(priv->regmap, TIM_CCER, ccen);
475
476 /*
477 * Timer DMA burst mode. Request 2 registers, 2 bursts, to get both
478 * CCR1 & CCR2 (or CCR3 & CCR4) on each capture event.
479 * We'll get two capture snapchots: { CCR1, CCR2 }, { CCR1, CCR2 }
480 * or { CCR3, CCR4 }, { CCR3, CCR4 }
481 */
482 ret = stm32_timers_dma_burst_read(parent, priv->capture, dma_id, ccr, 2,
483 2, tmo_ms);
484 if (ret)
485 goto stop;
486
487 /* Period: t2 - t0 (take care of counter overflow) */
488 if (priv->capture[0] <= priv->capture[2])
489 *raw_prd = priv->capture[2] - priv->capture[0];
490 else
491 *raw_prd = priv->max_arr - priv->capture[0] + priv->capture[2];
492
493 /* Duty cycle capture requires at least two capture units */
494 if (pwm->chip->npwm < 2)
495 *raw_dty = 0;
496 else if (priv->capture[0] <= priv->capture[3])
497 *raw_dty = priv->capture[3] - priv->capture[0];
498 else
499 *raw_dty = priv->max_arr - priv->capture[0] + priv->capture[3];
500
501 if (*raw_dty > *raw_prd) {
502 /*
503 * Race beetween PWM input and DMA: it may happen
504 * falling edge triggers new capture on TI2/4 before DMA
505 * had a chance to read CCR2/4. It means capture[1]
506 * contains period + duty_cycle. So, subtract period.
507 */
508 *raw_dty -= *raw_prd;
509 }
510
511stop:
512 regmap_clear_bits(priv->regmap, TIM_CCER, ccen);
513 regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
514
515 return ret;
516}
517
518static int stm32_pwm_capture(struct pwm_chip *chip, struct pwm_device *pwm,
519 struct pwm_capture *result, unsigned long tmo_ms)
520{
521 struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
522 unsigned long long prd, div, dty;
523 unsigned long rate;
524 unsigned int psc = 0, icpsc, scale;
525 u32 raw_prd = 0, raw_dty = 0;
526 int ret = 0;
527
528 mutex_lock(&priv->lock);
529
530 if (active_channels(priv)) {
531 ret = -EBUSY;
532 goto unlock;
533 }
534
535 ret = clk_enable(priv->clk);
536 if (ret) {
537 dev_err(pwmchip_parent(chip), "failed to enable counter clock\n");
538 goto unlock;
539 }
540
541 rate = clk_get_rate(priv->clk);
542 if (!rate) {
543 ret = -EINVAL;
544 goto clk_dis;
545 }
546
547 /* prescaler: fit timeout window provided by upper layer */
548 div = (unsigned long long)rate * (unsigned long long)tmo_ms;
549 do_div(div, MSEC_PER_SEC);
550 prd = div;
551 while ((div > priv->max_arr) && (psc < MAX_TIM_PSC)) {
552 psc++;
553 div = prd;
554 do_div(div, psc + 1);
555 }
556 regmap_write(priv->regmap, TIM_ARR, priv->max_arr);
557 regmap_write(priv->regmap, TIM_PSC, psc);
558
559 /* Reset input selector to its default input and disable slave mode */
560 regmap_write(priv->regmap, TIM_TISEL, 0x0);
561 regmap_write(priv->regmap, TIM_SMCR, 0x0);
562
563 /* Map TI1 or TI2 PWM input to IC1 & IC2 (or TI3/4 to IC3 & IC4) */
564 regmap_update_bits(priv->regmap,
565 pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2,
566 TIM_CCMR_CC1S | TIM_CCMR_CC2S, pwm->hwpwm & 0x1 ?
567 TIM_CCMR_CC1S_TI2 | TIM_CCMR_CC2S_TI2 :
568 TIM_CCMR_CC1S_TI1 | TIM_CCMR_CC2S_TI1);
569
570 /* Capture period on IC1/3 rising edge, duty cycle on IC2/4 falling. */
571 regmap_update_bits(priv->regmap, TIM_CCER, pwm->hwpwm < 2 ?
572 TIM_CCER_CC12P : TIM_CCER_CC34P, pwm->hwpwm < 2 ?
573 TIM_CCER_CC2P : TIM_CCER_CC4P);
574
575 ret = stm32_pwm_raw_capture(chip, pwm, tmo_ms, &raw_prd, &raw_dty);
576 if (ret)
577 goto stop;
578
579 /*
580 * Got a capture. Try to improve accuracy at high rates:
581 * - decrease counter clock prescaler, scale up to max rate.
582 * - use input prescaler, capture once every /2 /4 or /8 edges.
583 */
584 if (raw_prd) {
585 u32 max_arr = priv->max_arr - 0x1000; /* arbitrary margin */
586
587 scale = max_arr / min(max_arr, raw_prd);
588 } else {
589 scale = priv->max_arr; /* below resolution, use max scale */
590 }
591
592 if (psc && scale > 1) {
593 /* 2nd measure with new scale */
594 psc /= scale;
595 regmap_write(priv->regmap, TIM_PSC, psc);
596 ret = stm32_pwm_raw_capture(chip, pwm, tmo_ms, &raw_prd,
597 &raw_dty);
598 if (ret)
599 goto stop;
600 }
601
602 /* Compute intermediate period not to exceed timeout at low rates */
603 prd = (unsigned long long)raw_prd * (psc + 1) * NSEC_PER_SEC;
604 do_div(prd, rate);
605
606 for (icpsc = 0; icpsc < MAX_TIM_ICPSC ; icpsc++) {
607 /* input prescaler: also keep arbitrary margin */
608 if (raw_prd >= (priv->max_arr - 0x1000) >> (icpsc + 1))
609 break;
610 if (prd >= (tmo_ms * NSEC_PER_MSEC) >> (icpsc + 2))
611 break;
612 }
613
614 if (!icpsc)
615 goto done;
616
617 /* Last chance to improve period accuracy, using input prescaler */
618 regmap_update_bits(priv->regmap,
619 pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2,
620 TIM_CCMR_IC1PSC | TIM_CCMR_IC2PSC,
621 FIELD_PREP(TIM_CCMR_IC1PSC, icpsc) |
622 FIELD_PREP(TIM_CCMR_IC2PSC, icpsc));
623
624 ret = stm32_pwm_raw_capture(chip, pwm, tmo_ms, &raw_prd, &raw_dty);
625 if (ret)
626 goto stop;
627
628 if (raw_dty >= (raw_prd >> icpsc)) {
629 /*
630 * We may fall here using input prescaler, when input
631 * capture starts on high side (before falling edge).
632 * Example with icpsc to capture on each 4 events:
633 *
634 * start 1st capture 2nd capture
635 * v v v
636 * ___ _____ _____ _____ _____ ____
637 * TI1..4 |__| |__| |__| |__| |__|
638 * v v . . . . . v v
639 * icpsc1/3: . 0 . 1 . 2 . 3 . 0
640 * icpsc2/4: 0 1 2 3 0
641 * v v v v
642 * CCR1/3 ......t0..............................t2
643 * CCR2/4 ..t1..............................t1'...
644 * . . .
645 * Capture0: .<----------------------------->.
646 * Capture1: .<-------------------------->. .
647 * . . .
648 * Period: .<------> . .
649 * Low side: .<>.
650 *
651 * Result:
652 * - Period = Capture0 / icpsc
653 * - Duty = Period - Low side = Period - (Capture0 - Capture1)
654 */
655 raw_dty = (raw_prd >> icpsc) - (raw_prd - raw_dty);
656 }
657
658done:
659 prd = (unsigned long long)raw_prd * (psc + 1) * NSEC_PER_SEC;
660 result->period = DIV_ROUND_UP_ULL(prd, rate << icpsc);
661 dty = (unsigned long long)raw_dty * (psc + 1) * NSEC_PER_SEC;
662 result->duty_cycle = DIV_ROUND_UP_ULL(dty, rate);
663stop:
664 regmap_write(priv->regmap, TIM_CCER, 0);
665 regmap_write(priv->regmap, pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2, 0);
666 regmap_write(priv->regmap, TIM_PSC, 0);
667clk_dis:
668 clk_disable(priv->clk);
669unlock:
670 mutex_unlock(&priv->lock);
671
672 return ret;
673}
674
675static const struct pwm_ops stm32pwm_ops = {
676 .sizeof_wfhw = sizeof(struct stm32_pwm_waveform),
677 .round_waveform_tohw = stm32_pwm_round_waveform_tohw,
678 .round_waveform_fromhw = stm32_pwm_round_waveform_fromhw,
679 .read_waveform = stm32_pwm_read_waveform,
680 .write_waveform = stm32_pwm_write_waveform,
681
682 .capture = IS_ENABLED(CONFIG_DMA_ENGINE) ? stm32_pwm_capture : NULL,
683};
684
685static int stm32_pwm_set_breakinput(struct stm32_pwm *priv,
686 const struct stm32_breakinput *bi)
687{
688 u32 shift = TIM_BDTR_BKF_SHIFT(bi->index);
689 u32 bke = TIM_BDTR_BKE(bi->index);
690 u32 bkp = TIM_BDTR_BKP(bi->index);
691 u32 bkf = TIM_BDTR_BKF(bi->index);
692 u32 mask = bkf | bkp | bke;
693 u32 bdtr;
694
695 bdtr = (bi->filter & TIM_BDTR_BKF_MASK) << shift | bke;
696
697 if (bi->level)
698 bdtr |= bkp;
699
700 regmap_update_bits(priv->regmap, TIM_BDTR, mask, bdtr);
701
702 regmap_read(priv->regmap, TIM_BDTR, &bdtr);
703
704 return (bdtr & bke) ? 0 : -EINVAL;
705}
706
707static int stm32_pwm_apply_breakinputs(struct stm32_pwm *priv)
708{
709 unsigned int i;
710 int ret;
711
712 for (i = 0; i < priv->num_breakinputs; i++) {
713 ret = stm32_pwm_set_breakinput(priv, &priv->breakinputs[i]);
714 if (ret < 0)
715 return ret;
716 }
717
718 return 0;
719}
720
721static int stm32_pwm_probe_breakinputs(struct stm32_pwm *priv,
722 struct device_node *np)
723{
724 int nb, ret, array_size;
725 unsigned int i;
726
727 nb = of_property_count_elems_of_size(np, "st,breakinput",
728 sizeof(struct stm32_breakinput));
729
730 /*
731 * Because "st,breakinput" parameter is optional do not make probe
732 * failed if it doesn't exist.
733 */
734 if (nb <= 0)
735 return 0;
736
737 if (nb > MAX_BREAKINPUT)
738 return -EINVAL;
739
740 priv->num_breakinputs = nb;
741 array_size = nb * sizeof(struct stm32_breakinput) / sizeof(u32);
742 ret = of_property_read_u32_array(np, "st,breakinput",
743 (u32 *)priv->breakinputs, array_size);
744 if (ret)
745 return ret;
746
747 for (i = 0; i < priv->num_breakinputs; i++) {
748 if (priv->breakinputs[i].index > 1 ||
749 priv->breakinputs[i].level > 1 ||
750 priv->breakinputs[i].filter > 15)
751 return -EINVAL;
752 }
753
754 return stm32_pwm_apply_breakinputs(priv);
755}
756
757static void stm32_pwm_detect_complementary(struct stm32_pwm *priv, struct stm32_timers *ddata)
758{
759 u32 ccer;
760
761 if (ddata->ipidr) {
762 u32 val;
763
764 /* Simply read from HWCFGR the number of complementary outputs (MP25). */
765 regmap_read(priv->regmap, TIM_HWCFGR1, &val);
766 priv->have_complementary_output = !!FIELD_GET(TIM_HWCFGR1_NB_OF_DT, val);
767 return;
768 }
769
770 /*
771 * If complementary bit doesn't exist writing 1 will have no
772 * effect so we can detect it.
773 */
774 regmap_set_bits(priv->regmap, TIM_CCER, TIM_CCER_CC1NE);
775 regmap_read(priv->regmap, TIM_CCER, &ccer);
776 regmap_clear_bits(priv->regmap, TIM_CCER, TIM_CCER_CC1NE);
777
778 priv->have_complementary_output = (ccer != 0);
779}
780
781static unsigned int stm32_pwm_detect_channels(struct stm32_timers *ddata,
782 unsigned int *num_enabled)
783{
784 struct regmap *regmap = ddata->regmap;
785 u32 ccer, ccer_backup;
786
787 regmap_read(regmap, TIM_CCER, &ccer_backup);
788 *num_enabled = hweight32(ccer_backup & TIM_CCER_CCXE);
789
790 if (ddata->ipidr) {
791 u32 hwcfgr;
792 unsigned int npwm;
793
794 /* Deduce from HWCFGR the number of outputs (MP25). */
795 regmap_read(regmap, TIM_HWCFGR1, &hwcfgr);
796
797 /*
798 * Timers may have more capture/compare channels than the
799 * actual number of PWM channel outputs (e.g. TIM_CH[1..4]).
800 */
801 npwm = FIELD_GET(TIM_HWCFGR1_NB_OF_CC, hwcfgr);
802
803 return npwm < STM32_MAX_PWM_OUTPUT ? npwm : STM32_MAX_PWM_OUTPUT;
804 }
805
806 /*
807 * If channels enable bits don't exist writing 1 will have no
808 * effect so we can detect and count them.
809 */
810 regmap_set_bits(regmap, TIM_CCER, TIM_CCER_CCXE);
811 regmap_read(regmap, TIM_CCER, &ccer);
812 regmap_write(regmap, TIM_CCER, ccer_backup);
813
814 return hweight32(ccer & TIM_CCER_CCXE);
815}
816
817static int stm32_pwm_probe(struct platform_device *pdev)
818{
819 struct device *dev = &pdev->dev;
820 struct device_node *np = dev->of_node;
821 struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent);
822 struct pwm_chip *chip;
823 struct stm32_pwm *priv;
824 unsigned int npwm, num_enabled;
825 unsigned int i;
826 int ret;
827
828 npwm = stm32_pwm_detect_channels(ddata, &num_enabled);
829
830 chip = devm_pwmchip_alloc(dev, npwm, sizeof(*priv));
831 if (IS_ERR(chip))
832 return PTR_ERR(chip);
833 priv = to_stm32_pwm_dev(chip);
834
835 mutex_init(&priv->lock);
836 priv->regmap = ddata->regmap;
837 priv->clk = ddata->clk;
838 priv->max_arr = ddata->max_arr;
839
840 if (!priv->regmap || !priv->clk)
841 return dev_err_probe(dev, -EINVAL, "Failed to get %s\n",
842 priv->regmap ? "clk" : "regmap");
843
844 ret = stm32_pwm_probe_breakinputs(priv, np);
845 if (ret)
846 return dev_err_probe(dev, ret,
847 "Failed to configure breakinputs\n");
848
849 stm32_pwm_detect_complementary(priv, ddata);
850
851 ret = devm_clk_rate_exclusive_get(dev, priv->clk);
852 if (ret)
853 return dev_err_probe(dev, ret, "Failed to lock clock\n");
854
855 /*
856 * With the clk running with not more than 1 GHz the calculations in
857 * .apply() won't overflow.
858 */
859 if (clk_get_rate(priv->clk) > 1000000000)
860 return dev_err_probe(dev, -EINVAL, "Clock freq too high (%lu)\n",
861 clk_get_rate(priv->clk));
862
863 chip->ops = &stm32pwm_ops;
864
865 /* Initialize clock refcount to number of enabled PWM channels. */
866 for (i = 0; i < num_enabled; i++) {
867 ret = clk_enable(priv->clk);
868 if (ret)
869 return ret;
870 }
871
872 ret = devm_pwmchip_add(dev, chip);
873 if (ret < 0)
874 return dev_err_probe(dev, ret,
875 "Failed to register pwmchip\n");
876
877 platform_set_drvdata(pdev, chip);
878
879 return 0;
880}
881
882static int stm32_pwm_suspend(struct device *dev)
883{
884 struct pwm_chip *chip = dev_get_drvdata(dev);
885 struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
886 unsigned int i;
887 u32 ccer, mask;
888
889 /* Look for active channels */
890 ccer = active_channels(priv);
891
892 for (i = 0; i < chip->npwm; i++) {
893 mask = TIM_CCER_CCxE(i + 1);
894 if (ccer & mask) {
895 dev_err(dev, "PWM %u still in use by consumer %s\n",
896 i, chip->pwms[i].label);
897 return -EBUSY;
898 }
899 }
900
901 return pinctrl_pm_select_sleep_state(dev);
902}
903
904static int stm32_pwm_resume(struct device *dev)
905{
906 struct pwm_chip *chip = dev_get_drvdata(dev);
907 struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
908 int ret;
909
910 ret = pinctrl_pm_select_default_state(dev);
911 if (ret)
912 return ret;
913
914 /* restore breakinput registers that may have been lost in low power */
915 return stm32_pwm_apply_breakinputs(priv);
916}
917
918static DEFINE_SIMPLE_DEV_PM_OPS(stm32_pwm_pm_ops, stm32_pwm_suspend, stm32_pwm_resume);
919
920static const struct of_device_id stm32_pwm_of_match[] = {
921 { .compatible = "st,stm32-pwm" },
922 { .compatible = "st,stm32mp25-pwm" },
923 { /* end node */ }
924};
925MODULE_DEVICE_TABLE(of, stm32_pwm_of_match);
926
927static struct platform_driver stm32_pwm_driver = {
928 .probe = stm32_pwm_probe,
929 .driver = {
930 .name = "stm32-pwm",
931 .of_match_table = stm32_pwm_of_match,
932 .pm = pm_ptr(&stm32_pwm_pm_ops),
933 },
934};
935module_platform_driver(stm32_pwm_driver);
936
937MODULE_ALIAS("platform:stm32-pwm");
938MODULE_DESCRIPTION("STMicroelectronics STM32 PWM driver");
939MODULE_LICENSE("GPL v2");