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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2024 Samsung Electronics Co., Ltd.
4 * Author: Michal Wilczynski <[email protected]>
5 */
6
7#include <linux/of.h>
8#include <linux/platform_device.h>
9#include <linux/reset-controller.h>
10#include <linux/regmap.h>
11
12#include <dt-bindings/reset/thead,th1520-reset.h>
13
14 /* register offset in RSTGEN_R */
15#define TH1520_BROM_RST_CFG 0x0
16#define TH1520_C910_RST_CFG 0x4
17#define TH1520_CHIP_DBG_RST_CFG 0xc
18#define TH1520_AXI4_CPUSYS2_RST_CFG 0x10
19#define TH1520_X2H_CPUSYS_RST_CFG 0x18
20#define TH1520_AHB2_CPUSYS_RST_CFG 0x1c
21#define TH1520_APB3_CPUSYS_RST_CFG 0x20
22#define TH1520_MBOX0_RST_CFG 0x24
23#define TH1520_MBOX1_RST_CFG 0x28
24#define TH1520_MBOX2_RST_CFG 0x2c
25#define TH1520_MBOX3_RST_CFG 0x30
26#define TH1520_WDT0_RST_CFG 0x34
27#define TH1520_WDT1_RST_CFG 0x38
28#define TH1520_TIMER0_RST_CFG 0x3c
29#define TH1520_TIMER1_RST_CFG 0x40
30#define TH1520_PERISYS_AHB_RST_CFG 0x44
31#define TH1520_PERISYS_APB1_RST_CFG 0x48
32#define TH1520_PERISYS_APB2_RST_CFG 0x4c
33#define TH1520_GMAC0_RST_CFG 0x68
34#define TH1520_UART0_RST_CFG 0x70
35#define TH1520_UART1_RST_CFG 0x74
36#define TH1520_UART2_RST_CFG 0x78
37#define TH1520_UART3_RST_CFG 0x7c
38#define TH1520_UART4_RST_CFG 0x80
39#define TH1520_UART5_RST_CFG 0x84
40#define TH1520_QSPI0_RST_CFG 0x8c
41#define TH1520_QSPI1_RST_CFG 0x90
42#define TH1520_SPI_RST_CFG 0x94
43#define TH1520_I2C0_RST_CFG 0x98
44#define TH1520_I2C1_RST_CFG 0x9c
45#define TH1520_I2C2_RST_CFG 0xa0
46#define TH1520_I2C3_RST_CFG 0xa4
47#define TH1520_I2C4_RST_CFG 0xa8
48#define TH1520_I2C5_RST_CFG 0xac
49#define TH1520_GPIO0_RST_CFG 0xb0
50#define TH1520_GPIO1_RST_CFG 0xb4
51#define TH1520_GPIO2_RST_CFG 0xb8
52#define TH1520_PWM_RST_CFG 0xc0
53#define TH1520_PADCTRL0_APSYS_RST_CFG 0xc4
54#define TH1520_CPU2PERI_X2H_RST_CFG 0xcc
55#define TH1520_CPU2AON_X2H_RST_CFG 0xe4
56#define TH1520_AON2CPU_A2X_RST_CFG 0xfc
57#define TH1520_NPUSYS_AXI_RST_CFG 0x128
58#define TH1520_CPU2VP_X2P_RST_CFG 0x12c
59#define TH1520_CPU2VI_X2H_RST_CFG 0x138
60#define TH1520_BMU_C910_RST_CFG 0x148
61#define TH1520_DMAC_CPUSYS_RST_CFG 0x14c
62#define TH1520_SPINLOCK_RST_CFG 0x178
63#define TH1520_CFG2TEE_X2H_RST_CFG 0x188
64#define TH1520_DSMART_RST_CFG 0x18c
65#define TH1520_GPIO3_RST_CFG 0x1a8
66#define TH1520_I2S_RST_CFG 0x1ac
67#define TH1520_IMG_NNA_RST_CFG 0x1b0
68#define TH1520_PERI_APB3_RST_CFG 0x1dc
69#define TH1520_VP_SUBSYS_RST_CFG 0x1ec
70#define TH1520_PERISYS_APB4_RST_CFG 0x1f8
71#define TH1520_GMAC1_RST_CFG 0x204
72#define TH1520_GMAC_AXI_RST_CFG 0x208
73#define TH1520_PADCTRL1_APSYS_RST_CFG 0x20c
74#define TH1520_VOSYS_AXI_RST_CFG 0x210
75#define TH1520_VOSYS_X2X_RST_CFG 0x214
76#define TH1520_MISC2VP_X2X_RST_CFG 0x218
77#define TH1520_SUBSYS_RST_CFG 0x220
78
79 /* register offset in DSP_REGMAP */
80#define TH1520_DSPSYS_RST_CFG 0x0
81
82 /* register offset in MISCSYS_REGMAP */
83#define TH1520_EMMC_RST_CFG 0x0
84#define TH1520_MISCSYS_AXI_RST_CFG 0x8
85#define TH1520_SDIO0_RST_CFG 0xc
86#define TH1520_SDIO1_RST_CFG 0x10
87#define TH1520_USB3_DRD_RST_CFG 0x14
88
89 /* register offset in VISYS_REGMAP */
90#define TH1520_VISYS_RST_CFG 0x0
91#define TH1520_VISYS_2_RST_CFG 0x4
92
93 /* register offset in VOSYS_REGMAP */
94#define TH1520_GPU_RST_CFG 0x0
95#define TH1520_GPU_RST_CFG_MASK GENMASK(1, 0)
96#define TH1520_DPU_RST_CFG 0x4
97#define TH1520_DSI0_RST_CFG 0x8
98#define TH1520_DSI1_RST_CFG 0xc
99#define TH1520_HDMI_RST_CFG 0x14
100#define TH1520_AXI4_VO_DW_AXI_RST_CFG 0x18
101#define TH1520_X2H_X4_VOSYS_DW_RST_CFG 0x20
102
103/* register values */
104#define TH1520_GPU_SW_GPU_RST BIT(0)
105#define TH1520_GPU_SW_CLKGEN_RST BIT(1)
106#define TH1520_DPU_SW_DPU_HRST BIT(0)
107#define TH1520_DPU_SW_DPU_ARST BIT(1)
108#define TH1520_DPU_SW_DPU_CRST BIT(2)
109#define TH1520_DSI_SW_DSI_PRST BIT(0)
110#define TH1520_HDMI_SW_MAIN_RST BIT(0)
111#define TH1520_HDMI_SW_PRST BIT(1)
112
113 /* register offset in VPSYS_REGMAP */
114#define TH1520_AXIBUS_RST_CFG 0x0
115#define TH1520_FCE_RST_CFG 0x4
116#define TH1520_G2D_RST_CFG 0x8
117#define TH1520_VDEC_RST_CFG 0xc
118#define TH1520_VENC_RST_CFG 0x10
119
120struct th1520_reset_map {
121 u32 bit;
122 u32 reg;
123};
124
125struct th1520_reset_priv {
126 struct reset_controller_dev rcdev;
127 struct regmap *map;
128 const struct th1520_reset_map *resets;
129};
130
131struct th1520_reset_data {
132 const struct th1520_reset_map *resets;
133 size_t num;
134};
135
136static const struct th1520_reset_map th1520_resets[] = {
137 [TH1520_RESET_ID_GPU] = {
138 .bit = TH1520_GPU_SW_GPU_RST,
139 .reg = TH1520_GPU_RST_CFG,
140 },
141 [TH1520_RESET_ID_GPU_CLKGEN] = {
142 .bit = TH1520_GPU_SW_CLKGEN_RST,
143 .reg = TH1520_GPU_RST_CFG,
144 },
145 [TH1520_RESET_ID_DPU_AHB] = {
146 .bit = TH1520_DPU_SW_DPU_HRST,
147 .reg = TH1520_DPU_RST_CFG,
148 },
149 [TH1520_RESET_ID_DPU_AXI] = {
150 .bit = TH1520_DPU_SW_DPU_ARST,
151 .reg = TH1520_DPU_RST_CFG,
152 },
153 [TH1520_RESET_ID_DPU_CORE] = {
154 .bit = TH1520_DPU_SW_DPU_CRST,
155 .reg = TH1520_DPU_RST_CFG,
156 },
157 [TH1520_RESET_ID_DSI0_APB] = {
158 .bit = TH1520_DSI_SW_DSI_PRST,
159 .reg = TH1520_DSI0_RST_CFG,
160 },
161 [TH1520_RESET_ID_DSI1_APB] = {
162 .bit = TH1520_DSI_SW_DSI_PRST,
163 .reg = TH1520_DSI1_RST_CFG,
164 },
165 [TH1520_RESET_ID_HDMI] = {
166 .bit = TH1520_HDMI_SW_MAIN_RST,
167 .reg = TH1520_HDMI_RST_CFG,
168 },
169 [TH1520_RESET_ID_HDMI_APB] = {
170 .bit = TH1520_HDMI_SW_PRST,
171 .reg = TH1520_HDMI_RST_CFG,
172 },
173 [TH1520_RESET_ID_VOAXI] = {
174 .bit = BIT(0),
175 .reg = TH1520_AXI4_VO_DW_AXI_RST_CFG,
176 },
177 [TH1520_RESET_ID_VOAXI_APB] = {
178 .bit = BIT(1),
179 .reg = TH1520_AXI4_VO_DW_AXI_RST_CFG,
180 },
181 [TH1520_RESET_ID_X2H_DPU_AXI] = {
182 .bit = BIT(0),
183 .reg = TH1520_X2H_X4_VOSYS_DW_RST_CFG,
184 },
185 [TH1520_RESET_ID_X2H_DPU_AHB] = {
186 .bit = BIT(1),
187 .reg = TH1520_X2H_X4_VOSYS_DW_RST_CFG,
188 },
189 [TH1520_RESET_ID_X2H_DPU1_AXI] = {
190 .bit = BIT(2),
191 .reg = TH1520_X2H_X4_VOSYS_DW_RST_CFG,
192 },
193 [TH1520_RESET_ID_X2H_DPU1_AHB] = {
194 .bit = BIT(3),
195 .reg = TH1520_X2H_X4_VOSYS_DW_RST_CFG,
196 },
197};
198
199static const struct th1520_reset_map th1520_ap_resets[] = {
200 [TH1520_RESET_ID_BROM] = {
201 .bit = BIT(0),
202 .reg = TH1520_BROM_RST_CFG,
203 },
204 [TH1520_RESET_ID_C910_TOP] = {
205 .bit = BIT(0),
206 .reg = TH1520_C910_RST_CFG,
207 },
208 [TH1520_RESET_ID_NPU] = {
209 .bit = BIT(0),
210 .reg = TH1520_IMG_NNA_RST_CFG,
211 },
212 [TH1520_RESET_ID_WDT0] = {
213 .bit = BIT(0),
214 .reg = TH1520_WDT0_RST_CFG,
215 },
216 [TH1520_RESET_ID_WDT1] = {
217 .bit = BIT(0),
218 .reg = TH1520_WDT1_RST_CFG,
219 },
220 [TH1520_RESET_ID_C910_C0] = {
221 .bit = BIT(1),
222 .reg = TH1520_C910_RST_CFG,
223 },
224 [TH1520_RESET_ID_C910_C1] = {
225 .bit = BIT(2),
226 .reg = TH1520_C910_RST_CFG,
227 },
228 [TH1520_RESET_ID_C910_C2] = {
229 .bit = BIT(3),
230 .reg = TH1520_C910_RST_CFG,
231 },
232 [TH1520_RESET_ID_C910_C3] = {
233 .bit = BIT(4),
234 .reg = TH1520_C910_RST_CFG,
235 },
236 [TH1520_RESET_ID_CHIP_DBG_CORE] = {
237 .bit = BIT(0),
238 .reg = TH1520_CHIP_DBG_RST_CFG,
239 },
240 [TH1520_RESET_ID_CHIP_DBG_AXI] = {
241 .bit = BIT(1),
242 .reg = TH1520_CHIP_DBG_RST_CFG,
243 },
244 [TH1520_RESET_ID_AXI4_CPUSYS2_AXI] = {
245 .bit = BIT(0),
246 .reg = TH1520_AXI4_CPUSYS2_RST_CFG,
247 },
248 [TH1520_RESET_ID_AXI4_CPUSYS2_APB] = {
249 .bit = BIT(1),
250 .reg = TH1520_AXI4_CPUSYS2_RST_CFG,
251 },
252 [TH1520_RESET_ID_X2H_CPUSYS] = {
253 .bit = BIT(0),
254 .reg = TH1520_X2H_CPUSYS_RST_CFG,
255 },
256 [TH1520_RESET_ID_AHB2_CPUSYS] = {
257 .bit = BIT(0),
258 .reg = TH1520_AHB2_CPUSYS_RST_CFG,
259 },
260 [TH1520_RESET_ID_APB3_CPUSYS] = {
261 .bit = BIT(0),
262 .reg = TH1520_APB3_CPUSYS_RST_CFG,
263 },
264 [TH1520_RESET_ID_MBOX0_APB] = {
265 .bit = BIT(0),
266 .reg = TH1520_MBOX0_RST_CFG,
267 },
268 [TH1520_RESET_ID_MBOX1_APB] = {
269 .bit = BIT(0),
270 .reg = TH1520_MBOX1_RST_CFG,
271 },
272 [TH1520_RESET_ID_MBOX2_APB] = {
273 .bit = BIT(0),
274 .reg = TH1520_MBOX2_RST_CFG,
275 },
276 [TH1520_RESET_ID_MBOX3_APB] = {
277 .bit = BIT(0),
278 .reg = TH1520_MBOX3_RST_CFG,
279 },
280 [TH1520_RESET_ID_TIMER0_APB] = {
281 .bit = BIT(0),
282 .reg = TH1520_TIMER0_RST_CFG,
283 },
284 [TH1520_RESET_ID_TIMER0_CORE] = {
285 .bit = BIT(1),
286 .reg = TH1520_TIMER0_RST_CFG,
287 },
288 [TH1520_RESET_ID_TIMER1_APB] = {
289 .bit = BIT(0),
290 .reg = TH1520_TIMER1_RST_CFG,
291 },
292 [TH1520_RESET_ID_TIMER1_CORE] = {
293 .bit = BIT(1),
294 .reg = TH1520_TIMER1_RST_CFG,
295 },
296 [TH1520_RESET_ID_PERISYS_AHB] = {
297 .bit = BIT(0),
298 .reg = TH1520_PERISYS_AHB_RST_CFG,
299 },
300 [TH1520_RESET_ID_PERISYS_APB1] = {
301 .bit = BIT(0),
302 .reg = TH1520_PERISYS_APB1_RST_CFG,
303 },
304 [TH1520_RESET_ID_PERISYS_APB2] = {
305 .bit = BIT(0),
306 .reg = TH1520_PERISYS_APB2_RST_CFG,
307 },
308 [TH1520_RESET_ID_GMAC0_APB] = {
309 .bit = BIT(0),
310 .reg = TH1520_GMAC0_RST_CFG,
311 },
312 [TH1520_RESET_ID_GMAC0_AHB] = {
313 .bit = BIT(1),
314 .reg = TH1520_GMAC0_RST_CFG,
315 },
316 [TH1520_RESET_ID_GMAC0_CLKGEN] = {
317 .bit = BIT(2),
318 .reg = TH1520_GMAC0_RST_CFG,
319 },
320 [TH1520_RESET_ID_GMAC0_AXI] = {
321 .bit = BIT(3),
322 .reg = TH1520_GMAC0_RST_CFG,
323 },
324 [TH1520_RESET_ID_UART0_APB] = {
325 .bit = BIT(0),
326 .reg = TH1520_UART0_RST_CFG,
327 },
328 [TH1520_RESET_ID_UART0_IF] = {
329 .bit = BIT(1),
330 .reg = TH1520_UART0_RST_CFG,
331 },
332 [TH1520_RESET_ID_UART1_APB] = {
333 .bit = BIT(0),
334 .reg = TH1520_UART1_RST_CFG,
335 },
336 [TH1520_RESET_ID_UART1_IF] = {
337 .bit = BIT(1),
338 .reg = TH1520_UART1_RST_CFG,
339 },
340 [TH1520_RESET_ID_UART2_APB] = {
341 .bit = BIT(0),
342 .reg = TH1520_UART2_RST_CFG,
343 },
344 [TH1520_RESET_ID_UART2_IF] = {
345 .bit = BIT(1),
346 .reg = TH1520_UART2_RST_CFG,
347 },
348 [TH1520_RESET_ID_UART3_APB] = {
349 .bit = BIT(0),
350 .reg = TH1520_UART3_RST_CFG,
351 },
352 [TH1520_RESET_ID_UART3_IF] = {
353 .bit = BIT(1),
354 .reg = TH1520_UART3_RST_CFG,
355 },
356 [TH1520_RESET_ID_UART4_APB] = {
357 .bit = BIT(0),
358 .reg = TH1520_UART4_RST_CFG,
359 },
360 [TH1520_RESET_ID_UART4_IF] = {
361 .bit = BIT(1),
362 .reg = TH1520_UART4_RST_CFG,
363 },
364 [TH1520_RESET_ID_UART5_APB] = {
365 .bit = BIT(0),
366 .reg = TH1520_UART5_RST_CFG,
367 },
368 [TH1520_RESET_ID_UART5_IF] = {
369 .bit = BIT(1),
370 .reg = TH1520_UART5_RST_CFG,
371 },
372 [TH1520_RESET_ID_QSPI0_IF] = {
373 .bit = BIT(0),
374 .reg = TH1520_QSPI0_RST_CFG,
375 },
376 [TH1520_RESET_ID_QSPI0_APB] = {
377 .bit = BIT(1),
378 .reg = TH1520_QSPI0_RST_CFG,
379 },
380 [TH1520_RESET_ID_QSPI1_IF] = {
381 .bit = BIT(0),
382 .reg = TH1520_QSPI1_RST_CFG,
383 },
384 [TH1520_RESET_ID_QSPI1_APB] = {
385 .bit = BIT(1),
386 .reg = TH1520_QSPI1_RST_CFG,
387 },
388 [TH1520_RESET_ID_SPI_IF] = {
389 .bit = BIT(0),
390 .reg = TH1520_SPI_RST_CFG,
391 },
392 [TH1520_RESET_ID_SPI_APB] = {
393 .bit = BIT(1),
394 .reg = TH1520_SPI_RST_CFG,
395 },
396 [TH1520_RESET_ID_I2C0_APB] = {
397 .bit = BIT(0),
398 .reg = TH1520_I2C0_RST_CFG,
399 },
400 [TH1520_RESET_ID_I2C0_CORE] = {
401 .bit = BIT(1),
402 .reg = TH1520_I2C0_RST_CFG,
403 },
404 [TH1520_RESET_ID_I2C1_APB] = {
405 .bit = BIT(0),
406 .reg = TH1520_I2C1_RST_CFG,
407 },
408 [TH1520_RESET_ID_I2C1_CORE] = {
409 .bit = BIT(1),
410 .reg = TH1520_I2C1_RST_CFG,
411 },
412 [TH1520_RESET_ID_I2C2_APB] = {
413 .bit = BIT(0),
414 .reg = TH1520_I2C2_RST_CFG,
415 },
416 [TH1520_RESET_ID_I2C2_CORE] = {
417 .bit = BIT(1),
418 .reg = TH1520_I2C2_RST_CFG,
419 },
420 [TH1520_RESET_ID_I2C3_APB] = {
421 .bit = BIT(0),
422 .reg = TH1520_I2C3_RST_CFG,
423 },
424 [TH1520_RESET_ID_I2C3_CORE] = {
425 .bit = BIT(1),
426 .reg = TH1520_I2C3_RST_CFG,
427 },
428 [TH1520_RESET_ID_I2C4_APB] = {
429 .bit = BIT(0),
430 .reg = TH1520_I2C4_RST_CFG,
431 },
432 [TH1520_RESET_ID_I2C4_CORE] = {
433 .bit = BIT(1),
434 .reg = TH1520_I2C4_RST_CFG,
435 },
436 [TH1520_RESET_ID_I2C5_APB] = {
437 .bit = BIT(0),
438 .reg = TH1520_I2C5_RST_CFG,
439 },
440 [TH1520_RESET_ID_I2C5_CORE] = {
441 .bit = BIT(1),
442 .reg = TH1520_I2C5_RST_CFG,
443 },
444 [TH1520_RESET_ID_GPIO0_DB] = {
445 .bit = BIT(0),
446 .reg = TH1520_GPIO0_RST_CFG,
447 },
448 [TH1520_RESET_ID_GPIO0_APB] = {
449 .bit = BIT(1),
450 .reg = TH1520_GPIO0_RST_CFG,
451 },
452 [TH1520_RESET_ID_GPIO1_DB] = {
453 .bit = BIT(0),
454 .reg = TH1520_GPIO1_RST_CFG,
455 },
456 [TH1520_RESET_ID_GPIO1_APB] = {
457 .bit = BIT(1),
458 .reg = TH1520_GPIO1_RST_CFG,
459 },
460 [TH1520_RESET_ID_GPIO2_DB] = {
461 .bit = BIT(0),
462 .reg = TH1520_GPIO2_RST_CFG,
463 },
464 [TH1520_RESET_ID_GPIO2_APB] = {
465 .bit = BIT(1),
466 .reg = TH1520_GPIO2_RST_CFG,
467 },
468 [TH1520_RESET_ID_PWM_COUNTER] = {
469 .bit = BIT(0),
470 .reg = TH1520_PWM_RST_CFG,
471 },
472 [TH1520_RESET_ID_PWM_APB] = {
473 .bit = BIT(1),
474 .reg = TH1520_PWM_RST_CFG,
475 },
476 [TH1520_RESET_ID_PADCTRL0_APB] = {
477 .bit = BIT(0),
478 .reg = TH1520_PADCTRL0_APSYS_RST_CFG,
479 },
480 [TH1520_RESET_ID_CPU2PERI_X2H] = {
481 .bit = BIT(1),
482 .reg = TH1520_CPU2PERI_X2H_RST_CFG,
483 },
484 [TH1520_RESET_ID_CPU2AON_X2H] = {
485 .bit = BIT(0),
486 .reg = TH1520_CPU2AON_X2H_RST_CFG,
487 },
488 [TH1520_RESET_ID_AON2CPU_A2X] = {
489 .bit = BIT(0),
490 .reg = TH1520_AON2CPU_A2X_RST_CFG,
491 },
492 [TH1520_RESET_ID_NPUSYS_AXI] = {
493 .bit = BIT(0),
494 .reg = TH1520_NPUSYS_AXI_RST_CFG,
495 },
496 [TH1520_RESET_ID_NPUSYS_AXI_APB] = {
497 .bit = BIT(1),
498 .reg = TH1520_NPUSYS_AXI_RST_CFG,
499 },
500 [TH1520_RESET_ID_CPU2VP_X2P] = {
501 .bit = BIT(0),
502 .reg = TH1520_CPU2VP_X2P_RST_CFG,
503 },
504 [TH1520_RESET_ID_CPU2VI_X2H] = {
505 .bit = BIT(0),
506 .reg = TH1520_CPU2VI_X2H_RST_CFG,
507 },
508 [TH1520_RESET_ID_BMU_AXI] = {
509 .bit = BIT(0),
510 .reg = TH1520_BMU_C910_RST_CFG,
511 },
512 [TH1520_RESET_ID_BMU_APB] = {
513 .bit = BIT(1),
514 .reg = TH1520_BMU_C910_RST_CFG,
515 },
516 [TH1520_RESET_ID_DMAC_CPUSYS_AXI] = {
517 .bit = BIT(0),
518 .reg = TH1520_DMAC_CPUSYS_RST_CFG,
519 },
520 [TH1520_RESET_ID_DMAC_CPUSYS_AHB] = {
521 .bit = BIT(1),
522 .reg = TH1520_DMAC_CPUSYS_RST_CFG,
523 },
524 [TH1520_RESET_ID_SPINLOCK] = {
525 .bit = BIT(0),
526 .reg = TH1520_SPINLOCK_RST_CFG,
527 },
528 [TH1520_RESET_ID_CFG2TEE] = {
529 .bit = BIT(0),
530 .reg = TH1520_CFG2TEE_X2H_RST_CFG,
531 },
532 [TH1520_RESET_ID_DSMART] = {
533 .bit = BIT(0),
534 .reg = TH1520_DSMART_RST_CFG,
535 },
536 [TH1520_RESET_ID_GPIO3_DB] = {
537 .bit = BIT(0),
538 .reg = TH1520_GPIO3_RST_CFG,
539 },
540 [TH1520_RESET_ID_GPIO3_APB] = {
541 .bit = BIT(1),
542 .reg = TH1520_GPIO3_RST_CFG,
543 },
544 [TH1520_RESET_ID_PERI_I2S] = {
545 .bit = BIT(0),
546 .reg = TH1520_I2S_RST_CFG,
547 },
548 [TH1520_RESET_ID_PERI_APB3] = {
549 .bit = BIT(0),
550 .reg = TH1520_PERI_APB3_RST_CFG,
551 },
552 [TH1520_RESET_ID_PERI2PERI1_APB] = {
553 .bit = BIT(1),
554 .reg = TH1520_PERI_APB3_RST_CFG,
555 },
556 [TH1520_RESET_ID_VPSYS_APB] = {
557 .bit = BIT(0),
558 .reg = TH1520_VP_SUBSYS_RST_CFG,
559 },
560 [TH1520_RESET_ID_PERISYS_APB4] = {
561 .bit = BIT(0),
562 .reg = TH1520_PERISYS_APB4_RST_CFG,
563 },
564 [TH1520_RESET_ID_GMAC1_APB] = {
565 .bit = BIT(0),
566 .reg = TH1520_GMAC1_RST_CFG,
567 },
568 [TH1520_RESET_ID_GMAC1_AHB] = {
569 .bit = BIT(1),
570 .reg = TH1520_GMAC1_RST_CFG,
571 },
572 [TH1520_RESET_ID_GMAC1_CLKGEN] = {
573 .bit = BIT(2),
574 .reg = TH1520_GMAC1_RST_CFG,
575 },
576 [TH1520_RESET_ID_GMAC1_AXI] = {
577 .bit = BIT(3),
578 .reg = TH1520_GMAC1_RST_CFG,
579 },
580 [TH1520_RESET_ID_GMAC_AXI] = {
581 .bit = BIT(0),
582 .reg = TH1520_GMAC_AXI_RST_CFG,
583 },
584 [TH1520_RESET_ID_GMAC_AXI_APB] = {
585 .bit = BIT(1),
586 .reg = TH1520_GMAC_AXI_RST_CFG,
587 },
588 [TH1520_RESET_ID_PADCTRL1_APB] = {
589 .bit = BIT(0),
590 .reg = TH1520_PADCTRL1_APSYS_RST_CFG,
591 },
592 [TH1520_RESET_ID_VOSYS_AXI] = {
593 .bit = BIT(0),
594 .reg = TH1520_VOSYS_AXI_RST_CFG,
595 },
596 [TH1520_RESET_ID_VOSYS_AXI_APB] = {
597 .bit = BIT(1),
598 .reg = TH1520_VOSYS_AXI_RST_CFG,
599 },
600 [TH1520_RESET_ID_VOSYS_AXI_X2X] = {
601 .bit = BIT(0),
602 .reg = TH1520_VOSYS_X2X_RST_CFG,
603 },
604 [TH1520_RESET_ID_MISC2VP_X2X] = {
605 .bit = BIT(0),
606 .reg = TH1520_MISC2VP_X2X_RST_CFG,
607 },
608 [TH1520_RESET_ID_DSPSYS] = {
609 .bit = BIT(0),
610 .reg = TH1520_SUBSYS_RST_CFG,
611 },
612 [TH1520_RESET_ID_VISYS] = {
613 .bit = BIT(1),
614 .reg = TH1520_SUBSYS_RST_CFG,
615 },
616 [TH1520_RESET_ID_VOSYS] = {
617 .bit = BIT(2),
618 .reg = TH1520_SUBSYS_RST_CFG,
619 },
620 [TH1520_RESET_ID_VPSYS] = {
621 .bit = BIT(3),
622 .reg = TH1520_SUBSYS_RST_CFG,
623 },
624};
625
626static const struct th1520_reset_map th1520_dsp_resets[] = {
627 [TH1520_RESET_ID_X2X_DSP1] = {
628 .bit = BIT(0),
629 .reg = TH1520_DSPSYS_RST_CFG,
630 },
631 [TH1520_RESET_ID_X2X_DSP0] = {
632 .bit = BIT(1),
633 .reg = TH1520_DSPSYS_RST_CFG,
634 },
635 [TH1520_RESET_ID_X2X_SLAVE_DSP1] = {
636 .bit = BIT(2),
637 .reg = TH1520_DSPSYS_RST_CFG,
638 },
639 [TH1520_RESET_ID_X2X_SLAVE_DSP0] = {
640 .bit = BIT(3),
641 .reg = TH1520_DSPSYS_RST_CFG,
642 },
643 [TH1520_RESET_ID_DSP0_CORE] = {
644 .bit = BIT(8),
645 .reg = TH1520_DSPSYS_RST_CFG,
646 },
647 [TH1520_RESET_ID_DSP0_DEBUG] = {
648 .bit = BIT(9),
649 .reg = TH1520_DSPSYS_RST_CFG,
650 },
651 [TH1520_RESET_ID_DSP0_APB] = {
652 .bit = BIT(10),
653 .reg = TH1520_DSPSYS_RST_CFG,
654 },
655 [TH1520_RESET_ID_DSP1_CORE] = {
656 .bit = BIT(12),
657 .reg = TH1520_DSPSYS_RST_CFG,
658 },
659 [TH1520_RESET_ID_DSP1_DEBUG] = {
660 .bit = BIT(13),
661 .reg = TH1520_DSPSYS_RST_CFG,
662 },
663 [TH1520_RESET_ID_DSP1_APB] = {
664 .bit = BIT(14),
665 .reg = TH1520_DSPSYS_RST_CFG,
666 },
667 [TH1520_RESET_ID_DSPSYS_APB] = {
668 .bit = BIT(16),
669 .reg = TH1520_DSPSYS_RST_CFG,
670 },
671 [TH1520_RESET_ID_AXI4_DSPSYS_SLV] = {
672 .bit = BIT(20),
673 .reg = TH1520_DSPSYS_RST_CFG,
674 },
675 [TH1520_RESET_ID_AXI4_DSPSYS] = {
676 .bit = BIT(24),
677 .reg = TH1520_DSPSYS_RST_CFG,
678 },
679 [TH1520_RESET_ID_AXI4_DSP_RS] = {
680 .bit = BIT(26),
681 .reg = TH1520_DSPSYS_RST_CFG,
682 },
683};
684
685static const struct th1520_reset_map th1520_misc_resets[] = {
686 [TH1520_RESET_ID_EMMC_SDIO_CLKGEN] = {
687 .bit = BIT(0),
688 .reg = TH1520_EMMC_RST_CFG,
689 },
690 [TH1520_RESET_ID_EMMC] = {
691 .bit = BIT(1),
692 .reg = TH1520_EMMC_RST_CFG,
693 },
694 [TH1520_RESET_ID_MISCSYS_AXI] = {
695 .bit = BIT(0),
696 .reg = TH1520_MISCSYS_AXI_RST_CFG,
697 },
698 [TH1520_RESET_ID_MISCSYS_AXI_APB] = {
699 .bit = BIT(1),
700 .reg = TH1520_MISCSYS_AXI_RST_CFG,
701 },
702 [TH1520_RESET_ID_SDIO0] = {
703 .bit = BIT(0),
704 .reg = TH1520_SDIO0_RST_CFG,
705 },
706 [TH1520_RESET_ID_SDIO1] = {
707 .bit = BIT(1),
708 .reg = TH1520_SDIO1_RST_CFG,
709 },
710 [TH1520_RESET_ID_USB3_APB] = {
711 .bit = BIT(0),
712 .reg = TH1520_USB3_DRD_RST_CFG,
713 },
714 [TH1520_RESET_ID_USB3_PHY] = {
715 .bit = BIT(1),
716 .reg = TH1520_USB3_DRD_RST_CFG,
717 },
718 [TH1520_RESET_ID_USB3_VCC] = {
719 .bit = BIT(2),
720 .reg = TH1520_USB3_DRD_RST_CFG,
721 },
722};
723
724static const struct th1520_reset_map th1520_vi_resets[] = {
725 [TH1520_RESET_ID_ISP0] = {
726 .bit = BIT(0),
727 .reg = TH1520_VISYS_RST_CFG,
728 },
729 [TH1520_RESET_ID_ISP1] = {
730 .bit = BIT(4),
731 .reg = TH1520_VISYS_RST_CFG,
732 },
733 [TH1520_RESET_ID_CSI0_APB] = {
734 .bit = BIT(16),
735 .reg = TH1520_VISYS_RST_CFG,
736 },
737 [TH1520_RESET_ID_CSI1_APB] = {
738 .bit = BIT(17),
739 .reg = TH1520_VISYS_RST_CFG,
740 },
741 [TH1520_RESET_ID_CSI2_APB] = {
742 .bit = BIT(18),
743 .reg = TH1520_VISYS_RST_CFG,
744 },
745 [TH1520_RESET_ID_MIPI_FIFO] = {
746 .bit = BIT(20),
747 .reg = TH1520_VISYS_RST_CFG,
748 },
749 [TH1520_RESET_ID_ISP_VENC_APB] = {
750 .bit = BIT(24),
751 .reg = TH1520_VISYS_RST_CFG,
752 },
753 [TH1520_RESET_ID_VIPRE_APB] = {
754 .bit = BIT(28),
755 .reg = TH1520_VISYS_RST_CFG,
756 },
757 [TH1520_RESET_ID_VIPRE_AXI] = {
758 .bit = BIT(29),
759 .reg = TH1520_VISYS_RST_CFG,
760 },
761 [TH1520_RESET_ID_DW200_APB] = {
762 .bit = BIT(31),
763 .reg = TH1520_VISYS_RST_CFG,
764 },
765 [TH1520_RESET_ID_VISYS3_AXI] = {
766 .bit = BIT(8),
767 .reg = TH1520_VISYS_2_RST_CFG,
768 },
769 [TH1520_RESET_ID_VISYS2_AXI] = {
770 .bit = BIT(9),
771 .reg = TH1520_VISYS_2_RST_CFG,
772 },
773 [TH1520_RESET_ID_VISYS1_AXI] = {
774 .bit = BIT(10),
775 .reg = TH1520_VISYS_2_RST_CFG,
776 },
777 [TH1520_RESET_ID_VISYS_AXI] = {
778 .bit = BIT(12),
779 .reg = TH1520_VISYS_2_RST_CFG,
780 },
781 [TH1520_RESET_ID_VISYS_APB] = {
782 .bit = BIT(16),
783 .reg = TH1520_VISYS_2_RST_CFG,
784 },
785 [TH1520_RESET_ID_ISP_VENC_AXI] = {
786 .bit = BIT(20),
787 .reg = TH1520_VISYS_2_RST_CFG,
788 },
789};
790
791static const struct th1520_reset_map th1520_vp_resets[] = {
792 [TH1520_RESET_ID_VPSYS_AXI_APB] = {
793 .bit = BIT(0),
794 .reg = TH1520_AXIBUS_RST_CFG,
795 },
796 [TH1520_RESET_ID_VPSYS_AXI] = {
797 .bit = BIT(1),
798 .reg = TH1520_AXIBUS_RST_CFG,
799 },
800 [TH1520_RESET_ID_FCE_APB] = {
801 .bit = BIT(0),
802 .reg = TH1520_FCE_RST_CFG,
803 },
804 [TH1520_RESET_ID_FCE_CORE] = {
805 .bit = BIT(1),
806 .reg = TH1520_FCE_RST_CFG,
807 },
808 [TH1520_RESET_ID_FCE_X2X_MASTER] = {
809 .bit = BIT(4),
810 .reg = TH1520_FCE_RST_CFG,
811 },
812 [TH1520_RESET_ID_FCE_X2X_SLAVE] = {
813 .bit = BIT(5),
814 .reg = TH1520_FCE_RST_CFG,
815 },
816 [TH1520_RESET_ID_G2D_APB] = {
817 .bit = BIT(0),
818 .reg = TH1520_G2D_RST_CFG,
819 },
820 [TH1520_RESET_ID_G2D_ACLK] = {
821 .bit = BIT(1),
822 .reg = TH1520_G2D_RST_CFG,
823 },
824 [TH1520_RESET_ID_G2D_CORE] = {
825 .bit = BIT(2),
826 .reg = TH1520_G2D_RST_CFG,
827 },
828 [TH1520_RESET_ID_VDEC_APB] = {
829 .bit = BIT(0),
830 .reg = TH1520_VDEC_RST_CFG,
831 },
832 [TH1520_RESET_ID_VDEC_ACLK] = {
833 .bit = BIT(1),
834 .reg = TH1520_VDEC_RST_CFG,
835 },
836 [TH1520_RESET_ID_VDEC_CORE] = {
837 .bit = BIT(2),
838 .reg = TH1520_VDEC_RST_CFG,
839 },
840 [TH1520_RESET_ID_VENC_APB] = {
841 .bit = BIT(0),
842 .reg = TH1520_VENC_RST_CFG,
843 },
844 [TH1520_RESET_ID_VENC_CORE] = {
845 .bit = BIT(1),
846 .reg = TH1520_VENC_RST_CFG,
847 },
848};
849
850static inline struct th1520_reset_priv *
851to_th1520_reset(struct reset_controller_dev *rcdev)
852{
853 return container_of(rcdev, struct th1520_reset_priv, rcdev);
854}
855
856static int th1520_reset_assert(struct reset_controller_dev *rcdev,
857 unsigned long id)
858{
859 struct th1520_reset_priv *priv = to_th1520_reset(rcdev);
860 const struct th1520_reset_map *reset;
861
862 reset = &priv->resets[id];
863
864 return regmap_update_bits(priv->map, reset->reg, reset->bit, 0);
865}
866
867static int th1520_reset_deassert(struct reset_controller_dev *rcdev,
868 unsigned long id)
869{
870 struct th1520_reset_priv *priv = to_th1520_reset(rcdev);
871 const struct th1520_reset_map *reset;
872
873 reset = &priv->resets[id];
874
875 return regmap_update_bits(priv->map, reset->reg, reset->bit,
876 reset->bit);
877}
878
879static const struct reset_control_ops th1520_reset_ops = {
880 .assert = th1520_reset_assert,
881 .deassert = th1520_reset_deassert,
882};
883
884static const struct regmap_config th1520_reset_regmap_config = {
885 .reg_bits = 32,
886 .val_bits = 32,
887 .reg_stride = 4,
888};
889
890static int th1520_reset_probe(struct platform_device *pdev)
891{
892 const struct th1520_reset_data *data;
893 struct device *dev = &pdev->dev;
894 struct th1520_reset_priv *priv;
895 void __iomem *base;
896 int ret;
897
898 data = device_get_match_data(dev);
899
900 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
901 if (!priv)
902 return -ENOMEM;
903
904 base = devm_platform_ioremap_resource(pdev, 0);
905 if (IS_ERR(base))
906 return PTR_ERR(base);
907
908 priv->map = devm_regmap_init_mmio(dev, base,
909 &th1520_reset_regmap_config);
910 if (IS_ERR(priv->map))
911 return PTR_ERR(priv->map);
912
913 if (of_device_is_compatible(dev->of_node, "thead,th1520-reset")) {
914 /* Initialize GPU resets to asserted state */
915 ret = regmap_update_bits(priv->map, TH1520_GPU_RST_CFG,
916 TH1520_GPU_RST_CFG_MASK, 0);
917 if (ret)
918 return ret;
919 }
920
921 priv->rcdev.owner = THIS_MODULE;
922 priv->rcdev.nr_resets = data->num;
923 priv->rcdev.ops = &th1520_reset_ops;
924 priv->rcdev.of_node = dev->of_node;
925
926 priv->resets = data->resets;
927
928 return devm_reset_controller_register(dev, &priv->rcdev);
929}
930
931static const struct th1520_reset_data th1520_reset_data = {
932 .resets = th1520_resets,
933 .num = ARRAY_SIZE(th1520_resets),
934};
935
936static const struct th1520_reset_data th1520_ap_reset_data = {
937 .resets = th1520_ap_resets,
938 .num = ARRAY_SIZE(th1520_ap_resets),
939};
940
941static const struct th1520_reset_data th1520_dsp_reset_data = {
942 .resets = th1520_dsp_resets,
943 .num = ARRAY_SIZE(th1520_dsp_resets),
944};
945
946static const struct th1520_reset_data th1520_misc_reset_data = {
947 .resets = th1520_misc_resets,
948 .num = ARRAY_SIZE(th1520_misc_resets),
949};
950
951static const struct th1520_reset_data th1520_vi_reset_data = {
952 .resets = th1520_vi_resets,
953 .num = ARRAY_SIZE(th1520_vi_resets),
954};
955
956static const struct th1520_reset_data th1520_vp_reset_data = {
957 .resets = th1520_vp_resets,
958 .num = ARRAY_SIZE(th1520_vp_resets),
959};
960
961static const struct of_device_id th1520_reset_match[] = {
962 { .compatible = "thead,th1520-reset", .data = &th1520_reset_data },
963 { .compatible = "thead,th1520-reset-ap", .data = &th1520_ap_reset_data },
964 { .compatible = "thead,th1520-reset-dsp", .data = &th1520_dsp_reset_data },
965 { .compatible = "thead,th1520-reset-misc", .data = &th1520_misc_reset_data },
966 { .compatible = "thead,th1520-reset-vi", .data = &th1520_vi_reset_data },
967 { .compatible = "thead,th1520-reset-vp", .data = &th1520_vp_reset_data },
968 { /* sentinel */ }
969};
970MODULE_DEVICE_TABLE(of, th1520_reset_match);
971
972static struct platform_driver th1520_reset_driver = {
973 .driver = {
974 .name = "th1520-reset",
975 .of_match_table = th1520_reset_match,
976 },
977 .probe = th1520_reset_probe,
978};
979module_platform_driver(th1520_reset_driver);
980
981MODULE_AUTHOR("Michal Wilczynski <[email protected]>");
982MODULE_DESCRIPTION("T-HEAD TH1520 SoC reset controller");
983MODULE_LICENSE("GPL");