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| 2 | |
| 3 | * Delta TN48M CPLD reset driver
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| 4 | *
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| 5 | * Copyright (C) 2021 Sartura Ltd.
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| 6 | *
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| 7 | * Author: Robert Marko <[email protected]>
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| 8 |
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| 9 |
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| 10 | #include <linux/device.h>
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| 11 | #include <linux/kernel.h>
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| 12 | #include <linux/module.h>
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| 13 | #include <linux/platform_device.h>
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| 14 | #include <linux/regmap.h>
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| 15 | #include <linux/reset-controller.h>
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| 16 |
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| 17 | #include <dt-bindings/reset/delta,tn48m-reset.h>
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| 18 |
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| 19 | #define TN48M_RESET_REG 0x10
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| 20 |
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| 21 | #define TN48M_RESET_TIMEOUT_US 125000
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| 22 | #define TN48M_RESET_SLEEP_US 10
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| 23 |
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| 24 | struct tn48_reset_map {
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| 25 | u8 bit;
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| 26 | };
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| 27 |
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| 28 | struct tn48_reset_data {
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| 29 | struct reset_controller_dev rcdev;
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| 30 | struct regmap *regmap;
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| 31 | };
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| 32 |
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| 33 | static const struct tn48_reset_map tn48m_resets[] = {
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| 34 | [CPU_88F7040_RESET] = {0},
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| 35 | [CPU_88F6820_RESET] = {1},
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| 36 | [MAC_98DX3265_RESET] = {2},
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| 37 | [PHY_88E1680_RESET] = {4},
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| 38 | [PHY_88E1512_RESET] = {6},
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| 39 | [POE_RESET] = {7},
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| 40 | };
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| 41 |
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| 42 | static inline struct tn48_reset_data *to_tn48_reset_data(
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| 43 | struct reset_controller_dev *rcdev)
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| 44 | {
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| 45 | return container_of(rcdev, struct tn48_reset_data, rcdev);
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| 46 | }
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| 47 |
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| 48 | static int tn48m_control_reset(struct reset_controller_dev *rcdev,
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| 49 | unsigned long id)
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| 50 | {
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| 51 | struct tn48_reset_data *data = to_tn48_reset_data(rcdev);
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| 52 | unsigned int val;
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| 53 |
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| 54 | regmap_update_bits(data->regmap, TN48M_RESET_REG,
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| 55 | BIT(tn48m_resets[id].bit), 0);
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| 56 |
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| 57 | return regmap_read_poll_timeout(data->regmap,
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| 58 | TN48M_RESET_REG,
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| 59 | val,
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| 60 | val & BIT(tn48m_resets[id].bit),
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| 61 | TN48M_RESET_SLEEP_US,
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| 62 | TN48M_RESET_TIMEOUT_US);
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| 63 | }
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| 64 |
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| 65 | static int tn48m_control_status(struct reset_controller_dev *rcdev,
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| 66 | unsigned long id)
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| 67 | {
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| 68 | struct tn48_reset_data *data = to_tn48_reset_data(rcdev);
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| 69 | unsigned int regval;
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| 70 | int ret;
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| 71 |
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| 72 | ret = regmap_read(data->regmap, TN48M_RESET_REG, ®val);
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| 73 | if (ret < 0)
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| 74 | return ret;
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| 75 |
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| 76 | if (BIT(tn48m_resets[id].bit) & regval)
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| 77 | return 0;
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| 78 | else
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| 79 | return 1;
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| 80 | }
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| 81 |
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| 82 | static const struct reset_control_ops tn48_reset_ops = {
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| 83 | .reset = tn48m_control_reset,
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| 84 | .status = tn48m_control_status,
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| 85 | };
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| 86 |
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| 87 | static int tn48m_reset_probe(struct platform_device *pdev)
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| 88 | {
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| 89 | struct tn48_reset_data *data;
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| 90 | struct regmap *regmap;
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| 91 |
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| 92 | regmap = dev_get_regmap(pdev->dev.parent, NULL);
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| 93 | if (!regmap)
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| 94 | return -ENODEV;
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| 95 |
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| 96 | data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
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| 97 | if (!data)
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| 98 | return -ENOMEM;
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| 99 |
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| 100 | data->regmap = regmap;
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| 101 |
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| 102 | data->rcdev.owner = THIS_MODULE;
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| 103 | data->rcdev.ops = &tn48_reset_ops;
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| 104 | data->rcdev.nr_resets = ARRAY_SIZE(tn48m_resets);
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| 105 | data->rcdev.of_node = pdev->dev.of_node;
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| 106 |
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| 107 | return devm_reset_controller_register(&pdev->dev, &data->rcdev);
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| 108 | }
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| 109 |
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| 110 | static const struct of_device_id tn48m_reset_of_match[] = {
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| 111 | { .compatible = "delta,tn48m-reset" },
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| 112 | { }
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| 113 | };
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| 114 | MODULE_DEVICE_TABLE(of, tn48m_reset_of_match);
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| 115 |
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| 116 | static struct platform_driver tn48m_reset_driver = {
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| 117 | .driver = {
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| 118 | .name = "delta-tn48m-reset",
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| 119 | .of_match_table = tn48m_reset_of_match,
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| 120 | },
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| 121 | .probe = tn48m_reset_probe,
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| 122 | };
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| 123 | module_platform_driver(tn48m_reset_driver);
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| 124 |
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| 125 | MODULE_AUTHOR("Robert Marko <[email protected]>");
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| 126 | MODULE_DESCRIPTION("Delta TN48M CPLD reset driver");
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| 127 | MODULE_LICENSE("GPL");
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