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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips.
4 *
5 * Copyright (C) 2005 James Chapman (ds1337 core)
6 * Copyright (C) 2006 David Brownell
7 * Copyright (C) 2009 Matthias Fuchs (rx8025 support)
8 * Copyright (C) 2012 Bertrand Achard (nvram access fixes)
9 */
10
11#include <linux/bcd.h>
12#include <linux/i2c.h>
13#include <linux/init.h>
14#include <linux/kstrtox.h>
15#include <linux/module.h>
16#include <linux/property.h>
17#include <linux/rtc/ds1307.h>
18#include <linux/rtc.h>
19#include <linux/slab.h>
20#include <linux/string.h>
21#include <linux/hwmon.h>
22#include <linux/hwmon-sysfs.h>
23#include <linux/clk-provider.h>
24#include <linux/regmap.h>
25#include <linux/watchdog.h>
26
27/*
28 * We can't determine type by probing, but if we expect pre-Linux code
29 * to have set the chip up as a clock (turning on the oscillator and
30 * setting the date and time), Linux can ignore the non-clock features.
31 * That's a natural job for a factory or repair bench.
32 */
33enum ds_type {
34 unknown_ds_type, /* always first and 0 */
35 ds_1307,
36 ds_1308,
37 ds_1337,
38 ds_1338,
39 ds_1339,
40 ds_1340,
41 ds_1341,
42 ds_1388,
43 ds_3231,
44 m41t0,
45 m41t00,
46 m41t11,
47 mcp794xx,
48 rx_8025,
49 rx_8130,
50 last_ds_type /* always last */
51 /* rs5c372 too? different address... */
52};
53
54/* RTC registers don't differ much, except for the century flag */
55#define DS1307_REG_SECS 0x00 /* 00-59 */
56# define DS1307_BIT_CH 0x80
57# define DS1340_BIT_nEOSC 0x80
58# define MCP794XX_BIT_ST 0x80
59#define DS1307_REG_MIN 0x01 /* 00-59 */
60# define M41T0_BIT_OF 0x80
61#define DS1307_REG_HOUR 0x02 /* 00-23, or 1-12{am,pm} */
62# define DS1307_BIT_12HR 0x40 /* in REG_HOUR */
63# define DS1307_BIT_PM 0x20 /* in REG_HOUR */
64# define DS1340_BIT_CENTURY_EN 0x80 /* in REG_HOUR */
65# define DS1340_BIT_CENTURY 0x40 /* in REG_HOUR */
66#define DS1307_REG_WDAY 0x03 /* 01-07 */
67# define MCP794XX_BIT_OSCRUN BIT(5)
68# define MCP794XX_BIT_VBATEN 0x08
69#define DS1307_REG_MDAY 0x04 /* 01-31 */
70#define DS1307_REG_MONTH 0x05 /* 01-12 */
71# define DS1337_BIT_CENTURY 0x80 /* in REG_MONTH */
72#define DS1307_REG_YEAR 0x06 /* 00-99 */
73
74/*
75 * Other registers (control, status, alarms, trickle charge, NVRAM, etc)
76 * start at 7, and they differ a LOT. Only control and status matter for
77 * basic RTC date and time functionality; be careful using them.
78 */
79#define DS1307_REG_CONTROL 0x07 /* or ds1338 */
80# define DS1307_BIT_OUT 0x80
81# define DS1338_BIT_OSF 0x20
82# define DS1307_BIT_SQWE 0x10
83# define DS1307_BIT_RS1 0x02
84# define DS1307_BIT_RS0 0x01
85#define DS1337_REG_CONTROL 0x0e
86# define DS1337_BIT_nEOSC 0x80
87# define DS1339_BIT_BBSQI 0x20
88# define DS3231_BIT_BBSQW 0x40 /* same as BBSQI */
89# define DS1337_BIT_RS2 0x10
90# define DS1337_BIT_RS1 0x08
91# define DS1337_BIT_INTCN 0x04
92# define DS1337_BIT_A2IE 0x02
93# define DS1337_BIT_A1IE 0x01
94#define DS1340_REG_CONTROL 0x07
95# define DS1340_BIT_OUT 0x80
96# define DS1340_BIT_FT 0x40
97# define DS1340_BIT_CALIB_SIGN 0x20
98# define DS1340_M_CALIBRATION 0x1f
99#define DS1340_REG_FLAG 0x09
100# define DS1340_BIT_OSF 0x80
101#define DS1337_REG_STATUS 0x0f
102# define DS1337_BIT_OSF 0x80
103# define DS3231_BIT_EN32KHZ 0x08
104# define DS1337_BIT_A2I 0x02
105# define DS1337_BIT_A1I 0x01
106#define DS1339_REG_ALARM1_SECS 0x07
107
108#define DS13XX_TRICKLE_CHARGER_MAGIC 0xa0
109
110#define RX8025_REG_CTRL1 0x0e
111# define RX8025_BIT_2412 0x20
112#define RX8025_REG_CTRL2 0x0f
113# define RX8025_BIT_PON 0x10
114# define RX8025_BIT_VDET 0x40
115# define RX8025_BIT_XST 0x20
116
117#define RX8130_REG_ALARM_MIN 0x17
118#define RX8130_REG_ALARM_HOUR 0x18
119#define RX8130_REG_ALARM_WEEK_OR_DAY 0x19
120#define RX8130_REG_EXTENSION 0x1c
121#define RX8130_REG_EXTENSION_WADA BIT(3)
122#define RX8130_REG_FLAG 0x1d
123#define RX8130_REG_FLAG_VLF BIT(1)
124#define RX8130_REG_FLAG_AF BIT(3)
125#define RX8130_REG_CONTROL0 0x1e
126#define RX8130_REG_CONTROL0_AIE BIT(3)
127#define RX8130_REG_CONTROL1 0x1f
128#define RX8130_REG_CONTROL1_INIEN BIT(4)
129#define RX8130_REG_CONTROL1_CHGEN BIT(5)
130
131#define MCP794XX_REG_CONTROL 0x07
132# define MCP794XX_BIT_ALM0_EN 0x10
133# define MCP794XX_BIT_ALM1_EN 0x20
134#define MCP794XX_REG_ALARM0_BASE 0x0a
135#define MCP794XX_REG_ALARM0_CTRL 0x0d
136#define MCP794XX_REG_ALARM1_BASE 0x11
137#define MCP794XX_REG_ALARM1_CTRL 0x14
138# define MCP794XX_BIT_ALMX_IF BIT(3)
139# define MCP794XX_BIT_ALMX_C0 BIT(4)
140# define MCP794XX_BIT_ALMX_C1 BIT(5)
141# define MCP794XX_BIT_ALMX_C2 BIT(6)
142# define MCP794XX_BIT_ALMX_POL BIT(7)
143# define MCP794XX_MSK_ALMX_MATCH (MCP794XX_BIT_ALMX_C0 | \
144 MCP794XX_BIT_ALMX_C1 | \
145 MCP794XX_BIT_ALMX_C2)
146
147#define M41TXX_REG_CONTROL 0x07
148# define M41TXX_BIT_OUT BIT(7)
149# define M41TXX_BIT_FT BIT(6)
150# define M41TXX_BIT_CALIB_SIGN BIT(5)
151# define M41TXX_M_CALIBRATION GENMASK(4, 0)
152
153#define DS1388_REG_WDOG_HUN_SECS 0x08
154#define DS1388_REG_WDOG_SECS 0x09
155#define DS1388_REG_FLAG 0x0b
156# define DS1388_BIT_WF BIT(6)
157# define DS1388_BIT_OSF BIT(7)
158#define DS1388_REG_CONTROL 0x0c
159# define DS1388_BIT_RST BIT(0)
160# define DS1388_BIT_WDE BIT(1)
161# define DS1388_BIT_nEOSC BIT(7)
162
163/* negative offset step is -2.034ppm */
164#define M41TXX_NEG_OFFSET_STEP_PPB 2034
165/* positive offset step is +4.068ppm */
166#define M41TXX_POS_OFFSET_STEP_PPB 4068
167/* Min and max values supported with 'offset' interface by M41TXX */
168#define M41TXX_MIN_OFFSET ((-31) * M41TXX_NEG_OFFSET_STEP_PPB)
169#define M41TXX_MAX_OFFSET ((31) * M41TXX_POS_OFFSET_STEP_PPB)
170
171struct ds1307 {
172 enum ds_type type;
173 struct device *dev;
174 struct regmap *regmap;
175 const char *name;
176 struct rtc_device *rtc;
177#ifdef CONFIG_COMMON_CLK
178 struct clk_hw clks[2];
179#endif
180};
181
182struct chip_desc {
183 unsigned alarm:1;
184 u16 nvram_offset;
185 u16 nvram_size;
186 u8 offset; /* register's offset */
187 u8 century_reg;
188 u8 century_enable_bit;
189 u8 century_bit;
190 u8 bbsqi_bit;
191 irq_handler_t irq_handler;
192 const struct rtc_class_ops *rtc_ops;
193 u16 trickle_charger_reg;
194 u8 (*do_trickle_setup)(struct ds1307 *, u32,
195 bool);
196 /* Does the RTC require trickle-resistor-ohms to select the value of
197 * the resistor between Vcc and Vbackup?
198 */
199 bool requires_trickle_resistor;
200 /* Some RTC's batteries and supercaps were charged by default, others
201 * allow charging but were not configured previously to do so.
202 * Remember this behavior to stay backwards compatible.
203 */
204 bool charge_default;
205};
206
207static const struct chip_desc chips[last_ds_type];
208
209static int ds1307_get_time(struct device *dev, struct rtc_time *t)
210{
211 struct ds1307 *ds1307 = dev_get_drvdata(dev);
212 int tmp, ret;
213 const struct chip_desc *chip = &chips[ds1307->type];
214 u8 regs[7];
215
216 if (ds1307->type == rx_8130) {
217 unsigned int regflag;
218 ret = regmap_read(ds1307->regmap, RX8130_REG_FLAG, &regflag);
219 if (ret) {
220 dev_err(dev, "%s error %d\n", "read", ret);
221 return ret;
222 }
223
224 if (regflag & RX8130_REG_FLAG_VLF) {
225 dev_warn_once(dev, "oscillator failed, set time!\n");
226 return -EINVAL;
227 }
228 }
229
230 /* read the RTC date and time registers all at once */
231 ret = regmap_bulk_read(ds1307->regmap, chip->offset, regs,
232 sizeof(regs));
233 if (ret) {
234 dev_err(dev, "%s error %d\n", "read", ret);
235 return ret;
236 }
237
238 dev_dbg(dev, "%s: %7ph\n", "read", regs);
239
240 /* if oscillator fail bit is set, no data can be trusted */
241 if (ds1307->type == m41t0 &&
242 regs[DS1307_REG_MIN] & M41T0_BIT_OF) {
243 dev_warn_once(dev, "oscillator failed, set time!\n");
244 return -EINVAL;
245 } else if (ds1307->type == mcp794xx &&
246 !(regs[DS1307_REG_WDAY] & MCP794XX_BIT_OSCRUN)) {
247 dev_warn_once(dev, "oscillator failed, set time!\n");
248 return -EINVAL;
249 }
250
251 tmp = regs[DS1307_REG_SECS];
252 switch (ds1307->type) {
253 case ds_1307:
254 case m41t0:
255 case m41t00:
256 case m41t11:
257 if (tmp & DS1307_BIT_CH)
258 return -EINVAL;
259 break;
260 case ds_1308:
261 case ds_1338:
262 if (tmp & DS1307_BIT_CH)
263 return -EINVAL;
264
265 ret = regmap_read(ds1307->regmap, DS1307_REG_CONTROL, &tmp);
266 if (ret)
267 return ret;
268 if (tmp & DS1338_BIT_OSF)
269 return -EINVAL;
270 break;
271 case ds_1337:
272 case ds_1339:
273 case ds_1341:
274 case ds_3231:
275 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &tmp);
276 if (ret)
277 return ret;
278 if (tmp & DS1337_BIT_OSF)
279 return -EINVAL;
280 break;
281 case ds_1340:
282 if (tmp & DS1340_BIT_nEOSC)
283 return -EINVAL;
284
285 ret = regmap_read(ds1307->regmap, DS1340_REG_FLAG, &tmp);
286 if (ret)
287 return ret;
288 if (tmp & DS1340_BIT_OSF)
289 return -EINVAL;
290 break;
291 case ds_1388:
292 ret = regmap_read(ds1307->regmap, DS1388_REG_FLAG, &tmp);
293 if (ret)
294 return ret;
295 if (tmp & DS1388_BIT_OSF)
296 return -EINVAL;
297 break;
298 case mcp794xx:
299 if (!(tmp & MCP794XX_BIT_ST))
300 return -EINVAL;
301
302 break;
303 default:
304 break;
305 }
306
307 t->tm_sec = bcd2bin(regs[DS1307_REG_SECS] & 0x7f);
308 t->tm_min = bcd2bin(regs[DS1307_REG_MIN] & 0x7f);
309 tmp = regs[DS1307_REG_HOUR] & 0x3f;
310 t->tm_hour = bcd2bin(tmp);
311 /* rx8130 is bit position, not BCD */
312 if (ds1307->type == rx_8130)
313 t->tm_wday = fls(regs[DS1307_REG_WDAY] & 0x7f) - 1;
314 else
315 t->tm_wday = bcd2bin(regs[DS1307_REG_WDAY] & 0x07) - 1;
316 t->tm_mday = bcd2bin(regs[DS1307_REG_MDAY] & 0x3f);
317 tmp = regs[DS1307_REG_MONTH] & 0x1f;
318 t->tm_mon = bcd2bin(tmp) - 1;
319 t->tm_year = bcd2bin(regs[DS1307_REG_YEAR]) + 100;
320
321 if (regs[chip->century_reg] & chip->century_bit &&
322 IS_ENABLED(CONFIG_RTC_DRV_DS1307_CENTURY))
323 t->tm_year += 100;
324
325 dev_dbg(dev, "%s secs=%d, mins=%d, "
326 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
327 "read", t->tm_sec, t->tm_min,
328 t->tm_hour, t->tm_mday,
329 t->tm_mon, t->tm_year, t->tm_wday);
330
331 return 0;
332}
333
334static int ds1307_set_time(struct device *dev, struct rtc_time *t)
335{
336 struct ds1307 *ds1307 = dev_get_drvdata(dev);
337 const struct chip_desc *chip = &chips[ds1307->type];
338 int result;
339 int tmp;
340 u8 regs[7];
341
342 dev_dbg(dev, "%s secs=%d, mins=%d, "
343 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
344 "write", t->tm_sec, t->tm_min,
345 t->tm_hour, t->tm_mday,
346 t->tm_mon, t->tm_year, t->tm_wday);
347
348 if (t->tm_year < 100)
349 return -EINVAL;
350
351#ifdef CONFIG_RTC_DRV_DS1307_CENTURY
352 if (t->tm_year > (chip->century_bit ? 299 : 199))
353 return -EINVAL;
354#else
355 if (t->tm_year > 199)
356 return -EINVAL;
357#endif
358
359 regs[DS1307_REG_SECS] = bin2bcd(t->tm_sec);
360 regs[DS1307_REG_MIN] = bin2bcd(t->tm_min);
361 regs[DS1307_REG_HOUR] = bin2bcd(t->tm_hour);
362 /* rx8130 is bit position, not BCD */
363 if (ds1307->type == rx_8130)
364 regs[DS1307_REG_WDAY] = 1 << t->tm_wday;
365 else
366 regs[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1);
367 regs[DS1307_REG_MDAY] = bin2bcd(t->tm_mday);
368 regs[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1);
369
370 /* assume 20YY not 19YY */
371 tmp = t->tm_year % 100;
372 regs[DS1307_REG_YEAR] = bin2bcd(tmp);
373
374 if (chip->century_enable_bit)
375 regs[chip->century_reg] |= chip->century_enable_bit;
376 if (t->tm_year > 199 && chip->century_bit)
377 regs[chip->century_reg] |= chip->century_bit;
378
379 switch (ds1307->type) {
380 case ds_1308:
381 case ds_1338:
382 regmap_update_bits(ds1307->regmap, DS1307_REG_CONTROL,
383 DS1338_BIT_OSF, 0);
384 break;
385 case ds_1337:
386 case ds_1339:
387 case ds_1341:
388 case ds_3231:
389 regmap_update_bits(ds1307->regmap, DS1337_REG_STATUS,
390 DS1337_BIT_OSF, 0);
391 break;
392 case ds_1340:
393 regmap_update_bits(ds1307->regmap, DS1340_REG_FLAG,
394 DS1340_BIT_OSF, 0);
395 break;
396 case ds_1388:
397 regmap_update_bits(ds1307->regmap, DS1388_REG_FLAG,
398 DS1388_BIT_OSF, 0);
399 break;
400 case mcp794xx:
401 /*
402 * these bits were cleared when preparing the date/time
403 * values and need to be set again before writing the
404 * regsfer out to the device.
405 */
406 regs[DS1307_REG_SECS] |= MCP794XX_BIT_ST;
407 regs[DS1307_REG_WDAY] |= MCP794XX_BIT_VBATEN;
408 break;
409 default:
410 break;
411 }
412
413 dev_dbg(dev, "%s: %7ph\n", "write", regs);
414
415 result = regmap_bulk_write(ds1307->regmap, chip->offset, regs,
416 sizeof(regs));
417 if (result) {
418 dev_err(dev, "%s error %d\n", "write", result);
419 return result;
420 }
421
422 if (ds1307->type == rx_8130) {
423 /* clear Voltage Loss Flag as data is available now */
424 result = regmap_write(ds1307->regmap, RX8130_REG_FLAG,
425 ~(u8)RX8130_REG_FLAG_VLF);
426 if (result) {
427 dev_err(dev, "%s error %d\n", "write", result);
428 return result;
429 }
430 }
431
432 return 0;
433}
434
435static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t)
436{
437 struct ds1307 *ds1307 = dev_get_drvdata(dev);
438 int ret;
439 u8 regs[9];
440
441 /* read all ALARM1, ALARM2, and status registers at once */
442 ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS,
443 regs, sizeof(regs));
444 if (ret) {
445 dev_err(dev, "%s error %d\n", "alarm read", ret);
446 return ret;
447 }
448
449 dev_dbg(dev, "%s: %4ph, %3ph, %2ph\n", "alarm read",
450 &regs[0], &regs[4], &regs[7]);
451
452 /*
453 * report alarm time (ALARM1); assume 24 hour and day-of-month modes,
454 * and that all four fields are checked matches
455 */
456 t->time.tm_sec = bcd2bin(regs[0] & 0x7f);
457 t->time.tm_min = bcd2bin(regs[1] & 0x7f);
458 t->time.tm_hour = bcd2bin(regs[2] & 0x3f);
459 t->time.tm_mday = bcd2bin(regs[3] & 0x3f);
460
461 /* ... and status */
462 t->enabled = !!(regs[7] & DS1337_BIT_A1IE);
463 t->pending = !!(regs[8] & DS1337_BIT_A1I);
464
465 dev_dbg(dev, "%s secs=%d, mins=%d, "
466 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
467 "alarm read", t->time.tm_sec, t->time.tm_min,
468 t->time.tm_hour, t->time.tm_mday,
469 t->enabled, t->pending);
470
471 return 0;
472}
473
474static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t)
475{
476 struct ds1307 *ds1307 = dev_get_drvdata(dev);
477 unsigned char regs[9];
478 u8 control, status;
479 int ret;
480
481 dev_dbg(dev, "%s secs=%d, mins=%d, "
482 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
483 "alarm set", t->time.tm_sec, t->time.tm_min,
484 t->time.tm_hour, t->time.tm_mday,
485 t->enabled, t->pending);
486
487 /* read current status of both alarms and the chip */
488 ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs,
489 sizeof(regs));
490 if (ret) {
491 dev_err(dev, "%s error %d\n", "alarm write", ret);
492 return ret;
493 }
494 control = regs[7];
495 status = regs[8];
496
497 dev_dbg(dev, "%s: %4ph, %3ph, %02x %02x\n", "alarm set (old status)",
498 &regs[0], &regs[4], control, status);
499
500 /* set ALARM1, using 24 hour and day-of-month modes */
501 regs[0] = bin2bcd(t->time.tm_sec);
502 regs[1] = bin2bcd(t->time.tm_min);
503 regs[2] = bin2bcd(t->time.tm_hour);
504 regs[3] = bin2bcd(t->time.tm_mday);
505
506 /* set ALARM2 to non-garbage */
507 regs[4] = 0;
508 regs[5] = 0;
509 regs[6] = 0;
510
511 /* disable alarms */
512 regs[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE);
513 regs[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I);
514
515 ret = regmap_bulk_write(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs,
516 sizeof(regs));
517 if (ret) {
518 dev_err(dev, "can't set alarm time\n");
519 return ret;
520 }
521
522 /* optionally enable ALARM1 */
523 if (t->enabled) {
524 dev_dbg(dev, "alarm IRQ armed\n");
525 regs[7] |= DS1337_BIT_A1IE; /* only ALARM1 is used */
526 regmap_write(ds1307->regmap, DS1337_REG_CONTROL, regs[7]);
527 }
528
529 return 0;
530}
531
532static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled)
533{
534 struct ds1307 *ds1307 = dev_get_drvdata(dev);
535
536 return regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
537 DS1337_BIT_A1IE,
538 enabled ? DS1337_BIT_A1IE : 0);
539}
540
541static u8 do_trickle_setup_ds1339(struct ds1307 *ds1307, u32 ohms, bool diode)
542{
543 u8 setup = (diode) ? DS1307_TRICKLE_CHARGER_DIODE :
544 DS1307_TRICKLE_CHARGER_NO_DIODE;
545
546 setup |= DS13XX_TRICKLE_CHARGER_MAGIC;
547
548 switch (ohms) {
549 case 250:
550 setup |= DS1307_TRICKLE_CHARGER_250_OHM;
551 break;
552 case 2000:
553 setup |= DS1307_TRICKLE_CHARGER_2K_OHM;
554 break;
555 case 4000:
556 setup |= DS1307_TRICKLE_CHARGER_4K_OHM;
557 break;
558 default:
559 dev_warn(ds1307->dev,
560 "Unsupported ohm value %u in dt\n", ohms);
561 return 0;
562 }
563 return setup;
564}
565
566static u8 do_trickle_setup_rx8130(struct ds1307 *ds1307, u32 ohms, bool diode)
567{
568 /* make sure that the backup battery is enabled */
569 u8 setup = RX8130_REG_CONTROL1_INIEN;
570 if (diode)
571 setup |= RX8130_REG_CONTROL1_CHGEN;
572
573 return setup;
574}
575
576static irqreturn_t rx8130_irq(int irq, void *dev_id)
577{
578 struct ds1307 *ds1307 = dev_id;
579 u8 ctl[3];
580 int ret;
581
582 rtc_lock(ds1307->rtc);
583
584 /* Read control registers. */
585 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
586 sizeof(ctl));
587 if (ret < 0)
588 goto out;
589 if (!(ctl[1] & RX8130_REG_FLAG_AF))
590 goto out;
591 ctl[1] &= ~RX8130_REG_FLAG_AF;
592 ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
593
594 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
595 sizeof(ctl));
596 if (ret < 0)
597 goto out;
598
599 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
600
601out:
602 rtc_unlock(ds1307->rtc);
603
604 return IRQ_HANDLED;
605}
606
607static int rx8130_read_alarm(struct device *dev, struct rtc_wkalrm *t)
608{
609 struct ds1307 *ds1307 = dev_get_drvdata(dev);
610 u8 ald[3], ctl[3];
611 int ret;
612
613 /* Read alarm registers. */
614 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_ALARM_MIN, ald,
615 sizeof(ald));
616 if (ret < 0)
617 return ret;
618
619 /* Read control registers. */
620 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
621 sizeof(ctl));
622 if (ret < 0)
623 return ret;
624
625 t->enabled = !!(ctl[2] & RX8130_REG_CONTROL0_AIE);
626 t->pending = !!(ctl[1] & RX8130_REG_FLAG_AF);
627
628 /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
629 t->time.tm_sec = -1;
630 t->time.tm_min = bcd2bin(ald[0] & 0x7f);
631 t->time.tm_hour = bcd2bin(ald[1] & 0x7f);
632 t->time.tm_wday = -1;
633 t->time.tm_mday = bcd2bin(ald[2] & 0x7f);
634 t->time.tm_mon = -1;
635 t->time.tm_year = -1;
636 t->time.tm_yday = -1;
637 t->time.tm_isdst = -1;
638
639 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d enabled=%d\n",
640 __func__, t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
641 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled);
642
643 return 0;
644}
645
646static int rx8130_set_alarm(struct device *dev, struct rtc_wkalrm *t)
647{
648 struct ds1307 *ds1307 = dev_get_drvdata(dev);
649 u8 ald[3], ctl[3];
650 int ret;
651
652 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
653 "enabled=%d pending=%d\n", __func__,
654 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
655 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
656 t->enabled, t->pending);
657
658 /* Read control registers. */
659 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
660 sizeof(ctl));
661 if (ret < 0)
662 return ret;
663
664 ctl[0] |= RX8130_REG_EXTENSION_WADA;
665 ctl[1] &= ~RX8130_REG_FLAG_AF;
666 ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
667
668 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
669 sizeof(ctl));
670 if (ret < 0)
671 return ret;
672
673 /* Hardware alarm precision is 1 minute! */
674 ald[0] = bin2bcd(t->time.tm_min);
675 ald[1] = bin2bcd(t->time.tm_hour);
676 ald[2] = bin2bcd(t->time.tm_mday);
677
678 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_ALARM_MIN, ald,
679 sizeof(ald));
680 if (ret < 0)
681 return ret;
682
683 if (!t->enabled)
684 return 0;
685
686 ctl[2] |= RX8130_REG_CONTROL0_AIE;
687
688 return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, ctl[2]);
689}
690
691static int rx8130_alarm_irq_enable(struct device *dev, unsigned int enabled)
692{
693 struct ds1307 *ds1307 = dev_get_drvdata(dev);
694 int ret, reg;
695
696 ret = regmap_read(ds1307->regmap, RX8130_REG_CONTROL0, &reg);
697 if (ret < 0)
698 return ret;
699
700 if (enabled)
701 reg |= RX8130_REG_CONTROL0_AIE;
702 else
703 reg &= ~RX8130_REG_CONTROL0_AIE;
704
705 return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, reg);
706}
707
708static irqreturn_t mcp794xx_irq(int irq, void *dev_id)
709{
710 struct ds1307 *ds1307 = dev_id;
711 struct mutex *lock = &ds1307->rtc->ops_lock;
712 int reg, ret;
713
714 mutex_lock(lock);
715
716 /* Check and clear alarm 0 interrupt flag. */
717 ret = regmap_read(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, &reg);
718 if (ret)
719 goto out;
720 if (!(reg & MCP794XX_BIT_ALMX_IF))
721 goto out;
722 reg &= ~MCP794XX_BIT_ALMX_IF;
723 ret = regmap_write(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, reg);
724 if (ret)
725 goto out;
726
727 /* Disable alarm 0. */
728 ret = regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
729 MCP794XX_BIT_ALM0_EN, 0);
730 if (ret)
731 goto out;
732
733 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
734
735out:
736 mutex_unlock(lock);
737
738 return IRQ_HANDLED;
739}
740
741static int mcp794xx_read_alarm(struct device *dev, struct rtc_wkalrm *t)
742{
743 struct ds1307 *ds1307 = dev_get_drvdata(dev);
744 u8 regs[10];
745 int ret;
746
747 /* Read control and alarm 0 registers. */
748 ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
749 sizeof(regs));
750 if (ret)
751 return ret;
752
753 t->enabled = !!(regs[0] & MCP794XX_BIT_ALM0_EN);
754
755 /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
756 t->time.tm_sec = bcd2bin(regs[3] & 0x7f);
757 t->time.tm_min = bcd2bin(regs[4] & 0x7f);
758 t->time.tm_hour = bcd2bin(regs[5] & 0x3f);
759 t->time.tm_wday = bcd2bin(regs[6] & 0x7) - 1;
760 t->time.tm_mday = bcd2bin(regs[7] & 0x3f);
761 t->time.tm_mon = bcd2bin(regs[8] & 0x1f) - 1;
762 t->time.tm_year = -1;
763 t->time.tm_yday = -1;
764 t->time.tm_isdst = -1;
765
766 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
767 "enabled=%d polarity=%d irq=%d match=%lu\n", __func__,
768 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
769 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled,
770 !!(regs[6] & MCP794XX_BIT_ALMX_POL),
771 !!(regs[6] & MCP794XX_BIT_ALMX_IF),
772 (regs[6] & MCP794XX_MSK_ALMX_MATCH) >> 4);
773
774 return 0;
775}
776
777/*
778 * We may have a random RTC weekday, therefore calculate alarm weekday based
779 * on current weekday we read from the RTC timekeeping regs
780 */
781static int mcp794xx_alm_weekday(struct device *dev, struct rtc_time *tm_alarm)
782{
783 struct rtc_time tm_now;
784 int days_now, days_alarm, ret;
785
786 ret = ds1307_get_time(dev, &tm_now);
787 if (ret)
788 return ret;
789
790 days_now = div_s64(rtc_tm_to_time64(&tm_now), 24 * 60 * 60);
791 days_alarm = div_s64(rtc_tm_to_time64(tm_alarm), 24 * 60 * 60);
792
793 return (tm_now.tm_wday + days_alarm - days_now) % 7 + 1;
794}
795
796static int mcp794xx_set_alarm(struct device *dev, struct rtc_wkalrm *t)
797{
798 struct ds1307 *ds1307 = dev_get_drvdata(dev);
799 unsigned char regs[10];
800 int wday, ret;
801
802 wday = mcp794xx_alm_weekday(dev, &t->time);
803 if (wday < 0)
804 return wday;
805
806 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
807 "enabled=%d pending=%d\n", __func__,
808 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
809 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
810 t->enabled, t->pending);
811
812 /* Read control and alarm 0 registers. */
813 ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
814 sizeof(regs));
815 if (ret)
816 return ret;
817
818 /* Set alarm 0, using 24-hour and day-of-month modes. */
819 regs[3] = bin2bcd(t->time.tm_sec);
820 regs[4] = bin2bcd(t->time.tm_min);
821 regs[5] = bin2bcd(t->time.tm_hour);
822 regs[6] = wday;
823 regs[7] = bin2bcd(t->time.tm_mday);
824 regs[8] = bin2bcd(t->time.tm_mon + 1);
825
826 /* Clear the alarm 0 interrupt flag. */
827 regs[6] &= ~MCP794XX_BIT_ALMX_IF;
828 /* Set alarm match: second, minute, hour, day, date, month. */
829 regs[6] |= MCP794XX_MSK_ALMX_MATCH;
830 /* Disable interrupt. We will not enable until completely programmed */
831 regs[0] &= ~MCP794XX_BIT_ALM0_EN;
832
833 ret = regmap_bulk_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
834 sizeof(regs));
835 if (ret)
836 return ret;
837
838 if (!t->enabled)
839 return 0;
840 regs[0] |= MCP794XX_BIT_ALM0_EN;
841 return regmap_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs[0]);
842}
843
844static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled)
845{
846 struct ds1307 *ds1307 = dev_get_drvdata(dev);
847
848 return regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
849 MCP794XX_BIT_ALM0_EN,
850 enabled ? MCP794XX_BIT_ALM0_EN : 0);
851}
852
853static int m41txx_rtc_read_offset(struct device *dev, long *offset)
854{
855 struct ds1307 *ds1307 = dev_get_drvdata(dev);
856 unsigned int ctrl_reg;
857 u8 val;
858
859 regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg);
860
861 val = ctrl_reg & M41TXX_M_CALIBRATION;
862
863 /* check if positive */
864 if (ctrl_reg & M41TXX_BIT_CALIB_SIGN)
865 *offset = (val * M41TXX_POS_OFFSET_STEP_PPB);
866 else
867 *offset = -(val * M41TXX_NEG_OFFSET_STEP_PPB);
868
869 return 0;
870}
871
872static int m41txx_rtc_set_offset(struct device *dev, long offset)
873{
874 struct ds1307 *ds1307 = dev_get_drvdata(dev);
875 unsigned int ctrl_reg;
876
877 if ((offset < M41TXX_MIN_OFFSET) || (offset > M41TXX_MAX_OFFSET))
878 return -ERANGE;
879
880 if (offset >= 0) {
881 ctrl_reg = DIV_ROUND_CLOSEST(offset,
882 M41TXX_POS_OFFSET_STEP_PPB);
883 ctrl_reg |= M41TXX_BIT_CALIB_SIGN;
884 } else {
885 ctrl_reg = DIV_ROUND_CLOSEST(abs(offset),
886 M41TXX_NEG_OFFSET_STEP_PPB);
887 }
888
889 return regmap_update_bits(ds1307->regmap, M41TXX_REG_CONTROL,
890 M41TXX_M_CALIBRATION | M41TXX_BIT_CALIB_SIGN,
891 ctrl_reg);
892}
893
894#ifdef CONFIG_WATCHDOG_CORE
895static int ds1388_wdt_start(struct watchdog_device *wdt_dev)
896{
897 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
898 u8 regs[2];
899 int ret;
900
901 ret = regmap_update_bits(ds1307->regmap, DS1388_REG_FLAG,
902 DS1388_BIT_WF, 0);
903 if (ret)
904 return ret;
905
906 ret = regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL,
907 DS1388_BIT_WDE | DS1388_BIT_RST, 0);
908 if (ret)
909 return ret;
910
911 /*
912 * watchdog timeouts are measured in seconds. So ignore hundredths of
913 * seconds field.
914 */
915 regs[0] = 0;
916 regs[1] = bin2bcd(wdt_dev->timeout);
917
918 ret = regmap_bulk_write(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs,
919 sizeof(regs));
920 if (ret)
921 return ret;
922
923 return regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL,
924 DS1388_BIT_WDE | DS1388_BIT_RST,
925 DS1388_BIT_WDE | DS1388_BIT_RST);
926}
927
928static int ds1388_wdt_stop(struct watchdog_device *wdt_dev)
929{
930 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
931
932 return regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL,
933 DS1388_BIT_WDE | DS1388_BIT_RST, 0);
934}
935
936static int ds1388_wdt_ping(struct watchdog_device *wdt_dev)
937{
938 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
939 u8 regs[2];
940
941 return regmap_bulk_read(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs,
942 sizeof(regs));
943}
944
945static int ds1388_wdt_set_timeout(struct watchdog_device *wdt_dev,
946 unsigned int val)
947{
948 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
949 u8 regs[2];
950
951 wdt_dev->timeout = val;
952 regs[0] = 0;
953 regs[1] = bin2bcd(wdt_dev->timeout);
954
955 return regmap_bulk_write(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs,
956 sizeof(regs));
957}
958#endif
959
960static const struct rtc_class_ops rx8130_rtc_ops = {
961 .read_time = ds1307_get_time,
962 .set_time = ds1307_set_time,
963 .read_alarm = rx8130_read_alarm,
964 .set_alarm = rx8130_set_alarm,
965 .alarm_irq_enable = rx8130_alarm_irq_enable,
966};
967
968static const struct rtc_class_ops mcp794xx_rtc_ops = {
969 .read_time = ds1307_get_time,
970 .set_time = ds1307_set_time,
971 .read_alarm = mcp794xx_read_alarm,
972 .set_alarm = mcp794xx_set_alarm,
973 .alarm_irq_enable = mcp794xx_alarm_irq_enable,
974};
975
976static const struct rtc_class_ops m41txx_rtc_ops = {
977 .read_time = ds1307_get_time,
978 .set_time = ds1307_set_time,
979 .read_alarm = ds1337_read_alarm,
980 .set_alarm = ds1337_set_alarm,
981 .alarm_irq_enable = ds1307_alarm_irq_enable,
982 .read_offset = m41txx_rtc_read_offset,
983 .set_offset = m41txx_rtc_set_offset,
984};
985
986static const struct chip_desc chips[last_ds_type] = {
987 [ds_1307] = {
988 .nvram_offset = 8,
989 .nvram_size = 56,
990 },
991 [ds_1308] = {
992 .nvram_offset = 8,
993 .nvram_size = 56,
994 },
995 [ds_1337] = {
996 .alarm = 1,
997 .century_reg = DS1307_REG_MONTH,
998 .century_bit = DS1337_BIT_CENTURY,
999 },
1000 [ds_1338] = {
1001 .nvram_offset = 8,
1002 .nvram_size = 56,
1003 },
1004 [ds_1339] = {
1005 .alarm = 1,
1006 .century_reg = DS1307_REG_MONTH,
1007 .century_bit = DS1337_BIT_CENTURY,
1008 .bbsqi_bit = DS1339_BIT_BBSQI,
1009 .trickle_charger_reg = 0x10,
1010 .do_trickle_setup = &do_trickle_setup_ds1339,
1011 .requires_trickle_resistor = true,
1012 .charge_default = true,
1013 },
1014 [ds_1340] = {
1015 .century_reg = DS1307_REG_HOUR,
1016 .century_enable_bit = DS1340_BIT_CENTURY_EN,
1017 .century_bit = DS1340_BIT_CENTURY,
1018 .do_trickle_setup = &do_trickle_setup_ds1339,
1019 .trickle_charger_reg = 0x08,
1020 .requires_trickle_resistor = true,
1021 .charge_default = true,
1022 },
1023 [ds_1341] = {
1024 .century_reg = DS1307_REG_MONTH,
1025 .century_bit = DS1337_BIT_CENTURY,
1026 },
1027 [ds_1388] = {
1028 .offset = 1,
1029 .trickle_charger_reg = 0x0a,
1030 },
1031 [ds_3231] = {
1032 .alarm = 1,
1033 .century_reg = DS1307_REG_MONTH,
1034 .century_bit = DS1337_BIT_CENTURY,
1035 .bbsqi_bit = DS3231_BIT_BBSQW,
1036 },
1037 [rx_8130] = {
1038 .alarm = 1,
1039 /* this is battery backed SRAM */
1040 .nvram_offset = 0x20,
1041 .nvram_size = 4, /* 32bit (4 word x 8 bit) */
1042 .offset = 0x10,
1043 .irq_handler = rx8130_irq,
1044 .rtc_ops = &rx8130_rtc_ops,
1045 .trickle_charger_reg = RX8130_REG_CONTROL1,
1046 .do_trickle_setup = &do_trickle_setup_rx8130,
1047 },
1048 [m41t0] = {
1049 .rtc_ops = &m41txx_rtc_ops,
1050 },
1051 [m41t00] = {
1052 .rtc_ops = &m41txx_rtc_ops,
1053 },
1054 [m41t11] = {
1055 /* this is battery backed SRAM */
1056 .nvram_offset = 8,
1057 .nvram_size = 56,
1058 .rtc_ops = &m41txx_rtc_ops,
1059 },
1060 [mcp794xx] = {
1061 .alarm = 1,
1062 /* this is battery backed SRAM */
1063 .nvram_offset = 0x20,
1064 .nvram_size = 0x40,
1065 .irq_handler = mcp794xx_irq,
1066 .rtc_ops = &mcp794xx_rtc_ops,
1067 },
1068};
1069
1070static const struct i2c_device_id ds1307_id[] = {
1071 { .name = "ds1307", .driver_data = ds_1307 },
1072 { .name = "ds1308", .driver_data = ds_1308 },
1073 { .name = "ds1337", .driver_data = ds_1337 },
1074 { .name = "ds1338", .driver_data = ds_1338 },
1075 { .name = "ds1339", .driver_data = ds_1339 },
1076 { .name = "ds1388", .driver_data = ds_1388 },
1077 { .name = "ds1340", .driver_data = ds_1340 },
1078 { .name = "ds1341", .driver_data = ds_1341 },
1079 { .name = "ds3231", .driver_data = ds_3231 },
1080 { .name = "m41t0", .driver_data = m41t0 },
1081 { .name = "m41t00", .driver_data = m41t00 },
1082 { .name = "m41t11", .driver_data = m41t11 },
1083 { .name = "mcp7940x", .driver_data = mcp794xx },
1084 { .name = "mcp7941x", .driver_data = mcp794xx },
1085 { .name = "pt7c4338", .driver_data = ds_1307 },
1086 { .name = "rx8025", .driver_data = rx_8025 },
1087 { .name = "isl12057", .driver_data = ds_1337 },
1088 { .name = "rx8130", .driver_data = rx_8130 },
1089 { }
1090};
1091MODULE_DEVICE_TABLE(i2c, ds1307_id);
1092
1093static const struct of_device_id ds1307_of_match[] = {
1094 {
1095 .compatible = "dallas,ds1307",
1096 .data = (void *)ds_1307
1097 },
1098 {
1099 .compatible = "dallas,ds1308",
1100 .data = (void *)ds_1308
1101 },
1102 {
1103 .compatible = "dallas,ds1337",
1104 .data = (void *)ds_1337
1105 },
1106 {
1107 .compatible = "dallas,ds1338",
1108 .data = (void *)ds_1338
1109 },
1110 {
1111 .compatible = "dallas,ds1339",
1112 .data = (void *)ds_1339
1113 },
1114 {
1115 .compatible = "dallas,ds1388",
1116 .data = (void *)ds_1388
1117 },
1118 {
1119 .compatible = "dallas,ds1340",
1120 .data = (void *)ds_1340
1121 },
1122 {
1123 .compatible = "dallas,ds1341",
1124 .data = (void *)ds_1341
1125 },
1126 {
1127 .compatible = "maxim,ds3231",
1128 .data = (void *)ds_3231
1129 },
1130 {
1131 .compatible = "st,m41t0",
1132 .data = (void *)m41t0
1133 },
1134 {
1135 .compatible = "st,m41t00",
1136 .data = (void *)m41t00
1137 },
1138 {
1139 .compatible = "st,m41t11",
1140 .data = (void *)m41t11
1141 },
1142 {
1143 .compatible = "microchip,mcp7940x",
1144 .data = (void *)mcp794xx
1145 },
1146 {
1147 .compatible = "microchip,mcp7941x",
1148 .data = (void *)mcp794xx
1149 },
1150 {
1151 .compatible = "pericom,pt7c4338",
1152 .data = (void *)ds_1307
1153 },
1154 {
1155 .compatible = "epson,rx8025",
1156 .data = (void *)rx_8025
1157 },
1158 {
1159 .compatible = "isil,isl12057",
1160 .data = (void *)ds_1337
1161 },
1162 {
1163 .compatible = "epson,rx8130",
1164 .data = (void *)rx_8130
1165 },
1166 { }
1167};
1168MODULE_DEVICE_TABLE(of, ds1307_of_match);
1169
1170/*
1171 * The ds1337 and ds1339 both have two alarms, but we only use the first
1172 * one (with a "seconds" field). For ds1337 we expect nINTA is our alarm
1173 * signal; ds1339 chips have only one alarm signal.
1174 */
1175static irqreturn_t ds1307_irq(int irq, void *dev_id)
1176{
1177 struct ds1307 *ds1307 = dev_id;
1178 struct mutex *lock = &ds1307->rtc->ops_lock;
1179 int stat, ret;
1180
1181 mutex_lock(lock);
1182 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &stat);
1183 if (ret)
1184 goto out;
1185
1186 if (stat & DS1337_BIT_A1I) {
1187 stat &= ~DS1337_BIT_A1I;
1188 regmap_write(ds1307->regmap, DS1337_REG_STATUS, stat);
1189
1190 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
1191 DS1337_BIT_A1IE, 0);
1192 if (ret)
1193 goto out;
1194
1195 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
1196 }
1197
1198out:
1199 mutex_unlock(lock);
1200
1201 return IRQ_HANDLED;
1202}
1203
1204/*----------------------------------------------------------------------*/
1205
1206static const struct rtc_class_ops ds13xx_rtc_ops = {
1207 .read_time = ds1307_get_time,
1208 .set_time = ds1307_set_time,
1209 .read_alarm = ds1337_read_alarm,
1210 .set_alarm = ds1337_set_alarm,
1211 .alarm_irq_enable = ds1307_alarm_irq_enable,
1212};
1213
1214static ssize_t frequency_test_store(struct device *dev,
1215 struct device_attribute *attr,
1216 const char *buf, size_t count)
1217{
1218 struct ds1307 *ds1307 = dev_get_drvdata(dev->parent);
1219 bool freq_test_en;
1220 int ret;
1221
1222 ret = kstrtobool(buf, &freq_test_en);
1223 if (ret) {
1224 dev_err(dev, "Failed to store RTC Frequency Test attribute\n");
1225 return ret;
1226 }
1227
1228 regmap_update_bits(ds1307->regmap, M41TXX_REG_CONTROL, M41TXX_BIT_FT,
1229 freq_test_en ? M41TXX_BIT_FT : 0);
1230
1231 return count;
1232}
1233
1234static ssize_t frequency_test_show(struct device *dev,
1235 struct device_attribute *attr,
1236 char *buf)
1237{
1238 struct ds1307 *ds1307 = dev_get_drvdata(dev->parent);
1239 unsigned int ctrl_reg;
1240
1241 regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg);
1242
1243 return sysfs_emit(buf, (ctrl_reg & M41TXX_BIT_FT) ? "on\n" : "off\n");
1244}
1245
1246static DEVICE_ATTR_RW(frequency_test);
1247
1248static struct attribute *rtc_freq_test_attrs[] = {
1249 &dev_attr_frequency_test.attr,
1250 NULL,
1251};
1252
1253static const struct attribute_group rtc_freq_test_attr_group = {
1254 .attrs = rtc_freq_test_attrs,
1255};
1256
1257static int ds1307_add_frequency_test(struct ds1307 *ds1307)
1258{
1259 int err;
1260
1261 switch (ds1307->type) {
1262 case m41t0:
1263 case m41t00:
1264 case m41t11:
1265 err = rtc_add_group(ds1307->rtc, &rtc_freq_test_attr_group);
1266 if (err)
1267 return err;
1268 break;
1269 default:
1270 break;
1271 }
1272
1273 return 0;
1274}
1275
1276/*----------------------------------------------------------------------*/
1277
1278static int ds1307_nvram_read(void *priv, unsigned int offset, void *val,
1279 size_t bytes)
1280{
1281 struct ds1307 *ds1307 = priv;
1282 const struct chip_desc *chip = &chips[ds1307->type];
1283
1284 return regmap_bulk_read(ds1307->regmap, chip->nvram_offset + offset,
1285 val, bytes);
1286}
1287
1288static int ds1307_nvram_write(void *priv, unsigned int offset, void *val,
1289 size_t bytes)
1290{
1291 struct ds1307 *ds1307 = priv;
1292 const struct chip_desc *chip = &chips[ds1307->type];
1293
1294 return regmap_bulk_write(ds1307->regmap, chip->nvram_offset + offset,
1295 val, bytes);
1296}
1297
1298/*----------------------------------------------------------------------*/
1299
1300static u8 ds1307_trickle_init(struct ds1307 *ds1307,
1301 const struct chip_desc *chip)
1302{
1303 u32 ohms, chargeable;
1304 bool diode = chip->charge_default;
1305
1306 if (!chip->do_trickle_setup)
1307 return 0;
1308
1309 if (device_property_read_u32(ds1307->dev, "trickle-resistor-ohms",
1310 &ohms) && chip->requires_trickle_resistor)
1311 return 0;
1312
1313 /* aux-voltage-chargeable takes precedence over the deprecated
1314 * trickle-diode-disable
1315 */
1316 if (!device_property_read_u32(ds1307->dev, "aux-voltage-chargeable",
1317 &chargeable)) {
1318 switch (chargeable) {
1319 case 0:
1320 diode = false;
1321 break;
1322 case 1:
1323 diode = true;
1324 break;
1325 default:
1326 dev_warn(ds1307->dev,
1327 "unsupported aux-voltage-chargeable value\n");
1328 break;
1329 }
1330 } else if (device_property_read_bool(ds1307->dev,
1331 "trickle-diode-disable")) {
1332 diode = false;
1333 }
1334
1335 return chip->do_trickle_setup(ds1307, ohms, diode);
1336}
1337
1338/*----------------------------------------------------------------------*/
1339
1340#if IS_REACHABLE(CONFIG_HWMON)
1341
1342/*
1343 * Temperature sensor support for ds3231 devices.
1344 */
1345
1346#define DS3231_REG_TEMPERATURE 0x11
1347
1348/*
1349 * A user-initiated temperature conversion is not started by this function,
1350 * so the temperature is updated once every 64 seconds.
1351 */
1352static int ds3231_hwmon_read_temp(struct device *dev, s32 *mC)
1353{
1354 struct ds1307 *ds1307 = dev_get_drvdata(dev);
1355 u8 temp_buf[2];
1356 s16 temp;
1357 int ret;
1358
1359 ret = regmap_bulk_read(ds1307->regmap, DS3231_REG_TEMPERATURE,
1360 temp_buf, sizeof(temp_buf));
1361 if (ret)
1362 return ret;
1363 /*
1364 * Temperature is represented as a 10-bit code with a resolution of
1365 * 0.25 degree celsius and encoded in two's complement format.
1366 */
1367 temp = (temp_buf[0] << 8) | temp_buf[1];
1368 temp >>= 6;
1369 *mC = temp * 250;
1370
1371 return 0;
1372}
1373
1374static ssize_t ds3231_hwmon_show_temp(struct device *dev,
1375 struct device_attribute *attr, char *buf)
1376{
1377 int ret;
1378 s32 temp;
1379
1380 ret = ds3231_hwmon_read_temp(dev, &temp);
1381 if (ret)
1382 return ret;
1383
1384 return sprintf(buf, "%d\n", temp);
1385}
1386static SENSOR_DEVICE_ATTR(temp1_input, 0444, ds3231_hwmon_show_temp,
1387 NULL, 0);
1388
1389static struct attribute *ds3231_hwmon_attrs[] = {
1390 &sensor_dev_attr_temp1_input.dev_attr.attr,
1391 NULL,
1392};
1393ATTRIBUTE_GROUPS(ds3231_hwmon);
1394
1395static void ds1307_hwmon_register(struct ds1307 *ds1307)
1396{
1397 struct device *dev;
1398
1399 if (ds1307->type != ds_3231)
1400 return;
1401
1402 dev = devm_hwmon_device_register_with_groups(ds1307->dev, ds1307->name,
1403 ds1307,
1404 ds3231_hwmon_groups);
1405 if (IS_ERR(dev)) {
1406 dev_warn(ds1307->dev, "unable to register hwmon device %ld\n",
1407 PTR_ERR(dev));
1408 }
1409}
1410
1411#else
1412
1413static void ds1307_hwmon_register(struct ds1307 *ds1307)
1414{
1415}
1416
1417#endif /* IS_REACHABLE(CONFIG_HWMON) */
1418
1419/*----------------------------------------------------------------------*/
1420
1421/*
1422 * Square-wave output support for DS3231
1423 * Datasheet: https://datasheets.maximintegrated.com/en/ds/DS3231.pdf
1424 */
1425#ifdef CONFIG_COMMON_CLK
1426
1427enum {
1428 DS3231_CLK_SQW = 0,
1429 DS3231_CLK_32KHZ,
1430};
1431
1432#define clk_sqw_to_ds1307(clk) \
1433 container_of(clk, struct ds1307, clks[DS3231_CLK_SQW])
1434#define clk_32khz_to_ds1307(clk) \
1435 container_of(clk, struct ds1307, clks[DS3231_CLK_32KHZ])
1436
1437static int ds3231_clk_sqw_rates[] = {
1438 1,
1439 1024,
1440 4096,
1441 8192,
1442};
1443
1444static int ds1337_write_control(struct ds1307 *ds1307, u8 mask, u8 value)
1445{
1446 struct mutex *lock = &ds1307->rtc->ops_lock;
1447 int ret;
1448
1449 mutex_lock(lock);
1450 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
1451 mask, value);
1452 mutex_unlock(lock);
1453
1454 return ret;
1455}
1456
1457static unsigned long ds3231_clk_sqw_recalc_rate(struct clk_hw *hw,
1458 unsigned long parent_rate)
1459{
1460 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1461 int control, ret;
1462 int rate_sel = 0;
1463
1464 ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
1465 if (ret)
1466 return ret;
1467 if (control & DS1337_BIT_RS1)
1468 rate_sel += 1;
1469 if (control & DS1337_BIT_RS2)
1470 rate_sel += 2;
1471
1472 return ds3231_clk_sqw_rates[rate_sel];
1473}
1474
1475static int ds3231_clk_sqw_determine_rate(struct clk_hw *hw,
1476 struct clk_rate_request *req)
1477{
1478 int i;
1479
1480 for (i = ARRAY_SIZE(ds3231_clk_sqw_rates) - 1; i >= 0; i--) {
1481 if (ds3231_clk_sqw_rates[i] <= req->rate) {
1482 req->rate = ds3231_clk_sqw_rates[i];
1483
1484 return 0;
1485 }
1486 }
1487
1488 req->rate = ds3231_clk_sqw_rates[ARRAY_SIZE(ds3231_clk_sqw_rates) - 1];
1489
1490 return 0;
1491}
1492
1493static int ds3231_clk_sqw_set_rate(struct clk_hw *hw, unsigned long rate,
1494 unsigned long parent_rate)
1495{
1496 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1497 int control = 0;
1498 int rate_sel;
1499
1500 for (rate_sel = 0; rate_sel < ARRAY_SIZE(ds3231_clk_sqw_rates);
1501 rate_sel++) {
1502 if (ds3231_clk_sqw_rates[rate_sel] == rate)
1503 break;
1504 }
1505
1506 if (rate_sel == ARRAY_SIZE(ds3231_clk_sqw_rates))
1507 return -EINVAL;
1508
1509 if (rate_sel & 1)
1510 control |= DS1337_BIT_RS1;
1511 if (rate_sel & 2)
1512 control |= DS1337_BIT_RS2;
1513
1514 return ds1337_write_control(ds1307, DS1337_BIT_RS1 | DS1337_BIT_RS2,
1515 control);
1516}
1517
1518static int ds3231_clk_sqw_prepare(struct clk_hw *hw)
1519{
1520 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1521
1522 return ds1337_write_control(ds1307, DS1337_BIT_INTCN, 0);
1523}
1524
1525static void ds3231_clk_sqw_unprepare(struct clk_hw *hw)
1526{
1527 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1528
1529 ds1337_write_control(ds1307, DS1337_BIT_INTCN, DS1337_BIT_INTCN);
1530}
1531
1532static int ds3231_clk_sqw_is_prepared(struct clk_hw *hw)
1533{
1534 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1535 int control, ret;
1536
1537 ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
1538 if (ret)
1539 return ret;
1540
1541 return !(control & DS1337_BIT_INTCN);
1542}
1543
1544static const struct clk_ops ds3231_clk_sqw_ops = {
1545 .prepare = ds3231_clk_sqw_prepare,
1546 .unprepare = ds3231_clk_sqw_unprepare,
1547 .is_prepared = ds3231_clk_sqw_is_prepared,
1548 .recalc_rate = ds3231_clk_sqw_recalc_rate,
1549 .determine_rate = ds3231_clk_sqw_determine_rate,
1550 .set_rate = ds3231_clk_sqw_set_rate,
1551};
1552
1553static unsigned long ds3231_clk_32khz_recalc_rate(struct clk_hw *hw,
1554 unsigned long parent_rate)
1555{
1556 return 32768;
1557}
1558
1559static int ds3231_clk_32khz_control(struct ds1307 *ds1307, bool enable)
1560{
1561 struct mutex *lock = &ds1307->rtc->ops_lock;
1562 int ret;
1563
1564 mutex_lock(lock);
1565 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_STATUS,
1566 DS3231_BIT_EN32KHZ,
1567 enable ? DS3231_BIT_EN32KHZ : 0);
1568 mutex_unlock(lock);
1569
1570 return ret;
1571}
1572
1573static int ds3231_clk_32khz_prepare(struct clk_hw *hw)
1574{
1575 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1576
1577 return ds3231_clk_32khz_control(ds1307, true);
1578}
1579
1580static void ds3231_clk_32khz_unprepare(struct clk_hw *hw)
1581{
1582 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1583
1584 ds3231_clk_32khz_control(ds1307, false);
1585}
1586
1587static int ds3231_clk_32khz_is_prepared(struct clk_hw *hw)
1588{
1589 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1590 int status, ret;
1591
1592 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &status);
1593 if (ret)
1594 return ret;
1595
1596 return !!(status & DS3231_BIT_EN32KHZ);
1597}
1598
1599static const struct clk_ops ds3231_clk_32khz_ops = {
1600 .prepare = ds3231_clk_32khz_prepare,
1601 .unprepare = ds3231_clk_32khz_unprepare,
1602 .is_prepared = ds3231_clk_32khz_is_prepared,
1603 .recalc_rate = ds3231_clk_32khz_recalc_rate,
1604};
1605
1606static const char *ds3231_clks_names[] = {
1607 [DS3231_CLK_SQW] = "ds3231_clk_sqw",
1608 [DS3231_CLK_32KHZ] = "ds3231_clk_32khz",
1609};
1610
1611static struct clk_init_data ds3231_clks_init[] = {
1612 [DS3231_CLK_SQW] = {
1613 .ops = &ds3231_clk_sqw_ops,
1614 },
1615 [DS3231_CLK_32KHZ] = {
1616 .ops = &ds3231_clk_32khz_ops,
1617 },
1618};
1619
1620static int ds3231_clks_register(struct ds1307 *ds1307)
1621{
1622 struct device_node *node = ds1307->dev->of_node;
1623 struct clk_onecell_data *onecell;
1624 int i;
1625
1626 onecell = devm_kzalloc(ds1307->dev, sizeof(*onecell), GFP_KERNEL);
1627 if (!onecell)
1628 return -ENOMEM;
1629
1630 onecell->clk_num = ARRAY_SIZE(ds3231_clks_init);
1631 onecell->clks = devm_kcalloc(ds1307->dev, onecell->clk_num,
1632 sizeof(onecell->clks[0]), GFP_KERNEL);
1633 if (!onecell->clks)
1634 return -ENOMEM;
1635
1636 /* optional override of the clockname */
1637 device_property_read_string_array(ds1307->dev, "clock-output-names",
1638 ds3231_clks_names,
1639 ARRAY_SIZE(ds3231_clks_names));
1640
1641 for (i = 0; i < ARRAY_SIZE(ds3231_clks_init); i++) {
1642 struct clk_init_data init = ds3231_clks_init[i];
1643
1644 /*
1645 * Interrupt signal due to alarm conditions and square-wave
1646 * output share same pin, so don't initialize both.
1647 */
1648 if (i == DS3231_CLK_SQW && test_bit(RTC_FEATURE_ALARM, ds1307->rtc->features))
1649 continue;
1650
1651 init.name = ds3231_clks_names[i];
1652 ds1307->clks[i].init = &init;
1653
1654 onecell->clks[i] = devm_clk_register(ds1307->dev,
1655 &ds1307->clks[i]);
1656 if (IS_ERR(onecell->clks[i]))
1657 return PTR_ERR(onecell->clks[i]);
1658 }
1659
1660 if (node)
1661 of_clk_add_provider(node, of_clk_src_onecell_get, onecell);
1662
1663 return 0;
1664}
1665
1666/* ds1307 RTC clock output support */
1667static unsigned long ds1307_clk_rates[] = {
1668 1,
1669 4096,
1670 8192,
1671 32768,
1672};
1673
1674static unsigned long ds1307_clk_sqw_recalc_rate(struct clk_hw *hw,
1675 unsigned long parent_rate)
1676{
1677 int ret;
1678 unsigned int rate_id;
1679 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1680
1681 ret = regmap_read(ds1307->regmap, DS1307_REG_CONTROL, &rate_id);
1682 if (ret)
1683 return ret;
1684
1685 rate_id &= (DS1307_BIT_RS1 | DS1307_BIT_RS0);
1686
1687 return ds1307_clk_rates[rate_id];
1688}
1689
1690static int ds1307_clk_sqw_determine_rate(struct clk_hw *hw,
1691 struct clk_rate_request *req)
1692{
1693 int i;
1694
1695 for (i = 0; i < ARRAY_SIZE(ds1307_clk_rates); i++) {
1696 if (req->rate <= ds1307_clk_rates[i]) {
1697 req->rate = ds1307_clk_rates[i];
1698 return 0;
1699 }
1700 }
1701
1702 /* Default rate 1Hz */
1703 req->rate = ds1307_clk_rates[0];
1704
1705 return 0;
1706}
1707
1708static int ds1307_clk_sqw_set_rate(struct clk_hw *hw, unsigned long rate,
1709 unsigned long parent_rate)
1710{
1711 int id, ret;
1712 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1713
1714 for (id = 0; id < ARRAY_SIZE(ds1307_clk_rates); id++) {
1715 if (ds1307_clk_rates[id] == rate)
1716 break;
1717 }
1718
1719 if (id >= ARRAY_SIZE(ds1307_clk_rates))
1720 return -EINVAL;
1721
1722 ret = regmap_update_bits(ds1307->regmap, DS1307_REG_CONTROL,
1723 DS1307_BIT_RS0 | DS1307_BIT_RS1, id);
1724
1725 return ret;
1726}
1727
1728static int ds1307_clk_sqw_prepare(struct clk_hw *hw)
1729{
1730 int ret;
1731 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1732
1733 ret = regmap_update_bits(ds1307->regmap, DS1307_REG_CONTROL,
1734 DS1307_BIT_SQWE, DS1307_BIT_SQWE);
1735
1736 return ret;
1737}
1738
1739static void ds1307_clk_sqw_unprepare(struct clk_hw *hw)
1740{
1741 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1742
1743 regmap_update_bits(ds1307->regmap, DS1307_REG_CONTROL,
1744 DS1307_BIT_SQWE, ~DS1307_BIT_SQWE);
1745}
1746
1747static int ds1307_clk_sqw_is_prepared(struct clk_hw *hw)
1748{
1749 int ret;
1750 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1751 unsigned int status;
1752
1753 ret = regmap_read(ds1307->regmap, DS1307_REG_CONTROL, &status);
1754 if (ret)
1755 return ret;
1756
1757 return !!(status & DS1307_BIT_SQWE);
1758}
1759
1760static const struct clk_ops ds1307_clk_sqw_ops = {
1761 .prepare = ds1307_clk_sqw_prepare,
1762 .unprepare = ds1307_clk_sqw_unprepare,
1763 .is_prepared = ds1307_clk_sqw_is_prepared,
1764 .recalc_rate = ds1307_clk_sqw_recalc_rate,
1765 .set_rate = ds1307_clk_sqw_set_rate,
1766 .determine_rate = ds1307_clk_sqw_determine_rate,
1767};
1768
1769static int rtc_ds1307_clks_register(struct ds1307 *ds1307)
1770{
1771 struct device_node *node = ds1307->dev->of_node;
1772 struct clk *clk;
1773 struct clk_init_data init = {0};
1774
1775 init.name = "ds1307_clk_sqw";
1776 init.ops = &ds1307_clk_sqw_ops;
1777
1778 ds1307->clks[0].init = &init;
1779
1780 /* Register the clock with CCF */
1781 clk = devm_clk_register(ds1307->dev, &ds1307->clks[0]);
1782 if (IS_ERR(clk))
1783 return PTR_ERR(clk);
1784
1785 if (node)
1786 of_clk_add_provider(node, of_clk_src_simple_get, clk);
1787
1788 return 0;
1789}
1790
1791static void ds1307_clks_register(struct ds1307 *ds1307)
1792{
1793 int ret;
1794
1795 switch (ds1307->type) {
1796 case ds_3231:
1797 ret = ds3231_clks_register(ds1307);
1798 break;
1799
1800 case ds_1307:
1801 ret = rtc_ds1307_clks_register(ds1307);
1802 break;
1803
1804 default:
1805 return;
1806 }
1807
1808 if (ret) {
1809 dev_warn(ds1307->dev, "unable to register clock device %d\n",
1810 ret);
1811 }
1812
1813}
1814
1815#else
1816
1817static void ds1307_clks_register(struct ds1307 *ds1307)
1818{
1819}
1820
1821#endif /* CONFIG_COMMON_CLK */
1822
1823#ifdef CONFIG_WATCHDOG_CORE
1824static const struct watchdog_info ds1388_wdt_info = {
1825 .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
1826 .identity = "DS1388 watchdog",
1827};
1828
1829static const struct watchdog_ops ds1388_wdt_ops = {
1830 .owner = THIS_MODULE,
1831 .start = ds1388_wdt_start,
1832 .stop = ds1388_wdt_stop,
1833 .ping = ds1388_wdt_ping,
1834 .set_timeout = ds1388_wdt_set_timeout,
1835
1836};
1837
1838static void ds1307_wdt_register(struct ds1307 *ds1307)
1839{
1840 struct watchdog_device *wdt;
1841 int err;
1842 int val;
1843
1844 if (ds1307->type != ds_1388)
1845 return;
1846
1847 wdt = devm_kzalloc(ds1307->dev, sizeof(*wdt), GFP_KERNEL);
1848 if (!wdt)
1849 return;
1850
1851 err = regmap_read(ds1307->regmap, DS1388_REG_FLAG, &val);
1852 if (!err && val & DS1388_BIT_WF)
1853 wdt->bootstatus = WDIOF_CARDRESET;
1854
1855 wdt->info = &ds1388_wdt_info;
1856 wdt->ops = &ds1388_wdt_ops;
1857 wdt->timeout = 99;
1858 wdt->max_timeout = 99;
1859 wdt->min_timeout = 1;
1860
1861 watchdog_init_timeout(wdt, 0, ds1307->dev);
1862 watchdog_set_drvdata(wdt, ds1307);
1863 devm_watchdog_register_device(ds1307->dev, wdt);
1864}
1865#else
1866static void ds1307_wdt_register(struct ds1307 *ds1307)
1867{
1868}
1869#endif /* CONFIG_WATCHDOG_CORE */
1870
1871static const struct regmap_config regmap_config = {
1872 .reg_bits = 8,
1873 .val_bits = 8,
1874};
1875
1876static int ds1307_probe(struct i2c_client *client)
1877{
1878 const struct i2c_device_id *id = i2c_client_get_device_id(client);
1879 struct ds1307 *ds1307;
1880 const void *match;
1881 int err = -ENODEV;
1882 int tmp;
1883 const struct chip_desc *chip;
1884 bool want_irq;
1885 bool ds1307_can_wakeup_device = false;
1886 unsigned char regs[8];
1887 struct ds1307_platform_data *pdata = dev_get_platdata(&client->dev);
1888 u8 trickle_charger_setup = 0;
1889
1890 ds1307 = devm_kzalloc(&client->dev, sizeof(struct ds1307), GFP_KERNEL);
1891 if (!ds1307)
1892 return -ENOMEM;
1893
1894 dev_set_drvdata(&client->dev, ds1307);
1895 ds1307->dev = &client->dev;
1896 ds1307->name = client->name;
1897
1898 ds1307->regmap = devm_regmap_init_i2c(client, &regmap_config);
1899 if (IS_ERR(ds1307->regmap)) {
1900 dev_err(ds1307->dev, "regmap allocation failed\n");
1901 return PTR_ERR(ds1307->regmap);
1902 }
1903
1904 i2c_set_clientdata(client, ds1307);
1905
1906 match = device_get_match_data(&client->dev);
1907 if (match) {
1908 ds1307->type = (uintptr_t)match;
1909 chip = &chips[ds1307->type];
1910 } else if (id) {
1911 chip = &chips[id->driver_data];
1912 ds1307->type = id->driver_data;
1913 } else {
1914 return -ENODEV;
1915 }
1916
1917 want_irq = client->irq > 0 && chip->alarm;
1918
1919 if (!pdata)
1920 trickle_charger_setup = ds1307_trickle_init(ds1307, chip);
1921 else if (pdata->trickle_charger_setup)
1922 trickle_charger_setup = pdata->trickle_charger_setup;
1923
1924 if (trickle_charger_setup && chip->trickle_charger_reg) {
1925 dev_dbg(ds1307->dev,
1926 "writing trickle charger info 0x%x to 0x%x\n",
1927 trickle_charger_setup, chip->trickle_charger_reg);
1928 regmap_write(ds1307->regmap, chip->trickle_charger_reg,
1929 trickle_charger_setup);
1930 }
1931
1932/*
1933 * For devices with no IRQ directly connected to the SoC, the RTC chip
1934 * can be forced as a wakeup source by stating that explicitly in
1935 * the device's .dts file using the "wakeup-source" boolean property.
1936 * If the "wakeup-source" property is set, don't request an IRQ.
1937 * This will guarantee the 'wakealarm' sysfs entry is available on the device,
1938 * if supported by the RTC.
1939 */
1940 if (chip->alarm && device_property_read_bool(&client->dev, "wakeup-source"))
1941 ds1307_can_wakeup_device = true;
1942
1943 switch (ds1307->type) {
1944 case ds_1337:
1945 case ds_1339:
1946 case ds_1341:
1947 case ds_3231:
1948 /* get registers that the "rtc" read below won't read... */
1949 err = regmap_bulk_read(ds1307->regmap, DS1337_REG_CONTROL,
1950 regs, 2);
1951 if (err) {
1952 dev_dbg(ds1307->dev, "read error %d\n", err);
1953 goto exit;
1954 }
1955
1956 /* oscillator off? turn it on, so clock can tick. */
1957 if (regs[0] & DS1337_BIT_nEOSC)
1958 regs[0] &= ~DS1337_BIT_nEOSC;
1959
1960 /*
1961 * Using IRQ or defined as wakeup-source?
1962 * Disable the square wave and both alarms.
1963 * For some variants, be sure alarms can trigger when we're
1964 * running on Vbackup (BBSQI/BBSQW)
1965 */
1966 if (want_irq || ds1307_can_wakeup_device)
1967 regs[0] |= DS1337_BIT_INTCN | chip->bbsqi_bit;
1968
1969 regmap_write(ds1307->regmap, DS1337_REG_CONTROL,
1970 regs[0]);
1971
1972 /* oscillator fault? warn */
1973 if (regs[1] & DS1337_BIT_OSF) {
1974 dev_warn(ds1307->dev, "SET TIME!\n");
1975 }
1976 break;
1977
1978 case rx_8025:
1979 err = regmap_bulk_read(ds1307->regmap,
1980 RX8025_REG_CTRL1 << 4 | 0x08, regs, 2);
1981 if (err) {
1982 dev_dbg(ds1307->dev, "read error %d\n", err);
1983 goto exit;
1984 }
1985
1986 /* oscillator off? turn it on, so clock can tick. */
1987 if (!(regs[1] & RX8025_BIT_XST)) {
1988 regs[1] |= RX8025_BIT_XST;
1989 regmap_write(ds1307->regmap,
1990 RX8025_REG_CTRL2 << 4 | 0x08,
1991 regs[1]);
1992 dev_warn(ds1307->dev,
1993 "oscillator stop detected - SET TIME!\n");
1994 }
1995
1996 if (regs[1] & RX8025_BIT_PON) {
1997 regs[1] &= ~RX8025_BIT_PON;
1998 regmap_write(ds1307->regmap,
1999 RX8025_REG_CTRL2 << 4 | 0x08,
2000 regs[1]);
2001 dev_warn(ds1307->dev, "power-on detected\n");
2002 }
2003
2004 if (regs[1] & RX8025_BIT_VDET) {
2005 regs[1] &= ~RX8025_BIT_VDET;
2006 regmap_write(ds1307->regmap,
2007 RX8025_REG_CTRL2 << 4 | 0x08,
2008 regs[1]);
2009 dev_warn(ds1307->dev, "voltage drop detected\n");
2010 }
2011
2012 /* make sure we are running in 24hour mode */
2013 if (!(regs[0] & RX8025_BIT_2412)) {
2014 u8 hour;
2015
2016 /* switch to 24 hour mode */
2017 regmap_write(ds1307->regmap,
2018 RX8025_REG_CTRL1 << 4 | 0x08,
2019 regs[0] | RX8025_BIT_2412);
2020
2021 err = regmap_bulk_read(ds1307->regmap,
2022 RX8025_REG_CTRL1 << 4 | 0x08,
2023 regs, 2);
2024 if (err) {
2025 dev_dbg(ds1307->dev, "read error %d\n", err);
2026 goto exit;
2027 }
2028
2029 /* correct hour */
2030 hour = bcd2bin(regs[DS1307_REG_HOUR]);
2031 if (hour == 12)
2032 hour = 0;
2033 if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
2034 hour += 12;
2035
2036 regmap_write(ds1307->regmap,
2037 DS1307_REG_HOUR << 4 | 0x08, hour);
2038 }
2039 break;
2040 case ds_1388:
2041 err = regmap_read(ds1307->regmap, DS1388_REG_CONTROL, &tmp);
2042 if (err) {
2043 dev_dbg(ds1307->dev, "read error %d\n", err);
2044 goto exit;
2045 }
2046
2047 /* oscillator off? turn it on, so clock can tick. */
2048 if (tmp & DS1388_BIT_nEOSC) {
2049 tmp &= ~DS1388_BIT_nEOSC;
2050 regmap_write(ds1307->regmap, DS1388_REG_CONTROL, tmp);
2051 }
2052 break;
2053 default:
2054 break;
2055 }
2056
2057 /* read RTC registers */
2058 err = regmap_bulk_read(ds1307->regmap, chip->offset, regs,
2059 sizeof(regs));
2060 if (err) {
2061 dev_dbg(ds1307->dev, "read error %d\n", err);
2062 goto exit;
2063 }
2064
2065 if (ds1307->type == mcp794xx &&
2066 !(regs[DS1307_REG_WDAY] & MCP794XX_BIT_VBATEN)) {
2067 regmap_write(ds1307->regmap, DS1307_REG_WDAY,
2068 regs[DS1307_REG_WDAY] |
2069 MCP794XX_BIT_VBATEN);
2070 }
2071
2072 tmp = regs[DS1307_REG_HOUR];
2073 switch (ds1307->type) {
2074 case ds_1340:
2075 case m41t0:
2076 case m41t00:
2077 case m41t11:
2078 /*
2079 * NOTE: ignores century bits; fix before deploying
2080 * systems that will run through year 2100.
2081 */
2082 break;
2083 case rx_8025:
2084 break;
2085 default:
2086 if (!(tmp & DS1307_BIT_12HR))
2087 break;
2088
2089 /*
2090 * Be sure we're in 24 hour mode. Multi-master systems
2091 * take note...
2092 */
2093 tmp = bcd2bin(tmp & 0x1f);
2094 if (tmp == 12)
2095 tmp = 0;
2096 if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
2097 tmp += 12;
2098 regmap_write(ds1307->regmap, chip->offset + DS1307_REG_HOUR,
2099 bin2bcd(tmp));
2100 }
2101
2102 ds1307->rtc = devm_rtc_allocate_device(ds1307->dev);
2103 if (IS_ERR(ds1307->rtc))
2104 return PTR_ERR(ds1307->rtc);
2105
2106 if (want_irq || ds1307_can_wakeup_device)
2107 device_set_wakeup_capable(ds1307->dev, true);
2108 else
2109 clear_bit(RTC_FEATURE_ALARM, ds1307->rtc->features);
2110
2111 if (ds1307_can_wakeup_device && !want_irq) {
2112 dev_info(ds1307->dev,
2113 "'wakeup-source' is set, request for an IRQ is disabled!\n");
2114 /* We cannot support UIE mode if we do not have an IRQ line */
2115 clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, ds1307->rtc->features);
2116 }
2117
2118 if (want_irq) {
2119 err = devm_request_threaded_irq(ds1307->dev, client->irq, NULL,
2120 chip->irq_handler ?: ds1307_irq,
2121 IRQF_SHARED | IRQF_ONESHOT,
2122 ds1307->name, ds1307);
2123 if (err) {
2124 client->irq = 0;
2125 device_set_wakeup_capable(ds1307->dev, false);
2126 clear_bit(RTC_FEATURE_ALARM, ds1307->rtc->features);
2127 dev_err(ds1307->dev, "unable to request IRQ!\n");
2128 } else {
2129 dev_dbg(ds1307->dev, "got IRQ %d\n", client->irq);
2130 }
2131 }
2132
2133 ds1307->rtc->ops = chip->rtc_ops ?: &ds13xx_rtc_ops;
2134 err = ds1307_add_frequency_test(ds1307);
2135 if (err)
2136 return err;
2137
2138 err = devm_rtc_register_device(ds1307->rtc);
2139 if (err)
2140 return err;
2141
2142 if (chip->nvram_size) {
2143 struct nvmem_config nvmem_cfg = {
2144 .name = "ds1307_nvram",
2145 .word_size = 1,
2146 .stride = 1,
2147 .size = chip->nvram_size,
2148 .reg_read = ds1307_nvram_read,
2149 .reg_write = ds1307_nvram_write,
2150 .priv = ds1307,
2151 };
2152
2153 devm_rtc_nvmem_register(ds1307->rtc, &nvmem_cfg);
2154 }
2155
2156 ds1307_hwmon_register(ds1307);
2157 ds1307_clks_register(ds1307);
2158 ds1307_wdt_register(ds1307);
2159
2160 return 0;
2161
2162exit:
2163 return err;
2164}
2165
2166static struct i2c_driver ds1307_driver = {
2167 .driver = {
2168 .name = "rtc-ds1307",
2169 .of_match_table = ds1307_of_match,
2170 },
2171 .probe = ds1307_probe,
2172 .id_table = ds1307_id,
2173};
2174
2175module_i2c_driver(ds1307_driver);
2176
2177MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips");
2178MODULE_LICENSE("GPL");