projects/linux·blob master · refs

248 lines · 6.2 KiB

1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Real time clocks driver for MStar/SigmaStar ARMv7 SoCs.
4 * Based on "Real Time Clock driver for msb252x." that was contained
5 * in various MStar kernels.
6 *
7 * (C) 2019 Daniel Palmer
8 * (C) 2021 Romain Perier
9 */
10
11#include <linux/clk.h>
12#include <linux/delay.h>
13#include <linux/io.h>
14#include <linux/module.h>
15#include <linux/platform_device.h>
16#include <linux/rtc.h>
17
18/* Registers */
19#define REG_RTC_CTRL 0x00
20#define REG_RTC_FREQ_CW_L 0x04
21#define REG_RTC_FREQ_CW_H 0x08
22#define REG_RTC_LOAD_VAL_L 0x0C
23#define REG_RTC_LOAD_VAL_H 0x10
24#define REG_RTC_MATCH_VAL_L 0x14
25#define REG_RTC_MATCH_VAL_H 0x18
26#define REG_RTC_STATUS_INT 0x1C
27#define REG_RTC_CNT_VAL_L 0x20
28#define REG_RTC_CNT_VAL_H 0x24
29
30/* Control bits for REG_RTC_CTRL */
31#define SOFT_RSTZ_BIT BIT(0)
32#define CNT_EN_BIT BIT(1)
33#define WRAP_EN_BIT BIT(2)
34#define LOAD_EN_BIT BIT(3)
35#define READ_EN_BIT BIT(4)
36#define INT_MASK_BIT BIT(5)
37#define INT_FORCE_BIT BIT(6)
38#define INT_CLEAR_BIT BIT(7)
39
40/* Control bits for REG_RTC_STATUS_INT */
41#define RAW_INT_BIT BIT(0)
42#define ALM_INT_BIT BIT(1)
43
44struct msc313_rtc {
45 struct rtc_device *rtc_dev;
46 void __iomem *rtc_base;
47};
48
49static int msc313_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
50{
51 struct msc313_rtc *priv = dev_get_drvdata(dev);
52 unsigned long seconds;
53
54 seconds = readw(priv->rtc_base + REG_RTC_MATCH_VAL_L)
55 | ((unsigned long)readw(priv->rtc_base + REG_RTC_MATCH_VAL_H) << 16);
56
57 rtc_time64_to_tm(seconds, &alarm->time);
58
59 if (!(readw(priv->rtc_base + REG_RTC_CTRL) & INT_MASK_BIT))
60 alarm->enabled = 1;
61
62 return 0;
63}
64
65static int msc313_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
66{
67 struct msc313_rtc *priv = dev_get_drvdata(dev);
68 u16 reg;
69
70 reg = readw(priv->rtc_base + REG_RTC_CTRL);
71 if (enabled)
72 reg &= ~INT_MASK_BIT;
73 else
74 reg |= INT_MASK_BIT;
75 writew(reg, priv->rtc_base + REG_RTC_CTRL);
76 return 0;
77}
78
79static int msc313_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
80{
81 struct msc313_rtc *priv = dev_get_drvdata(dev);
82 unsigned long seconds;
83
84 seconds = rtc_tm_to_time64(&alarm->time);
85 writew((seconds & 0xFFFF), priv->rtc_base + REG_RTC_MATCH_VAL_L);
86 writew((seconds >> 16) & 0xFFFF, priv->rtc_base + REG_RTC_MATCH_VAL_H);
87
88 msc313_rtc_alarm_irq_enable(dev, alarm->enabled);
89
90 return 0;
91}
92
93static bool msc313_rtc_get_enabled(struct msc313_rtc *priv)
94{
95 return readw(priv->rtc_base + REG_RTC_CTRL) & CNT_EN_BIT;
96}
97
98static void msc313_rtc_set_enabled(struct msc313_rtc *priv)
99{
100 u16 reg;
101
102 reg = readw(priv->rtc_base + REG_RTC_CTRL);
103 reg |= CNT_EN_BIT;
104 writew(reg, priv->rtc_base + REG_RTC_CTRL);
105}
106
107static int msc313_rtc_read_time(struct device *dev, struct rtc_time *tm)
108{
109 struct msc313_rtc *priv = dev_get_drvdata(dev);
110 u32 seconds;
111 u16 reg;
112
113 if (!msc313_rtc_get_enabled(priv))
114 return -EINVAL;
115
116 reg = readw(priv->rtc_base + REG_RTC_CTRL);
117 writew(reg | READ_EN_BIT, priv->rtc_base + REG_RTC_CTRL);
118
119 /* Wait for HW latch done */
120 while (readw(priv->rtc_base + REG_RTC_CTRL) & READ_EN_BIT)
121 udelay(1);
122
123 seconds = readw(priv->rtc_base + REG_RTC_CNT_VAL_L)
124 | ((unsigned long)readw(priv->rtc_base + REG_RTC_CNT_VAL_H) << 16);
125
126 rtc_time64_to_tm(seconds, tm);
127
128 return 0;
129}
130
131static int msc313_rtc_set_time(struct device *dev, struct rtc_time *tm)
132{
133 struct msc313_rtc *priv = dev_get_drvdata(dev);
134 unsigned long seconds;
135 u16 reg;
136
137 seconds = rtc_tm_to_time64(tm);
138 writew(seconds & 0xFFFF, priv->rtc_base + REG_RTC_LOAD_VAL_L);
139 writew((seconds >> 16) & 0xFFFF, priv->rtc_base + REG_RTC_LOAD_VAL_H);
140
141 /* Enable load for loading value into internal RTC counter */
142 reg = readw(priv->rtc_base + REG_RTC_CTRL);
143 writew(reg | LOAD_EN_BIT, priv->rtc_base + REG_RTC_CTRL);
144
145 /* Wait for HW latch done */
146 while (readw(priv->rtc_base + REG_RTC_CTRL) & LOAD_EN_BIT)
147 udelay(1);
148 msc313_rtc_set_enabled(priv);
149 return 0;
150}
151
152static const struct rtc_class_ops msc313_rtc_ops = {
153 .read_time = msc313_rtc_read_time,
154 .set_time = msc313_rtc_set_time,
155 .read_alarm = msc313_rtc_read_alarm,
156 .set_alarm = msc313_rtc_set_alarm,
157 .alarm_irq_enable = msc313_rtc_alarm_irq_enable,
158};
159
160static irqreturn_t msc313_rtc_interrupt(s32 irq, void *dev_id)
161{
162 struct msc313_rtc *priv = dev_id;
163 u16 reg;
164
165 reg = readw(priv->rtc_base + REG_RTC_STATUS_INT);
166 if (!(reg & ALM_INT_BIT))
167 return IRQ_NONE;
168
169 reg = readw(priv->rtc_base + REG_RTC_CTRL);
170 reg |= INT_CLEAR_BIT;
171 reg &= ~INT_FORCE_BIT;
172 writew(reg, priv->rtc_base + REG_RTC_CTRL);
173
174 rtc_update_irq(priv->rtc_dev, 1, RTC_IRQF | RTC_AF);
175
176 return IRQ_HANDLED;
177}
178
179static int msc313_rtc_probe(struct platform_device *pdev)
180{
181 struct device *dev = &pdev->dev;
182 struct msc313_rtc *priv;
183 unsigned long rate;
184 struct clk *clk;
185 int ret;
186 int irq;
187
188 priv = devm_kzalloc(&pdev->dev, sizeof(struct msc313_rtc), GFP_KERNEL);
189 if (!priv)
190 return -ENOMEM;
191
192 priv->rtc_base = devm_platform_ioremap_resource(pdev, 0);
193 if (IS_ERR(priv->rtc_base))
194 return PTR_ERR(priv->rtc_base);
195
196 irq = platform_get_irq(pdev, 0);
197 if (irq < 0)
198 return -EINVAL;
199
200 priv->rtc_dev = devm_rtc_allocate_device(dev);
201 if (IS_ERR(priv->rtc_dev))
202 return PTR_ERR(priv->rtc_dev);
203
204 priv->rtc_dev->ops = &msc313_rtc_ops;
205 priv->rtc_dev->range_max = U32_MAX;
206
207 ret = devm_request_irq(dev, irq, msc313_rtc_interrupt, IRQF_SHARED,
208 dev_name(&pdev->dev), priv);
209 if (ret) {
210 dev_err(dev, "Could not request IRQ\n");
211 return ret;
212 }
213
214 clk = devm_clk_get_enabled(dev, NULL);
215 if (IS_ERR(clk)) {
216 dev_err(dev, "No input reference clock\n");
217 return PTR_ERR(clk);
218 }
219
220 rate = clk_get_rate(clk);
221 writew(rate & 0xFFFF, priv->rtc_base + REG_RTC_FREQ_CW_L);
222 writew((rate >> 16) & 0xFFFF, priv->rtc_base + REG_RTC_FREQ_CW_H);
223
224 platform_set_drvdata(pdev, priv);
225
226 return devm_rtc_register_device(priv->rtc_dev);
227}
228
229static const struct of_device_id msc313_rtc_of_match_table[] = {
230 { .compatible = "mstar,msc313-rtc" },
231 { }
232};
233MODULE_DEVICE_TABLE(of, msc313_rtc_of_match_table);
234
235static struct platform_driver msc313_rtc_driver = {
236 .probe = msc313_rtc_probe,
237 .driver = {
238 .name = "msc313-rtc",
239 .of_match_table = msc313_rtc_of_match_table,
240 },
241};
242
243module_platform_driver(msc313_rtc_driver);
244
245MODULE_AUTHOR("Daniel Palmer <[email protected]>");
246MODULE_AUTHOR("Romain Perier <[email protected]>");
247MODULE_DESCRIPTION("MStar RTC Driver");
248MODULE_LICENSE("GPL v2");