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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3* Copyright (c) 2014-2015 MediaTek Inc.
4* Author: Tianping.Fang <[email protected]>
5*/
6
7#include <linux/err.h>
8#include <linux/interrupt.h>
9#include <linux/mfd/mt6397/core.h>
10#include <linux/module.h>
11#include <linux/mutex.h>
12#include <linux/of.h>
13#include <linux/platform_device.h>
14#include <linux/regmap.h>
15#include <linux/rtc.h>
16#include <linux/mfd/mt6397/rtc.h>
17
18static int mtk_rtc_write_trigger(struct mt6397_rtc *rtc)
19{
20 int ret;
21 u32 data;
22
23 ret = regmap_write(rtc->regmap, rtc->addr_base + rtc->data->wrtgr, 1);
24 if (ret < 0)
25 return ret;
26
27 ret = regmap_read_poll_timeout(rtc->regmap,
28 rtc->addr_base + RTC_BBPU, data,
29 !(data & RTC_BBPU_CBUSY),
30 MTK_RTC_POLL_DELAY_US,
31 MTK_RTC_POLL_TIMEOUT);
32 if (ret < 0)
33 dev_err(rtc->rtc_dev->dev.parent,
34 "failed to write WRTGR: %d\n", ret);
35
36 return ret;
37}
38
39static irqreturn_t mtk_rtc_irq_handler_thread(int irq, void *data)
40{
41 struct mt6397_rtc *rtc = data;
42 u32 irqsta, irqen;
43 int ret;
44
45 ret = regmap_read(rtc->regmap, rtc->addr_base + RTC_IRQ_STA, &irqsta);
46 if ((ret >= 0) && (irqsta & RTC_IRQ_STA_AL)) {
47 rtc_update_irq(rtc->rtc_dev, 1, RTC_IRQF | RTC_AF);
48 irqen = irqsta & ~RTC_IRQ_EN_AL;
49 mutex_lock(&rtc->lock);
50 if (regmap_write(rtc->regmap, rtc->addr_base + RTC_IRQ_EN,
51 irqen) == 0)
52 mtk_rtc_write_trigger(rtc);
53 mutex_unlock(&rtc->lock);
54
55 return IRQ_HANDLED;
56 }
57
58 return IRQ_NONE;
59}
60
61static int __mtk_rtc_read_time(struct mt6397_rtc *rtc,
62 struct rtc_time *tm, int *sec)
63{
64 int ret;
65 u16 data[RTC_OFFSET_COUNT];
66
67 mutex_lock(&rtc->lock);
68 ret = regmap_bulk_read(rtc->regmap, rtc->addr_base + RTC_TC_SEC,
69 data, RTC_OFFSET_COUNT);
70 if (ret < 0)
71 goto exit;
72
73 tm->tm_sec = data[RTC_OFFSET_SEC];
74 tm->tm_min = data[RTC_OFFSET_MIN];
75 tm->tm_hour = data[RTC_OFFSET_HOUR];
76 tm->tm_mday = data[RTC_OFFSET_DOM];
77 tm->tm_wday = data[RTC_OFFSET_DOW];
78 tm->tm_mon = data[RTC_OFFSET_MTH] & RTC_TC_MTH_MASK;
79 tm->tm_year = data[RTC_OFFSET_YEAR];
80
81 ret = regmap_read(rtc->regmap, rtc->addr_base + RTC_TC_SEC, sec);
82exit:
83 mutex_unlock(&rtc->lock);
84 return ret;
85}
86
87static int mtk_rtc_read_time(struct device *dev, struct rtc_time *tm)
88{
89 struct mt6397_rtc *rtc = dev_get_drvdata(dev);
90 int sec, ret;
91
92 do {
93 ret = __mtk_rtc_read_time(rtc, tm, &sec);
94 if (ret < 0)
95 goto exit;
96 } while (sec < tm->tm_sec);
97
98 /* HW register start mon/wday from one, but tm_mon/tm_wday start from zero. */
99 tm->tm_mon--;
100 tm->tm_wday--;
101
102exit:
103 return ret;
104}
105
106static int mtk_rtc_set_time(struct device *dev, struct rtc_time *tm)
107{
108 struct mt6397_rtc *rtc = dev_get_drvdata(dev);
109 int ret;
110 u16 data[RTC_OFFSET_COUNT];
111
112 tm->tm_mon++;
113 tm->tm_wday++;
114
115 data[RTC_OFFSET_SEC] = tm->tm_sec;
116 data[RTC_OFFSET_MIN] = tm->tm_min;
117 data[RTC_OFFSET_HOUR] = tm->tm_hour;
118 data[RTC_OFFSET_DOM] = tm->tm_mday;
119 data[RTC_OFFSET_DOW] = tm->tm_wday;
120 data[RTC_OFFSET_MTH] = tm->tm_mon;
121 data[RTC_OFFSET_YEAR] = tm->tm_year;
122
123 mutex_lock(&rtc->lock);
124 ret = regmap_bulk_write(rtc->regmap, rtc->addr_base + RTC_TC_SEC,
125 data, RTC_OFFSET_COUNT);
126 if (ret < 0)
127 goto exit;
128
129 /* Time register write to hardware after call trigger function */
130 ret = mtk_rtc_write_trigger(rtc);
131
132exit:
133 mutex_unlock(&rtc->lock);
134 return ret;
135}
136
137static int mtk_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
138{
139 struct rtc_time *tm = &alm->time;
140 struct mt6397_rtc *rtc = dev_get_drvdata(dev);
141 u32 irqen, pdn2;
142 int ret;
143 u16 data[RTC_OFFSET_COUNT];
144
145 mutex_lock(&rtc->lock);
146 ret = regmap_read(rtc->regmap, rtc->addr_base + RTC_IRQ_EN, &irqen);
147 if (ret < 0)
148 goto err_exit;
149 ret = regmap_read(rtc->regmap, rtc->addr_base + RTC_PDN2, &pdn2);
150 if (ret < 0)
151 goto err_exit;
152
153 ret = regmap_bulk_read(rtc->regmap, rtc->addr_base + RTC_AL_SEC,
154 data, RTC_OFFSET_COUNT);
155 if (ret < 0)
156 goto err_exit;
157
158 alm->enabled = !!(irqen & RTC_IRQ_EN_AL);
159 alm->pending = !!(pdn2 & RTC_PDN2_PWRON_ALARM);
160 mutex_unlock(&rtc->lock);
161
162 tm->tm_sec = data[RTC_OFFSET_SEC] & RTC_AL_SEC_MASK;
163 tm->tm_min = data[RTC_OFFSET_MIN] & RTC_AL_MIN_MASK;
164 tm->tm_hour = data[RTC_OFFSET_HOUR] & RTC_AL_HOU_MASK;
165 tm->tm_mday = data[RTC_OFFSET_DOM] & RTC_AL_DOM_MASK;
166 tm->tm_mon = data[RTC_OFFSET_MTH] & RTC_AL_MTH_MASK;
167 tm->tm_year = data[RTC_OFFSET_YEAR] & RTC_AL_YEA_MASK;
168
169 tm->tm_mon--;
170
171 return 0;
172err_exit:
173 mutex_unlock(&rtc->lock);
174 return ret;
175}
176
177static int mtk_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
178{
179 struct rtc_time *tm = &alm->time;
180 struct mt6397_rtc *rtc = dev_get_drvdata(dev);
181 int ret;
182 u16 data[RTC_OFFSET_COUNT];
183
184 tm->tm_mon++;
185
186 mutex_lock(&rtc->lock);
187 ret = regmap_bulk_read(rtc->regmap, rtc->addr_base + RTC_AL_SEC,
188 data, RTC_OFFSET_COUNT);
189 if (ret < 0)
190 goto exit;
191
192 data[RTC_OFFSET_SEC] = ((data[RTC_OFFSET_SEC] & ~(RTC_AL_SEC_MASK)) |
193 (tm->tm_sec & RTC_AL_SEC_MASK));
194 data[RTC_OFFSET_MIN] = ((data[RTC_OFFSET_MIN] & ~(RTC_AL_MIN_MASK)) |
195 (tm->tm_min & RTC_AL_MIN_MASK));
196 data[RTC_OFFSET_HOUR] = ((data[RTC_OFFSET_HOUR] & ~(RTC_AL_HOU_MASK)) |
197 (tm->tm_hour & RTC_AL_HOU_MASK));
198 data[RTC_OFFSET_DOM] = ((data[RTC_OFFSET_DOM] & ~(RTC_AL_DOM_MASK)) |
199 (tm->tm_mday & RTC_AL_DOM_MASK));
200 data[RTC_OFFSET_MTH] = ((data[RTC_OFFSET_MTH] & ~(RTC_AL_MTH_MASK)) |
201 (tm->tm_mon & RTC_AL_MTH_MASK));
202 data[RTC_OFFSET_YEAR] = ((data[RTC_OFFSET_YEAR] & ~(RTC_AL_YEA_MASK)) |
203 (tm->tm_year & RTC_AL_YEA_MASK));
204
205 if (alm->enabled) {
206 ret = regmap_bulk_write(rtc->regmap,
207 rtc->addr_base + RTC_AL_SEC,
208 data, RTC_OFFSET_COUNT);
209 if (ret < 0)
210 goto exit;
211 ret = regmap_write(rtc->regmap, rtc->addr_base + RTC_AL_MASK,
212 RTC_AL_MASK_DOW);
213 if (ret < 0)
214 goto exit;
215 ret = regmap_update_bits(rtc->regmap,
216 rtc->addr_base + RTC_IRQ_EN,
217 RTC_IRQ_EN_ONESHOT_AL,
218 RTC_IRQ_EN_ONESHOT_AL);
219 if (ret < 0)
220 goto exit;
221 } else {
222 ret = regmap_update_bits(rtc->regmap,
223 rtc->addr_base + RTC_IRQ_EN,
224 RTC_IRQ_EN_ONESHOT_AL, 0);
225 if (ret < 0)
226 goto exit;
227 }
228
229 /* All alarm time register write to hardware after calling
230 * mtk_rtc_write_trigger. This can avoid race condition if alarm
231 * occur happen during writing alarm time register.
232 */
233 ret = mtk_rtc_write_trigger(rtc);
234exit:
235 mutex_unlock(&rtc->lock);
236 return ret;
237}
238
239static const struct rtc_class_ops mtk_rtc_ops = {
240 .read_time = mtk_rtc_read_time,
241 .set_time = mtk_rtc_set_time,
242 .read_alarm = mtk_rtc_read_alarm,
243 .set_alarm = mtk_rtc_set_alarm,
244};
245
246static int mtk_rtc_probe(struct platform_device *pdev)
247{
248 struct resource *res;
249 struct mt6397_chip *mt6397_chip = dev_get_drvdata(pdev->dev.parent);
250 struct mt6397_rtc *rtc;
251 int ret;
252
253 rtc = devm_kzalloc(&pdev->dev, sizeof(struct mt6397_rtc), GFP_KERNEL);
254 if (!rtc)
255 return -ENOMEM;
256
257 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
258 if (!res)
259 return -EINVAL;
260 rtc->addr_base = res->start;
261
262 rtc->data = of_device_get_match_data(&pdev->dev);
263
264 rtc->irq = platform_get_irq(pdev, 0);
265 if (rtc->irq < 0)
266 return rtc->irq;
267
268 rtc->regmap = mt6397_chip->regmap;
269 mutex_init(&rtc->lock);
270
271 platform_set_drvdata(pdev, rtc);
272
273 rtc->rtc_dev = devm_rtc_allocate_device(&pdev->dev);
274 if (IS_ERR(rtc->rtc_dev))
275 return PTR_ERR(rtc->rtc_dev);
276
277 ret = devm_request_threaded_irq(&pdev->dev, rtc->irq, NULL,
278 mtk_rtc_irq_handler_thread,
279 IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
280 "mt6397-rtc", rtc);
281
282 if (ret) {
283 dev_err(&pdev->dev, "Failed to request alarm IRQ: %d: %d\n",
284 rtc->irq, ret);
285 return ret;
286 }
287
288 device_init_wakeup(&pdev->dev, true);
289
290 rtc->rtc_dev->ops = &mtk_rtc_ops;
291 rtc->rtc_dev->range_min = RTC_TIMESTAMP_BEGIN_1900;
292 rtc->rtc_dev->range_max = mktime64(2027, 12, 31, 23, 59, 59);
293 rtc->rtc_dev->start_secs = mktime64(1968, 1, 2, 0, 0, 0);
294 rtc->rtc_dev->set_start_time = true;
295
296 return devm_rtc_register_device(rtc->rtc_dev);
297}
298
299#ifdef CONFIG_PM_SLEEP
300static int mt6397_rtc_suspend(struct device *dev)
301{
302 struct mt6397_rtc *rtc = dev_get_drvdata(dev);
303
304 if (device_may_wakeup(dev))
305 enable_irq_wake(rtc->irq);
306
307 return 0;
308}
309
310static int mt6397_rtc_resume(struct device *dev)
311{
312 struct mt6397_rtc *rtc = dev_get_drvdata(dev);
313
314 if (device_may_wakeup(dev))
315 disable_irq_wake(rtc->irq);
316
317 return 0;
318}
319#endif
320
321static SIMPLE_DEV_PM_OPS(mt6397_pm_ops, mt6397_rtc_suspend,
322 mt6397_rtc_resume);
323
324static const struct mtk_rtc_data mt6358_rtc_data = {
325 .wrtgr = RTC_WRTGR_MT6358,
326};
327
328static const struct mtk_rtc_data mt6397_rtc_data = {
329 .wrtgr = RTC_WRTGR_MT6397,
330};
331
332static const struct of_device_id mt6397_rtc_of_match[] = {
333 { .compatible = "mediatek,mt6323-rtc", .data = &mt6397_rtc_data },
334 { .compatible = "mediatek,mt6357-rtc", .data = &mt6358_rtc_data },
335 { .compatible = "mediatek,mt6358-rtc", .data = &mt6358_rtc_data },
336 { .compatible = "mediatek,mt6397-rtc", .data = &mt6397_rtc_data },
337 { }
338};
339MODULE_DEVICE_TABLE(of, mt6397_rtc_of_match);
340
341static struct platform_driver mtk_rtc_driver = {
342 .driver = {
343 .name = "mt6397-rtc",
344 .of_match_table = mt6397_rtc_of_match,
345 .pm = &mt6397_pm_ops,
346 },
347 .probe = mtk_rtc_probe,
348};
349
350module_platform_driver(mtk_rtc_driver);
351
352MODULE_LICENSE("GPL v2");
353MODULE_AUTHOR("Tianping Fang <[email protected]>");
354MODULE_DESCRIPTION("RTC Driver for MediaTek MT6397 PMIC");