projects/linux·blob master · refs

1631 lines · 41.6 KiB

1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * An I2C and SPI driver for the NXP PCF2127/29/31 RTC
4 * Copyright 2013 Til-Technologies
5 *
6 * Author: Renaud Cerrato <[email protected]>
7 *
8 * Watchdog and tamper functions
9 * Author: Bruno Thomsen <[email protected]>
10 *
11 * PCF2131 support
12 * Author: Hugo Villeneuve <[email protected]>
13 *
14 * based on the other drivers in this same directory.
15 *
16 * Datasheets: https://www.nxp.com/docs/en/data-sheet/PCF2127.pdf
17 * https://www.nxp.com/docs/en/data-sheet/PCF2131DS.pdf
18 */
19
20#include <linux/i2c.h>
21#include <linux/spi/spi.h>
22#include <linux/bcd.h>
23#include <linux/bitfield.h>
24#include <linux/rtc.h>
25#include <linux/slab.h>
26#include <linux/module.h>
27#include <linux/of.h>
28#include <linux/of_irq.h>
29#include <linux/of_device.h>
30#include <linux/regmap.h>
31#include <linux/watchdog.h>
32
33/* Control register 1 */
34#define PCF2127_REG_CTRL1 0x00
35#define PCF2127_BIT_CTRL1_POR_OVRD BIT(3)
36#define PCF2127_BIT_CTRL1_TSF1 BIT(4)
37#define PCF2127_BIT_CTRL1_STOP BIT(5)
38/* Control register 2 */
39#define PCF2127_REG_CTRL2 0x01
40#define PCF2127_BIT_CTRL2_AIE BIT(1)
41#define PCF2127_BIT_CTRL2_TSIE BIT(2)
42#define PCF2127_BIT_CTRL2_AF BIT(4)
43#define PCF2127_BIT_CTRL2_TSF2 BIT(5)
44#define PCF2127_BIT_CTRL2_WDTF BIT(6)
45#define PCF2127_BIT_CTRL2_MSF BIT(7)
46/* Control register 3 */
47#define PCF2127_REG_CTRL3 0x02
48#define PCF2127_BIT_CTRL3_BLIE BIT(0)
49#define PCF2127_BIT_CTRL3_BIE BIT(1)
50#define PCF2127_BIT_CTRL3_BLF BIT(2)
51#define PCF2127_BIT_CTRL3_BF BIT(3)
52#define PCF2127_BIT_CTRL3_BTSE BIT(4)
53#define PCF2127_CTRL3_PM GENMASK(7, 5)
54/* Time and date registers */
55#define PCF2127_REG_TIME_BASE 0x03
56#define PCF2127_BIT_SC_OSF BIT(7)
57/* Alarm registers */
58#define PCF2127_REG_ALARM_BASE 0x0A
59#define PCF2127_BIT_ALARM_AE BIT(7)
60/* CLKOUT control register */
61#define PCF2127_REG_CLKOUT 0x0f
62#define PCF2127_BIT_CLKOUT_OTPR BIT(5)
63/* Watchdog registers */
64#define PCF2127_REG_WD_CTL 0x10
65#define PCF2127_BIT_WD_CTL_TF0 BIT(0)
66#define PCF2127_BIT_WD_CTL_TF1 BIT(1)
67#define PCF2127_BIT_WD_CTL_CD0 BIT(6)
68#define PCF2127_BIT_WD_CTL_CD1 BIT(7)
69#define PCF2127_REG_WD_VAL 0x11
70/* Tamper timestamp1 registers */
71#define PCF2127_REG_TS1_BASE 0x12
72#define PCF2127_BIT_TS_CTRL_TSOFF BIT(6)
73#define PCF2127_BIT_TS_CTRL_TSM BIT(7)
74/*
75 * RAM registers
76 * PCF2127 has 512 bytes general-purpose static RAM (SRAM) that is
77 * battery backed and can survive a power outage.
78 * PCF2129/31 doesn't have this feature.
79 */
80#define PCF2127_REG_RAM_ADDR_MSB 0x1A
81#define PCF2127_REG_RAM_WRT_CMD 0x1C
82#define PCF2127_REG_RAM_RD_CMD 0x1D
83
84/* Watchdog timer value constants */
85#define PCF2127_WD_VAL_STOP 0
86/* PCF2127/29 watchdog timer value constants */
87#define PCF2127_WD_CLOCK_HZ_X1000 1000 /* 1Hz */
88#define PCF2127_WD_MIN_HW_HEARTBEAT_MS 500
89/* PCF2131 watchdog timer value constants */
90#define PCF2131_WD_CLOCK_HZ_X1000 250 /* 1/4Hz */
91#define PCF2131_WD_MIN_HW_HEARTBEAT_MS 4000
92
93#define PCF2127_WD_DEFAULT_TIMEOUT_S 60
94
95/* Mask for currently enabled interrupts */
96#define PCF2127_CTRL1_IRQ_MASK (PCF2127_BIT_CTRL1_TSF1)
97#define PCF2127_CTRL2_IRQ_MASK ( \
98 PCF2127_BIT_CTRL2_AF | \
99 PCF2127_BIT_CTRL2_WDTF | \
100 PCF2127_BIT_CTRL2_TSF2 | \
101 PCF2127_BIT_CTRL2_MSF)
102
103#define PCF2127_MAX_TS_SUPPORTED 4
104
105/* Control register 4 */
106#define PCF2131_REG_CTRL4 0x03
107#define PCF2131_BIT_CTRL4_TSF4 BIT(4)
108#define PCF2131_BIT_CTRL4_TSF3 BIT(5)
109#define PCF2131_BIT_CTRL4_TSF2 BIT(6)
110#define PCF2131_BIT_CTRL4_TSF1 BIT(7)
111/* Control register 5 */
112#define PCF2131_REG_CTRL5 0x04
113#define PCF2131_BIT_CTRL5_TSIE4 BIT(4)
114#define PCF2131_BIT_CTRL5_TSIE3 BIT(5)
115#define PCF2131_BIT_CTRL5_TSIE2 BIT(6)
116#define PCF2131_BIT_CTRL5_TSIE1 BIT(7)
117/* Software reset register */
118#define PCF2131_REG_SR_RESET 0x05
119#define PCF2131_SR_RESET_READ_PATTERN (BIT(2) | BIT(5))
120#define PCF2131_SR_RESET_CPR_CMD (PCF2131_SR_RESET_READ_PATTERN | BIT(7))
121/* Time and date registers */
122#define PCF2131_REG_TIME_BASE 0x07
123/* Alarm registers */
124#define PCF2131_REG_ALARM_BASE 0x0E
125/* CLKOUT control register */
126#define PCF2131_REG_CLKOUT 0x13
127/* Watchdog registers */
128#define PCF2131_REG_WD_CTL 0x35
129#define PCF2131_REG_WD_VAL 0x36
130/* Tamper timestamp1 registers */
131#define PCF2131_REG_TS1_BASE 0x14
132/* Tamper timestamp2 registers */
133#define PCF2131_REG_TS2_BASE 0x1B
134/* Tamper timestamp3 registers */
135#define PCF2131_REG_TS3_BASE 0x22
136/* Tamper timestamp4 registers */
137#define PCF2131_REG_TS4_BASE 0x29
138/* Interrupt mask registers */
139#define PCF2131_REG_INT_A_MASK1 0x31
140#define PCF2131_REG_INT_A_MASK2 0x32
141#define PCF2131_REG_INT_B_MASK1 0x33
142#define PCF2131_REG_INT_B_MASK2 0x34
143#define PCF2131_BIT_INT_BLIE BIT(0)
144#define PCF2131_BIT_INT_BIE BIT(1)
145#define PCF2131_BIT_INT_AIE BIT(2)
146#define PCF2131_BIT_INT_WD_CD BIT(3)
147#define PCF2131_BIT_INT_SI BIT(4)
148#define PCF2131_BIT_INT_MI BIT(5)
149#define PCF2131_CTRL2_IRQ_MASK ( \
150 PCF2127_BIT_CTRL2_AF | \
151 PCF2127_BIT_CTRL2_WDTF)
152#define PCF2131_CTRL4_IRQ_MASK ( \
153 PCF2131_BIT_CTRL4_TSF4 | \
154 PCF2131_BIT_CTRL4_TSF3 | \
155 PCF2131_BIT_CTRL4_TSF2 | \
156 PCF2131_BIT_CTRL4_TSF1)
157
158enum pcf21xx_type {
159 PCF2127,
160 PCF2129,
161 PCF2131,
162 PCF21XX_LAST_ID
163};
164
165struct pcf21xx_ts_config {
166 u8 reg_base; /* Base register to read timestamp values. */
167
168 /*
169 * If the TS input pin is driven to GND, an interrupt can be generated
170 * (supported by all variants).
171 */
172 u8 gnd_detect_reg; /* Interrupt control register address. */
173 u8 gnd_detect_bit; /* Interrupt bit. */
174
175 /*
176 * If the TS input pin is driven to an intermediate level between GND
177 * and supply, an interrupt can be generated (optional feature depending
178 * on variant).
179 */
180 u8 inter_detect_reg; /* Interrupt control register address. */
181 u8 inter_detect_bit; /* Interrupt bit. */
182
183 u8 ie_reg; /* Interrupt enable control register. */
184 u8 ie_bit; /* Interrupt enable bit. */
185};
186
187struct pcf21xx_config {
188 int type; /* IC variant */
189 int max_register;
190 unsigned int has_nvmem:1;
191 unsigned int has_bit_wd_ctl_cd0:1;
192 unsigned int wd_val_reg_readable:1; /* If watchdog value register can be read. */
193 unsigned int has_int_a_b:1; /* PCF2131 supports two interrupt outputs. */
194 u8 reg_time_base; /* Time/date base register. */
195 u8 regs_alarm_base; /* Alarm function base registers. */
196 u8 reg_wd_ctl; /* Watchdog control register. */
197 u8 reg_wd_val; /* Watchdog value register. */
198 u8 reg_clkout; /* Clkout register. */
199 int wdd_clock_hz_x1000; /* Watchdog clock in Hz multiplicated by 1000 */
200 int wdd_min_hw_heartbeat_ms;
201 unsigned int ts_count;
202 struct pcf21xx_ts_config ts[PCF2127_MAX_TS_SUPPORTED];
203 struct attribute_group attribute_group;
204};
205
206struct pcf2127 {
207 struct rtc_device *rtc;
208 struct watchdog_device wdd;
209 struct regmap *regmap;
210 const struct pcf21xx_config *cfg;
211 bool irq_enabled;
212 time64_t ts[PCF2127_MAX_TS_SUPPORTED]; /* Timestamp values. */
213 bool ts_valid[PCF2127_MAX_TS_SUPPORTED]; /* Timestamp valid indication. */
214};
215
216/*
217 * In the routines that deal directly with the pcf2127 hardware, we use
218 * rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch.
219 */
220static int pcf2127_rtc_read_time(struct device *dev, struct rtc_time *tm)
221{
222 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
223 unsigned char buf[7];
224 int ret;
225
226 /*
227 * Avoid reading CTRL2 register as it causes WD_VAL register
228 * value to reset to 0 which means watchdog is stopped.
229 */
230 ret = regmap_bulk_read(pcf2127->regmap, pcf2127->cfg->reg_time_base,
231 buf, sizeof(buf));
232 if (ret) {
233 dev_err(dev, "%s: read error\n", __func__);
234 return ret;
235 }
236
237 /* Clock integrity is not guaranteed when OSF flag is set. */
238 if (buf[0] & PCF2127_BIT_SC_OSF) {
239 /*
240 * no need clear the flag here,
241 * it will be cleared once the new date is saved
242 */
243 dev_warn(dev,
244 "oscillator stop detected, date/time is not reliable\n");
245 return -EINVAL;
246 }
247
248 dev_dbg(dev,
249 "%s: raw data is sec=%02x, min=%02x, hr=%02x, "
250 "mday=%02x, wday=%02x, mon=%02x, year=%02x\n",
251 __func__, buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6]);
252
253 tm->tm_sec = bcd2bin(buf[0] & 0x7F);
254 tm->tm_min = bcd2bin(buf[1] & 0x7F);
255 tm->tm_hour = bcd2bin(buf[2] & 0x3F);
256 tm->tm_mday = bcd2bin(buf[3] & 0x3F);
257 tm->tm_wday = buf[4] & 0x07;
258 tm->tm_mon = bcd2bin(buf[5] & 0x1F) - 1;
259 tm->tm_year = bcd2bin(buf[6]);
260 tm->tm_year += 100;
261
262 dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
263 "mday=%d, mon=%d, year=%d, wday=%d\n",
264 __func__,
265 tm->tm_sec, tm->tm_min, tm->tm_hour,
266 tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
267
268 return 0;
269}
270
271static int pcf2127_rtc_set_time(struct device *dev, struct rtc_time *tm)
272{
273 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
274 unsigned char buf[7];
275 int i = 0, err;
276
277 dev_dbg(dev, "%s: secs=%d, mins=%d, hours=%d, "
278 "mday=%d, mon=%d, year=%d, wday=%d\n",
279 __func__,
280 tm->tm_sec, tm->tm_min, tm->tm_hour,
281 tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
282
283 /* hours, minutes and seconds */
284 buf[i++] = bin2bcd(tm->tm_sec); /* this will also clear OSF flag */
285 buf[i++] = bin2bcd(tm->tm_min);
286 buf[i++] = bin2bcd(tm->tm_hour);
287 buf[i++] = bin2bcd(tm->tm_mday);
288 buf[i++] = tm->tm_wday & 0x07;
289
290 /* month, 1 - 12 */
291 buf[i++] = bin2bcd(tm->tm_mon + 1);
292
293 /* year */
294 buf[i++] = bin2bcd(tm->tm_year - 100);
295
296 /* Write access to time registers:
297 * PCF2127/29: no special action required.
298 * PCF2131: requires setting the STOP and CPR bits. STOP bit needs to
299 * be cleared after time registers are updated.
300 */
301 if (pcf2127->cfg->type == PCF2131) {
302 err = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL1,
303 PCF2127_BIT_CTRL1_STOP,
304 PCF2127_BIT_CTRL1_STOP);
305 if (err) {
306 dev_dbg(dev, "setting STOP bit failed\n");
307 return err;
308 }
309
310 err = regmap_write(pcf2127->regmap, PCF2131_REG_SR_RESET,
311 PCF2131_SR_RESET_CPR_CMD);
312 if (err) {
313 dev_dbg(dev, "sending CPR cmd failed\n");
314 return err;
315 }
316 }
317
318 /* write time register's data */
319 err = regmap_bulk_write(pcf2127->regmap, pcf2127->cfg->reg_time_base, buf, i);
320 if (err) {
321 dev_dbg(dev, "%s: err=%d", __func__, err);
322 return err;
323 }
324
325 if (pcf2127->cfg->type == PCF2131) {
326 /* Clear STOP bit (PCF2131 only) after write is completed. */
327 err = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL1,
328 PCF2127_BIT_CTRL1_STOP, 0);
329 if (err) {
330 dev_dbg(dev, "clearing STOP bit failed\n");
331 return err;
332 }
333 }
334
335 return 0;
336}
337
338static int pcf2127_param_get(struct device *dev, struct rtc_param *param)
339{
340 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
341 u32 value;
342 int ret;
343
344 switch (param->param) {
345 case RTC_PARAM_BACKUP_SWITCH_MODE:
346 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL3, &value);
347 if (ret < 0)
348 return ret;
349
350 value = FIELD_GET(PCF2127_CTRL3_PM, value);
351
352 if (value < 0x3)
353 param->uvalue = RTC_BSM_LEVEL;
354 else if (value < 0x6)
355 param->uvalue = RTC_BSM_DIRECT;
356 else
357 param->uvalue = RTC_BSM_DISABLED;
358
359 break;
360
361 default:
362 return -EINVAL;
363 }
364
365 return 0;
366}
367
368static int pcf2127_param_set(struct device *dev, struct rtc_param *param)
369{
370 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
371 u8 mode = 0;
372 u32 value;
373 int ret;
374
375 switch (param->param) {
376 case RTC_PARAM_BACKUP_SWITCH_MODE:
377 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL3, &value);
378 if (ret < 0)
379 return ret;
380
381 value = FIELD_GET(PCF2127_CTRL3_PM, value);
382
383 if (value > 5)
384 value -= 5;
385 else if (value > 2)
386 value -= 3;
387
388 switch (param->uvalue) {
389 case RTC_BSM_LEVEL:
390 break;
391 case RTC_BSM_DIRECT:
392 mode = 3;
393 break;
394 case RTC_BSM_DISABLED:
395 if (value == 0)
396 value = 1;
397 mode = 5;
398 break;
399 default:
400 return -EINVAL;
401 }
402
403 return regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL3,
404 PCF2127_CTRL3_PM,
405 FIELD_PREP(PCF2127_CTRL3_PM, mode + value));
406
407 break;
408
409 default:
410 return -EINVAL;
411 }
412
413 return 0;
414}
415
416static int pcf2127_rtc_ioctl(struct device *dev,
417 unsigned int cmd, unsigned long arg)
418{
419 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
420 int val, touser = 0;
421 int ret;
422
423 switch (cmd) {
424 case RTC_VL_READ:
425 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL3, &val);
426 if (ret)
427 return ret;
428
429 if (val & PCF2127_BIT_CTRL3_BLF)
430 touser |= RTC_VL_BACKUP_LOW;
431
432 if (val & PCF2127_BIT_CTRL3_BF)
433 touser |= RTC_VL_BACKUP_SWITCH;
434
435 return put_user(touser, (unsigned int __user *)arg);
436
437 case RTC_VL_CLR:
438 return regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL3,
439 PCF2127_BIT_CTRL3_BF, 0);
440
441 default:
442 return -ENOIOCTLCMD;
443 }
444}
445
446static int pcf2127_nvmem_read(void *priv, unsigned int offset,
447 void *val, size_t bytes)
448{
449 struct pcf2127 *pcf2127 = priv;
450 int ret;
451 unsigned char offsetbuf[] = { offset >> 8, offset };
452
453 ret = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_ADDR_MSB,
454 offsetbuf, 2);
455 if (ret)
456 return ret;
457
458 return regmap_bulk_read(pcf2127->regmap, PCF2127_REG_RAM_RD_CMD,
459 val, bytes);
460}
461
462static int pcf2127_nvmem_write(void *priv, unsigned int offset,
463 void *val, size_t bytes)
464{
465 struct pcf2127 *pcf2127 = priv;
466 int ret;
467 unsigned char offsetbuf[] = { offset >> 8, offset };
468
469 ret = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_ADDR_MSB,
470 offsetbuf, 2);
471 if (ret)
472 return ret;
473
474 return regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_WRT_CMD,
475 val, bytes);
476}
477
478/* watchdog driver */
479
480static int pcf2127_wdt_ping(struct watchdog_device *wdd)
481{
482 int wd_val;
483 struct pcf2127 *pcf2127 = watchdog_get_drvdata(wdd);
484
485 /*
486 * Compute counter value of WATCHDG_TIM_VAL to obtain desired period
487 * in seconds, depending on the source clock frequency.
488 */
489 wd_val = ((wdd->timeout * pcf2127->cfg->wdd_clock_hz_x1000) / 1000) + 1;
490
491 return regmap_write(pcf2127->regmap, pcf2127->cfg->reg_wd_val, wd_val);
492}
493
494/*
495 * Restart watchdog timer if feature is active.
496 *
497 * Note: Reading CTRL2 register causes watchdog to stop which is unfortunate,
498 * since register also contain control/status flags for other features.
499 * Always call this function after reading CTRL2 register.
500 */
501static int pcf2127_wdt_active_ping(struct watchdog_device *wdd)
502{
503 int ret = 0;
504
505 if (watchdog_active(wdd)) {
506 ret = pcf2127_wdt_ping(wdd);
507 if (ret)
508 dev_err(wdd->parent,
509 "%s: watchdog restart failed, ret=%d\n",
510 __func__, ret);
511 }
512
513 return ret;
514}
515
516static int pcf2127_wdt_start(struct watchdog_device *wdd)
517{
518 return pcf2127_wdt_ping(wdd);
519}
520
521static int pcf2127_wdt_stop(struct watchdog_device *wdd)
522{
523 struct pcf2127 *pcf2127 = watchdog_get_drvdata(wdd);
524
525 return regmap_write(pcf2127->regmap, pcf2127->cfg->reg_wd_val,
526 PCF2127_WD_VAL_STOP);
527}
528
529static int pcf2127_wdt_set_timeout(struct watchdog_device *wdd,
530 unsigned int new_timeout)
531{
532 dev_dbg(wdd->parent, "new watchdog timeout: %is (old: %is)\n",
533 new_timeout, wdd->timeout);
534
535 wdd->timeout = new_timeout;
536
537 return pcf2127_wdt_active_ping(wdd);
538}
539
540static const struct watchdog_info pcf2127_wdt_info = {
541 .identity = "NXP PCF2127/PCF2129 Watchdog",
542 .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT,
543};
544
545static const struct watchdog_ops pcf2127_watchdog_ops = {
546 .owner = THIS_MODULE,
547 .start = pcf2127_wdt_start,
548 .stop = pcf2127_wdt_stop,
549 .ping = pcf2127_wdt_ping,
550 .set_timeout = pcf2127_wdt_set_timeout,
551};
552
553/*
554 * Compute watchdog period, t, in seconds, from the WATCHDG_TIM_VAL register
555 * value, n, and the clock frequency, f1000, in Hz x 1000.
556 *
557 * The PCF2127/29 datasheet gives t as:
558 * t = n / f
559 * The PCF2131 datasheet gives t as:
560 * t = (n - 1) / f
561 * For both variants, the watchdog is triggered when the WATCHDG_TIM_VAL reaches
562 * the value 1, and not zero. Consequently, the equation from the PCF2131
563 * datasheet seems to be the correct one for both variants.
564 */
565static int pcf2127_watchdog_get_period(int n, int f1000)
566{
567 return (1000 * (n - 1)) / f1000;
568}
569
570static int pcf2127_watchdog_init(struct device *dev, struct pcf2127 *pcf2127)
571{
572 int ret;
573
574 if (!IS_ENABLED(CONFIG_WATCHDOG) ||
575 !device_property_read_bool(dev, "reset-source"))
576 return 0;
577
578 pcf2127->wdd.parent = dev;
579 pcf2127->wdd.info = &pcf2127_wdt_info;
580 pcf2127->wdd.ops = &pcf2127_watchdog_ops;
581
582 pcf2127->wdd.min_timeout =
583 pcf2127_watchdog_get_period(
584 2, pcf2127->cfg->wdd_clock_hz_x1000);
585 pcf2127->wdd.max_timeout =
586 pcf2127_watchdog_get_period(
587 255, pcf2127->cfg->wdd_clock_hz_x1000);
588 pcf2127->wdd.timeout = PCF2127_WD_DEFAULT_TIMEOUT_S;
589
590 dev_dbg(dev, "%s clock = %d Hz / 1000\n", __func__,
591 pcf2127->cfg->wdd_clock_hz_x1000);
592
593 pcf2127->wdd.min_hw_heartbeat_ms = pcf2127->cfg->wdd_min_hw_heartbeat_ms;
594 pcf2127->wdd.status = WATCHDOG_NOWAYOUT_INIT_STATUS;
595
596 watchdog_set_drvdata(&pcf2127->wdd, pcf2127);
597
598 /* Test if watchdog timer is started by bootloader */
599 if (pcf2127->cfg->wd_val_reg_readable) {
600 u32 wdd_timeout;
601
602 ret = regmap_read(pcf2127->regmap, pcf2127->cfg->reg_wd_val,
603 &wdd_timeout);
604 if (ret)
605 return ret;
606
607 if (wdd_timeout)
608 set_bit(WDOG_HW_RUNNING, &pcf2127->wdd.status);
609 }
610
611 /*
612 * When using interrupt pin (INT A) as watchdog output, only allow
613 * watchdog interrupt (PCF2131_BIT_INT_WD_CD) and disable (mask) all
614 * other interrupts.
615 */
616 if (pcf2127->cfg->type == PCF2131) {
617 ret = regmap_write(pcf2127->regmap,
618 PCF2131_REG_INT_A_MASK1,
619 PCF2131_BIT_INT_BLIE |
620 PCF2131_BIT_INT_BIE |
621 PCF2131_BIT_INT_AIE |
622 PCF2131_BIT_INT_SI |
623 PCF2131_BIT_INT_MI);
624 }
625
626 return devm_watchdog_register_device(dev, &pcf2127->wdd);
627}
628
629/* Alarm */
630static int pcf2127_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
631{
632 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
633 u8 buf[5];
634 unsigned int ctrl2;
635 int ret;
636
637 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2);
638 if (ret)
639 return ret;
640
641 ret = pcf2127_wdt_active_ping(&pcf2127->wdd);
642 if (ret)
643 return ret;
644
645 ret = regmap_bulk_read(pcf2127->regmap, pcf2127->cfg->regs_alarm_base,
646 buf, sizeof(buf));
647 if (ret)
648 return ret;
649
650 alrm->enabled = ctrl2 & PCF2127_BIT_CTRL2_AIE;
651 alrm->pending = ctrl2 & PCF2127_BIT_CTRL2_AF;
652
653 alrm->time.tm_sec = bcd2bin(buf[0] & 0x7F);
654 alrm->time.tm_min = bcd2bin(buf[1] & 0x7F);
655 alrm->time.tm_hour = bcd2bin(buf[2] & 0x3F);
656 alrm->time.tm_mday = bcd2bin(buf[3] & 0x3F);
657
658 return 0;
659}
660
661static int pcf2127_rtc_alarm_irq_enable(struct device *dev, u32 enable)
662{
663 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
664 int ret;
665
666 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2,
667 PCF2127_BIT_CTRL2_AIE,
668 enable ? PCF2127_BIT_CTRL2_AIE : 0);
669 if (ret)
670 return ret;
671
672 return pcf2127_wdt_active_ping(&pcf2127->wdd);
673}
674
675static int pcf2127_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
676{
677 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
678 uint8_t buf[5];
679 int ret;
680
681 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2,
682 PCF2127_BIT_CTRL2_AF, 0);
683 if (ret)
684 return ret;
685
686 ret = pcf2127_wdt_active_ping(&pcf2127->wdd);
687 if (ret)
688 return ret;
689
690 buf[0] = bin2bcd(alrm->time.tm_sec);
691 buf[1] = bin2bcd(alrm->time.tm_min);
692 buf[2] = bin2bcd(alrm->time.tm_hour);
693 buf[3] = bin2bcd(alrm->time.tm_mday);
694 buf[4] = PCF2127_BIT_ALARM_AE; /* Do not match on week day */
695
696 ret = regmap_bulk_write(pcf2127->regmap, pcf2127->cfg->regs_alarm_base,
697 buf, sizeof(buf));
698 if (ret)
699 return ret;
700
701 return pcf2127_rtc_alarm_irq_enable(dev, alrm->enabled);
702}
703
704/*
705 * This function reads one timestamp function data, caller is responsible for
706 * calling pcf2127_wdt_active_ping()
707 */
708static int pcf2127_rtc_ts_read(struct device *dev, time64_t *ts,
709 int ts_id)
710{
711 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
712 struct rtc_time tm;
713 int ret;
714 unsigned char data[7];
715
716 ret = regmap_bulk_read(pcf2127->regmap, pcf2127->cfg->ts[ts_id].reg_base,
717 data, sizeof(data));
718 if (ret) {
719 dev_err(dev, "%s: read error ret=%d\n", __func__, ret);
720 return ret;
721 }
722
723 dev_dbg(dev,
724 "%s: raw data is ts_sc=%02x, ts_mn=%02x, ts_hr=%02x, ts_dm=%02x, ts_mo=%02x, ts_yr=%02x\n",
725 __func__, data[1], data[2], data[3], data[4], data[5], data[6]);
726
727 tm.tm_sec = bcd2bin(data[1] & 0x7F);
728 tm.tm_min = bcd2bin(data[2] & 0x7F);
729 tm.tm_hour = bcd2bin(data[3] & 0x3F);
730 tm.tm_mday = bcd2bin(data[4] & 0x3F);
731 /* TS_MO register (month) value range: 1-12 */
732 tm.tm_mon = bcd2bin(data[5] & 0x1F) - 1;
733 tm.tm_year = bcd2bin(data[6]);
734 if (tm.tm_year < 70)
735 tm.tm_year += 100; /* assume we are in 1970...2069 */
736
737 ret = rtc_valid_tm(&tm);
738 if (ret) {
739 dev_err(dev, "Invalid timestamp. ret=%d\n", ret);
740 return ret;
741 }
742
743 *ts = rtc_tm_to_time64(&tm);
744 return 0;
745};
746
747static void pcf2127_rtc_ts_snapshot(struct device *dev, int ts_id)
748{
749 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
750 int ret;
751
752 if (ts_id >= pcf2127->cfg->ts_count)
753 return;
754
755 /* Let userspace read the first timestamp */
756 if (pcf2127->ts_valid[ts_id])
757 return;
758
759 ret = pcf2127_rtc_ts_read(dev, &pcf2127->ts[ts_id], ts_id);
760 if (!ret)
761 pcf2127->ts_valid[ts_id] = true;
762}
763
764static irqreturn_t pcf2127_rtc_irq(int irq, void *dev)
765{
766 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
767 unsigned int ctrl2;
768 int ret = 0;
769
770 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2);
771 if (ret)
772 return IRQ_NONE;
773
774 if (pcf2127->cfg->ts_count == 1) {
775 /* PCF2127/29 */
776 unsigned int ctrl1;
777
778 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL1, &ctrl1);
779 if (ret)
780 return IRQ_NONE;
781
782 if (!(ctrl1 & PCF2127_CTRL1_IRQ_MASK || ctrl2 & PCF2127_CTRL2_IRQ_MASK))
783 return IRQ_NONE;
784
785 if (ctrl1 & PCF2127_BIT_CTRL1_TSF1 || ctrl2 & PCF2127_BIT_CTRL2_TSF2)
786 pcf2127_rtc_ts_snapshot(dev, 0);
787
788 if (ctrl1 & PCF2127_CTRL1_IRQ_MASK)
789 regmap_write(pcf2127->regmap, PCF2127_REG_CTRL1,
790 ctrl1 & ~PCF2127_CTRL1_IRQ_MASK);
791
792 if (ctrl2 & PCF2127_CTRL2_IRQ_MASK)
793 regmap_write(pcf2127->regmap, PCF2127_REG_CTRL2,
794 ctrl2 & ~PCF2127_CTRL2_IRQ_MASK);
795 } else {
796 /* PCF2131. */
797 unsigned int ctrl4;
798
799 ret = regmap_read(pcf2127->regmap, PCF2131_REG_CTRL4, &ctrl4);
800 if (ret)
801 return IRQ_NONE;
802
803 if (!(ctrl4 & PCF2131_CTRL4_IRQ_MASK || ctrl2 & PCF2131_CTRL2_IRQ_MASK))
804 return IRQ_NONE;
805
806 if (ctrl4 & PCF2131_CTRL4_IRQ_MASK) {
807 int i;
808 int tsf_bit = PCF2131_BIT_CTRL4_TSF1; /* Start at bit 7. */
809
810 for (i = 0; i < pcf2127->cfg->ts_count; i++) {
811 if (ctrl4 & tsf_bit)
812 pcf2127_rtc_ts_snapshot(dev, i);
813
814 tsf_bit = tsf_bit >> 1;
815 }
816
817 regmap_write(pcf2127->regmap, PCF2131_REG_CTRL4,
818 ctrl4 & ~PCF2131_CTRL4_IRQ_MASK);
819 }
820
821 if (ctrl2 & PCF2131_CTRL2_IRQ_MASK)
822 regmap_write(pcf2127->regmap, PCF2127_REG_CTRL2,
823 ctrl2 & ~PCF2131_CTRL2_IRQ_MASK);
824 }
825
826 if (ctrl2 & PCF2127_BIT_CTRL2_AF)
827 rtc_update_irq(pcf2127->rtc, 1, RTC_IRQF | RTC_AF);
828
829 pcf2127_wdt_active_ping(&pcf2127->wdd);
830
831 return IRQ_HANDLED;
832}
833
834static const struct rtc_class_ops pcf2127_rtc_ops = {
835 .ioctl = pcf2127_rtc_ioctl,
836 .read_time = pcf2127_rtc_read_time,
837 .set_time = pcf2127_rtc_set_time,
838 .read_alarm = pcf2127_rtc_read_alarm,
839 .set_alarm = pcf2127_rtc_set_alarm,
840 .alarm_irq_enable = pcf2127_rtc_alarm_irq_enable,
841 .param_get = pcf2127_param_get,
842 .param_set = pcf2127_param_set,
843};
844
845/* sysfs interface */
846
847static ssize_t timestamp_store(struct device *dev,
848 struct device_attribute *attr,
849 const char *buf, size_t count, int ts_id)
850{
851 struct pcf2127 *pcf2127 = dev_get_drvdata(dev->parent);
852 int ret;
853
854 if (ts_id >= pcf2127->cfg->ts_count)
855 return 0;
856
857 if (pcf2127->irq_enabled) {
858 pcf2127->ts_valid[ts_id] = false;
859 } else {
860 /* Always clear GND interrupt bit. */
861 ret = regmap_update_bits(pcf2127->regmap,
862 pcf2127->cfg->ts[ts_id].gnd_detect_reg,
863 pcf2127->cfg->ts[ts_id].gnd_detect_bit,
864 0);
865
866 if (ret) {
867 dev_err(dev, "%s: update TS gnd detect ret=%d\n", __func__, ret);
868 return ret;
869 }
870
871 if (pcf2127->cfg->ts[ts_id].inter_detect_bit) {
872 /* Clear intermediate level interrupt bit if supported. */
873 ret = regmap_update_bits(pcf2127->regmap,
874 pcf2127->cfg->ts[ts_id].inter_detect_reg,
875 pcf2127->cfg->ts[ts_id].inter_detect_bit,
876 0);
877 if (ret) {
878 dev_err(dev, "%s: update TS intermediate level detect ret=%d\n",
879 __func__, ret);
880 return ret;
881 }
882 }
883
884 ret = pcf2127_wdt_active_ping(&pcf2127->wdd);
885 if (ret)
886 return ret;
887 }
888
889 return count;
890}
891
892static ssize_t timestamp0_store(struct device *dev,
893 struct device_attribute *attr,
894 const char *buf, size_t count)
895{
896 return timestamp_store(dev, attr, buf, count, 0);
897};
898
899static ssize_t timestamp1_store(struct device *dev,
900 struct device_attribute *attr,
901 const char *buf, size_t count)
902{
903 return timestamp_store(dev, attr, buf, count, 1);
904};
905
906static ssize_t timestamp2_store(struct device *dev,
907 struct device_attribute *attr,
908 const char *buf, size_t count)
909{
910 return timestamp_store(dev, attr, buf, count, 2);
911};
912
913static ssize_t timestamp3_store(struct device *dev,
914 struct device_attribute *attr,
915 const char *buf, size_t count)
916{
917 return timestamp_store(dev, attr, buf, count, 3);
918};
919
920static ssize_t timestamp_show(struct device *dev,
921 struct device_attribute *attr, char *buf,
922 int ts_id)
923{
924 struct pcf2127 *pcf2127 = dev_get_drvdata(dev->parent);
925 int ret;
926 time64_t ts;
927
928 if (ts_id >= pcf2127->cfg->ts_count)
929 return 0;
930
931 if (pcf2127->irq_enabled) {
932 if (!pcf2127->ts_valid[ts_id])
933 return 0;
934 ts = pcf2127->ts[ts_id];
935 } else {
936 u8 valid_low = 0;
937 u8 valid_inter = 0;
938 unsigned int ctrl;
939
940 /* Check if TS input pin is driven to GND, supported by all
941 * variants.
942 */
943 ret = regmap_read(pcf2127->regmap,
944 pcf2127->cfg->ts[ts_id].gnd_detect_reg,
945 &ctrl);
946 if (ret)
947 return 0;
948
949 valid_low = ctrl & pcf2127->cfg->ts[ts_id].gnd_detect_bit;
950
951 if (pcf2127->cfg->ts[ts_id].inter_detect_bit) {
952 /* Check if TS input pin is driven to intermediate level
953 * between GND and supply, if supported by variant.
954 */
955 ret = regmap_read(pcf2127->regmap,
956 pcf2127->cfg->ts[ts_id].inter_detect_reg,
957 &ctrl);
958 if (ret)
959 return 0;
960
961 valid_inter = ctrl & pcf2127->cfg->ts[ts_id].inter_detect_bit;
962 }
963
964 if (!valid_low && !valid_inter)
965 return 0;
966
967 ret = pcf2127_rtc_ts_read(dev->parent, &ts, ts_id);
968 if (ret)
969 return 0;
970
971 ret = pcf2127_wdt_active_ping(&pcf2127->wdd);
972 if (ret)
973 return ret;
974 }
975 return sprintf(buf, "%llu\n", (unsigned long long)ts);
976}
977
978static ssize_t timestamp0_show(struct device *dev,
979 struct device_attribute *attr, char *buf)
980{
981 return timestamp_show(dev, attr, buf, 0);
982};
983
984static ssize_t timestamp1_show(struct device *dev,
985 struct device_attribute *attr, char *buf)
986{
987 return timestamp_show(dev, attr, buf, 1);
988};
989
990static ssize_t timestamp2_show(struct device *dev,
991 struct device_attribute *attr, char *buf)
992{
993 return timestamp_show(dev, attr, buf, 2);
994};
995
996static ssize_t timestamp3_show(struct device *dev,
997 struct device_attribute *attr, char *buf)
998{
999 return timestamp_show(dev, attr, buf, 3);
1000};
1001
1002static DEVICE_ATTR_RW(timestamp0);
1003static DEVICE_ATTR_RW(timestamp1);
1004static DEVICE_ATTR_RW(timestamp2);
1005static DEVICE_ATTR_RW(timestamp3);
1006
1007static struct attribute *pcf2127_attrs[] = {
1008 &dev_attr_timestamp0.attr,
1009 NULL
1010};
1011
1012static struct attribute *pcf2131_attrs[] = {
1013 &dev_attr_timestamp0.attr,
1014 &dev_attr_timestamp1.attr,
1015 &dev_attr_timestamp2.attr,
1016 &dev_attr_timestamp3.attr,
1017 NULL
1018};
1019
1020static struct pcf21xx_config pcf21xx_cfg[] = {
1021 [PCF2127] = {
1022 .type = PCF2127,
1023 .max_register = 0x1d,
1024 .has_nvmem = 1,
1025 .has_bit_wd_ctl_cd0 = 1,
1026 .wd_val_reg_readable = 1,
1027 .has_int_a_b = 0,
1028 .reg_time_base = PCF2127_REG_TIME_BASE,
1029 .regs_alarm_base = PCF2127_REG_ALARM_BASE,
1030 .reg_wd_ctl = PCF2127_REG_WD_CTL,
1031 .reg_wd_val = PCF2127_REG_WD_VAL,
1032 .reg_clkout = PCF2127_REG_CLKOUT,
1033 .wdd_clock_hz_x1000 = PCF2127_WD_CLOCK_HZ_X1000,
1034 .wdd_min_hw_heartbeat_ms = PCF2127_WD_MIN_HW_HEARTBEAT_MS,
1035 .ts_count = 1,
1036 .ts[0] = {
1037 .reg_base = PCF2127_REG_TS1_BASE,
1038 .gnd_detect_reg = PCF2127_REG_CTRL1,
1039 .gnd_detect_bit = PCF2127_BIT_CTRL1_TSF1,
1040 .inter_detect_reg = PCF2127_REG_CTRL2,
1041 .inter_detect_bit = PCF2127_BIT_CTRL2_TSF2,
1042 .ie_reg = PCF2127_REG_CTRL2,
1043 .ie_bit = PCF2127_BIT_CTRL2_TSIE,
1044 },
1045 .attribute_group = {
1046 .attrs = pcf2127_attrs,
1047 },
1048 },
1049 [PCF2129] = {
1050 .type = PCF2129,
1051 .max_register = 0x19,
1052 .has_nvmem = 0,
1053 .has_bit_wd_ctl_cd0 = 0,
1054 .wd_val_reg_readable = 1,
1055 .has_int_a_b = 0,
1056 .reg_time_base = PCF2127_REG_TIME_BASE,
1057 .regs_alarm_base = PCF2127_REG_ALARM_BASE,
1058 .reg_wd_ctl = PCF2127_REG_WD_CTL,
1059 .reg_wd_val = PCF2127_REG_WD_VAL,
1060 .reg_clkout = PCF2127_REG_CLKOUT,
1061 .wdd_clock_hz_x1000 = PCF2127_WD_CLOCK_HZ_X1000,
1062 .wdd_min_hw_heartbeat_ms = PCF2127_WD_MIN_HW_HEARTBEAT_MS,
1063 .ts_count = 1,
1064 .ts[0] = {
1065 .reg_base = PCF2127_REG_TS1_BASE,
1066 .gnd_detect_reg = PCF2127_REG_CTRL1,
1067 .gnd_detect_bit = PCF2127_BIT_CTRL1_TSF1,
1068 .inter_detect_reg = PCF2127_REG_CTRL2,
1069 .inter_detect_bit = PCF2127_BIT_CTRL2_TSF2,
1070 .ie_reg = PCF2127_REG_CTRL2,
1071 .ie_bit = PCF2127_BIT_CTRL2_TSIE,
1072 },
1073 .attribute_group = {
1074 .attrs = pcf2127_attrs,
1075 },
1076 },
1077 [PCF2131] = {
1078 .type = PCF2131,
1079 .max_register = 0x36,
1080 .has_nvmem = 0,
1081 .has_bit_wd_ctl_cd0 = 0,
1082 .wd_val_reg_readable = 0,
1083 .has_int_a_b = 1,
1084 .reg_time_base = PCF2131_REG_TIME_BASE,
1085 .regs_alarm_base = PCF2131_REG_ALARM_BASE,
1086 .reg_wd_ctl = PCF2131_REG_WD_CTL,
1087 .reg_wd_val = PCF2131_REG_WD_VAL,
1088 .reg_clkout = PCF2131_REG_CLKOUT,
1089 .wdd_clock_hz_x1000 = PCF2131_WD_CLOCK_HZ_X1000,
1090 .wdd_min_hw_heartbeat_ms = PCF2131_WD_MIN_HW_HEARTBEAT_MS,
1091 .ts_count = 4,
1092 .ts[0] = {
1093 .reg_base = PCF2131_REG_TS1_BASE,
1094 .gnd_detect_reg = PCF2131_REG_CTRL4,
1095 .gnd_detect_bit = PCF2131_BIT_CTRL4_TSF1,
1096 .inter_detect_bit = 0,
1097 .ie_reg = PCF2131_REG_CTRL5,
1098 .ie_bit = PCF2131_BIT_CTRL5_TSIE1,
1099 },
1100 .ts[1] = {
1101 .reg_base = PCF2131_REG_TS2_BASE,
1102 .gnd_detect_reg = PCF2131_REG_CTRL4,
1103 .gnd_detect_bit = PCF2131_BIT_CTRL4_TSF2,
1104 .inter_detect_bit = 0,
1105 .ie_reg = PCF2131_REG_CTRL5,
1106 .ie_bit = PCF2131_BIT_CTRL5_TSIE2,
1107 },
1108 .ts[2] = {
1109 .reg_base = PCF2131_REG_TS3_BASE,
1110 .gnd_detect_reg = PCF2131_REG_CTRL4,
1111 .gnd_detect_bit = PCF2131_BIT_CTRL4_TSF3,
1112 .inter_detect_bit = 0,
1113 .ie_reg = PCF2131_REG_CTRL5,
1114 .ie_bit = PCF2131_BIT_CTRL5_TSIE3,
1115 },
1116 .ts[3] = {
1117 .reg_base = PCF2131_REG_TS4_BASE,
1118 .gnd_detect_reg = PCF2131_REG_CTRL4,
1119 .gnd_detect_bit = PCF2131_BIT_CTRL4_TSF4,
1120 .inter_detect_bit = 0,
1121 .ie_reg = PCF2131_REG_CTRL5,
1122 .ie_bit = PCF2131_BIT_CTRL5_TSIE4,
1123 },
1124 .attribute_group = {
1125 .attrs = pcf2131_attrs,
1126 },
1127 },
1128};
1129
1130/*
1131 * Enable timestamp function and corresponding interrupt(s).
1132 */
1133static int pcf2127_enable_ts(struct device *dev, int ts_id)
1134{
1135 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
1136 int ret;
1137
1138 if (ts_id >= pcf2127->cfg->ts_count) {
1139 dev_err(dev, "%s: invalid tamper detection ID (%d)\n",
1140 __func__, ts_id);
1141 return -EINVAL;
1142 }
1143
1144 /* Enable timestamp function. */
1145 ret = regmap_update_bits(pcf2127->regmap,
1146 pcf2127->cfg->ts[ts_id].reg_base,
1147 PCF2127_BIT_TS_CTRL_TSOFF |
1148 PCF2127_BIT_TS_CTRL_TSM,
1149 PCF2127_BIT_TS_CTRL_TSM);
1150 if (ret) {
1151 dev_err(dev, "%s: tamper detection config (ts%d_ctrl) failed\n",
1152 __func__, ts_id);
1153 return ret;
1154 }
1155
1156 /*
1157 * Enable interrupt generation when TSF timestamp flag is set.
1158 * Interrupt signals are open-drain outputs and can be left floating if
1159 * unused.
1160 */
1161 ret = regmap_update_bits(pcf2127->regmap, pcf2127->cfg->ts[ts_id].ie_reg,
1162 pcf2127->cfg->ts[ts_id].ie_bit,
1163 pcf2127->cfg->ts[ts_id].ie_bit);
1164 if (ret) {
1165 dev_err(dev, "%s: tamper detection TSIE%d config failed\n",
1166 __func__, ts_id);
1167 return ret;
1168 }
1169
1170 return ret;
1171}
1172
1173/* Route all interrupt sources to INT A pin. */
1174static int pcf2127_configure_interrupt_pins(struct device *dev)
1175{
1176 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
1177 int ret;
1178
1179 /* Mask bits need to be cleared to enable corresponding
1180 * interrupt source.
1181 */
1182 ret = regmap_write(pcf2127->regmap,
1183 PCF2131_REG_INT_A_MASK1, 0);
1184 if (ret)
1185 return ret;
1186
1187 return regmap_write(pcf2127->regmap, PCF2131_REG_INT_A_MASK2, 0);
1188}
1189
1190static int pcf2127_probe(struct device *dev, struct regmap *regmap,
1191 int alarm_irq, const struct pcf21xx_config *config)
1192{
1193 struct pcf2127 *pcf2127;
1194 int ret = 0;
1195 unsigned int val;
1196
1197 dev_dbg(dev, "%s\n", __func__);
1198
1199 pcf2127 = devm_kzalloc(dev, sizeof(*pcf2127), GFP_KERNEL);
1200 if (!pcf2127)
1201 return -ENOMEM;
1202
1203 pcf2127->regmap = regmap;
1204 pcf2127->cfg = config;
1205
1206 dev_set_drvdata(dev, pcf2127);
1207
1208 pcf2127->rtc = devm_rtc_allocate_device(dev);
1209 if (IS_ERR(pcf2127->rtc))
1210 return PTR_ERR(pcf2127->rtc);
1211
1212 pcf2127->rtc->ops = &pcf2127_rtc_ops;
1213 pcf2127->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
1214 pcf2127->rtc->range_max = RTC_TIMESTAMP_END_2099;
1215 pcf2127->rtc->set_start_time = true; /* Sets actual start to 1970 */
1216
1217 /*
1218 * PCF2127/29 do not work correctly when setting alarms at 1s intervals.
1219 * PCF2131 is ok.
1220 */
1221 if (pcf2127->cfg->type == PCF2127 || pcf2127->cfg->type == PCF2129) {
1222 set_bit(RTC_FEATURE_ALARM_RES_2S, pcf2127->rtc->features);
1223 clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, pcf2127->rtc->features);
1224 }
1225
1226 clear_bit(RTC_FEATURE_ALARM, pcf2127->rtc->features);
1227
1228 if (alarm_irq > 0) {
1229 unsigned long flags;
1230
1231 /*
1232 * If flags = 0, devm_request_threaded_irq() will use IRQ flags
1233 * obtained from device tree.
1234 */
1235 if (dev_fwnode(dev))
1236 flags = 0;
1237 else
1238 flags = IRQF_TRIGGER_LOW;
1239
1240 ret = devm_request_threaded_irq(dev, alarm_irq, NULL,
1241 pcf2127_rtc_irq,
1242 flags | IRQF_ONESHOT,
1243 dev_name(dev), dev);
1244 if (ret) {
1245 dev_err(dev, "failed to request alarm irq\n");
1246 return ret;
1247 }
1248 pcf2127->irq_enabled = true;
1249 }
1250
1251 if (alarm_irq > 0 || device_property_read_bool(dev, "wakeup-source")) {
1252 device_init_wakeup(dev, true);
1253 set_bit(RTC_FEATURE_ALARM, pcf2127->rtc->features);
1254 }
1255
1256 if (pcf2127->cfg->has_int_a_b) {
1257 /* Configure int A/B pins, independently of alarm_irq. */
1258 ret = pcf2127_configure_interrupt_pins(dev);
1259 if (ret) {
1260 dev_err(dev, "failed to configure interrupt pins\n");
1261 return ret;
1262 }
1263 }
1264
1265 if (pcf2127->cfg->has_nvmem) {
1266 struct nvmem_config nvmem_cfg = {
1267 .priv = pcf2127,
1268 .reg_read = pcf2127_nvmem_read,
1269 .reg_write = pcf2127_nvmem_write,
1270 .size = 512,
1271 };
1272
1273 ret = devm_rtc_nvmem_register(pcf2127->rtc, &nvmem_cfg);
1274 }
1275
1276 /*
1277 * The "Power-On Reset Override" facility prevents the RTC to do a reset
1278 * after power on. For normal operation the PORO must be disabled.
1279 */
1280 ret = regmap_clear_bits(pcf2127->regmap, PCF2127_REG_CTRL1,
1281 PCF2127_BIT_CTRL1_POR_OVRD);
1282 if (ret < 0)
1283 return ret;
1284
1285 ret = regmap_read(pcf2127->regmap, pcf2127->cfg->reg_clkout, &val);
1286 if (ret < 0)
1287 return ret;
1288
1289 if (!(val & PCF2127_BIT_CLKOUT_OTPR)) {
1290 ret = regmap_set_bits(pcf2127->regmap, pcf2127->cfg->reg_clkout,
1291 PCF2127_BIT_CLKOUT_OTPR);
1292 if (ret < 0)
1293 return ret;
1294
1295 msleep(100);
1296 }
1297
1298 /*
1299 * Watchdog timer enabled and reset pin /RST activated when timed out.
1300 * Select 1Hz clock source for watchdog timer (1/4Hz for PCF2131).
1301 * Note: Countdown timer disabled and not available.
1302 * For pca2129, pcf2129 and pcf2131, only bit[7] is for Symbol WD_CD
1303 * of register watchdg_tim_ctl. The bit[6] is labeled
1304 * as T. Bits labeled as T must always be written with
1305 * logic 0.
1306 */
1307 ret = regmap_update_bits(pcf2127->regmap, pcf2127->cfg->reg_wd_ctl,
1308 PCF2127_BIT_WD_CTL_CD1 |
1309 PCF2127_BIT_WD_CTL_CD0 |
1310 PCF2127_BIT_WD_CTL_TF1 |
1311 PCF2127_BIT_WD_CTL_TF0,
1312 PCF2127_BIT_WD_CTL_CD1 |
1313 (pcf2127->cfg->has_bit_wd_ctl_cd0 ? PCF2127_BIT_WD_CTL_CD0 : 0) |
1314 PCF2127_BIT_WD_CTL_TF1);
1315 if (ret) {
1316 dev_err(dev, "%s: watchdog config (wd_ctl) failed\n", __func__);
1317 return ret;
1318 }
1319
1320 pcf2127_watchdog_init(dev, pcf2127);
1321
1322 /*
1323 * Disable battery low/switch-over timestamp and interrupts.
1324 * Clear battery interrupt flags which can block new trigger events.
1325 * Note: This is the default chip behaviour but added to ensure
1326 * correct tamper timestamp and interrupt function.
1327 */
1328 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL3,
1329 PCF2127_BIT_CTRL3_BTSE |
1330 PCF2127_BIT_CTRL3_BIE |
1331 PCF2127_BIT_CTRL3_BLIE, 0);
1332 if (ret) {
1333 dev_err(dev, "%s: interrupt config (ctrl3) failed\n",
1334 __func__);
1335 return ret;
1336 }
1337
1338 /*
1339 * Enable timestamp functions 1 to 4.
1340 */
1341 for (int i = 0; i < pcf2127->cfg->ts_count; i++) {
1342 ret = pcf2127_enable_ts(dev, i);
1343 if (ret)
1344 return ret;
1345 }
1346
1347 ret = rtc_add_group(pcf2127->rtc, &pcf2127->cfg->attribute_group);
1348 if (ret) {
1349 dev_err(dev, "%s: tamper sysfs registering failed\n",
1350 __func__);
1351 return ret;
1352 }
1353
1354 return devm_rtc_register_device(pcf2127->rtc);
1355}
1356
1357#ifdef CONFIG_OF
1358static const struct of_device_id pcf2127_of_match[] = {
1359 { .compatible = "nxp,pcf2127", .data = &pcf21xx_cfg[PCF2127] },
1360 { .compatible = "nxp,pcf2129", .data = &pcf21xx_cfg[PCF2129] },
1361 { .compatible = "nxp,pca2129", .data = &pcf21xx_cfg[PCF2129] },
1362 { .compatible = "nxp,pcf2131", .data = &pcf21xx_cfg[PCF2131] },
1363 {}
1364};
1365MODULE_DEVICE_TABLE(of, pcf2127_of_match);
1366#endif
1367
1368#if IS_ENABLED(CONFIG_I2C)
1369
1370static int pcf2127_i2c_write(void *context, const void *data, size_t count)
1371{
1372 struct device *dev = context;
1373 struct i2c_client *client = to_i2c_client(dev);
1374 int ret;
1375
1376 ret = i2c_master_send(client, data, count);
1377 if (ret != count)
1378 return ret < 0 ? ret : -EIO;
1379
1380 return 0;
1381}
1382
1383static int pcf2127_i2c_gather_write(void *context,
1384 const void *reg, size_t reg_size,
1385 const void *val, size_t val_size)
1386{
1387 struct device *dev = context;
1388 struct i2c_client *client = to_i2c_client(dev);
1389 int ret;
1390 void *buf;
1391
1392 if (WARN_ON(reg_size != 1))
1393 return -EINVAL;
1394
1395 buf = kmalloc(val_size + 1, GFP_KERNEL);
1396 if (!buf)
1397 return -ENOMEM;
1398
1399 memcpy(buf, reg, 1);
1400 memcpy(buf + 1, val, val_size);
1401
1402 ret = i2c_master_send(client, buf, val_size + 1);
1403
1404 kfree(buf);
1405
1406 if (ret != val_size + 1)
1407 return ret < 0 ? ret : -EIO;
1408
1409 return 0;
1410}
1411
1412static int pcf2127_i2c_read(void *context, const void *reg, size_t reg_size,
1413 void *val, size_t val_size)
1414{
1415 struct device *dev = context;
1416 struct i2c_client *client = to_i2c_client(dev);
1417 int ret;
1418
1419 if (WARN_ON(reg_size != 1))
1420 return -EINVAL;
1421
1422 ret = i2c_master_send(client, reg, 1);
1423 if (ret != 1)
1424 return ret < 0 ? ret : -EIO;
1425
1426 ret = i2c_master_recv(client, val, val_size);
1427 if (ret != val_size)
1428 return ret < 0 ? ret : -EIO;
1429
1430 return 0;
1431}
1432
1433/*
1434 * The reason we need this custom regmap_bus instead of using regmap_init_i2c()
1435 * is that the STOP condition is required between set register address and
1436 * read register data when reading from registers.
1437 */
1438static const struct regmap_bus pcf2127_i2c_regmap = {
1439 .write = pcf2127_i2c_write,
1440 .gather_write = pcf2127_i2c_gather_write,
1441 .read = pcf2127_i2c_read,
1442};
1443
1444static struct i2c_driver pcf2127_i2c_driver;
1445
1446static const struct i2c_device_id pcf2127_i2c_id[] = {
1447 { .name = "pcf2127", .driver_data = (kernel_ulong_t)&pcf21xx_cfg[PCF2127] },
1448 { .name = "pcf2129", .driver_data = (kernel_ulong_t)&pcf21xx_cfg[PCF2129] },
1449 { .name = "pca2129", .driver_data = (kernel_ulong_t)&pcf21xx_cfg[PCF2129] },
1450 { .name = "pcf2131", .driver_data = (kernel_ulong_t)&pcf21xx_cfg[PCF2131] },
1451 { }
1452};
1453MODULE_DEVICE_TABLE(i2c, pcf2127_i2c_id);
1454
1455static int pcf2127_i2c_probe(struct i2c_client *client)
1456{
1457 struct regmap *regmap;
1458 static struct regmap_config config = {
1459 .reg_bits = 8,
1460 .val_bits = 8,
1461 };
1462 const struct pcf21xx_config *variant;
1463
1464 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
1465 return -ENODEV;
1466
1467 variant = i2c_get_match_data(client);
1468 if (!variant)
1469 return -ENODEV;
1470
1471 config.max_register = variant->max_register,
1472
1473 regmap = devm_regmap_init(&client->dev, &pcf2127_i2c_regmap,
1474 &client->dev, &config);
1475 if (IS_ERR(regmap)) {
1476 dev_err(&client->dev, "%s: regmap allocation failed: %ld\n",
1477 __func__, PTR_ERR(regmap));
1478 return PTR_ERR(regmap);
1479 }
1480
1481 return pcf2127_probe(&client->dev, regmap, client->irq, variant);
1482}
1483
1484static struct i2c_driver pcf2127_i2c_driver = {
1485 .driver = {
1486 .name = "rtc-pcf2127-i2c",
1487 .of_match_table = of_match_ptr(pcf2127_of_match),
1488 },
1489 .probe = pcf2127_i2c_probe,
1490 .id_table = pcf2127_i2c_id,
1491};
1492
1493static int pcf2127_i2c_register_driver(void)
1494{
1495 return i2c_add_driver(&pcf2127_i2c_driver);
1496}
1497
1498static void pcf2127_i2c_unregister_driver(void)
1499{
1500 i2c_del_driver(&pcf2127_i2c_driver);
1501}
1502
1503#else
1504
1505static int pcf2127_i2c_register_driver(void)
1506{
1507 return 0;
1508}
1509
1510static void pcf2127_i2c_unregister_driver(void)
1511{
1512}
1513
1514#endif
1515
1516#if IS_ENABLED(CONFIG_SPI_MASTER)
1517
1518static struct spi_driver pcf2127_spi_driver;
1519static const struct spi_device_id pcf2127_spi_id[];
1520
1521static int pcf2127_spi_probe(struct spi_device *spi)
1522{
1523 static struct regmap_config config = {
1524 .reg_bits = 8,
1525 .val_bits = 8,
1526 .read_flag_mask = 0xa0,
1527 .write_flag_mask = 0x20,
1528 };
1529 struct regmap *regmap;
1530 const struct pcf21xx_config *variant;
1531
1532 if (spi->dev.of_node) {
1533 variant = of_device_get_match_data(&spi->dev);
1534 if (!variant)
1535 return -ENODEV;
1536 } else {
1537 enum pcf21xx_type type = spi_get_device_id(spi)->driver_data;
1538
1539 if (type >= PCF21XX_LAST_ID)
1540 return -ENODEV;
1541 variant = &pcf21xx_cfg[type];
1542 }
1543
1544 if (variant->type == PCF2131) {
1545 config.read_flag_mask = 0x0;
1546 config.write_flag_mask = 0x0;
1547 }
1548
1549 config.max_register = variant->max_register;
1550
1551 regmap = devm_regmap_init_spi(spi, &config);
1552 if (IS_ERR(regmap)) {
1553 dev_err(&spi->dev, "%s: regmap allocation failed: %ld\n",
1554 __func__, PTR_ERR(regmap));
1555 return PTR_ERR(regmap);
1556 }
1557
1558 return pcf2127_probe(&spi->dev, regmap, spi->irq, variant);
1559}
1560
1561static const struct spi_device_id pcf2127_spi_id[] = {
1562 { "pcf2127", PCF2127 },
1563 { "pcf2129", PCF2129 },
1564 { "pca2129", PCF2129 },
1565 { "pcf2131", PCF2131 },
1566 { }
1567};
1568MODULE_DEVICE_TABLE(spi, pcf2127_spi_id);
1569
1570static struct spi_driver pcf2127_spi_driver = {
1571 .driver = {
1572 .name = "rtc-pcf2127-spi",
1573 .of_match_table = of_match_ptr(pcf2127_of_match),
1574 },
1575 .probe = pcf2127_spi_probe,
1576 .id_table = pcf2127_spi_id,
1577};
1578
1579static int pcf2127_spi_register_driver(void)
1580{
1581 return spi_register_driver(&pcf2127_spi_driver);
1582}
1583
1584static void pcf2127_spi_unregister_driver(void)
1585{
1586 spi_unregister_driver(&pcf2127_spi_driver);
1587}
1588
1589#else
1590
1591static int pcf2127_spi_register_driver(void)
1592{
1593 return 0;
1594}
1595
1596static void pcf2127_spi_unregister_driver(void)
1597{
1598}
1599
1600#endif
1601
1602static int __init pcf2127_init(void)
1603{
1604 int ret;
1605
1606 ret = pcf2127_i2c_register_driver();
1607 if (ret) {
1608 pr_err("Failed to register pcf2127 i2c driver: %d\n", ret);
1609 return ret;
1610 }
1611
1612 ret = pcf2127_spi_register_driver();
1613 if (ret) {
1614 pr_err("Failed to register pcf2127 spi driver: %d\n", ret);
1615 pcf2127_i2c_unregister_driver();
1616 }
1617
1618 return ret;
1619}
1620module_init(pcf2127_init)
1621
1622static void __exit pcf2127_exit(void)
1623{
1624 pcf2127_spi_unregister_driver();
1625 pcf2127_i2c_unregister_driver();
1626}
1627module_exit(pcf2127_exit)
1628
1629MODULE_AUTHOR("Renaud Cerrato <[email protected]>");
1630MODULE_DESCRIPTION("NXP PCF2127/29/31 RTC driver");
1631MODULE_LICENSE("GPL v2");