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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * RTC driver for the Micro Crystal RV3032
4 *
5 * Copyright (C) 2020 Micro Crystal SA
6 *
7 * Alexandre Belloni <[email protected]>
8 *
9 */
10
11#include <linux/clk.h>
12#include <linux/clk-provider.h>
13#include <linux/bcd.h>
14#include <linux/bitfield.h>
15#include <linux/bitops.h>
16#include <linux/hwmon.h>
17#include <linux/i2c.h>
18#include <linux/interrupt.h>
19#include <linux/kernel.h>
20#include <linux/log2.h>
21#include <linux/module.h>
22#include <linux/of.h>
23#include <linux/regmap.h>
24#include <linux/rtc.h>
25
26#define RV3032_SEC 0x01
27#define RV3032_MIN 0x02
28#define RV3032_HOUR 0x03
29#define RV3032_WDAY 0x04
30#define RV3032_DAY 0x05
31#define RV3032_MONTH 0x06
32#define RV3032_YEAR 0x07
33#define RV3032_ALARM_MIN 0x08
34#define RV3032_ALARM_HOUR 0x09
35#define RV3032_ALARM_DAY 0x0A
36#define RV3032_STATUS 0x0D
37#define RV3032_TLSB 0x0E
38#define RV3032_TMSB 0x0F
39#define RV3032_CTRL1 0x10
40#define RV3032_CTRL2 0x11
41#define RV3032_CTRL3 0x12
42#define RV3032_TS_CTRL 0x13
43#define RV3032_CLK_IRQ 0x14
44#define RV3032_EEPROM_ADDR 0x3D
45#define RV3032_EEPROM_DATA 0x3E
46#define RV3032_EEPROM_CMD 0x3F
47#define RV3032_RAM1 0x40
48#define RV3032_PMU 0xC0
49#define RV3032_OFFSET 0xC1
50#define RV3032_CLKOUT1 0xC2
51#define RV3032_CLKOUT2 0xC3
52#define RV3032_TREF0 0xC4
53#define RV3032_TREF1 0xC5
54
55#define RV3032_STATUS_VLF BIT(0)
56#define RV3032_STATUS_PORF BIT(1)
57#define RV3032_STATUS_EVF BIT(2)
58#define RV3032_STATUS_AF BIT(3)
59#define RV3032_STATUS_TF BIT(4)
60#define RV3032_STATUS_UF BIT(5)
61#define RV3032_STATUS_TLF BIT(6)
62#define RV3032_STATUS_THF BIT(7)
63
64#define RV3032_TLSB_CLKF BIT(1)
65#define RV3032_TLSB_EEBUSY BIT(2)
66#define RV3032_TLSB_TEMP GENMASK(7, 4)
67
68#define RV3032_CLKOUT2_HFD_MSK GENMASK(4, 0)
69#define RV3032_CLKOUT2_FD_MSK GENMASK(6, 5)
70#define RV3032_CLKOUT2_OS BIT(7)
71
72#define RV3032_CTRL1_EERD BIT(2)
73
74#define RV3032_CTRL2_STOP BIT(0)
75#define RV3032_CTRL2_EIE BIT(2)
76#define RV3032_CTRL2_AIE BIT(3)
77#define RV3032_CTRL2_TIE BIT(4)
78#define RV3032_CTRL2_UIE BIT(5)
79#define RV3032_CTRL2_CLKIE BIT(6)
80#define RV3032_CTRL2_TSE BIT(7)
81
82#define RV3032_PMU_TCM GENMASK(1, 0)
83#define RV3032_PMU_TCR GENMASK(3, 2)
84#define RV3032_PMU_BSM GENMASK(5, 4)
85#define RV3032_PMU_NCLKE BIT(6)
86
87#define RV3032_PMU_BSM_DSM 1
88#define RV3032_PMU_BSM_LSM 2
89
90#define RV3032_OFFSET_MSK GENMASK(5, 0)
91
92#define RV3032_EVT_CTRL_TSR BIT(2)
93
94#define RV3032_EEPROM_CMD_UPDATE 0x11
95#define RV3032_EEPROM_CMD_WRITE 0x21
96#define RV3032_EEPROM_CMD_READ 0x22
97
98#define RV3032_EEPROM_USER 0xCB
99
100#define RV3032_EEBUSY_POLL 10000
101#define RV3032_EEBUSY_TIMEOUT 100000
102
103#define OFFSET_STEP_PPT 238419
104
105struct rv3032_data {
106 struct regmap *regmap;
107 struct rtc_device *rtc;
108 bool trickle_charger_set;
109#ifdef CONFIG_COMMON_CLK
110 struct clk_hw clkout_hw;
111#endif
112};
113
114static u16 rv3032_trickle_resistors[] = {1000, 2000, 7000, 11000};
115static u16 rv3032_trickle_voltages[] = {0, 1750, 3000, 4400};
116
117static int rv3032_exit_eerd(struct rv3032_data *rv3032, u32 eerd)
118{
119 if (eerd)
120 return 0;
121
122 return regmap_update_bits(rv3032->regmap, RV3032_CTRL1, RV3032_CTRL1_EERD, 0);
123}
124
125static int rv3032_enter_eerd(struct rv3032_data *rv3032, u32 *eerd)
126{
127 u32 ctrl1, status;
128 int ret;
129
130 ret = regmap_read(rv3032->regmap, RV3032_CTRL1, &ctrl1);
131 if (ret)
132 return ret;
133
134 *eerd = ctrl1 & RV3032_CTRL1_EERD;
135 if (*eerd)
136 return 0;
137
138 ret = regmap_update_bits(rv3032->regmap, RV3032_CTRL1,
139 RV3032_CTRL1_EERD, RV3032_CTRL1_EERD);
140 if (ret)
141 return ret;
142
143 ret = regmap_read_poll_timeout(rv3032->regmap, RV3032_TLSB, status,
144 !(status & RV3032_TLSB_EEBUSY),
145 RV3032_EEBUSY_POLL, RV3032_EEBUSY_TIMEOUT);
146 if (ret) {
147 rv3032_exit_eerd(rv3032, *eerd);
148
149 return ret;
150 }
151
152 return 0;
153}
154
155static int rv3032_update_cfg(struct rv3032_data *rv3032, unsigned int reg,
156 unsigned int mask, unsigned int val)
157{
158 u32 status, eerd;
159 int ret;
160
161 ret = rv3032_enter_eerd(rv3032, &eerd);
162 if (ret)
163 return ret;
164
165 ret = regmap_update_bits(rv3032->regmap, reg, mask, val);
166 if (ret)
167 goto exit_eerd;
168
169 ret = regmap_write(rv3032->regmap, RV3032_EEPROM_CMD, RV3032_EEPROM_CMD_UPDATE);
170 if (ret)
171 goto exit_eerd;
172
173 usleep_range(46000, RV3032_EEBUSY_TIMEOUT);
174
175 ret = regmap_read_poll_timeout(rv3032->regmap, RV3032_TLSB, status,
176 !(status & RV3032_TLSB_EEBUSY),
177 RV3032_EEBUSY_POLL, RV3032_EEBUSY_TIMEOUT);
178
179exit_eerd:
180 rv3032_exit_eerd(rv3032, eerd);
181
182 return ret;
183}
184
185static irqreturn_t rv3032_handle_irq(int irq, void *dev_id)
186{
187 struct rv3032_data *rv3032 = dev_id;
188 unsigned long events = 0;
189 u32 status = 0, ctrl = 0;
190
191 if (regmap_read(rv3032->regmap, RV3032_STATUS, &status) < 0 ||
192 status == 0) {
193 return IRQ_NONE;
194 }
195
196 if (status & RV3032_STATUS_TF) {
197 status |= RV3032_STATUS_TF;
198 ctrl |= RV3032_CTRL2_TIE;
199 events |= RTC_PF;
200 }
201
202 if (status & RV3032_STATUS_AF) {
203 status |= RV3032_STATUS_AF;
204 ctrl |= RV3032_CTRL2_AIE;
205 events |= RTC_AF;
206 }
207
208 if (status & RV3032_STATUS_UF) {
209 status |= RV3032_STATUS_UF;
210 ctrl |= RV3032_CTRL2_UIE;
211 events |= RTC_UF;
212 }
213
214 if (events) {
215 rtc_update_irq(rv3032->rtc, 1, events);
216 regmap_update_bits(rv3032->regmap, RV3032_STATUS, status, 0);
217 regmap_update_bits(rv3032->regmap, RV3032_CTRL2, ctrl, 0);
218 }
219
220 return IRQ_HANDLED;
221}
222
223static int rv3032_get_time(struct device *dev, struct rtc_time *tm)
224{
225 struct rv3032_data *rv3032 = dev_get_drvdata(dev);
226 u8 date[7];
227 int ret, status;
228
229 ret = regmap_read(rv3032->regmap, RV3032_STATUS, &status);
230 if (ret < 0)
231 return ret;
232
233 if (status & (RV3032_STATUS_PORF | RV3032_STATUS_VLF))
234 return -EINVAL;
235
236 ret = regmap_bulk_read(rv3032->regmap, RV3032_SEC, date, sizeof(date));
237 if (ret)
238 return ret;
239
240 tm->tm_sec = bcd2bin(date[0] & 0x7f);
241 tm->tm_min = bcd2bin(date[1] & 0x7f);
242 tm->tm_hour = bcd2bin(date[2] & 0x3f);
243 tm->tm_wday = date[3] & 0x7;
244 tm->tm_mday = bcd2bin(date[4] & 0x3f);
245 tm->tm_mon = bcd2bin(date[5] & 0x1f) - 1;
246 tm->tm_year = bcd2bin(date[6]) + 100;
247
248 return 0;
249}
250
251static int rv3032_set_time(struct device *dev, struct rtc_time *tm)
252{
253 struct rv3032_data *rv3032 = dev_get_drvdata(dev);
254 u8 date[7];
255 int ret;
256
257 date[0] = bin2bcd(tm->tm_sec);
258 date[1] = bin2bcd(tm->tm_min);
259 date[2] = bin2bcd(tm->tm_hour);
260 date[3] = tm->tm_wday;
261 date[4] = bin2bcd(tm->tm_mday);
262 date[5] = bin2bcd(tm->tm_mon + 1);
263 date[6] = bin2bcd(tm->tm_year - 100);
264
265 ret = regmap_bulk_write(rv3032->regmap, RV3032_SEC, date,
266 sizeof(date));
267 if (ret)
268 return ret;
269
270 ret = regmap_update_bits(rv3032->regmap, RV3032_STATUS,
271 RV3032_STATUS_PORF | RV3032_STATUS_VLF, 0);
272
273 return ret;
274}
275
276static int rv3032_get_alarm(struct device *dev, struct rtc_wkalrm *alrm)
277{
278 struct rv3032_data *rv3032 = dev_get_drvdata(dev);
279 u8 alarmvals[3];
280 int status, ctrl, ret;
281
282 ret = regmap_bulk_read(rv3032->regmap, RV3032_ALARM_MIN, alarmvals,
283 sizeof(alarmvals));
284 if (ret)
285 return ret;
286
287 ret = regmap_read(rv3032->regmap, RV3032_STATUS, &status);
288 if (ret < 0)
289 return ret;
290
291 ret = regmap_read(rv3032->regmap, RV3032_CTRL2, &ctrl);
292 if (ret < 0)
293 return ret;
294
295 alrm->time.tm_sec = 0;
296 alrm->time.tm_min = bcd2bin(alarmvals[0] & 0x7f);
297 alrm->time.tm_hour = bcd2bin(alarmvals[1] & 0x3f);
298 alrm->time.tm_mday = bcd2bin(alarmvals[2] & 0x3f);
299
300 alrm->enabled = !!(ctrl & RV3032_CTRL2_AIE);
301 alrm->pending = (status & RV3032_STATUS_AF) && alrm->enabled;
302
303 return 0;
304}
305
306static int rv3032_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
307{
308 struct rv3032_data *rv3032 = dev_get_drvdata(dev);
309 u8 alarmvals[3];
310 u8 ctrl = 0;
311 int ret;
312
313 ret = regmap_update_bits(rv3032->regmap, RV3032_CTRL2,
314 RV3032_CTRL2_AIE | RV3032_CTRL2_UIE, 0);
315 if (ret)
316 return ret;
317
318 alarmvals[0] = bin2bcd(alrm->time.tm_min);
319 alarmvals[1] = bin2bcd(alrm->time.tm_hour);
320 alarmvals[2] = bin2bcd(alrm->time.tm_mday);
321
322 ret = regmap_update_bits(rv3032->regmap, RV3032_STATUS,
323 RV3032_STATUS_AF, 0);
324 if (ret)
325 return ret;
326
327 ret = regmap_bulk_write(rv3032->regmap, RV3032_ALARM_MIN, alarmvals,
328 sizeof(alarmvals));
329 if (ret)
330 return ret;
331
332 if (alrm->enabled) {
333 if (rv3032->rtc->uie_rtctimer.enabled)
334 ctrl |= RV3032_CTRL2_UIE;
335 if (rv3032->rtc->aie_timer.enabled)
336 ctrl |= RV3032_CTRL2_AIE;
337 }
338
339 ret = regmap_update_bits(rv3032->regmap, RV3032_CTRL2,
340 RV3032_CTRL2_UIE | RV3032_CTRL2_AIE, ctrl);
341
342 return ret;
343}
344
345static int rv3032_alarm_irq_enable(struct device *dev, unsigned int enabled)
346{
347 struct rv3032_data *rv3032 = dev_get_drvdata(dev);
348 int ctrl = 0, ret;
349
350 if (enabled) {
351 if (rv3032->rtc->uie_rtctimer.enabled)
352 ctrl |= RV3032_CTRL2_UIE;
353 if (rv3032->rtc->aie_timer.enabled)
354 ctrl |= RV3032_CTRL2_AIE;
355 }
356
357 ret = regmap_update_bits(rv3032->regmap, RV3032_STATUS,
358 RV3032_STATUS_AF | RV3032_STATUS_UF, 0);
359 if (ret)
360 return ret;
361
362 ret = regmap_update_bits(rv3032->regmap, RV3032_CTRL2,
363 RV3032_CTRL2_UIE | RV3032_CTRL2_AIE, ctrl);
364 if (ret)
365 return ret;
366
367 return 0;
368}
369
370static int rv3032_read_offset(struct device *dev, long *offset)
371{
372 struct rv3032_data *rv3032 = dev_get_drvdata(dev);
373 int ret, value, steps;
374
375 ret = regmap_read(rv3032->regmap, RV3032_OFFSET, &value);
376 if (ret < 0)
377 return ret;
378
379 steps = FIELD_GET_SIGNED(RV3032_OFFSET_MSK, value);
380
381 *offset = DIV_ROUND_CLOSEST(steps * OFFSET_STEP_PPT, 1000);
382
383 return 0;
384}
385
386static int rv3032_set_offset(struct device *dev, long offset)
387{
388 struct rv3032_data *rv3032 = dev_get_drvdata(dev);
389
390 offset = clamp(offset, -7629L, 7391L) * 1000;
391 offset = DIV_ROUND_CLOSEST(offset, OFFSET_STEP_PPT);
392
393 return rv3032_update_cfg(rv3032, RV3032_OFFSET, RV3032_OFFSET_MSK,
394 FIELD_PREP(RV3032_OFFSET_MSK, offset));
395}
396
397static int rv3032_param_get(struct device *dev, struct rtc_param *param)
398{
399 struct rv3032_data *rv3032 = dev_get_drvdata(dev);
400 int ret;
401
402 switch(param->param) {
403 u32 value;
404
405 case RTC_PARAM_BACKUP_SWITCH_MODE:
406 ret = regmap_read(rv3032->regmap, RV3032_PMU, &value);
407 if (ret < 0)
408 return ret;
409
410 value = FIELD_GET(RV3032_PMU_BSM, value);
411
412 switch(value) {
413 case RV3032_PMU_BSM_DSM:
414 param->uvalue = RTC_BSM_DIRECT;
415 break;
416 case RV3032_PMU_BSM_LSM:
417 param->uvalue = RTC_BSM_LEVEL;
418 break;
419 default:
420 param->uvalue = RTC_BSM_DISABLED;
421 }
422
423 break;
424
425 default:
426 return -EINVAL;
427 }
428
429 return 0;
430}
431
432static int rv3032_param_set(struct device *dev, struct rtc_param *param)
433{
434 struct rv3032_data *rv3032 = dev_get_drvdata(dev);
435
436 switch(param->param) {
437 u8 mode;
438 case RTC_PARAM_BACKUP_SWITCH_MODE:
439 if (rv3032->trickle_charger_set)
440 return -EINVAL;
441
442 switch (param->uvalue) {
443 case RTC_BSM_DISABLED:
444 mode = 0;
445 break;
446 case RTC_BSM_DIRECT:
447 mode = RV3032_PMU_BSM_DSM;
448 break;
449 case RTC_BSM_LEVEL:
450 mode = RV3032_PMU_BSM_LSM;
451 break;
452 default:
453 return -EINVAL;
454 }
455
456 return rv3032_update_cfg(rv3032, RV3032_PMU, RV3032_PMU_BSM,
457 FIELD_PREP(RV3032_PMU_BSM, mode));
458
459 default:
460 return -EINVAL;
461 }
462
463 return 0;
464}
465
466static int rv3032_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
467{
468 struct rv3032_data *rv3032 = dev_get_drvdata(dev);
469 int status, val = 0, ret = 0;
470
471 switch (cmd) {
472 case RTC_VL_READ:
473 ret = regmap_read(rv3032->regmap, RV3032_STATUS, &status);
474 if (ret < 0)
475 return ret;
476
477 if (status & (RV3032_STATUS_PORF | RV3032_STATUS_VLF))
478 val = RTC_VL_DATA_INVALID;
479 return put_user(val, (unsigned int __user *)arg);
480
481 default:
482 return -ENOIOCTLCMD;
483 }
484}
485
486static int rv3032_nvram_write(void *priv, unsigned int offset, void *val, size_t bytes)
487{
488 return regmap_bulk_write(priv, RV3032_RAM1 + offset, val, bytes);
489}
490
491static int rv3032_nvram_read(void *priv, unsigned int offset, void *val, size_t bytes)
492{
493 return regmap_bulk_read(priv, RV3032_RAM1 + offset, val, bytes);
494}
495
496static int rv3032_eeprom_write(void *priv, unsigned int offset, void *val, size_t bytes)
497{
498 struct rv3032_data *rv3032 = priv;
499 u32 status, eerd;
500 int i, ret;
501 u8 *buf = val;
502
503 ret = rv3032_enter_eerd(rv3032, &eerd);
504 if (ret)
505 return ret;
506
507 for (i = 0; i < bytes; i++) {
508 ret = regmap_write(rv3032->regmap, RV3032_EEPROM_ADDR,
509 RV3032_EEPROM_USER + offset + i);
510 if (ret)
511 goto exit_eerd;
512
513 ret = regmap_write(rv3032->regmap, RV3032_EEPROM_DATA, buf[i]);
514 if (ret)
515 goto exit_eerd;
516
517 ret = regmap_write(rv3032->regmap, RV3032_EEPROM_CMD,
518 RV3032_EEPROM_CMD_WRITE);
519 if (ret)
520 goto exit_eerd;
521
522 usleep_range(RV3032_EEBUSY_POLL, RV3032_EEBUSY_TIMEOUT);
523
524 ret = regmap_read_poll_timeout(rv3032->regmap, RV3032_TLSB, status,
525 !(status & RV3032_TLSB_EEBUSY),
526 RV3032_EEBUSY_POLL, RV3032_EEBUSY_TIMEOUT);
527 if (ret)
528 goto exit_eerd;
529 }
530
531exit_eerd:
532 rv3032_exit_eerd(rv3032, eerd);
533
534 return ret;
535}
536
537static int rv3032_eeprom_read(void *priv, unsigned int offset, void *val, size_t bytes)
538{
539 struct rv3032_data *rv3032 = priv;
540 u32 status, eerd, data;
541 int i, ret;
542 u8 *buf = val;
543
544 ret = rv3032_enter_eerd(rv3032, &eerd);
545 if (ret)
546 return ret;
547
548 for (i = 0; i < bytes; i++) {
549 ret = regmap_write(rv3032->regmap, RV3032_EEPROM_ADDR,
550 RV3032_EEPROM_USER + offset + i);
551 if (ret)
552 goto exit_eerd;
553
554 ret = regmap_write(rv3032->regmap, RV3032_EEPROM_CMD,
555 RV3032_EEPROM_CMD_READ);
556 if (ret)
557 goto exit_eerd;
558
559 ret = regmap_read_poll_timeout(rv3032->regmap, RV3032_TLSB, status,
560 !(status & RV3032_TLSB_EEBUSY),
561 RV3032_EEBUSY_POLL, RV3032_EEBUSY_TIMEOUT);
562 if (ret)
563 goto exit_eerd;
564
565 ret = regmap_read(rv3032->regmap, RV3032_EEPROM_DATA, &data);
566 if (ret)
567 goto exit_eerd;
568 buf[i] = data;
569 }
570
571exit_eerd:
572 rv3032_exit_eerd(rv3032, eerd);
573
574 return ret;
575}
576
577static int rv3032_trickle_charger_setup(struct device *dev, struct rv3032_data *rv3032)
578{
579 u32 val, ohms, voltage;
580 int i;
581
582 val = FIELD_PREP(RV3032_PMU_TCM, 1) | FIELD_PREP(RV3032_PMU_BSM, RV3032_PMU_BSM_DSM);
583 if (!device_property_read_u32(dev, "trickle-voltage-millivolt", &voltage)) {
584 for (i = 0; i < ARRAY_SIZE(rv3032_trickle_voltages); i++)
585 if (voltage == rv3032_trickle_voltages[i])
586 break;
587 if (i < ARRAY_SIZE(rv3032_trickle_voltages))
588 val = FIELD_PREP(RV3032_PMU_TCM, i) |
589 FIELD_PREP(RV3032_PMU_BSM, RV3032_PMU_BSM_LSM);
590 }
591
592 if (device_property_read_u32(dev, "trickle-resistor-ohms", &ohms))
593 return 0;
594
595 for (i = 0; i < ARRAY_SIZE(rv3032_trickle_resistors); i++)
596 if (ohms == rv3032_trickle_resistors[i])
597 break;
598
599 if (i >= ARRAY_SIZE(rv3032_trickle_resistors)) {
600 dev_warn(dev, "invalid trickle resistor value\n");
601
602 return 0;
603 }
604
605 rv3032->trickle_charger_set = true;
606
607 return rv3032_update_cfg(rv3032, RV3032_PMU,
608 RV3032_PMU_TCR | RV3032_PMU_TCM | RV3032_PMU_BSM,
609 val | FIELD_PREP(RV3032_PMU_TCR, i));
610}
611
612#ifdef CONFIG_COMMON_CLK
613#define clkout_hw_to_rv3032(hw) container_of(hw, struct rv3032_data, clkout_hw)
614
615static int clkout_xtal_rates[] = {
616 32768,
617 1024,
618 64,
619 1,
620};
621
622#define RV3032_HFD_STEP 8192
623
624static unsigned long rv3032_clkout_recalc_rate(struct clk_hw *hw,
625 unsigned long parent_rate)
626{
627 int clkout, ret;
628 struct rv3032_data *rv3032 = clkout_hw_to_rv3032(hw);
629
630 ret = regmap_read(rv3032->regmap, RV3032_CLKOUT2, &clkout);
631 if (ret < 0)
632 return 0;
633
634 if (clkout & RV3032_CLKOUT2_OS) {
635 unsigned long rate = FIELD_GET(RV3032_CLKOUT2_HFD_MSK, clkout) << 8;
636
637 ret = regmap_read(rv3032->regmap, RV3032_CLKOUT1, &clkout);
638 if (ret < 0)
639 return 0;
640
641 rate += clkout + 1;
642
643 return rate * RV3032_HFD_STEP;
644 }
645
646 return clkout_xtal_rates[FIELD_GET(RV3032_CLKOUT2_FD_MSK, clkout)];
647}
648
649static int rv3032_clkout_determine_rate(struct clk_hw *hw,
650 struct clk_rate_request *req)
651{
652 int i, hfd;
653
654 if (req->rate < RV3032_HFD_STEP)
655 for (i = 0; i < ARRAY_SIZE(clkout_xtal_rates); i++)
656 if (clkout_xtal_rates[i] <= req->rate) {
657 req->rate = clkout_xtal_rates[i];
658
659 return 0;
660 }
661
662 hfd = DIV_ROUND_CLOSEST(req->rate, RV3032_HFD_STEP);
663
664 req->rate = RV3032_HFD_STEP * clamp(hfd, 0, 8192);
665
666 return 0;
667}
668
669static int rv3032_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
670 unsigned long parent_rate)
671{
672 struct rv3032_data *rv3032 = clkout_hw_to_rv3032(hw);
673 u32 status, eerd;
674 int i, hfd, ret;
675
676 for (i = 0; i < ARRAY_SIZE(clkout_xtal_rates); i++) {
677 if (clkout_xtal_rates[i] == rate) {
678 return rv3032_update_cfg(rv3032, RV3032_CLKOUT2, 0xff,
679 FIELD_PREP(RV3032_CLKOUT2_FD_MSK, i));
680 }
681 }
682
683 hfd = DIV_ROUND_CLOSEST(rate, RV3032_HFD_STEP);
684 hfd = clamp(hfd, 1, 8192) - 1;
685
686 ret = rv3032_enter_eerd(rv3032, &eerd);
687 if (ret)
688 return ret;
689
690 ret = regmap_write(rv3032->regmap, RV3032_CLKOUT1, hfd & 0xff);
691 if (ret)
692 goto exit_eerd;
693
694 ret = regmap_write(rv3032->regmap, RV3032_CLKOUT2, RV3032_CLKOUT2_OS |
695 FIELD_PREP(RV3032_CLKOUT2_HFD_MSK, hfd >> 8));
696 if (ret)
697 goto exit_eerd;
698
699 ret = regmap_write(rv3032->regmap, RV3032_EEPROM_CMD, RV3032_EEPROM_CMD_UPDATE);
700 if (ret)
701 goto exit_eerd;
702
703 usleep_range(46000, RV3032_EEBUSY_TIMEOUT);
704
705 ret = regmap_read_poll_timeout(rv3032->regmap, RV3032_TLSB, status,
706 !(status & RV3032_TLSB_EEBUSY),
707 RV3032_EEBUSY_POLL, RV3032_EEBUSY_TIMEOUT);
708
709exit_eerd:
710 rv3032_exit_eerd(rv3032, eerd);
711
712 return ret;
713}
714
715static int rv3032_clkout_prepare(struct clk_hw *hw)
716{
717 struct rv3032_data *rv3032 = clkout_hw_to_rv3032(hw);
718
719 return rv3032_update_cfg(rv3032, RV3032_PMU, RV3032_PMU_NCLKE, 0);
720}
721
722static void rv3032_clkout_unprepare(struct clk_hw *hw)
723{
724 struct rv3032_data *rv3032 = clkout_hw_to_rv3032(hw);
725
726 rv3032_update_cfg(rv3032, RV3032_PMU, RV3032_PMU_NCLKE, RV3032_PMU_NCLKE);
727}
728
729static int rv3032_clkout_is_prepared(struct clk_hw *hw)
730{
731 int val, ret;
732 struct rv3032_data *rv3032 = clkout_hw_to_rv3032(hw);
733
734 ret = regmap_read(rv3032->regmap, RV3032_PMU, &val);
735 if (ret < 0)
736 return ret;
737
738 return !(val & RV3032_PMU_NCLKE);
739}
740
741static const struct clk_ops rv3032_clkout_ops = {
742 .prepare = rv3032_clkout_prepare,
743 .unprepare = rv3032_clkout_unprepare,
744 .is_prepared = rv3032_clkout_is_prepared,
745 .recalc_rate = rv3032_clkout_recalc_rate,
746 .determine_rate = rv3032_clkout_determine_rate,
747 .set_rate = rv3032_clkout_set_rate,
748};
749
750static int rv3032_clkout_register_clk(struct rv3032_data *rv3032,
751 struct i2c_client *client)
752{
753 int ret;
754 struct clk *clk;
755 struct clk_init_data init = {};
756 struct device_node *node = client->dev.of_node;
757
758 ret = regmap_update_bits(rv3032->regmap, RV3032_TLSB, RV3032_TLSB_CLKF, 0);
759 if (ret < 0)
760 return ret;
761
762 ret = regmap_update_bits(rv3032->regmap, RV3032_CTRL2, RV3032_CTRL2_CLKIE, 0);
763 if (ret < 0)
764 return ret;
765
766 ret = regmap_write(rv3032->regmap, RV3032_CLK_IRQ, 0);
767 if (ret < 0)
768 return ret;
769
770 init.name = "rv3032-clkout";
771 init.ops = &rv3032_clkout_ops;
772 init.flags = 0;
773 init.parent_names = NULL;
774 init.num_parents = 0;
775 rv3032->clkout_hw.init = &init;
776
777 of_property_read_string(node, "clock-output-names", &init.name);
778
779 clk = devm_clk_register(&client->dev, &rv3032->clkout_hw);
780 if (!IS_ERR(clk))
781 of_clk_add_provider(node, of_clk_src_simple_get, clk);
782
783 return 0;
784}
785#endif
786
787static int rv3032_hwmon_read_temp(struct device *dev, long *mC)
788{
789 struct rv3032_data *rv3032 = dev_get_drvdata(dev);
790 u8 buf[2];
791 int temp, prev = 0;
792 int ret;
793
794 ret = regmap_bulk_read(rv3032->regmap, RV3032_TLSB, buf, sizeof(buf));
795 if (ret)
796 return ret;
797
798 temp = sign_extend32(buf[1], 7) << 4;
799 temp |= FIELD_GET(RV3032_TLSB_TEMP, buf[0]);
800
801 /* No blocking or shadowing on RV3032_TLSB and RV3032_TMSB */
802 do {
803 prev = temp;
804
805 ret = regmap_bulk_read(rv3032->regmap, RV3032_TLSB, buf, sizeof(buf));
806 if (ret)
807 return ret;
808
809 temp = sign_extend32(buf[1], 7) << 4;
810 temp |= FIELD_GET(RV3032_TLSB_TEMP, buf[0]);
811 } while (temp != prev);
812
813 *mC = (temp * 1000) / 16;
814
815 return 0;
816}
817
818static umode_t rv3032_hwmon_is_visible(const void *data, enum hwmon_sensor_types type,
819 u32 attr, int channel)
820{
821 if (type != hwmon_temp)
822 return 0;
823
824 switch (attr) {
825 case hwmon_temp_input:
826 return 0444;
827 default:
828 return 0;
829 }
830}
831
832static int rv3032_hwmon_read(struct device *dev, enum hwmon_sensor_types type,
833 u32 attr, int channel, long *temp)
834{
835 int err;
836
837 switch (attr) {
838 case hwmon_temp_input:
839 err = rv3032_hwmon_read_temp(dev, temp);
840 break;
841 default:
842 err = -EOPNOTSUPP;
843 break;
844 }
845
846 return err;
847}
848
849static const struct hwmon_channel_info * const rv3032_hwmon_info[] = {
850 HWMON_CHANNEL_INFO(chip, HWMON_C_REGISTER_TZ),
851 HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST),
852 NULL
853};
854
855static const struct hwmon_ops rv3032_hwmon_hwmon_ops = {
856 .is_visible = rv3032_hwmon_is_visible,
857 .read = rv3032_hwmon_read,
858};
859
860static const struct hwmon_chip_info rv3032_hwmon_chip_info = {
861 .ops = &rv3032_hwmon_hwmon_ops,
862 .info = rv3032_hwmon_info,
863};
864
865static void rv3032_hwmon_register(struct device *dev)
866{
867 struct rv3032_data *rv3032 = dev_get_drvdata(dev);
868
869 if (!IS_REACHABLE(CONFIG_HWMON))
870 return;
871
872 devm_hwmon_device_register_with_info(dev, "rv3032", rv3032, &rv3032_hwmon_chip_info, NULL);
873}
874
875static const struct rtc_class_ops rv3032_rtc_ops = {
876 .read_time = rv3032_get_time,
877 .set_time = rv3032_set_time,
878 .read_offset = rv3032_read_offset,
879 .set_offset = rv3032_set_offset,
880 .ioctl = rv3032_ioctl,
881 .read_alarm = rv3032_get_alarm,
882 .set_alarm = rv3032_set_alarm,
883 .alarm_irq_enable = rv3032_alarm_irq_enable,
884 .param_get = rv3032_param_get,
885 .param_set = rv3032_param_set,
886};
887
888static const struct regmap_config regmap_config = {
889 .reg_bits = 8,
890 .val_bits = 8,
891 .max_register = 0xCA,
892};
893
894static int rv3032_probe(struct i2c_client *client)
895{
896 struct rv3032_data *rv3032;
897 int ret, status;
898 struct nvmem_config nvmem_cfg = {
899 .name = "rv3032_nvram",
900 .word_size = 1,
901 .stride = 1,
902 .size = 16,
903 .type = NVMEM_TYPE_BATTERY_BACKED,
904 .reg_read = rv3032_nvram_read,
905 .reg_write = rv3032_nvram_write,
906 };
907 struct nvmem_config eeprom_cfg = {
908 .name = "rv3032_eeprom",
909 .word_size = 1,
910 .stride = 1,
911 .size = 32,
912 .type = NVMEM_TYPE_EEPROM,
913 .reg_read = rv3032_eeprom_read,
914 .reg_write = rv3032_eeprom_write,
915 };
916
917 rv3032 = devm_kzalloc(&client->dev, sizeof(struct rv3032_data),
918 GFP_KERNEL);
919 if (!rv3032)
920 return -ENOMEM;
921
922 rv3032->regmap = devm_regmap_init_i2c(client, &regmap_config);
923 if (IS_ERR(rv3032->regmap))
924 return PTR_ERR(rv3032->regmap);
925
926 i2c_set_clientdata(client, rv3032);
927
928 ret = regmap_read(rv3032->regmap, RV3032_STATUS, &status);
929 if (ret < 0)
930 return ret;
931
932 rv3032->rtc = devm_rtc_allocate_device(&client->dev);
933 if (IS_ERR(rv3032->rtc))
934 return PTR_ERR(rv3032->rtc);
935
936 if (client->irq > 0) {
937 unsigned long irqflags = IRQF_TRIGGER_LOW;
938
939 if (dev_fwnode(&client->dev))
940 irqflags = 0;
941
942 ret = devm_request_threaded_irq(&client->dev, client->irq,
943 NULL, rv3032_handle_irq,
944 irqflags | IRQF_ONESHOT,
945 "rv3032", rv3032);
946 if (ret) {
947 dev_warn(&client->dev, "unable to request IRQ, alarms disabled\n");
948 client->irq = 0;
949 }
950 }
951 if (!client->irq)
952 clear_bit(RTC_FEATURE_ALARM, rv3032->rtc->features);
953
954 rv3032_trickle_charger_setup(&client->dev, rv3032);
955
956 set_bit(RTC_FEATURE_BACKUP_SWITCH_MODE, rv3032->rtc->features);
957 set_bit(RTC_FEATURE_ALARM_RES_MINUTE, rv3032->rtc->features);
958
959 rv3032->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
960 rv3032->rtc->range_max = RTC_TIMESTAMP_END_2099;
961 rv3032->rtc->ops = &rv3032_rtc_ops;
962 ret = devm_rtc_register_device(rv3032->rtc);
963 if (ret)
964 return ret;
965
966 nvmem_cfg.priv = rv3032->regmap;
967 devm_rtc_nvmem_register(rv3032->rtc, &nvmem_cfg);
968 eeprom_cfg.priv = rv3032;
969 devm_rtc_nvmem_register(rv3032->rtc, &eeprom_cfg);
970
971#ifdef CONFIG_COMMON_CLK
972 rv3032_clkout_register_clk(rv3032, client);
973#endif
974
975 rv3032_hwmon_register(&client->dev);
976
977 return 0;
978}
979
980static const struct acpi_device_id rv3032_i2c_acpi_match[] = {
981 { "MCRY3032" },
982 { }
983};
984MODULE_DEVICE_TABLE(acpi, rv3032_i2c_acpi_match);
985
986static const __maybe_unused struct of_device_id rv3032_of_match[] = {
987 { .compatible = "microcrystal,rv3032", },
988 { }
989};
990MODULE_DEVICE_TABLE(of, rv3032_of_match);
991
992static struct i2c_driver rv3032_driver = {
993 .driver = {
994 .name = "rtc-rv3032",
995 .acpi_match_table = rv3032_i2c_acpi_match,
996 .of_match_table = of_match_ptr(rv3032_of_match),
997 },
998 .probe = rv3032_probe,
999};
1000module_i2c_driver(rv3032_driver);
1001
1002MODULE_AUTHOR("Alexandre Belloni <[email protected]>");
1003MODULE_DESCRIPTION("Micro Crystal RV3032 RTC driver");
1004MODULE_LICENSE("GPL v2");