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1// SPDX-License-Identifier: GPL-2.0+
2//
3// Copyright (c) 2013-2014 Samsung Electronics Co., Ltd
4// http://www.samsung.com
5//
6// Copyright (C) 2013 Google, Inc
7
8#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
10#include <linux/module.h>
11#include <linux/i2c.h>
12#include <linux/bcd.h>
13#include <linux/reboot.h>
14#include <linux/regmap.h>
15#include <linux/rtc.h>
16#include <linux/platform_device.h>
17#include <linux/mfd/samsung/core.h>
18#include <linux/mfd/samsung/rtc.h>
19#include <linux/mfd/samsung/s2mps14.h>
20
21/*
22 * Maximum number of retries for checking changes in UDR field
23 * of S5M_RTC_UDR_CON register (to limit possible endless loop).
24 *
25 * After writing to RTC registers (setting time or alarm) read the UDR field
26 * in S5M_RTC_UDR_CON register. UDR is auto-cleared when data have
27 * been transferred.
28 */
29#define UDR_READ_RETRY_CNT 5
30
31enum {
32 RTC_SEC = 0,
33 RTC_MIN,
34 RTC_HOUR,
35 RTC_WEEKDAY,
36 RTC_DATE,
37 RTC_MONTH,
38 RTC_YEAR1,
39 RTC_YEAR2,
40 /* Make sure this is always the last enum name. */
41 RTC_MAX_NUM_TIME_REGS
42};
43
44/*
45 * Registers used by the driver which are different between chipsets.
46 *
47 * Operations like read time and write alarm/time require updating
48 * specific fields in UDR register. These fields usually are auto-cleared
49 * (with some exceptions).
50 *
51 * Table of operations per device:
52 *
53 * Device | Write time | Read time | Write alarm
54 * =================================================
55 * S5M8767 | UDR + TIME | | UDR
56 * S2MPG10 | WUDR | RUDR | AUDR
57 * S2MPS11/14 | WUDR | RUDR | WUDR + RUDR
58 * S2MPS13 | WUDR | RUDR | WUDR + AUDR
59 * S2MPS15 | WUDR | RUDR | AUDR
60 */
61struct s5m_rtc_reg_config {
62 /* Number of registers used for setting time/alarm0/alarm1 */
63 unsigned int regs_count;
64 /* First register for time, seconds */
65 unsigned int time;
66 /* RTC control register */
67 unsigned int ctrl;
68 /* First register for alarm 0, seconds */
69 unsigned int alarm0;
70 /* First register for alarm 1, seconds */
71 unsigned int alarm1;
72 /*
73 * Register for update flag (UDR). Typically setting UDR field to 1
74 * will enable update of time or alarm register. Then it will be
75 * auto-cleared after successful update.
76 */
77 unsigned int udr_update;
78 /* Auto-cleared mask in UDR field for writing time and alarm */
79 unsigned int autoclear_udr_mask;
80 /*
81 * Masks in UDR field for time and alarm operations.
82 * The read time mask can be 0. Rest should not.
83 */
84 unsigned int read_time_udr_mask;
85 unsigned int write_time_udr_mask;
86 unsigned int write_alarm_udr_mask;
87};
88
89/* Register map for S5M8767 */
90static const struct s5m_rtc_reg_config s5m_rtc_regs = {
91 .regs_count = 8,
92 .time = S5M_RTC_SEC,
93 .ctrl = S5M_ALARM1_CONF,
94 .alarm0 = S5M_ALARM0_SEC,
95 .alarm1 = S5M_ALARM1_SEC,
96 .udr_update = S5M_RTC_UDR_CON,
97 .autoclear_udr_mask = S5M_RTC_UDR_MASK,
98 .read_time_udr_mask = 0, /* Not needed */
99 .write_time_udr_mask = S5M_RTC_UDR_MASK | S5M_RTC_TIME_EN_MASK,
100 .write_alarm_udr_mask = S5M_RTC_UDR_MASK,
101};
102
103/* Register map for S2MPG10 */
104static const struct s5m_rtc_reg_config s2mpg10_rtc_regs = {
105 .regs_count = 7,
106 .time = S2MPG10_RTC_SEC,
107 .ctrl = S2MPG10_RTC_CTRL,
108 .alarm0 = S2MPG10_RTC_A0SEC,
109 .alarm1 = S2MPG10_RTC_A1SEC,
110 .udr_update = S2MPG10_RTC_UPDATE,
111 .autoclear_udr_mask = S2MPS15_RTC_WUDR_MASK | S2MPS15_RTC_AUDR_MASK,
112 .read_time_udr_mask = S2MPS_RTC_RUDR_MASK,
113 .write_time_udr_mask = S2MPS15_RTC_WUDR_MASK,
114 .write_alarm_udr_mask = S2MPS15_RTC_AUDR_MASK,
115};
116
117/* Register map for S2MPS13 */
118static const struct s5m_rtc_reg_config s2mps13_rtc_regs = {
119 .regs_count = 7,
120 .time = S2MPS_RTC_SEC,
121 .ctrl = S2MPS_RTC_CTRL,
122 .alarm0 = S2MPS_ALARM0_SEC,
123 .alarm1 = S2MPS_ALARM1_SEC,
124 .udr_update = S2MPS_RTC_UDR_CON,
125 .autoclear_udr_mask = S2MPS_RTC_WUDR_MASK,
126 .read_time_udr_mask = S2MPS_RTC_RUDR_MASK,
127 .write_time_udr_mask = S2MPS_RTC_WUDR_MASK,
128 .write_alarm_udr_mask = S2MPS_RTC_WUDR_MASK | S2MPS13_RTC_AUDR_MASK,
129};
130
131/* Register map for S2MPS11/14 */
132static const struct s5m_rtc_reg_config s2mps14_rtc_regs = {
133 .regs_count = 7,
134 .time = S2MPS_RTC_SEC,
135 .ctrl = S2MPS_RTC_CTRL,
136 .alarm0 = S2MPS_ALARM0_SEC,
137 .alarm1 = S2MPS_ALARM1_SEC,
138 .udr_update = S2MPS_RTC_UDR_CON,
139 .autoclear_udr_mask = S2MPS_RTC_WUDR_MASK,
140 .read_time_udr_mask = S2MPS_RTC_RUDR_MASK,
141 .write_time_udr_mask = S2MPS_RTC_WUDR_MASK,
142 .write_alarm_udr_mask = S2MPS_RTC_WUDR_MASK | S2MPS_RTC_RUDR_MASK,
143};
144
145/*
146 * Register map for S2MPS15 - in comparison to S2MPS14 the WUDR and AUDR bits
147 * are swapped.
148 */
149static const struct s5m_rtc_reg_config s2mps15_rtc_regs = {
150 .regs_count = 7,
151 .time = S2MPS_RTC_SEC,
152 .ctrl = S2MPS_RTC_CTRL,
153 .alarm0 = S2MPS_ALARM0_SEC,
154 .alarm1 = S2MPS_ALARM1_SEC,
155 .udr_update = S2MPS_RTC_UDR_CON,
156 .autoclear_udr_mask = S2MPS_RTC_WUDR_MASK,
157 .read_time_udr_mask = S2MPS_RTC_RUDR_MASK,
158 .write_time_udr_mask = S2MPS15_RTC_WUDR_MASK,
159 .write_alarm_udr_mask = S2MPS15_RTC_AUDR_MASK,
160};
161
162struct s5m_rtc_info {
163 struct device *dev;
164 struct sec_pmic_dev *s5m87xx;
165 struct regmap *regmap;
166 struct rtc_device *rtc_dev;
167 int irq;
168 enum sec_device_type device_type;
169 int rtc_24hr_mode;
170 const struct s5m_rtc_reg_config *regs;
171};
172
173static const struct regmap_config s5m_rtc_regmap_config = {
174 .reg_bits = 8,
175 .val_bits = 8,
176
177 .max_register = S5M_RTC_REG_MAX,
178};
179
180static const struct regmap_config s2mps14_rtc_regmap_config = {
181 .reg_bits = 8,
182 .val_bits = 8,
183
184 .max_register = S2MPS_RTC_REG_MAX,
185};
186
187static void s5m8767_data_to_tm(u8 *data, struct rtc_time *tm,
188 int rtc_24hr_mode)
189{
190 tm->tm_sec = data[RTC_SEC] & 0x7f;
191 tm->tm_min = data[RTC_MIN] & 0x7f;
192 if (rtc_24hr_mode) {
193 tm->tm_hour = data[RTC_HOUR] & 0x1f;
194 } else {
195 tm->tm_hour = data[RTC_HOUR] & 0x0f;
196 if (data[RTC_HOUR] & HOUR_PM_MASK)
197 tm->tm_hour += 12;
198 }
199
200 tm->tm_wday = ffs(data[RTC_WEEKDAY] & 0x7f);
201 tm->tm_mday = data[RTC_DATE] & 0x1f;
202 tm->tm_mon = (data[RTC_MONTH] & 0x0f) - 1;
203 tm->tm_year = (data[RTC_YEAR1] & 0x7f) + 100;
204 tm->tm_yday = 0;
205 tm->tm_isdst = 0;
206}
207
208static int s5m8767_tm_to_data(struct rtc_time *tm, u8 *data)
209{
210 data[RTC_SEC] = tm->tm_sec;
211 data[RTC_MIN] = tm->tm_min;
212
213 if (tm->tm_hour >= 12)
214 data[RTC_HOUR] = tm->tm_hour | HOUR_PM_MASK;
215 else
216 data[RTC_HOUR] = tm->tm_hour & ~HOUR_PM_MASK;
217
218 data[RTC_WEEKDAY] = 1 << tm->tm_wday;
219 data[RTC_DATE] = tm->tm_mday;
220 data[RTC_MONTH] = tm->tm_mon + 1;
221 data[RTC_YEAR1] = tm->tm_year - 100;
222
223 return 0;
224}
225
226/*
227 * Read RTC_UDR_CON register and wait till UDR field is cleared.
228 * This indicates that time/alarm update ended.
229 */
230static int s5m8767_wait_for_udr_update(struct s5m_rtc_info *info)
231{
232 int ret, retry = UDR_READ_RETRY_CNT;
233 unsigned int data;
234
235 do {
236 ret = regmap_read(info->regmap, info->regs->udr_update, &data);
237 } while (--retry && (data & info->regs->autoclear_udr_mask) && !ret);
238
239 if (!retry)
240 dev_err(info->dev, "waiting for UDR update, reached max number of retries\n");
241
242 return ret;
243}
244
245static int s5m_check_pending_alarm_interrupt(struct s5m_rtc_info *info,
246 struct rtc_wkalrm *alarm)
247{
248 int ret;
249 unsigned int val;
250
251 switch (info->device_type) {
252 case S5M8767X:
253 ret = regmap_read(info->regmap, S5M_RTC_STATUS, &val);
254 val &= S5M_ALARM0_STATUS;
255 break;
256 case S2MPG10:
257 case S2MPS15X:
258 case S2MPS14X:
259 case S2MPS13X:
260 ret = regmap_read(info->s5m87xx->regmap_pmic, S2MPS14_REG_ST2,
261 &val);
262 val &= S2MPS_ALARM0_STATUS;
263 break;
264 default:
265 return -EINVAL;
266 }
267 if (ret < 0)
268 return ret;
269
270 if (val)
271 alarm->pending = 1;
272 else
273 alarm->pending = 0;
274
275 return 0;
276}
277
278static int s5m8767_rtc_set_time_reg(struct s5m_rtc_info *info)
279{
280 int ret;
281
282 ret = regmap_set_bits(info->regmap, info->regs->udr_update,
283 info->regs->write_time_udr_mask);
284 if (ret < 0) {
285 dev_err(info->dev, "failed to write update reg(%d)\n", ret);
286 return ret;
287 }
288
289 ret = s5m8767_wait_for_udr_update(info);
290
291 return ret;
292}
293
294static int s5m8767_rtc_set_alarm_reg(struct s5m_rtc_info *info)
295{
296 int ret;
297 unsigned int udr_mask;
298
299 udr_mask = info->regs->write_alarm_udr_mask;
300 switch (info->device_type) {
301 case S5M8767X:
302 udr_mask |= S5M_RTC_TIME_EN_MASK;
303 break;
304 case S2MPG10:
305 case S2MPS15X:
306 case S2MPS14X:
307 case S2MPS13X:
308 /* No exceptions needed */
309 break;
310 default:
311 return -EINVAL;
312 }
313
314 ret = regmap_update_bits(info->regmap, info->regs->udr_update,
315 udr_mask, info->regs->write_alarm_udr_mask);
316 if (ret < 0) {
317 dev_err(info->dev, "%s: fail to write update reg(%d)\n",
318 __func__, ret);
319 return ret;
320 }
321
322 ret = s5m8767_wait_for_udr_update(info);
323
324 /* On S2MPS13 the AUDR is not auto-cleared */
325 if (info->device_type == S2MPS13X)
326 regmap_clear_bits(info->regmap, info->regs->udr_update,
327 S2MPS13_RTC_AUDR_MASK);
328
329 return ret;
330}
331
332static int s5m_rtc_read_time(struct device *dev, struct rtc_time *tm)
333{
334 struct s5m_rtc_info *info = dev_get_drvdata(dev);
335 u8 data[RTC_MAX_NUM_TIME_REGS];
336 int ret;
337
338 if (info->regs->read_time_udr_mask) {
339 ret = regmap_set_bits(info->regmap, info->regs->udr_update,
340 info->regs->read_time_udr_mask);
341 if (ret) {
342 dev_err(dev,
343 "Failed to prepare registers for time reading: %d\n",
344 ret);
345 return ret;
346 }
347 }
348 ret = regmap_bulk_read(info->regmap, info->regs->time, data,
349 info->regs->regs_count);
350 if (ret < 0)
351 return ret;
352
353 switch (info->device_type) {
354 case S5M8767X:
355 case S2MPG10:
356 case S2MPS15X:
357 case S2MPS14X:
358 case S2MPS13X:
359 s5m8767_data_to_tm(data, tm, info->rtc_24hr_mode);
360 break;
361
362 default:
363 return -EINVAL;
364 }
365
366 dev_dbg(dev, "%s: %ptR(%d)\n", __func__, tm, tm->tm_wday);
367
368 return 0;
369}
370
371static int s5m_rtc_set_time(struct device *dev, struct rtc_time *tm)
372{
373 struct s5m_rtc_info *info = dev_get_drvdata(dev);
374 u8 data[RTC_MAX_NUM_TIME_REGS];
375 int ret = 0;
376
377 switch (info->device_type) {
378 case S5M8767X:
379 case S2MPG10:
380 case S2MPS15X:
381 case S2MPS14X:
382 case S2MPS13X:
383 ret = s5m8767_tm_to_data(tm, data);
384 break;
385 default:
386 return -EINVAL;
387 }
388
389 if (ret < 0)
390 return ret;
391
392 dev_dbg(dev, "%s: %ptR(%d)\n", __func__, tm, tm->tm_wday);
393
394 ret = regmap_raw_write(info->regmap, info->regs->time, data,
395 info->regs->regs_count);
396 if (ret < 0)
397 return ret;
398
399 ret = s5m8767_rtc_set_time_reg(info);
400
401 return ret;
402}
403
404static int s5m_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
405{
406 struct s5m_rtc_info *info = dev_get_drvdata(dev);
407 u8 data[RTC_MAX_NUM_TIME_REGS];
408 int ret, i;
409
410 ret = regmap_bulk_read(info->regmap, info->regs->alarm0, data,
411 info->regs->regs_count);
412 if (ret < 0)
413 return ret;
414
415 switch (info->device_type) {
416 case S5M8767X:
417 case S2MPG10:
418 case S2MPS15X:
419 case S2MPS14X:
420 case S2MPS13X:
421 s5m8767_data_to_tm(data, &alrm->time, info->rtc_24hr_mode);
422 alrm->enabled = 0;
423 for (i = 0; i < info->regs->regs_count; i++) {
424 if (data[i] & ALARM_ENABLE_MASK) {
425 alrm->enabled = 1;
426 break;
427 }
428 }
429 break;
430
431 default:
432 return -EINVAL;
433 }
434
435 dev_dbg(dev, "%s: %ptR(%d)\n", __func__, &alrm->time, alrm->time.tm_wday);
436
437 return s5m_check_pending_alarm_interrupt(info, alrm);
438}
439
440static int s5m_rtc_stop_alarm(struct s5m_rtc_info *info)
441{
442 u8 data[RTC_MAX_NUM_TIME_REGS];
443 int ret, i;
444 struct rtc_time tm;
445
446 ret = regmap_bulk_read(info->regmap, info->regs->alarm0, data,
447 info->regs->regs_count);
448 if (ret < 0)
449 return ret;
450
451 s5m8767_data_to_tm(data, &tm, info->rtc_24hr_mode);
452 dev_dbg(info->dev, "%s: %ptR(%d)\n", __func__, &tm, tm.tm_wday);
453
454 switch (info->device_type) {
455 case S5M8767X:
456 case S2MPG10:
457 case S2MPS15X:
458 case S2MPS14X:
459 case S2MPS13X:
460 for (i = 0; i < info->regs->regs_count; i++)
461 data[i] &= ~ALARM_ENABLE_MASK;
462
463 ret = regmap_raw_write(info->regmap, info->regs->alarm0, data,
464 info->regs->regs_count);
465 if (ret < 0)
466 return ret;
467
468 ret = s5m8767_rtc_set_alarm_reg(info);
469
470 break;
471
472 default:
473 return -EINVAL;
474 }
475
476 return ret;
477}
478
479static int s5m_rtc_start_alarm(struct s5m_rtc_info *info)
480{
481 int ret;
482 u8 data[RTC_MAX_NUM_TIME_REGS];
483 struct rtc_time tm;
484
485 ret = regmap_bulk_read(info->regmap, info->regs->alarm0, data,
486 info->regs->regs_count);
487 if (ret < 0)
488 return ret;
489
490 s5m8767_data_to_tm(data, &tm, info->rtc_24hr_mode);
491 dev_dbg(info->dev, "%s: %ptR(%d)\n", __func__, &tm, tm.tm_wday);
492
493 switch (info->device_type) {
494 case S5M8767X:
495 case S2MPG10:
496 case S2MPS15X:
497 case S2MPS14X:
498 case S2MPS13X:
499 data[RTC_SEC] |= ALARM_ENABLE_MASK;
500 data[RTC_MIN] |= ALARM_ENABLE_MASK;
501 data[RTC_HOUR] |= ALARM_ENABLE_MASK;
502 data[RTC_WEEKDAY] &= ~ALARM_ENABLE_MASK;
503 if (data[RTC_DATE] & 0x1f)
504 data[RTC_DATE] |= ALARM_ENABLE_MASK;
505 if (data[RTC_MONTH] & 0xf)
506 data[RTC_MONTH] |= ALARM_ENABLE_MASK;
507 if (data[RTC_YEAR1] & 0x7f)
508 data[RTC_YEAR1] |= ALARM_ENABLE_MASK;
509
510 ret = regmap_raw_write(info->regmap, info->regs->alarm0, data,
511 info->regs->regs_count);
512 if (ret < 0)
513 return ret;
514 ret = s5m8767_rtc_set_alarm_reg(info);
515
516 break;
517
518 default:
519 return -EINVAL;
520 }
521
522 return ret;
523}
524
525static int s5m_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
526{
527 struct s5m_rtc_info *info = dev_get_drvdata(dev);
528 u8 data[RTC_MAX_NUM_TIME_REGS];
529 int ret;
530
531 switch (info->device_type) {
532 case S5M8767X:
533 case S2MPG10:
534 case S2MPS15X:
535 case S2MPS14X:
536 case S2MPS13X:
537 s5m8767_tm_to_data(&alrm->time, data);
538 break;
539
540 default:
541 return -EINVAL;
542 }
543
544 dev_dbg(dev, "%s: %ptR(%d)\n", __func__, &alrm->time, alrm->time.tm_wday);
545
546 ret = s5m_rtc_stop_alarm(info);
547 if (ret < 0)
548 return ret;
549
550 ret = regmap_raw_write(info->regmap, info->regs->alarm0, data,
551 info->regs->regs_count);
552 if (ret < 0)
553 return ret;
554
555 ret = s5m8767_rtc_set_alarm_reg(info);
556 if (ret < 0)
557 return ret;
558
559 if (alrm->enabled)
560 ret = s5m_rtc_start_alarm(info);
561
562 return ret;
563}
564
565static int s5m_rtc_alarm_irq_enable(struct device *dev,
566 unsigned int enabled)
567{
568 struct s5m_rtc_info *info = dev_get_drvdata(dev);
569
570 if (enabled)
571 return s5m_rtc_start_alarm(info);
572 else
573 return s5m_rtc_stop_alarm(info);
574}
575
576static irqreturn_t s5m_rtc_alarm_irq(int irq, void *data)
577{
578 struct s5m_rtc_info *info = data;
579
580 rtc_update_irq(info->rtc_dev, 1, RTC_IRQF | RTC_AF);
581
582 return IRQ_HANDLED;
583}
584
585static const struct rtc_class_ops s5m_rtc_ops = {
586 .read_time = s5m_rtc_read_time,
587 .set_time = s5m_rtc_set_time,
588 .read_alarm = s5m_rtc_read_alarm,
589 .set_alarm = s5m_rtc_set_alarm,
590 .alarm_irq_enable = s5m_rtc_alarm_irq_enable,
591};
592
593static int s5m8767_rtc_init_reg(struct s5m_rtc_info *info)
594{
595 u8 data[2];
596 int ret;
597
598 switch (info->device_type) {
599 case S5M8767X:
600 /* UDR update time. Default of 7.32 ms is too long. */
601 ret = regmap_update_bits(info->regmap, S5M_RTC_UDR_CON,
602 S5M_RTC_UDR_T_MASK, S5M_RTC_UDR_T_450_US);
603 if (ret < 0)
604 dev_err(info->dev, "%s: fail to change UDR time: %d\n",
605 __func__, ret);
606
607 /* Set RTC control register : Binary mode, 24hour mode */
608 data[0] = (1 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT);
609 data[1] = (0 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT);
610
611 ret = regmap_raw_write(info->regmap, S5M_ALARM0_CONF, data, 2);
612 break;
613
614 case S2MPG10:
615 case S2MPS15X:
616 case S2MPS14X:
617 case S2MPS13X:
618 data[0] = (0 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT);
619 ret = regmap_write(info->regmap, info->regs->ctrl, data[0]);
620 if (ret < 0)
621 break;
622
623 /*
624 * Should set WUDR & (RUDR or AUDR) bits to high after writing
625 * RTC_CTRL register like writing Alarm registers. We can't find
626 * the description from datasheet but vendor code does that
627 * really.
628 */
629 ret = s5m8767_rtc_set_alarm_reg(info);
630 break;
631
632 default:
633 return -EINVAL;
634 }
635
636 info->rtc_24hr_mode = 1;
637 if (ret < 0)
638 return dev_err_probe(info->dev, ret,
639 "%s: fail to write controlm reg\n",
640 __func__);
641
642 return ret;
643}
644
645static int s5m_rtc_restart_s2mpg10(struct sys_off_data *data)
646{
647 struct s5m_rtc_info *info = data->cb_data;
648 int ret;
649
650 if (data->mode != REBOOT_COLD && data->mode != REBOOT_HARD)
651 return NOTIFY_DONE;
652
653 /*
654 * Arm watchdog with maximum timeout (2 seconds), and perform full reset
655 * on expiry.
656 */
657 ret = regmap_set_bits(info->regmap, S2MPG10_RTC_WTSR,
658 (S2MPG10_WTSR_COLDTIMER | S2MPG10_WTSR_COLDRST
659 | S2MPG10_WTSR_WTSRT | S2MPG10_WTSR_WTSR_EN));
660
661 return ret ? NOTIFY_BAD : NOTIFY_DONE;
662}
663
664static int s5m_rtc_probe(struct platform_device *pdev)
665{
666 struct sec_pmic_dev *s5m87xx = dev_get_drvdata(pdev->dev.parent);
667 enum sec_device_type device_type =
668 platform_get_device_id(pdev)->driver_data;
669 struct s5m_rtc_info *info;
670 int ret, alarm_irq;
671
672 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
673 if (!info)
674 return -ENOMEM;
675
676 info->regmap = dev_get_regmap(pdev->dev.parent, "rtc");
677 if (!info->regmap) {
678 const struct regmap_config *regmap_cfg;
679 struct i2c_client *i2c;
680
681 switch (device_type) {
682 case S2MPS15X:
683 regmap_cfg = &s2mps14_rtc_regmap_config;
684 info->regs = &s2mps15_rtc_regs;
685 break;
686 case S2MPS14X:
687 regmap_cfg = &s2mps14_rtc_regmap_config;
688 info->regs = &s2mps14_rtc_regs;
689 break;
690 case S2MPS13X:
691 regmap_cfg = &s2mps14_rtc_regmap_config;
692 info->regs = &s2mps13_rtc_regs;
693 break;
694 case S5M8767X:
695 regmap_cfg = &s5m_rtc_regmap_config;
696 info->regs = &s5m_rtc_regs;
697 break;
698 default:
699 return dev_err_probe(&pdev->dev, -ENODEV,
700 "Unsupported device type %d\n",
701 device_type);
702 }
703
704 i2c = devm_i2c_new_dummy_device(&pdev->dev,
705 s5m87xx->i2c->adapter,
706 RTC_I2C_ADDR);
707 if (IS_ERR(i2c))
708 return dev_err_probe(&pdev->dev, PTR_ERR(i2c),
709 "Failed to allocate I2C\n");
710
711 info->regmap = devm_regmap_init_i2c(i2c, regmap_cfg);
712 if (IS_ERR(info->regmap))
713 return dev_err_probe(&pdev->dev, PTR_ERR(info->regmap),
714 "Failed to allocate regmap\n");
715 } else if (device_type == S2MPG10) {
716 info->regs = &s2mpg10_rtc_regs;
717 } else {
718 return dev_err_probe(&pdev->dev, -ENODEV,
719 "Unsupported device type %d\n",
720 device_type);
721 }
722
723 info->dev = &pdev->dev;
724 info->s5m87xx = s5m87xx;
725 info->device_type = device_type;
726
727 alarm_irq = platform_get_irq_byname_optional(pdev, "alarm");
728 if (alarm_irq > 0)
729 info->irq = alarm_irq;
730 else if (alarm_irq == -ENXIO)
731 info->irq = 0;
732 else
733 return dev_err_probe(&pdev->dev, alarm_irq ? : -EINVAL,
734 "IRQ 'alarm' not found\n");
735
736 platform_set_drvdata(pdev, info);
737
738 ret = s5m8767_rtc_init_reg(info);
739 if (ret)
740 return ret;
741
742 info->rtc_dev = devm_rtc_allocate_device(&pdev->dev);
743 if (IS_ERR(info->rtc_dev))
744 return PTR_ERR(info->rtc_dev);
745
746 info->rtc_dev->ops = &s5m_rtc_ops;
747
748 info->rtc_dev->range_min = RTC_TIMESTAMP_BEGIN_2000;
749 info->rtc_dev->range_max = RTC_TIMESTAMP_END_2099;
750
751 if (!info->irq) {
752 clear_bit(RTC_FEATURE_ALARM, info->rtc_dev->features);
753 } else {
754 ret = devm_request_threaded_irq(&pdev->dev, info->irq, NULL,
755 s5m_rtc_alarm_irq, 0, "rtc-alarm0",
756 info);
757 if (ret < 0)
758 return dev_err_probe(&pdev->dev, ret,
759 "Failed to request alarm IRQ %d\n",
760 info->irq);
761
762 ret = devm_device_init_wakeup(&pdev->dev);
763 if (ret < 0)
764 return dev_err_probe(&pdev->dev, ret,
765 "Failed to init wakeup\n");
766 }
767
768 if (of_device_is_system_power_controller(pdev->dev.parent->of_node) &&
769 info->device_type == S2MPG10) {
770 ret = devm_register_sys_off_handler(&pdev->dev,
771 SYS_OFF_MODE_RESTART,
772 SYS_OFF_PRIO_HIGH + 1,
773 s5m_rtc_restart_s2mpg10,
774 info);
775 if (ret)
776 return dev_err_probe(&pdev->dev, ret,
777 "Failed to register restart handler\n");
778 }
779
780 return devm_rtc_register_device(info->rtc_dev);
781}
782
783#ifdef CONFIG_PM_SLEEP
784static int s5m_rtc_resume(struct device *dev)
785{
786 struct s5m_rtc_info *info = dev_get_drvdata(dev);
787 int ret = 0;
788
789 if (info->irq && device_may_wakeup(dev))
790 ret = disable_irq_wake(info->irq);
791
792 return ret;
793}
794
795static int s5m_rtc_suspend(struct device *dev)
796{
797 struct s5m_rtc_info *info = dev_get_drvdata(dev);
798 int ret = 0;
799
800 if (info->irq && device_may_wakeup(dev))
801 ret = enable_irq_wake(info->irq);
802
803 return ret;
804}
805#endif /* CONFIG_PM_SLEEP */
806
807static SIMPLE_DEV_PM_OPS(s5m_rtc_pm_ops, s5m_rtc_suspend, s5m_rtc_resume);
808
809static const struct platform_device_id s5m_rtc_id[] = {
810 { .name = "s5m-rtc", .driver_data = S5M8767X },
811 { .name = "s2mpg10-rtc", .driver_data = S2MPG10 },
812 { .name = "s2mps13-rtc", .driver_data = S2MPS13X },
813 { .name = "s2mps14-rtc", .driver_data = S2MPS14X },
814 { .name = "s2mps15-rtc", .driver_data = S2MPS15X },
815 { }
816};
817MODULE_DEVICE_TABLE(platform, s5m_rtc_id);
818
819static struct platform_driver s5m_rtc_driver = {
820 .driver = {
821 .name = "s5m-rtc",
822 .pm = &s5m_rtc_pm_ops,
823 },
824 .probe = s5m_rtc_probe,
825 .id_table = s5m_rtc_id,
826};
827
828module_platform_driver(s5m_rtc_driver);
829
830/* Module information */
831MODULE_AUTHOR("Sangbeom Kim <[email protected]>");
832MODULE_DESCRIPTION("Samsung S5M/S2MPS14 RTC driver");
833MODULE_LICENSE("GPL");