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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * RTC driver for tps6594 PMIC
4 *
5 * Copyright (C) 2023 BayLibre Incorporated - https://www.baylibre.com/
6 */
7
8#include <linux/bcd.h>
9#include <linux/errno.h>
10#include <linux/init.h>
11#include <linux/interrupt.h>
12#include <linux/kernel.h>
13#include <linux/limits.h>
14#include <linux/math64.h>
15#include <linux/module.h>
16#include <linux/platform_device.h>
17#include <linux/property.h>
18#include <linux/rtc.h>
19#include <linux/types.h>
20#include <linux/units.h>
21
22#include <linux/mfd/tps6594.h>
23
24// Total number of RTC registers needed to set time
25#define NUM_TIME_REGS (TPS6594_REG_RTC_WEEKS - TPS6594_REG_RTC_SECONDS + 1)
26
27// Total number of RTC alarm registers
28#define NUM_TIME_ALARM_REGS (NUM_TIME_REGS - 1)
29
30/*
31 * Min and max values supported by 'offset' interface (swapped sign).
32 * After conversion, the values do not exceed the range [-32767, 33767]
33 * which COMP_REG must conform to.
34 */
35#define MIN_OFFSET (-277774)
36#define MAX_OFFSET (277774)
37
38// Number of ticks per hour
39#define TICKS_PER_HOUR (32768 * 3600LL)
40
41// Multiplier for ppb conversions
42#define PPB_MULT NANO
43
44struct tps6594_rtc {
45 struct rtc_device *rtc_dev;
46 int irq;
47};
48
49static int tps6594_rtc_alarm_irq_enable(struct device *dev,
50 unsigned int enabled)
51{
52 struct tps6594 *tps = dev_get_drvdata(dev->parent);
53 u8 val;
54
55 val = enabled ? TPS6594_BIT_IT_ALARM : 0;
56
57 return regmap_update_bits(tps->regmap, TPS6594_REG_RTC_INTERRUPTS,
58 TPS6594_BIT_IT_ALARM, val);
59}
60
61/* Pulse GET_TIME field of RTC_CTRL_1 to store a timestamp in shadow registers. */
62static int tps6594_rtc_shadow_timestamp(struct device *dev, struct tps6594 *tps)
63{
64 int ret;
65
66 /*
67 * Set GET_TIME to 0. Next time we set GET_TIME to 1 we will be sure to store
68 * an up-to-date timestamp.
69 */
70 ret = regmap_clear_bits(tps->regmap, TPS6594_REG_RTC_CTRL_1,
71 TPS6594_BIT_GET_TIME);
72 if (ret < 0)
73 return ret;
74
75 /*
76 * Copy content of RTC registers to shadow registers or latches to read
77 * a coherent timestamp.
78 */
79 return regmap_set_bits(tps->regmap, TPS6594_REG_RTC_CTRL_1,
80 TPS6594_BIT_GET_TIME);
81}
82
83static int tps6594_rtc_read_time(struct device *dev, struct rtc_time *tm)
84{
85 unsigned char rtc_data[NUM_TIME_REGS];
86 struct tps6594 *tps = dev_get_drvdata(dev->parent);
87 int ret;
88
89 // Check if RTC is running.
90 ret = regmap_test_bits(tps->regmap, TPS6594_REG_RTC_STATUS,
91 TPS6594_BIT_RUN);
92 if (ret < 0)
93 return ret;
94 if (ret == 0)
95 return -EINVAL;
96
97 ret = tps6594_rtc_shadow_timestamp(dev, tps);
98 if (ret < 0)
99 return ret;
100
101 // Read shadowed RTC registers.
102 ret = regmap_bulk_read(tps->regmap, TPS6594_REG_RTC_SECONDS, rtc_data,
103 NUM_TIME_REGS);
104 if (ret < 0)
105 return ret;
106
107 tm->tm_sec = bcd2bin(rtc_data[0]);
108 tm->tm_min = bcd2bin(rtc_data[1]);
109 tm->tm_hour = bcd2bin(rtc_data[2]);
110 tm->tm_mday = bcd2bin(rtc_data[3]);
111 tm->tm_mon = bcd2bin(rtc_data[4]) - 1;
112 tm->tm_year = bcd2bin(rtc_data[5]) + 100;
113 tm->tm_wday = bcd2bin(rtc_data[6]);
114
115 return 0;
116}
117
118static int tps6594_rtc_set_time(struct device *dev, struct rtc_time *tm)
119{
120 unsigned char rtc_data[NUM_TIME_REGS];
121 struct tps6594 *tps = dev_get_drvdata(dev->parent);
122 int ret;
123
124 rtc_data[0] = bin2bcd(tm->tm_sec);
125 rtc_data[1] = bin2bcd(tm->tm_min);
126 rtc_data[2] = bin2bcd(tm->tm_hour);
127 rtc_data[3] = bin2bcd(tm->tm_mday);
128 rtc_data[4] = bin2bcd(tm->tm_mon + 1);
129 rtc_data[5] = bin2bcd(tm->tm_year - 100);
130 rtc_data[6] = bin2bcd(tm->tm_wday);
131
132 // Stop RTC while updating the RTC time registers.
133 ret = regmap_clear_bits(tps->regmap, TPS6594_REG_RTC_CTRL_1,
134 TPS6594_BIT_STOP_RTC);
135 if (ret < 0)
136 return ret;
137
138 // Update all the time registers in one shot.
139 ret = regmap_bulk_write(tps->regmap, TPS6594_REG_RTC_SECONDS, rtc_data,
140 NUM_TIME_REGS);
141 if (ret < 0)
142 return ret;
143
144 // Start back RTC.
145 return regmap_set_bits(tps->regmap, TPS6594_REG_RTC_CTRL_1,
146 TPS6594_BIT_STOP_RTC);
147}
148
149static int tps6594_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
150{
151 unsigned char alarm_data[NUM_TIME_ALARM_REGS];
152 u32 int_val;
153 struct tps6594 *tps = dev_get_drvdata(dev->parent);
154 int ret;
155
156 ret = regmap_bulk_read(tps->regmap, TPS6594_REG_ALARM_SECONDS,
157 alarm_data, NUM_TIME_ALARM_REGS);
158 if (ret < 0)
159 return ret;
160
161 alm->time.tm_sec = bcd2bin(alarm_data[0]);
162 alm->time.tm_min = bcd2bin(alarm_data[1]);
163 alm->time.tm_hour = bcd2bin(alarm_data[2]);
164 alm->time.tm_mday = bcd2bin(alarm_data[3]);
165 alm->time.tm_mon = bcd2bin(alarm_data[4]) - 1;
166 alm->time.tm_year = bcd2bin(alarm_data[5]) + 100;
167
168 ret = regmap_read(tps->regmap, TPS6594_REG_RTC_INTERRUPTS, &int_val);
169 if (ret < 0)
170 return ret;
171
172 alm->enabled = int_val & TPS6594_BIT_IT_ALARM;
173
174 return 0;
175}
176
177static int tps6594_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
178{
179 unsigned char alarm_data[NUM_TIME_ALARM_REGS];
180 struct tps6594 *tps = dev_get_drvdata(dev->parent);
181 int ret;
182
183 // Disable alarm irq before changing the alarm timestamp.
184 ret = tps6594_rtc_alarm_irq_enable(dev, 0);
185 if (ret)
186 return ret;
187
188 alarm_data[0] = bin2bcd(alm->time.tm_sec);
189 alarm_data[1] = bin2bcd(alm->time.tm_min);
190 alarm_data[2] = bin2bcd(alm->time.tm_hour);
191 alarm_data[3] = bin2bcd(alm->time.tm_mday);
192 alarm_data[4] = bin2bcd(alm->time.tm_mon + 1);
193 alarm_data[5] = bin2bcd(alm->time.tm_year - 100);
194
195 // Update all the alarm registers in one shot.
196 ret = regmap_bulk_write(tps->regmap, TPS6594_REG_ALARM_SECONDS,
197 alarm_data, NUM_TIME_ALARM_REGS);
198 if (ret < 0)
199 return ret;
200
201 if (alm->enabled)
202 ret = tps6594_rtc_alarm_irq_enable(dev, 1);
203
204 return ret;
205}
206
207static int tps6594_rtc_set_calibration(struct device *dev, int calibration)
208{
209 struct tps6594 *tps = dev_get_drvdata(dev->parent);
210 __le16 value;
211 int ret;
212
213 /*
214 * TPS6594 uses two's complement 16 bit value for compensation of RTC
215 * crystal inaccuracies. One time every hour when seconds counter
216 * increments from 0 to 1 compensation value will be added to internal
217 * RTC counter value.
218 *
219 * Valid range for compensation value: [-32767 .. 32767].
220 */
221 if (calibration < S16_MIN + 1 || calibration > S16_MAX)
222 return -ERANGE;
223
224 value = cpu_to_le16(calibration);
225
226 // Update all the compensation registers in one shot.
227 ret = regmap_bulk_write(tps->regmap, TPS6594_REG_RTC_COMP_LSB, &value,
228 sizeof(value));
229 if (ret < 0)
230 return ret;
231
232 // Enable automatic compensation.
233 return regmap_set_bits(tps->regmap, TPS6594_REG_RTC_CTRL_1,
234 TPS6594_BIT_AUTO_COMP);
235}
236
237static int tps6594_rtc_get_calibration(struct device *dev, int *calibration)
238{
239 struct tps6594 *tps = dev_get_drvdata(dev->parent);
240 unsigned int ctrl;
241 __le16 value;
242 int ret;
243
244 ret = regmap_read(tps->regmap, TPS6594_REG_RTC_CTRL_1, &ctrl);
245 if (ret < 0)
246 return ret;
247
248 // If automatic compensation is not enabled report back zero.
249 if (!(ctrl & TPS6594_BIT_AUTO_COMP)) {
250 *calibration = 0;
251 return 0;
252 }
253
254 ret = regmap_bulk_read(tps->regmap, TPS6594_REG_RTC_COMP_LSB, &value,
255 sizeof(value));
256 if (ret < 0)
257 return ret;
258
259 *calibration = le16_to_cpu(value);
260
261 return 0;
262}
263
264static int tps6594_rtc_read_offset(struct device *dev, long *offset)
265{
266 int calibration;
267 s64 tmp;
268 int ret;
269
270 ret = tps6594_rtc_get_calibration(dev, &calibration);
271 if (ret < 0)
272 return ret;
273
274 // Convert from RTC calibration register format to ppb format.
275 tmp = calibration * PPB_MULT;
276
277 if (tmp < 0)
278 tmp -= TICKS_PER_HOUR / 2LL;
279 else
280 tmp += TICKS_PER_HOUR / 2LL;
281 tmp = div_s64(tmp, TICKS_PER_HOUR);
282
283 /*
284 * SAFETY:
285 * Computatiion is the reverse operation of the one done in
286 * `tps6594_rtc_set_offset`. The safety remarks applie here too.
287 */
288
289 /*
290 * Offset value operates in negative way, so swap sign.
291 * See 8.3.10.5, (32768 - COMP_REG).
292 */
293 *offset = (long)-tmp;
294
295 return 0;
296}
297
298static int tps6594_rtc_set_offset(struct device *dev, long offset)
299{
300 int calibration;
301 s64 tmp;
302
303 // Make sure offset value is within supported range.
304 if (offset < MIN_OFFSET || offset > MAX_OFFSET)
305 return -ERANGE;
306
307 // Convert from ppb format to RTC calibration register format.
308
309 tmp = offset * TICKS_PER_HOUR;
310 if (tmp < 0)
311 tmp -= PPB_MULT / 2LL;
312 else
313 tmp += PPB_MULT / 2LL;
314 tmp = div_s64(tmp, PPB_MULT);
315
316 /*
317 * SAFETY:
318 * - tmp = offset * TICK_PER_HOUR :
319 * `offset` can't be more than 277774, so `tmp` can't exceed 277774000000000
320 * which is lower than the maximum value in an `s64` (2^63-1). No overflow here.
321 *
322 * - tmp += TICK_PER_HOUR / 2LL :
323 * tmp will have a maximum value of 277774117964800 which is still inferior to 2^63-1.
324 */
325
326 // Offset value operates in negative way, so swap sign.
327 calibration = (int)-tmp;
328
329 return tps6594_rtc_set_calibration(dev, calibration);
330}
331
332static irqreturn_t tps6594_rtc_interrupt(int irq, void *data)
333{
334 struct device *dev = data;
335 struct tps6594 *tps = dev_get_drvdata(dev->parent);
336 struct tps6594_rtc *rtc = dev_get_drvdata(dev);
337 int ret;
338 u32 rtc_reg;
339
340 ret = regmap_read(tps->regmap, TPS6594_REG_RTC_STATUS, &rtc_reg);
341 if (ret)
342 return IRQ_NONE;
343
344 rtc_update_irq(rtc->rtc_dev, 1, RTC_IRQF | RTC_AF);
345
346 return IRQ_HANDLED;
347}
348
349static const struct rtc_class_ops tps6594_rtc_ops = {
350 .read_time = tps6594_rtc_read_time,
351 .set_time = tps6594_rtc_set_time,
352 .read_alarm = tps6594_rtc_read_alarm,
353 .set_alarm = tps6594_rtc_set_alarm,
354 .alarm_irq_enable = tps6594_rtc_alarm_irq_enable,
355 .read_offset = tps6594_rtc_read_offset,
356 .set_offset = tps6594_rtc_set_offset,
357};
358
359static int tps6594_rtc_probe(struct platform_device *pdev)
360{
361 struct tps6594 *tps = dev_get_drvdata(pdev->dev.parent);
362 struct device *dev = &pdev->dev;
363 struct tps6594_rtc *rtc;
364 int irq;
365 int ret;
366
367 rtc = devm_kzalloc(dev, sizeof(*rtc), GFP_KERNEL);
368 if (!rtc)
369 return -ENOMEM;
370
371 rtc->rtc_dev = devm_rtc_allocate_device(dev);
372 if (IS_ERR(rtc->rtc_dev))
373 return PTR_ERR(rtc->rtc_dev);
374
375 // Enable crystal oscillator.
376 ret = regmap_set_bits(tps->regmap, TPS6594_REG_RTC_CTRL_2,
377 TPS6594_BIT_XTAL_EN);
378 if (ret < 0)
379 return ret;
380
381 ret = regmap_test_bits(tps->regmap, TPS6594_REG_RTC_STATUS,
382 TPS6594_BIT_RUN);
383 if (ret < 0)
384 return ret;
385 // RTC not running.
386 if (ret == 0) {
387 ret = regmap_set_bits(tps->regmap, TPS6594_REG_RTC_CTRL_1,
388 TPS6594_BIT_STOP_RTC);
389 if (ret < 0)
390 return ret;
391
392 /*
393 * On some boards, a 40 ms delay is needed before BIT_RUN is set.
394 * 80 ms should provide sufficient margin.
395 */
396 mdelay(80);
397
398 /*
399 * RTC should be running now. Check if this is the case.
400 * If not it might be a missing oscillator.
401 */
402 ret = regmap_test_bits(tps->regmap, TPS6594_REG_RTC_STATUS,
403 TPS6594_BIT_RUN);
404 if (ret < 0)
405 return ret;
406 if (ret == 0)
407 return -ENODEV;
408
409 // Stop RTC until first call to `tps6594_rtc_set_time`.
410 ret = regmap_clear_bits(tps->regmap, TPS6594_REG_RTC_CTRL_1,
411 TPS6594_BIT_STOP_RTC);
412 if (ret < 0)
413 return ret;
414 }
415
416 platform_set_drvdata(pdev, rtc);
417
418 irq = platform_get_irq_byname(pdev, TPS6594_IRQ_NAME_ALARM);
419 if (irq < 0)
420 return dev_err_probe(dev, irq, "Failed to get irq\n");
421
422 rtc->irq = irq;
423
424 ret = devm_request_threaded_irq(dev, irq, NULL, tps6594_rtc_interrupt,
425 IRQF_ONESHOT, TPS6594_IRQ_NAME_ALARM,
426 dev);
427 if (ret < 0)
428 return dev_err_probe(dev, ret,
429 "Failed to request_threaded_irq\n");
430
431 ret = device_init_wakeup(dev, true);
432 if (ret < 0)
433 return dev_err_probe(dev, ret,
434 "Failed to init rtc as wakeup source\n");
435
436 rtc->rtc_dev->ops = &tps6594_rtc_ops;
437 rtc->rtc_dev->range_min = RTC_TIMESTAMP_BEGIN_2000;
438 rtc->rtc_dev->range_max = RTC_TIMESTAMP_END_2099;
439
440 return devm_rtc_register_device(rtc->rtc_dev);
441}
442
443static int tps6594_rtc_resume(struct device *dev)
444{
445 struct tps6594 *tps = dev_get_drvdata(dev->parent);
446 struct tps6594_rtc *rtc = dev_get_drvdata(dev);
447 int ret;
448
449 ret = regmap_test_bits(tps->regmap, TPS6594_REG_INT_STARTUP,
450 TPS6594_BIT_RTC_INT);
451 if (ret < 0) {
452 dev_err(dev, "failed to read REG_INT_STARTUP: %d\n", ret);
453 goto out;
454 }
455
456 if (ret > 0) {
457 /*
458 * If the alarm bit is set, it means that the IRQ has been
459 * fired. But, the kernel may not have woke up yet when it
460 * happened. So, we have to clear it.
461 */
462 ret = regmap_write(tps->regmap, TPS6594_REG_RTC_STATUS,
463 TPS6594_BIT_ALARM);
464 if (ret < 0)
465 dev_err(dev, "error clearing alarm bit: %d", ret);
466
467 rtc_update_irq(rtc->rtc_dev, 1, RTC_IRQF | RTC_AF);
468 }
469out:
470 disable_irq_wake(rtc->irq);
471
472 return 0;
473}
474
475static int tps6594_rtc_suspend(struct device *dev)
476{
477 struct tps6594_rtc *rtc = dev_get_drvdata(dev);
478
479 enable_irq_wake(rtc->irq);
480
481 return 0;
482}
483
484static DEFINE_SIMPLE_DEV_PM_OPS(tps6594_rtc_pm_ops, tps6594_rtc_suspend, tps6594_rtc_resume);
485
486static const struct platform_device_id tps6594_rtc_id_table[] = {
487 { .name = "tps6594-rtc" },
488 { }
489};
490MODULE_DEVICE_TABLE(platform, tps6594_rtc_id_table);
491
492static struct platform_driver tps6594_rtc_driver = {
493 .probe = tps6594_rtc_probe,
494 .driver = {
495 .name = "tps6594-rtc",
496 .pm = pm_sleep_ptr(&tps6594_rtc_pm_ops),
497 },
498 .id_table = tps6594_rtc_id_table,
499};
500
501module_platform_driver(tps6594_rtc_driver);
502MODULE_AUTHOR("Esteban Blanc <[email protected]>");
503MODULE_DESCRIPTION("TPS6594 RTC driver");
504MODULE_LICENSE("GPL");