projects/linux·blob master · refs

422 lines · 10.9 KiB

1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Xilinx Zynq Ultrascale+ MPSoC Real Time Clock Driver
4 *
5 * Copyright (C) 2015 Xilinx, Inc.
6 *
7 */
8
9#include <linux/clk.h>
10#include <linux/delay.h>
11#include <linux/init.h>
12#include <linux/io.h>
13#include <linux/module.h>
14#include <linux/of.h>
15#include <linux/platform_device.h>
16#include <linux/rtc.h>
17
18/* RTC Registers */
19#define RTC_SET_TM_WR 0x00
20#define RTC_SET_TM_RD 0x04
21#define RTC_CALIB_WR 0x08
22#define RTC_CALIB_RD 0x0C
23#define RTC_CUR_TM 0x10
24#define RTC_CUR_TICK 0x14
25#define RTC_ALRM 0x18
26#define RTC_INT_STS 0x20
27#define RTC_INT_MASK 0x24
28#define RTC_INT_EN 0x28
29#define RTC_INT_DIS 0x2C
30#define RTC_CTRL 0x40
31
32#define RTC_FR_EN BIT(20)
33#define RTC_FR_DATSHIFT 16
34#define RTC_TICK_MASK 0xFFFF
35#define RTC_INT_SEC BIT(0)
36#define RTC_INT_ALRM BIT(1)
37#define RTC_OSC_EN BIT(24)
38#define RTC_BATT_EN BIT(31)
39
40#define RTC_CALIB_DEF 0x7FFF
41#define RTC_CALIB_MASK 0x1FFFFF
42#define RTC_ALRM_MASK BIT(1)
43#define RTC_MSEC 1000
44#define RTC_FR_MASK 0xF0000
45#define RTC_FR_MAX_TICKS 16
46#define RTC_PPB 1000000000
47
48struct xlnx_rtc_dev {
49 struct rtc_device *rtc;
50 void __iomem *reg_base;
51 int alarm_irq;
52 int sec_irq;
53 struct clk *rtc_clk;
54 unsigned int freq;
55};
56
57static int xlnx_rtc_set_time(struct device *dev, struct rtc_time *tm)
58{
59 struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
60 unsigned long new_time;
61
62 /*
63 * The value written will be updated after 1 sec into the
64 * seconds read register, so we need to program time +1 sec
65 * to get the correct time on read.
66 */
67 new_time = rtc_tm_to_time64(tm) + 1;
68
69 writel(new_time, xrtcdev->reg_base + RTC_SET_TM_WR);
70
71 /*
72 * Clear the rtc interrupt status register after setting the
73 * time. During a read_time function, the code should read the
74 * RTC_INT_STATUS register and if bit 0 is still 0, it means
75 * that one second has not elapsed yet since RTC was set and
76 * the current time should be read from SET_TIME_READ register;
77 * otherwise, CURRENT_TIME register is read to report the time
78 */
79 writel(RTC_INT_SEC, xrtcdev->reg_base + RTC_INT_STS);
80
81 return 0;
82}
83
84static int xlnx_rtc_read_time(struct device *dev, struct rtc_time *tm)
85{
86 u32 status;
87 unsigned long read_time;
88 struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
89
90 status = readl(xrtcdev->reg_base + RTC_INT_STS);
91
92 if (status & RTC_INT_SEC) {
93 /*
94 * RTC has updated the CURRENT_TIME with the time written into
95 * SET_TIME_WRITE register.
96 */
97 read_time = readl(xrtcdev->reg_base + RTC_CUR_TM);
98 } else {
99 /*
100 * Time written in SET_TIME_WRITE has not yet updated into
101 * the seconds read register, so read the time from the
102 * SET_TIME_WRITE instead of CURRENT_TIME register.
103 * Since we add +1 sec while writing, we need to -1 sec while
104 * reading.
105 */
106 read_time = readl(xrtcdev->reg_base + RTC_SET_TM_RD) - 1;
107 }
108 rtc_time64_to_tm(read_time, tm);
109
110 return 0;
111}
112
113static int xlnx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
114{
115 struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
116
117 rtc_time64_to_tm(readl(xrtcdev->reg_base + RTC_ALRM), &alrm->time);
118 alrm->enabled = readl(xrtcdev->reg_base + RTC_INT_MASK) & RTC_INT_ALRM;
119
120 return 0;
121}
122
123static int xlnx_rtc_alarm_irq_enable(struct device *dev, u32 enabled)
124{
125 struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
126 unsigned int status;
127 ulong timeout;
128
129 timeout = jiffies + msecs_to_jiffies(RTC_MSEC);
130
131 if (enabled) {
132 while (1) {
133 status = readl(xrtcdev->reg_base + RTC_INT_STS);
134 if (!((status & RTC_ALRM_MASK) == RTC_ALRM_MASK))
135 break;
136
137 if (time_after_eq(jiffies, timeout)) {
138 dev_err(dev, "Time out occur, while clearing alarm status bit\n");
139 return -ETIMEDOUT;
140 }
141 writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_STS);
142 }
143
144 writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_EN);
145 } else {
146 writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_DIS);
147 }
148
149 return 0;
150}
151
152static int xlnx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
153{
154 struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
155 unsigned long alarm_time;
156
157 alarm_time = rtc_tm_to_time64(&alrm->time);
158
159 writel((u32)alarm_time, (xrtcdev->reg_base + RTC_ALRM));
160
161 xlnx_rtc_alarm_irq_enable(dev, alrm->enabled);
162
163 return 0;
164}
165
166static void xlnx_init_rtc(struct xlnx_rtc_dev *xrtcdev)
167{
168 u32 rtc_ctrl;
169
170 /* Enable RTC switch to battery when VCC_PSAUX is not available */
171 rtc_ctrl = readl(xrtcdev->reg_base + RTC_CTRL);
172 rtc_ctrl |= RTC_BATT_EN;
173 writel(rtc_ctrl, xrtcdev->reg_base + RTC_CTRL);
174}
175
176static int xlnx_rtc_read_offset(struct device *dev, long *offset)
177{
178 struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
179 unsigned int calibval, fract_data, fract_part;
180 int freq = xrtcdev->freq;
181 int max_tick, tick_mult;
182 long offset_val;
183
184 /* Tick to offset multiplier */
185 tick_mult = DIV_ROUND_CLOSEST(RTC_PPB, freq);
186
187 calibval = readl(xrtcdev->reg_base + RTC_CALIB_RD);
188 /* Offset with seconds ticks */
189 max_tick = calibval & RTC_TICK_MASK;
190 offset_val = max_tick - freq;
191 /* Convert to ppb */
192 offset_val *= tick_mult;
193
194 /* Offset with fractional ticks */
195 if (calibval & RTC_FR_EN) {
196 fract_data = (calibval & RTC_FR_MASK) >> RTC_FR_DATSHIFT;
197 fract_part = DIV_ROUND_UP(tick_mult, RTC_FR_MAX_TICKS);
198 offset_val += (fract_part * fract_data);
199 }
200
201 *offset = offset_val;
202
203 return 0;
204}
205
206static int xlnx_rtc_set_offset(struct device *dev, long offset)
207{
208 struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
209 int max_tick, tick_mult, fract_offset, fract_part;
210 int freq = xrtcdev->freq;
211 unsigned int calibval;
212 int fract_data = 0;
213
214 /* Tick to offset multiplier */
215 tick_mult = DIV_ROUND_CLOSEST(RTC_PPB, freq);
216
217 /* Number ticks for given offset */
218 max_tick = div_s64_rem(offset, tick_mult, &fract_offset);
219
220 if (freq + max_tick > RTC_TICK_MASK || (freq + max_tick < 1))
221 return -ERANGE;
222
223 /* Number fractional ticks for given offset */
224 if (fract_offset) {
225 fract_part = DIV_ROUND_UP(tick_mult, RTC_FR_MAX_TICKS);
226 fract_data = fract_offset / fract_part;
227 /* Subtract one from max_tick while adding fract_offset */
228 if (fract_offset < 0 && fract_data) {
229 max_tick--;
230 fract_data += RTC_FR_MAX_TICKS;
231 }
232 }
233
234 /* Zynqmp RTC uses second and fractional tick
235 * counters for compensation
236 */
237 calibval = max_tick + freq;
238
239 if (fract_data)
240 calibval |= (RTC_FR_EN | (fract_data << RTC_FR_DATSHIFT));
241
242 writel(calibval, (xrtcdev->reg_base + RTC_CALIB_WR));
243
244 return 0;
245}
246
247static const struct rtc_class_ops xlnx_rtc_ops = {
248 .set_time = xlnx_rtc_set_time,
249 .read_time = xlnx_rtc_read_time,
250 .read_alarm = xlnx_rtc_read_alarm,
251 .set_alarm = xlnx_rtc_set_alarm,
252 .alarm_irq_enable = xlnx_rtc_alarm_irq_enable,
253 .read_offset = xlnx_rtc_read_offset,
254 .set_offset = xlnx_rtc_set_offset,
255};
256
257static irqreturn_t xlnx_rtc_interrupt(int irq, void *id)
258{
259 struct xlnx_rtc_dev *xrtcdev = (struct xlnx_rtc_dev *)id;
260 unsigned int status;
261
262 status = readl(xrtcdev->reg_base + RTC_INT_STS);
263 /* Check if interrupt asserted */
264 if (!(status & (RTC_INT_SEC | RTC_INT_ALRM)))
265 return IRQ_NONE;
266
267 /* Disable RTC_INT_ALRM interrupt only */
268 writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_DIS);
269
270 if (status & RTC_INT_ALRM)
271 rtc_update_irq(xrtcdev->rtc, 1, RTC_IRQF | RTC_AF);
272
273 return IRQ_HANDLED;
274}
275
276static int xlnx_rtc_probe(struct platform_device *pdev)
277{
278 struct xlnx_rtc_dev *xrtcdev;
279 bool is_alarm_set = false;
280 u32 pending_alrm_irq;
281 u32 current_time;
282 u32 alarm_time;
283 int ret;
284
285 xrtcdev = devm_kzalloc(&pdev->dev, sizeof(*xrtcdev), GFP_KERNEL);
286 if (!xrtcdev)
287 return -ENOMEM;
288
289 platform_set_drvdata(pdev, xrtcdev);
290
291 xrtcdev->rtc = devm_rtc_allocate_device(&pdev->dev);
292 if (IS_ERR(xrtcdev->rtc))
293 return PTR_ERR(xrtcdev->rtc);
294
295 xrtcdev->rtc->ops = &xlnx_rtc_ops;
296 xrtcdev->rtc->range_max = U32_MAX;
297
298 xrtcdev->reg_base = devm_platform_ioremap_resource(pdev, 0);
299 if (IS_ERR(xrtcdev->reg_base))
300 return PTR_ERR(xrtcdev->reg_base);
301
302 /* Clear any pending alarm interrupts from previous kernel/boot */
303 pending_alrm_irq = readl(xrtcdev->reg_base + RTC_INT_STS) & RTC_INT_ALRM;
304 if (pending_alrm_irq)
305 writel(pending_alrm_irq, xrtcdev->reg_base + RTC_INT_STS);
306
307 /* Check if a valid alarm is already set from previous kernel/boot */
308 alarm_time = readl(xrtcdev->reg_base + RTC_ALRM);
309 current_time = readl(xrtcdev->reg_base + RTC_CUR_TM);
310 if (alarm_time > current_time && alarm_time != 0)
311 is_alarm_set = true;
312
313 xrtcdev->alarm_irq = platform_get_irq_byname(pdev, "alarm");
314 if (xrtcdev->alarm_irq < 0)
315 return xrtcdev->alarm_irq;
316 ret = devm_request_irq(&pdev->dev, xrtcdev->alarm_irq,
317 xlnx_rtc_interrupt, 0,
318 dev_name(&pdev->dev), xrtcdev);
319 if (ret) {
320 dev_err(&pdev->dev, "request irq failed\n");
321 return ret;
322 }
323
324 xrtcdev->sec_irq = platform_get_irq_byname(pdev, "sec");
325 if (xrtcdev->sec_irq < 0)
326 return xrtcdev->sec_irq;
327 ret = devm_request_irq(&pdev->dev, xrtcdev->sec_irq,
328 xlnx_rtc_interrupt, 0,
329 dev_name(&pdev->dev), xrtcdev);
330 if (ret) {
331 dev_err(&pdev->dev, "request irq failed\n");
332 return ret;
333 }
334
335 /* Getting the rtc info */
336 xrtcdev->rtc_clk = devm_clk_get_optional(&pdev->dev, "rtc");
337 if (IS_ERR(xrtcdev->rtc_clk))
338 return dev_err_probe(&pdev->dev, PTR_ERR(xrtcdev->rtc_clk),
339 "Failed to get rtc clock\n");
340 xrtcdev->freq = clk_get_rate(xrtcdev->rtc_clk);
341 if (!xrtcdev->freq) {
342 ret = of_property_read_u32(pdev->dev.of_node, "calibration",
343 &xrtcdev->freq);
344 if (ret)
345 xrtcdev->freq = RTC_CALIB_DEF;
346 } else {
347 xrtcdev->freq--;
348 }
349
350 if (xrtcdev->freq > RTC_TICK_MASK) {
351 dev_err(&pdev->dev, "Invalid RTC calibration value\n");
352 return -EINVAL;
353 }
354
355 ret = readl(xrtcdev->reg_base + RTC_CALIB_RD);
356 if (!ret)
357 writel(xrtcdev->freq, (xrtcdev->reg_base + RTC_CALIB_WR));
358
359 xlnx_init_rtc(xrtcdev);
360
361 /* Re-enable alarm interrupt if a valid alarm was found */
362 if (is_alarm_set)
363 writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_EN);
364
365 device_init_wakeup(&pdev->dev, true);
366
367 return devm_rtc_register_device(xrtcdev->rtc);
368}
369
370static void xlnx_rtc_remove(struct platform_device *pdev)
371{
372 xlnx_rtc_alarm_irq_enable(&pdev->dev, 0);
373 device_init_wakeup(&pdev->dev, false);
374}
375
376static int __maybe_unused xlnx_rtc_suspend(struct device *dev)
377{
378 struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
379
380 if (device_may_wakeup(dev))
381 enable_irq_wake(xrtcdev->alarm_irq);
382 else
383 xlnx_rtc_alarm_irq_enable(dev, 0);
384
385 return 0;
386}
387
388static int __maybe_unused xlnx_rtc_resume(struct device *dev)
389{
390 struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
391
392 if (device_may_wakeup(dev))
393 disable_irq_wake(xrtcdev->alarm_irq);
394 else
395 xlnx_rtc_alarm_irq_enable(dev, 1);
396
397 return 0;
398}
399
400static SIMPLE_DEV_PM_OPS(xlnx_rtc_pm_ops, xlnx_rtc_suspend, xlnx_rtc_resume);
401
402static const struct of_device_id xlnx_rtc_of_match[] = {
403 {.compatible = "xlnx,zynqmp-rtc" },
404 { }
405};
406MODULE_DEVICE_TABLE(of, xlnx_rtc_of_match);
407
408static struct platform_driver xlnx_rtc_driver = {
409 .probe = xlnx_rtc_probe,
410 .remove = xlnx_rtc_remove,
411 .driver = {
412 .name = KBUILD_MODNAME,
413 .pm = &xlnx_rtc_pm_ops,
414 .of_match_table = xlnx_rtc_of_match,
415 },
416};
417
418module_platform_driver(xlnx_rtc_driver);
419
420MODULE_DESCRIPTION("Xilinx Zynq MPSoC RTC driver");
421MODULE_AUTHOR("Xilinx Inc.");
422MODULE_LICENSE("GPL v2");