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1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2// Copyright(c) 2015-2023 Intel Corporation
3
4#include <linux/acpi.h>
5#include <linux/soundwire/sdw_registers.h>
6#include <linux/soundwire/sdw.h>
7#include <linux/soundwire/sdw_intel.h>
8#include "cadence_master.h"
9#include "bus.h"
10#include "intel.h"
11
12int intel_start_bus(struct sdw_intel *sdw)
13{
14 struct device *dev = sdw->cdns.dev;
15 struct sdw_cdns *cdns = &sdw->cdns;
16 struct sdw_bus *bus = &cdns->bus;
17 int ret;
18
19 ret = sdw_cdns_soft_reset(cdns);
20 if (ret < 0) {
21 dev_err(dev, "%s: unable to soft-reset Cadence IP: %d\n", __func__, ret);
22 return ret;
23 }
24
25 /*
26 * follow recommended programming flows to avoid timeouts when
27 * gsync is enabled
28 */
29 if (bus->multi_link)
30 sdw_intel_sync_arm(sdw);
31
32 ret = sdw_cdns_init(cdns);
33 if (ret < 0) {
34 dev_err(dev, "%s: unable to initialize Cadence IP: %d\n", __func__, ret);
35 return ret;
36 }
37
38 sdw_cdns_config_update(cdns);
39
40 if (bus->multi_link) {
41 ret = sdw_intel_sync_go(sdw);
42 if (ret < 0) {
43 dev_err(dev, "%s: sync go failed: %d\n", __func__, ret);
44 return ret;
45 }
46 }
47
48 ret = sdw_cdns_config_update_set_wait(cdns);
49 if (ret < 0) {
50 dev_err(dev, "%s: CONFIG_UPDATE BIT still set\n", __func__);
51 return ret;
52 }
53
54 ret = sdw_cdns_enable_interrupt(cdns, true);
55 if (ret < 0) {
56 dev_err(dev, "%s: cannot enable interrupts: %d\n", __func__, ret);
57 return ret;
58 }
59
60 ret = sdw_cdns_exit_reset(cdns);
61 if (ret < 0) {
62 dev_err(dev, "%s: unable to exit bus reset sequence: %d\n", __func__, ret);
63 return ret;
64 }
65
66 sdw_cdns_check_self_clearing_bits(cdns, __func__,
67 true, INTEL_MASTER_RESET_ITERATIONS);
68
69 schedule_delayed_work(&cdns->attach_dwork,
70 msecs_to_jiffies(SDW_INTEL_DELAYED_ENUMERATION_MS));
71
72 return 0;
73}
74
75int intel_start_bus_after_reset(struct sdw_intel *sdw)
76{
77 struct device *dev = sdw->cdns.dev;
78 struct sdw_cdns *cdns = &sdw->cdns;
79 struct sdw_bus *bus = &cdns->bus;
80 bool clock_stop0;
81 int status;
82 int ret;
83
84 /*
85 * An exception condition occurs for the CLK_STOP_BUS_RESET
86 * case if one or more masters remain active. In this condition,
87 * all the masters are powered on for they are in the same power
88 * domain. Master can preserve its context for clock stop0, so
89 * there is no need to clear slave status and reset bus.
90 */
91 clock_stop0 = sdw_cdns_is_clock_stop(&sdw->cdns);
92
93 if (!clock_stop0) {
94
95 /*
96 * make sure all Slaves are tagged as UNATTACHED and
97 * provide reason for reinitialization
98 */
99
100 status = SDW_UNATTACH_REQUEST_MASTER_RESET;
101 sdw_clear_slave_status(bus, status);
102
103 /*
104 * follow recommended programming flows to avoid
105 * timeouts when gsync is enabled
106 */
107 if (bus->multi_link)
108 sdw_intel_sync_arm(sdw);
109
110 /*
111 * Re-initialize the IP since it was powered-off
112 */
113 sdw_cdns_init(&sdw->cdns);
114
115 } else {
116 ret = sdw_cdns_enable_interrupt(cdns, true);
117 if (ret < 0) {
118 dev_err(dev, "cannot enable interrupts during resume\n");
119 return ret;
120 }
121 }
122
123 ret = sdw_cdns_clock_restart(cdns, !clock_stop0);
124 if (ret < 0) {
125 dev_err(dev, "unable to restart clock during resume\n");
126 if (!clock_stop0)
127 sdw_cdns_enable_interrupt(cdns, false);
128 return ret;
129 }
130
131 if (!clock_stop0) {
132 sdw_cdns_config_update(cdns);
133
134 if (bus->multi_link) {
135 ret = sdw_intel_sync_go(sdw);
136 if (ret < 0) {
137 dev_err(sdw->cdns.dev, "sync go failed during resume\n");
138 return ret;
139 }
140 }
141
142 ret = sdw_cdns_config_update_set_wait(cdns);
143 if (ret < 0) {
144 dev_err(dev, "%s: CONFIG_UPDATE BIT still set\n", __func__);
145 return ret;
146 }
147
148 ret = sdw_cdns_enable_interrupt(cdns, true);
149 if (ret < 0) {
150 dev_err(dev, "cannot enable interrupts during resume\n");
151 return ret;
152 }
153
154 ret = sdw_cdns_exit_reset(cdns);
155 if (ret < 0) {
156 dev_err(dev, "unable to exit bus reset sequence during resume\n");
157 return ret;
158 }
159
160 }
161 sdw_cdns_check_self_clearing_bits(cdns, __func__, true, INTEL_MASTER_RESET_ITERATIONS);
162
163 schedule_delayed_work(&cdns->attach_dwork,
164 msecs_to_jiffies(SDW_INTEL_DELAYED_ENUMERATION_MS));
165
166 return 0;
167}
168
169void intel_check_clock_stop(struct sdw_intel *sdw)
170{
171 struct device *dev = sdw->cdns.dev;
172 bool clock_stop0;
173
174 clock_stop0 = sdw_cdns_is_clock_stop(&sdw->cdns);
175 if (!clock_stop0)
176 dev_err(dev, "%s: invalid configuration, clock was not stopped\n", __func__);
177}
178
179int intel_start_bus_after_clock_stop(struct sdw_intel *sdw)
180{
181 struct device *dev = sdw->cdns.dev;
182 struct sdw_cdns *cdns = &sdw->cdns;
183 int ret;
184
185 ret = sdw_cdns_clock_restart(cdns, false);
186 if (ret < 0) {
187 dev_err(dev, "%s: unable to restart clock: %d\n", __func__, ret);
188 return ret;
189 }
190
191 ret = sdw_cdns_enable_interrupt(cdns, true);
192 if (ret < 0) {
193 dev_err(dev, "%s: cannot enable interrupts: %d\n", __func__, ret);
194 return ret;
195 }
196
197 sdw_cdns_check_self_clearing_bits(cdns, __func__, true, INTEL_MASTER_RESET_ITERATIONS);
198
199 schedule_delayed_work(&cdns->attach_dwork,
200 msecs_to_jiffies(SDW_INTEL_DELAYED_ENUMERATION_MS));
201
202 return 0;
203}
204
205int intel_stop_bus(struct sdw_intel *sdw, bool clock_stop)
206{
207 struct device *dev = sdw->cdns.dev;
208 struct sdw_cdns *cdns = &sdw->cdns;
209 bool wake_enable = false;
210 int ret;
211
212 cancel_delayed_work_sync(&cdns->attach_dwork);
213
214 if (clock_stop) {
215 ret = sdw_cdns_clock_stop(cdns, true);
216 if (ret < 0)
217 dev_err(dev, "%s: cannot stop clock: %d\n", __func__, ret);
218 else
219 wake_enable = true;
220 }
221
222 ret = sdw_cdns_enable_interrupt(cdns, false);
223 if (ret < 0) {
224 dev_err(dev, "%s: cannot disable interrupts: %d\n", __func__, ret);
225 return ret;
226 }
227
228 ret = sdw_intel_link_power_down(sdw);
229 if (ret) {
230 dev_err(dev, "%s: Link power down failed: %d\n", __func__, ret);
231 return ret;
232 }
233
234 sdw_intel_shim_wake(sdw, wake_enable);
235
236 return 0;
237}
238
239/*
240 * bank switch routines
241 */
242
243int intel_pre_bank_switch(struct sdw_intel *sdw)
244{
245 struct sdw_cdns *cdns = &sdw->cdns;
246 struct sdw_bus *bus = &cdns->bus;
247
248 /* Write to register only for multi-link */
249 if (!bus->multi_link)
250 return 0;
251
252 sdw_intel_sync_arm(sdw);
253
254 return 0;
255}
256
257int intel_post_bank_switch(struct sdw_intel *sdw)
258{
259 struct sdw_cdns *cdns = &sdw->cdns;
260 struct sdw_bus *bus = &cdns->bus;
261 int ret = 0;
262
263 /* Write to register only for multi-link */
264 if (!bus->multi_link)
265 return 0;
266
267 mutex_lock(sdw->link_res->shim_lock);
268
269 /*
270 * post_bank_switch() ops is called from the bus in loop for
271 * all the Masters in the steam with the expectation that
272 * we trigger the bankswitch for the only first Master in the list
273 * and do nothing for the other Masters
274 *
275 * So, set the SYNCGO bit only if CMDSYNC bit is set for any Master.
276 */
277 if (sdw_intel_sync_check_cmdsync_unlocked(sdw))
278 ret = sdw_intel_sync_go_unlocked(sdw);
279
280 mutex_unlock(sdw->link_res->shim_lock);
281
282 if (ret < 0)
283 dev_err(sdw->cdns.dev, "Post bank switch failed: %d\n", ret);
284
285 return ret;
286}