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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Driver for Amlogic A1 SPI flash controller (SPIFC)
4 *
5 * Copyright (c) 2023, SberDevices. All Rights Reserved.
6 *
7 * Author: Martin Kurbanov <[email protected]>
8 */
9
10#include <linux/bitfield.h>
11#include <linux/clk.h>
12#include <linux/device.h>
13#include <linux/io.h>
14#include <linux/iopoll.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/of.h>
18#include <linux/platform_device.h>
19#include <linux/pm_runtime.h>
20#include <linux/spi/spi.h>
21#include <linux/spi/spi-mem.h>
22#include <linux/types.h>
23
24#define SPIFC_A1_AHB_CTRL_REG 0x0
25#define SPIFC_A1_AHB_BUS_EN BIT(31)
26
27#define SPIFC_A1_USER_CTRL0_REG 0x200
28#define SPIFC_A1_USER_REQUEST_ENABLE BIT(31)
29#define SPIFC_A1_USER_REQUEST_FINISH BIT(30)
30#define SPIFC_A1_USER_DATA_UPDATED BIT(0)
31
32#define SPIFC_A1_USER_CTRL1_REG 0x204
33#define SPIFC_A1_USER_CMD_ENABLE BIT(30)
34#define SPIFC_A1_USER_CMD_MODE GENMASK(29, 28)
35#define SPIFC_A1_USER_CMD_CODE GENMASK(27, 20)
36#define SPIFC_A1_USER_ADDR_ENABLE BIT(19)
37#define SPIFC_A1_USER_ADDR_MODE GENMASK(18, 17)
38#define SPIFC_A1_USER_ADDR_BYTES GENMASK(16, 15)
39#define SPIFC_A1_USER_DOUT_ENABLE BIT(14)
40#define SPIFC_A1_USER_DOUT_MODE GENMASK(11, 10)
41#define SPIFC_A1_USER_DOUT_BYTES GENMASK(9, 0)
42
43#define SPIFC_A1_USER_CTRL2_REG 0x208
44#define SPIFC_A1_USER_DUMMY_ENABLE BIT(31)
45#define SPIFC_A1_USER_DUMMY_MODE GENMASK(30, 29)
46#define SPIFC_A1_USER_DUMMY_CLK_SYCLES GENMASK(28, 23)
47
48#define SPIFC_A1_USER_CTRL3_REG 0x20c
49#define SPIFC_A1_USER_DIN_ENABLE BIT(31)
50#define SPIFC_A1_USER_DIN_MODE GENMASK(28, 27)
51#define SPIFC_A1_USER_DIN_BYTES GENMASK(25, 16)
52
53#define SPIFC_A1_USER_ADDR_REG 0x210
54
55#define SPIFC_A1_AHB_REQ_CTRL_REG 0x214
56#define SPIFC_A1_AHB_REQ_ENABLE BIT(31)
57
58#define SPIFC_A1_ACTIMING0_REG (0x0088 << 2)
59#define SPIFC_A1_TSLCH GENMASK(31, 30)
60#define SPIFC_A1_TCLSH GENMASK(29, 28)
61#define SPIFC_A1_TSHWL GENMASK(20, 16)
62#define SPIFC_A1_TSHSL2 GENMASK(15, 12)
63#define SPIFC_A1_TSHSL1 GENMASK(11, 8)
64#define SPIFC_A1_TWHSL GENMASK(7, 0)
65
66#define SPIFC_A1_DBUF_CTRL_REG 0x240
67#define SPIFC_A1_DBUF_DIR BIT(31)
68#define SPIFC_A1_DBUF_AUTO_UPDATE_ADDR BIT(30)
69#define SPIFC_A1_DBUF_ADDR GENMASK(7, 0)
70
71#define SPIFC_A1_DBUF_DATA_REG 0x244
72
73#define SPIFC_A1_USER_DBUF_ADDR_REG 0x248
74
75#define SPIFC_A1_BUFFER_SIZE 512U
76
77#define SPIFC_A1_MAX_HZ 200000000
78#define SPIFC_A1_MIN_HZ 1000000
79
80#define SPIFC_A1_USER_CMD(op) ( \
81 SPIFC_A1_USER_CMD_ENABLE | \
82 FIELD_PREP(SPIFC_A1_USER_CMD_CODE, (op)->cmd.opcode) | \
83 FIELD_PREP(SPIFC_A1_USER_CMD_MODE, ilog2((op)->cmd.buswidth)))
84
85#define SPIFC_A1_USER_ADDR(op) ( \
86 SPIFC_A1_USER_ADDR_ENABLE | \
87 FIELD_PREP(SPIFC_A1_USER_ADDR_MODE, ilog2((op)->addr.buswidth)) | \
88 FIELD_PREP(SPIFC_A1_USER_ADDR_BYTES, (op)->addr.nbytes - 1))
89
90#define SPIFC_A1_USER_DUMMY(op) ( \
91 SPIFC_A1_USER_DUMMY_ENABLE | \
92 FIELD_PREP(SPIFC_A1_USER_DUMMY_MODE, ilog2((op)->dummy.buswidth)) | \
93 FIELD_PREP(SPIFC_A1_USER_DUMMY_CLK_SYCLES, (op)->dummy.nbytes << 3))
94
95#define SPIFC_A1_TSLCH_VAL FIELD_PREP(SPIFC_A1_TSLCH, 1)
96#define SPIFC_A1_TCLSH_VAL FIELD_PREP(SPIFC_A1_TCLSH, 1)
97#define SPIFC_A1_TSHWL_VAL FIELD_PREP(SPIFC_A1_TSHWL, 7)
98#define SPIFC_A1_TSHSL2_VAL FIELD_PREP(SPIFC_A1_TSHSL2, 7)
99#define SPIFC_A1_TSHSL1_VAL FIELD_PREP(SPIFC_A1_TSHSL1, 7)
100#define SPIFC_A1_TWHSL_VAL FIELD_PREP(SPIFC_A1_TWHSL, 2)
101#define SPIFC_A1_ACTIMING0_VAL (SPIFC_A1_TSLCH_VAL | SPIFC_A1_TCLSH_VAL | \
102 SPIFC_A1_TSHWL_VAL | SPIFC_A1_TSHSL2_VAL | \
103 SPIFC_A1_TSHSL1_VAL | SPIFC_A1_TWHSL_VAL)
104
105struct amlogic_spifc_a1 {
106 struct spi_controller *ctrl;
107 struct clk *clk;
108 struct device *dev;
109 void __iomem *base;
110 u32 curr_speed_hz;
111};
112
113static int amlogic_spifc_a1_request(struct amlogic_spifc_a1 *spifc, bool read)
114{
115 u32 mask = SPIFC_A1_USER_REQUEST_FINISH |
116 (read ? SPIFC_A1_USER_DATA_UPDATED : 0);
117 u32 val;
118
119 writel(SPIFC_A1_USER_REQUEST_ENABLE,
120 spifc->base + SPIFC_A1_USER_CTRL0_REG);
121
122 return readl_poll_timeout(spifc->base + SPIFC_A1_USER_CTRL0_REG,
123 val, (val & mask) == mask, 0,
124 200 * USEC_PER_MSEC);
125}
126
127static void amlogic_spifc_a1_drain_buffer(struct amlogic_spifc_a1 *spifc,
128 char *buf, u32 len)
129{
130 u32 data;
131 const u32 count = len / sizeof(data);
132 const u32 pad = len % sizeof(data);
133
134 writel(SPIFC_A1_DBUF_AUTO_UPDATE_ADDR,
135 spifc->base + SPIFC_A1_DBUF_CTRL_REG);
136 ioread32_rep(spifc->base + SPIFC_A1_DBUF_DATA_REG, buf, count);
137
138 if (pad) {
139 data = readl(spifc->base + SPIFC_A1_DBUF_DATA_REG);
140 memcpy(buf + len - pad, &data, pad);
141 }
142}
143
144static void amlogic_spifc_a1_fill_buffer(struct amlogic_spifc_a1 *spifc,
145 const char *buf, u32 len)
146{
147 u32 data;
148 const u32 count = len / sizeof(data);
149 const u32 pad = len % sizeof(data);
150
151 writel(SPIFC_A1_DBUF_DIR | SPIFC_A1_DBUF_AUTO_UPDATE_ADDR,
152 spifc->base + SPIFC_A1_DBUF_CTRL_REG);
153 iowrite32_rep(spifc->base + SPIFC_A1_DBUF_DATA_REG, buf, count);
154
155 if (pad) {
156 memcpy(&data, buf + len - pad, pad);
157 writel(data, spifc->base + SPIFC_A1_DBUF_DATA_REG);
158 }
159}
160
161static void amlogic_spifc_a1_user_init(struct amlogic_spifc_a1 *spifc)
162{
163 writel(0, spifc->base + SPIFC_A1_USER_CTRL0_REG);
164 writel(0, spifc->base + SPIFC_A1_USER_CTRL1_REG);
165 writel(0, spifc->base + SPIFC_A1_USER_CTRL2_REG);
166 writel(0, spifc->base + SPIFC_A1_USER_CTRL3_REG);
167}
168
169static void amlogic_spifc_a1_set_cmd(struct amlogic_spifc_a1 *spifc,
170 u32 cmd_cfg)
171{
172 u32 val;
173
174 val = readl(spifc->base + SPIFC_A1_USER_CTRL1_REG);
175 val &= ~(SPIFC_A1_USER_CMD_MODE | SPIFC_A1_USER_CMD_CODE);
176 val |= cmd_cfg;
177 writel(val, spifc->base + SPIFC_A1_USER_CTRL1_REG);
178}
179
180static void amlogic_spifc_a1_set_addr(struct amlogic_spifc_a1 *spifc, u32 addr,
181 u32 addr_cfg)
182{
183 u32 val;
184
185 writel(addr, spifc->base + SPIFC_A1_USER_ADDR_REG);
186
187 val = readl(spifc->base + SPIFC_A1_USER_CTRL1_REG);
188 val &= ~(SPIFC_A1_USER_ADDR_MODE | SPIFC_A1_USER_ADDR_BYTES);
189 val |= addr_cfg;
190 writel(val, spifc->base + SPIFC_A1_USER_CTRL1_REG);
191}
192
193static void amlogic_spifc_a1_set_dummy(struct amlogic_spifc_a1 *spifc,
194 u32 dummy_cfg)
195{
196 u32 val = readl(spifc->base + SPIFC_A1_USER_CTRL2_REG);
197
198 val &= ~(SPIFC_A1_USER_DUMMY_MODE | SPIFC_A1_USER_DUMMY_CLK_SYCLES);
199 val |= dummy_cfg;
200 writel(val, spifc->base + SPIFC_A1_USER_CTRL2_REG);
201}
202
203static int amlogic_spifc_a1_read(struct amlogic_spifc_a1 *spifc, void *buf,
204 u32 size, u32 mode)
205{
206 u32 val = readl(spifc->base + SPIFC_A1_USER_CTRL3_REG);
207 int ret;
208
209 val |= SPIFC_A1_USER_DIN_ENABLE;
210 FIELD_MODIFY(SPIFC_A1_USER_DIN_MODE, &val, mode);
211 FIELD_MODIFY(SPIFC_A1_USER_DIN_BYTES, &val, size);
212 writel(val, spifc->base + SPIFC_A1_USER_CTRL3_REG);
213
214 ret = amlogic_spifc_a1_request(spifc, true);
215 if (!ret)
216 amlogic_spifc_a1_drain_buffer(spifc, buf, size);
217
218 return ret;
219}
220
221static int amlogic_spifc_a1_write(struct amlogic_spifc_a1 *spifc,
222 const void *buf, u32 size, u32 mode)
223{
224 u32 val;
225
226 amlogic_spifc_a1_fill_buffer(spifc, buf, size);
227
228 val = readl(spifc->base + SPIFC_A1_USER_CTRL1_REG);
229 val &= ~(SPIFC_A1_USER_DOUT_MODE | SPIFC_A1_USER_DOUT_BYTES);
230 val |= FIELD_PREP(SPIFC_A1_USER_DOUT_MODE, mode);
231 val |= FIELD_PREP(SPIFC_A1_USER_DOUT_BYTES, size);
232 val |= SPIFC_A1_USER_DOUT_ENABLE;
233 writel(val, spifc->base + SPIFC_A1_USER_CTRL1_REG);
234
235 return amlogic_spifc_a1_request(spifc, false);
236}
237
238static int amlogic_spifc_a1_set_freq(struct amlogic_spifc_a1 *spifc, u32 freq)
239{
240 int ret;
241
242 if (freq == spifc->curr_speed_hz)
243 return 0;
244
245 ret = clk_set_rate(spifc->clk, freq);
246 if (ret)
247 return ret;
248
249 spifc->curr_speed_hz = freq;
250 return 0;
251}
252
253static int amlogic_spifc_a1_exec_op(struct spi_mem *mem,
254 const struct spi_mem_op *op)
255{
256 struct amlogic_spifc_a1 *spifc =
257 spi_controller_get_devdata(mem->spi->controller);
258 size_t data_size = op->data.nbytes;
259 int ret;
260
261 ret = amlogic_spifc_a1_set_freq(spifc, op->max_freq);
262 if (ret)
263 return ret;
264
265 amlogic_spifc_a1_user_init(spifc);
266 amlogic_spifc_a1_set_cmd(spifc, SPIFC_A1_USER_CMD(op));
267
268 if (op->addr.nbytes)
269 amlogic_spifc_a1_set_addr(spifc, op->addr.val,
270 SPIFC_A1_USER_ADDR(op));
271
272 if (op->dummy.nbytes)
273 amlogic_spifc_a1_set_dummy(spifc, SPIFC_A1_USER_DUMMY(op));
274
275 if (data_size) {
276 u32 mode = ilog2(op->data.buswidth);
277
278 writel(0, spifc->base + SPIFC_A1_USER_DBUF_ADDR_REG);
279
280 if (op->data.dir == SPI_MEM_DATA_IN)
281 ret = amlogic_spifc_a1_read(spifc, op->data.buf.in,
282 data_size, mode);
283 else
284 ret = amlogic_spifc_a1_write(spifc, op->data.buf.out,
285 data_size, mode);
286 } else {
287 ret = amlogic_spifc_a1_request(spifc, false);
288 }
289
290 return ret;
291}
292
293static int amlogic_spifc_a1_adjust_op_size(struct spi_mem *mem,
294 struct spi_mem_op *op)
295{
296 op->data.nbytes = min(op->data.nbytes, SPIFC_A1_BUFFER_SIZE);
297 return 0;
298}
299
300static void amlogic_spifc_a1_hw_init(struct amlogic_spifc_a1 *spifc)
301{
302 u32 regv;
303
304 regv = readl(spifc->base + SPIFC_A1_AHB_REQ_CTRL_REG);
305 regv &= ~(SPIFC_A1_AHB_REQ_ENABLE);
306 writel(regv, spifc->base + SPIFC_A1_AHB_REQ_CTRL_REG);
307
308 regv = readl(spifc->base + SPIFC_A1_AHB_CTRL_REG);
309 regv &= ~(SPIFC_A1_AHB_BUS_EN);
310 writel(regv, spifc->base + SPIFC_A1_AHB_CTRL_REG);
311
312 writel(SPIFC_A1_ACTIMING0_VAL, spifc->base + SPIFC_A1_ACTIMING0_REG);
313
314 writel(0, spifc->base + SPIFC_A1_USER_DBUF_ADDR_REG);
315}
316
317static const struct spi_controller_mem_ops amlogic_spifc_a1_mem_ops = {
318 .exec_op = amlogic_spifc_a1_exec_op,
319 .adjust_op_size = amlogic_spifc_a1_adjust_op_size,
320};
321
322static const struct spi_controller_mem_caps amlogic_spifc_a1_mem_caps = {
323 .per_op_freq = true,
324};
325
326static int amlogic_spifc_a1_probe(struct platform_device *pdev)
327{
328 struct spi_controller *ctrl;
329 struct amlogic_spifc_a1 *spifc;
330 int ret;
331
332 ctrl = devm_spi_alloc_host(&pdev->dev, sizeof(*spifc));
333 if (!ctrl)
334 return -ENOMEM;
335
336 spifc = spi_controller_get_devdata(ctrl);
337 platform_set_drvdata(pdev, spifc);
338
339 spifc->dev = &pdev->dev;
340 spifc->ctrl = ctrl;
341
342 spifc->base = devm_platform_ioremap_resource(pdev, 0);
343 if (IS_ERR(spifc->base))
344 return PTR_ERR(spifc->base);
345
346 spifc->clk = devm_clk_get_enabled(spifc->dev, NULL);
347 if (IS_ERR(spifc->clk))
348 return dev_err_probe(spifc->dev, PTR_ERR(spifc->clk),
349 "unable to get clock\n");
350
351 amlogic_spifc_a1_hw_init(spifc);
352
353 pm_runtime_set_autosuspend_delay(spifc->dev, 500);
354 pm_runtime_use_autosuspend(spifc->dev);
355 ret = devm_pm_runtime_enable(spifc->dev);
356 if (ret)
357 return ret;
358
359 ctrl->num_chipselect = 1;
360 ctrl->bits_per_word_mask = SPI_BPW_MASK(8);
361 ctrl->auto_runtime_pm = true;
362 ctrl->mem_ops = &amlogic_spifc_a1_mem_ops;
363 ctrl->mem_caps = &amlogic_spifc_a1_mem_caps;
364 ctrl->min_speed_hz = SPIFC_A1_MIN_HZ;
365 ctrl->max_speed_hz = SPIFC_A1_MAX_HZ;
366 ctrl->mode_bits = (SPI_RX_DUAL | SPI_TX_DUAL |
367 SPI_RX_QUAD | SPI_TX_QUAD);
368
369 ret = devm_spi_register_controller(spifc->dev, ctrl);
370 if (ret)
371 return dev_err_probe(spifc->dev, ret,
372 "failed to register spi controller\n");
373
374 return 0;
375}
376
377static int amlogic_spifc_a1_suspend(struct device *dev)
378{
379 struct amlogic_spifc_a1 *spifc = dev_get_drvdata(dev);
380 int ret;
381
382 ret = spi_controller_suspend(spifc->ctrl);
383 if (ret)
384 return ret;
385
386 if (!pm_runtime_suspended(dev))
387 clk_disable_unprepare(spifc->clk);
388
389 return 0;
390}
391
392static int amlogic_spifc_a1_resume(struct device *dev)
393{
394 struct amlogic_spifc_a1 *spifc = dev_get_drvdata(dev);
395 int ret = 0;
396
397 if (!pm_runtime_suspended(dev)) {
398 ret = clk_prepare_enable(spifc->clk);
399 if (ret)
400 return ret;
401 }
402
403 amlogic_spifc_a1_hw_init(spifc);
404
405 ret = spi_controller_resume(spifc->ctrl);
406 if (ret)
407 clk_disable_unprepare(spifc->clk);
408
409 return ret;
410}
411
412static int amlogic_spifc_a1_runtime_suspend(struct device *dev)
413{
414 struct amlogic_spifc_a1 *spifc = dev_get_drvdata(dev);
415
416 clk_disable_unprepare(spifc->clk);
417
418 return 0;
419}
420
421static int amlogic_spifc_a1_runtime_resume(struct device *dev)
422{
423 struct amlogic_spifc_a1 *spifc = dev_get_drvdata(dev);
424 int ret;
425
426 ret = clk_prepare_enable(spifc->clk);
427 if (!ret)
428 amlogic_spifc_a1_hw_init(spifc);
429
430 return ret;
431}
432
433static const struct dev_pm_ops amlogic_spifc_a1_pm_ops = {
434 SYSTEM_SLEEP_PM_OPS(amlogic_spifc_a1_suspend, amlogic_spifc_a1_resume)
435 RUNTIME_PM_OPS(amlogic_spifc_a1_runtime_suspend,
436 amlogic_spifc_a1_runtime_resume,
437 NULL)
438};
439
440#ifdef CONFIG_OF
441static const struct of_device_id amlogic_spifc_a1_dt_match[] = {
442 { .compatible = "amlogic,a1-spifc", },
443 { },
444};
445MODULE_DEVICE_TABLE(of, amlogic_spifc_a1_dt_match);
446#endif /* CONFIG_OF */
447
448static struct platform_driver amlogic_spifc_a1_driver = {
449 .probe = amlogic_spifc_a1_probe,
450 .driver = {
451 .name = "amlogic-spifc-a1",
452 .of_match_table = of_match_ptr(amlogic_spifc_a1_dt_match),
453 .pm = pm_ptr(&amlogic_spifc_a1_pm_ops),
454 },
455};
456module_platform_driver(amlogic_spifc_a1_driver);
457
458MODULE_AUTHOR("Martin Kurbanov <[email protected]>");
459MODULE_DESCRIPTION("Amlogic A1 SPIFC driver");
460MODULE_LICENSE("GPL");