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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Driver for Amlogic SPI communication Scatter-Gather Controller
4 *
5 * Copyright (C) 2025 Amlogic, Inc. All rights reserved
6 *
7 * Author: Sunny Luo <[email protected]>
8 * Author: Xianwei Zhao <[email protected]>
9 */
10
11#include <linux/bitfield.h>
12#include <linux/device.h>
13#include <linux/module.h>
14#include <linux/of.h>
15#include <linux/clk.h>
16#include <linux/clk-provider.h>
17#include <linux/dma-mapping.h>
18#include <linux/platform_device.h>
19#include <linux/pinctrl/consumer.h>
20#include <linux/pm_runtime.h>
21#include <linux/spi/spi.h>
22#include <linux/types.h>
23#include <linux/interrupt.h>
24#include <linux/reset.h>
25#include <linux/regmap.h>
26
27/* Register Map */
28#define SPISG_REG_CFG_READY 0x00
29
30#define SPISG_REG_CFG_SPI 0x04
31#define CFG_BUS64_EN BIT(0)
32#define CFG_SLAVE_EN BIT(1)
33#define CFG_SLAVE_SELECT GENMASK(3, 2)
34#define CFG_SFLASH_WP BIT(4)
35#define CFG_SFLASH_HD BIT(5)
36/* start on vsync rising */
37#define CFG_HW_POS BIT(6)
38/* start on vsync falling */
39#define CFG_HW_NEG BIT(7)
40
41#define SPISG_REG_CFG_START 0x08
42#define CFG_BLOCK_NUM GENMASK(19, 0)
43#define CFG_BLOCK_SIZE GENMASK(22, 20)
44#define CFG_DATA_COMMAND BIT(23)
45#define CFG_OP_MODE GENMASK(25, 24)
46#define CFG_RXD_MODE GENMASK(27, 26)
47#define CFG_TXD_MODE GENMASK(29, 28)
48#define CFG_EOC BIT(30)
49#define CFG_PEND BIT(31)
50
51#define SPISG_REG_CFG_BUS 0x0C
52#define CFG_CLK_DIV GENMASK(7, 0)
53#define CLK_DIV_WIDTH 8
54#define CFG_RX_TUNING GENMASK(11, 8)
55#define CFG_TX_TUNING GENMASK(15, 12)
56#define CFG_CS_SETUP GENMASK(19, 16)
57#define CFG_LANE GENMASK(21, 20)
58#define CFG_HALF_DUPLEX BIT(22)
59#define CFG_B_L_ENDIAN BIT(23)
60#define CFG_DC_MODE BIT(24)
61#define CFG_NULL_CTL BIT(25)
62#define CFG_DUMMY_CTL BIT(26)
63#define CFG_READ_TURN GENMASK(28, 27)
64#define CFG_KEEP_SS BIT(29)
65#define CFG_CPHA BIT(30)
66#define CFG_CPOL BIT(31)
67
68#define SPISG_REG_PIO_TX_DATA_L 0x10
69#define SPISG_REG_PIO_TX_DATA_H 0x14
70#define SPISG_REG_PIO_RX_DATA_L 0x18
71#define SPISG_REG_PIO_RX_DATA_H 0x1C
72#define SPISG_REG_MEM_TX_ADDR_L 0x10
73#define SPISG_REG_MEM_TX_ADDR_H 0x14
74#define SPISG_REG_MEM_RX_ADDR_L 0x18
75#define SPISG_REG_MEM_RX_ADDR_H 0x1C
76#define SPISG_REG_DESC_LIST_L 0x20
77#define SPISG_REG_DESC_LIST_H 0x24
78#define LIST_DESC_PENDING BIT(31)
79#define SPISG_REG_DESC_CURRENT_L 0x28
80#define SPISG_REG_DESC_CURRENT_H 0x2c
81#define SPISG_REG_IRQ_STS 0x30
82#define SPISG_REG_IRQ_ENABLE 0x34
83#define IRQ_RCH_DESC_EOC BIT(0)
84#define IRQ_RCH_DESC_INVALID BIT(1)
85#define IRQ_RCH_DESC_RESP BIT(2)
86#define IRQ_RCH_DATA_RESP BIT(3)
87#define IRQ_WCH_DESC_EOC BIT(4)
88#define IRQ_WCH_DESC_INVALID BIT(5)
89#define IRQ_WCH_DESC_RESP BIT(6)
90#define IRQ_WCH_DATA_RESP BIT(7)
91#define IRQ_DESC_ERR BIT(8)
92#define IRQ_SPI_READY BIT(9)
93#define IRQ_DESC_DONE BIT(10)
94#define IRQ_DESC_CHAIN_DONE BIT(11)
95
96#define SPISG_MAX_REG 0x40
97
98#define SPISG_BLOCK_MAX 0x100000
99
100#define SPISG_OP_MODE_WRITE_CMD 0
101#define SPISG_OP_MODE_READ_STS 1
102#define SPISG_OP_MODE_WRITE 2
103#define SPISG_OP_MODE_READ 3
104
105#define SPISG_DATA_MODE_NONE 0
106#define SPISG_DATA_MODE_PIO 1
107#define SPISG_DATA_MODE_MEM 2
108#define SPISG_DATA_MODE_SG 3
109
110#define SPISG_CLK_DIV_MAX 256
111/* recommended by specification */
112#define SPISG_CLK_DIV_MIN 4
113#define DIV_NUM (SPISG_CLK_DIV_MAX - SPISG_CLK_DIV_MIN + 1)
114
115#define SPISG_PCLK_RATE_MIN 24000000
116
117#define SPISG_SINGLE_SPI 0
118#define SPISG_DUAL_SPI 1
119#define SPISG_QUAD_SPI 2
120
121struct spisg_sg_link {
122#define LINK_ADDR_VALID BIT(0)
123#define LINK_ADDR_EOC BIT(1)
124#define LINK_ADDR_IRQ BIT(2)
125#define LINK_ADDR_ACT GENMASK(5, 3)
126#define LINK_ADDR_RING BIT(6)
127#define LINK_ADDR_LEN GENMASK(31, 8)
128 u32 addr;
129 u32 addr1;
130};
131
132struct spisg_descriptor {
133 u32 cfg_start;
134 u32 cfg_bus;
135 u64 tx_paddr;
136 u64 rx_paddr;
137};
138
139struct spisg_descriptor_extra {
140 struct spisg_sg_link *tx_ccsg;
141 struct spisg_sg_link *rx_ccsg;
142 int tx_ccsg_len;
143 int rx_ccsg_len;
144};
145
146struct spisg_device {
147 struct spi_controller *controller;
148 struct platform_device *pdev;
149 struct regmap *map;
150 struct clk *core;
151 struct clk *pclk;
152 struct clk *sclk;
153 struct clk_div_table *tbl;
154 struct completion completion;
155 u32 status;
156 u32 speed_hz;
157 u32 effective_speed_hz;
158 u32 bytes_per_word;
159 u32 cfg_spi;
160 u32 cfg_start;
161 u32 cfg_bus;
162};
163
164static int spi_delay_to_sclk(u32 slck_speed_hz, struct spi_delay *delay)
165{
166 s32 ns;
167
168 if (!delay)
169 return 0;
170
171 if (delay->unit == SPI_DELAY_UNIT_SCK)
172 return delay->value;
173
174 ns = spi_delay_to_ns(delay, NULL);
175 if (ns < 0)
176 return 0;
177
178 return DIV_ROUND_UP_ULL(slck_speed_hz * ns, NSEC_PER_SEC);
179}
180
181static inline u32 aml_spisg_sem_down_read(struct spisg_device *spisg)
182{
183 u32 ret;
184
185 regmap_read(spisg->map, SPISG_REG_CFG_READY, &ret);
186 if (ret)
187 regmap_write(spisg->map, SPISG_REG_CFG_READY, 0);
188
189 return ret;
190}
191
192static inline void aml_spisg_sem_up_write(struct spisg_device *spisg)
193{
194 regmap_write(spisg->map, SPISG_REG_CFG_READY, 1);
195}
196
197static int aml_spisg_set_speed(struct spisg_device *spisg, uint speed_hz)
198{
199 u32 cfg_bus;
200
201 if (!speed_hz || speed_hz == spisg->speed_hz)
202 return 0;
203
204 spisg->speed_hz = speed_hz;
205 clk_set_rate(spisg->sclk, speed_hz);
206 /* Store the div for the descriptor mode */
207 regmap_read(spisg->map, SPISG_REG_CFG_BUS, &cfg_bus);
208 spisg->cfg_bus &= ~CFG_CLK_DIV;
209 spisg->cfg_bus |= cfg_bus & CFG_CLK_DIV;
210 spisg->effective_speed_hz = clk_get_rate(spisg->sclk);
211 dev_dbg(&spisg->pdev->dev,
212 "desired speed %dHz, effective speed %dHz\n",
213 speed_hz, spisg->effective_speed_hz);
214
215 return 0;
216}
217
218static bool aml_spisg_can_dma(struct spi_controller *ctlr,
219 struct spi_device *spi,
220 struct spi_transfer *xfer)
221{
222 return true;
223}
224
225static void aml_spisg_sg_xlate(struct sg_table *sgt, struct spisg_sg_link *ccsg)
226{
227 struct scatterlist *sg;
228 int i;
229
230 for_each_sg(sgt->sgl, sg, sgt->nents, i) {
231 ccsg->addr = FIELD_PREP(LINK_ADDR_VALID, 1) |
232 FIELD_PREP(LINK_ADDR_RING, 0) |
233 FIELD_PREP(LINK_ADDR_EOC, sg_is_last(sg)) |
234 FIELD_PREP(LINK_ADDR_LEN, sg_dma_len(sg));
235 ccsg->addr1 = (u32)sg_dma_address(sg);
236 ccsg++;
237 }
238}
239
240static int nbits_to_lane[] = {
241 SPISG_SINGLE_SPI,
242 SPISG_SINGLE_SPI,
243 SPISG_DUAL_SPI,
244 -EINVAL,
245 SPISG_QUAD_SPI
246};
247
248static int aml_spisg_setup_transfer(struct spisg_device *spisg,
249 struct spi_transfer *xfer,
250 struct spisg_descriptor *desc,
251 struct spisg_descriptor_extra *exdesc)
252{
253 int block_size, blocks;
254 struct device *dev = &spisg->pdev->dev;
255 struct spisg_sg_link *ccsg;
256 int ccsg_len;
257 dma_addr_t paddr;
258 int ret;
259
260 memset(desc, 0, sizeof(*desc));
261 memset(exdesc, 0, sizeof(*exdesc));
262 aml_spisg_set_speed(spisg, xfer->speed_hz);
263 xfer->effective_speed_hz = spisg->effective_speed_hz;
264
265 desc->cfg_start = spisg->cfg_start;
266 desc->cfg_bus = spisg->cfg_bus;
267
268 block_size = xfer->bits_per_word >> 3;
269 blocks = xfer->len / block_size;
270
271 desc->cfg_start |= FIELD_PREP(CFG_EOC, 0);
272 desc->cfg_bus |= FIELD_PREP(CFG_KEEP_SS, !xfer->cs_change);
273 desc->cfg_bus |= FIELD_PREP(CFG_NULL_CTL, 0);
274
275 if (xfer->tx_buf || xfer->tx_dma) {
276 desc->cfg_bus |= FIELD_PREP(CFG_LANE, nbits_to_lane[xfer->tx_nbits]);
277 desc->cfg_start |= FIELD_PREP(CFG_OP_MODE, SPISG_OP_MODE_WRITE);
278 }
279 if (xfer->rx_buf || xfer->rx_dma) {
280 desc->cfg_bus |= FIELD_PREP(CFG_LANE, nbits_to_lane[xfer->rx_nbits]);
281 desc->cfg_start |= FIELD_PREP(CFG_OP_MODE, SPISG_OP_MODE_READ);
282 }
283
284 if (FIELD_GET(CFG_OP_MODE, desc->cfg_start) == SPISG_OP_MODE_READ_STS) {
285 desc->cfg_start |= FIELD_PREP(CFG_BLOCK_SIZE, blocks) |
286 FIELD_PREP(CFG_BLOCK_NUM, 1);
287 } else {
288 blocks = min_t(int, blocks, SPISG_BLOCK_MAX);
289 desc->cfg_start |= FIELD_PREP(CFG_BLOCK_SIZE, block_size & 0x7) |
290 FIELD_PREP(CFG_BLOCK_NUM, blocks);
291 }
292
293 if (xfer->tx_sg.nents && xfer->tx_sg.sgl) {
294 ccsg_len = xfer->tx_sg.nents * sizeof(struct spisg_sg_link);
295 ccsg = kzalloc(ccsg_len, GFP_KERNEL | GFP_DMA);
296 if (!ccsg) {
297 dev_err(dev, "alloc tx_ccsg failed\n");
298 return -ENOMEM;
299 }
300
301 aml_spisg_sg_xlate(&xfer->tx_sg, ccsg);
302 paddr = dma_map_single(dev, (void *)ccsg,
303 ccsg_len, DMA_TO_DEVICE);
304 ret = dma_mapping_error(dev, paddr);
305 if (ret) {
306 kfree(ccsg);
307 dev_err(dev, "tx ccsg map failed\n");
308 return ret;
309 }
310
311 desc->tx_paddr = paddr;
312 desc->cfg_start |= FIELD_PREP(CFG_TXD_MODE, SPISG_DATA_MODE_SG);
313 exdesc->tx_ccsg = ccsg;
314 exdesc->tx_ccsg_len = ccsg_len;
315 dma_sync_sgtable_for_device(spisg->controller->cur_tx_dma_dev,
316 &xfer->tx_sg, DMA_TO_DEVICE);
317 } else if (xfer->tx_buf || xfer->tx_dma) {
318 paddr = xfer->tx_dma;
319 if (!paddr) {
320 paddr = dma_map_single(dev, (void *)xfer->tx_buf,
321 xfer->len, DMA_TO_DEVICE);
322 ret = dma_mapping_error(dev, paddr);
323 if (ret) {
324 dev_err(dev, "tx buf map failed\n");
325 return ret;
326 }
327 }
328 desc->tx_paddr = paddr;
329 desc->cfg_start |= FIELD_PREP(CFG_TXD_MODE, SPISG_DATA_MODE_MEM);
330 }
331
332 if (xfer->rx_sg.nents && xfer->rx_sg.sgl) {
333 ccsg_len = xfer->rx_sg.nents * sizeof(struct spisg_sg_link);
334 ccsg = kzalloc(ccsg_len, GFP_KERNEL | GFP_DMA);
335 if (!ccsg) {
336 dev_err(dev, "alloc rx_ccsg failed\n");
337 return -ENOMEM;
338 }
339
340 aml_spisg_sg_xlate(&xfer->rx_sg, ccsg);
341 paddr = dma_map_single(dev, (void *)ccsg,
342 ccsg_len, DMA_TO_DEVICE);
343 ret = dma_mapping_error(dev, paddr);
344 if (ret) {
345 kfree(ccsg);
346 dev_err(dev, "rx ccsg map failed\n");
347 return ret;
348 }
349
350 desc->rx_paddr = paddr;
351 desc->cfg_start |= FIELD_PREP(CFG_RXD_MODE, SPISG_DATA_MODE_SG);
352 exdesc->rx_ccsg = ccsg;
353 exdesc->rx_ccsg_len = ccsg_len;
354 dma_sync_sgtable_for_device(spisg->controller->cur_rx_dma_dev,
355 &xfer->rx_sg, DMA_FROM_DEVICE);
356 } else if (xfer->rx_buf || xfer->rx_dma) {
357 paddr = xfer->rx_dma;
358 if (!paddr) {
359 paddr = dma_map_single(dev, xfer->rx_buf,
360 xfer->len, DMA_FROM_DEVICE);
361 ret = dma_mapping_error(dev, paddr);
362 if (ret) {
363 dev_err(dev, "rx buf map failed\n");
364 return ret;
365 }
366 }
367
368 desc->rx_paddr = paddr;
369 desc->cfg_start |= FIELD_PREP(CFG_RXD_MODE, SPISG_DATA_MODE_MEM);
370 }
371
372 return 0;
373}
374
375static void aml_spisg_cleanup_transfer(struct spisg_device *spisg,
376 struct spi_transfer *xfer,
377 struct spisg_descriptor *desc,
378 struct spisg_descriptor_extra *exdesc)
379{
380 struct device *dev = &spisg->pdev->dev;
381
382 if (desc->tx_paddr) {
383 if (FIELD_GET(CFG_TXD_MODE, desc->cfg_start) == SPISG_DATA_MODE_SG) {
384 dma_unmap_single(dev, (dma_addr_t)desc->tx_paddr,
385 exdesc->tx_ccsg_len, DMA_TO_DEVICE);
386 kfree(exdesc->tx_ccsg);
387 dma_sync_sgtable_for_cpu(spisg->controller->cur_tx_dma_dev,
388 &xfer->tx_sg, DMA_TO_DEVICE);
389 } else if (!xfer->tx_dma) {
390 dma_unmap_single(dev, (dma_addr_t)desc->tx_paddr,
391 xfer->len, DMA_TO_DEVICE);
392 }
393 }
394
395 if (desc->rx_paddr) {
396 if (FIELD_GET(CFG_RXD_MODE, desc->cfg_start) == SPISG_DATA_MODE_SG) {
397 dma_unmap_single(dev, (dma_addr_t)desc->rx_paddr,
398 exdesc->rx_ccsg_len, DMA_TO_DEVICE);
399 kfree(exdesc->rx_ccsg);
400 dma_sync_sgtable_for_cpu(spisg->controller->cur_rx_dma_dev,
401 &xfer->rx_sg, DMA_FROM_DEVICE);
402 } else if (!xfer->rx_dma) {
403 dma_unmap_single(dev, (dma_addr_t)desc->rx_paddr,
404 xfer->len, DMA_FROM_DEVICE);
405 }
406 }
407}
408
409static void aml_spisg_setup_null_desc(struct spisg_device *spisg,
410 struct spisg_descriptor *desc,
411 u32 n_sclk)
412{
413 /* unit is the last xfer sclk */
414 desc->cfg_start = spisg->cfg_start;
415 desc->cfg_bus = spisg->cfg_bus;
416
417 desc->cfg_start |= FIELD_PREP(CFG_OP_MODE, SPISG_OP_MODE_WRITE) |
418 FIELD_PREP(CFG_BLOCK_SIZE, 1) |
419 FIELD_PREP(CFG_BLOCK_NUM, DIV_ROUND_UP(n_sclk, 8));
420
421 desc->cfg_bus |= FIELD_PREP(CFG_NULL_CTL, 1);
422}
423
424static void aml_spisg_pending(struct spisg_device *spisg,
425 dma_addr_t desc_paddr,
426 bool trig,
427 bool irq_en)
428{
429 u32 desc_l, desc_h, cfg_spi, irq_enable;
430
431#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
432 desc_l = (u64)desc_paddr & 0xffffffff;
433 desc_h = (u64)desc_paddr >> 32;
434#else
435 desc_l = desc_paddr & 0xffffffff;
436 desc_h = 0;
437#endif
438
439 cfg_spi = spisg->cfg_spi;
440 if (trig)
441 cfg_spi |= CFG_HW_POS;
442 else
443 desc_h |= LIST_DESC_PENDING;
444
445 irq_enable = IRQ_RCH_DESC_INVALID | IRQ_RCH_DESC_RESP |
446 IRQ_RCH_DATA_RESP | IRQ_WCH_DESC_INVALID |
447 IRQ_WCH_DESC_RESP | IRQ_WCH_DATA_RESP |
448 IRQ_DESC_ERR | IRQ_DESC_CHAIN_DONE;
449 regmap_write(spisg->map, SPISG_REG_IRQ_ENABLE, irq_en ? irq_enable : 0);
450 regmap_write(spisg->map, SPISG_REG_CFG_SPI, cfg_spi);
451 regmap_write(spisg->map, SPISG_REG_DESC_LIST_L, desc_l);
452 regmap_write(spisg->map, SPISG_REG_DESC_LIST_H, desc_h);
453}
454
455static irqreturn_t aml_spisg_irq(int irq, void *data)
456{
457 struct spisg_device *spisg = (void *)data;
458 u32 sts;
459
460 spisg->status = 0;
461 regmap_read(spisg->map, SPISG_REG_IRQ_STS, &sts);
462 regmap_write(spisg->map, SPISG_REG_IRQ_STS, sts);
463 if (sts & (IRQ_RCH_DESC_INVALID |
464 IRQ_RCH_DESC_RESP |
465 IRQ_RCH_DATA_RESP |
466 IRQ_WCH_DESC_INVALID |
467 IRQ_WCH_DESC_RESP |
468 IRQ_WCH_DATA_RESP |
469 IRQ_DESC_ERR))
470 spisg->status = sts;
471 else if (sts & IRQ_DESC_CHAIN_DONE)
472 spisg->status = 0;
473 else
474 return IRQ_NONE;
475
476 complete(&spisg->completion);
477
478 return IRQ_HANDLED;
479}
480
481static int aml_spisg_transfer_one_message(struct spi_controller *ctlr,
482 struct spi_message *msg)
483{
484 struct spisg_device *spisg = spi_controller_get_devdata(ctlr);
485 struct device *dev = &spisg->pdev->dev;
486 unsigned long long ms = 0;
487 struct spi_transfer *xfer;
488 struct spisg_descriptor *descs, *desc;
489 struct spisg_descriptor_extra *exdescs, *exdesc;
490 dma_addr_t descs_paddr;
491 int desc_num = 1, descs_len;
492 u32 cs_hold_in_sclk = 0;
493 int ret = -EIO;
494
495 if (!aml_spisg_sem_down_read(spisg)) {
496 spi_finalize_current_message(ctlr);
497 dev_err(dev, "controller busy\n");
498 return -EBUSY;
499 }
500
501 /* calculate the desc num for all xfer */
502 list_for_each_entry(xfer, &msg->transfers, transfer_list)
503 desc_num++;
504
505 /* alloc descriptor/extra-descriptor table */
506 descs = kcalloc(desc_num, sizeof(*desc) + sizeof(*exdesc),
507 GFP_KERNEL | GFP_DMA);
508 if (!descs) {
509 spi_finalize_current_message(ctlr);
510 aml_spisg_sem_up_write(spisg);
511 return -ENOMEM;
512 }
513 descs_len = sizeof(*desc) * desc_num;
514 exdescs = (struct spisg_descriptor_extra *)(descs + desc_num);
515
516 /* config descriptor for each xfer */
517 desc = descs;
518 exdesc = exdescs;
519 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
520 ret = aml_spisg_setup_transfer(spisg, xfer, desc, exdesc);
521 if (ret) {
522 dev_err(dev, "config descriptor failed\n");
523 goto end;
524 }
525
526 /* calculate cs-setup delay with the first xfer speed */
527 if (list_is_first(&xfer->transfer_list, &msg->transfers))
528 desc->cfg_bus |= FIELD_PREP(CFG_CS_SETUP,
529 spi_delay_to_sclk(xfer->effective_speed_hz, &msg->spi->cs_setup));
530
531 /* calculate cs-hold delay with the last xfer speed */
532 if (list_is_last(&xfer->transfer_list, &msg->transfers))
533 cs_hold_in_sclk =
534 spi_delay_to_sclk(xfer->effective_speed_hz, &msg->spi->cs_hold);
535
536 desc++;
537 exdesc++;
538 ms += DIV_ROUND_UP_ULL(8LL * MSEC_PER_SEC * xfer->len,
539 xfer->effective_speed_hz);
540 }
541
542 if (cs_hold_in_sclk)
543 /* additional null-descriptor to achieve the cs-hold delay */
544 aml_spisg_setup_null_desc(spisg, desc, cs_hold_in_sclk);
545 else
546 desc--;
547
548 desc->cfg_bus |= FIELD_PREP(CFG_KEEP_SS, 0);
549 desc->cfg_start |= FIELD_PREP(CFG_EOC, 1);
550
551 /* some tolerances */
552 ms += ms + 20;
553 if (ms > UINT_MAX)
554 ms = UINT_MAX;
555
556 descs_paddr = dma_map_single(dev, (void *)descs,
557 descs_len, DMA_TO_DEVICE);
558 ret = dma_mapping_error(dev, descs_paddr);
559 if (ret) {
560 dev_err(dev, "desc table map failed\n");
561 goto end;
562 }
563
564 reinit_completion(&spisg->completion);
565 aml_spisg_pending(spisg, descs_paddr, false, true);
566 if (wait_for_completion_timeout(&spisg->completion,
567 spi_controller_is_target(spisg->controller) ?
568 MAX_SCHEDULE_TIMEOUT : msecs_to_jiffies(ms)))
569 ret = spisg->status ? -EIO : 0;
570 else
571 ret = -ETIMEDOUT;
572
573 dma_unmap_single(dev, descs_paddr, descs_len, DMA_TO_DEVICE);
574end:
575 desc = descs;
576 exdesc = exdescs;
577 list_for_each_entry(xfer, &msg->transfers, transfer_list)
578 aml_spisg_cleanup_transfer(spisg, xfer, desc++, exdesc++);
579 kfree(descs);
580
581 if (!ret)
582 msg->actual_length = msg->frame_length;
583 msg->status = ret;
584 spi_finalize_current_message(ctlr);
585 aml_spisg_sem_up_write(spisg);
586
587 return ret;
588}
589
590static int aml_spisg_prepare_message(struct spi_controller *ctlr,
591 struct spi_message *message)
592{
593 struct spisg_device *spisg = spi_controller_get_devdata(ctlr);
594 struct spi_device *spi = message->spi;
595
596 if (!spi->bits_per_word || spi->bits_per_word % 8) {
597 dev_err(&spisg->pdev->dev, "invalid wordlen %d\n", spi->bits_per_word);
598 return -EINVAL;
599 }
600
601 spisg->bytes_per_word = spi->bits_per_word >> 3;
602
603 FIELD_MODIFY(CFG_SLAVE_SELECT, &spisg->cfg_spi, spi_get_chipselect(spi, 0));
604 FIELD_MODIFY(CFG_CPOL, &spisg->cfg_bus, !!(spi->mode & SPI_CPOL));
605 FIELD_MODIFY(CFG_CPHA, &spisg->cfg_bus, !!(spi->mode & SPI_CPHA));
606 FIELD_MODIFY(CFG_B_L_ENDIAN, &spisg->cfg_bus, !!(spi->mode & SPI_LSB_FIRST));
607 FIELD_MODIFY(CFG_HALF_DUPLEX, &spisg->cfg_bus, !!(spi->mode & SPI_3WIRE));
608
609 return 0;
610}
611
612static int aml_spisg_setup(struct spi_device *spi)
613{
614 if (!spi->controller_state)
615 spi->controller_state = spi_controller_get_devdata(spi->controller);
616
617 return 0;
618}
619
620static void aml_spisg_cleanup(struct spi_device *spi)
621{
622 spi->controller_state = NULL;
623}
624
625static int aml_spisg_target_abort(struct spi_controller *ctlr)
626{
627 struct spisg_device *spisg = spi_controller_get_devdata(ctlr);
628
629 spisg->status = 0;
630 regmap_write(spisg->map, SPISG_REG_DESC_LIST_H, 0);
631 complete(&spisg->completion);
632
633 return 0;
634}
635
636static int aml_spisg_clk_init(struct spisg_device *spisg, void __iomem *base)
637{
638 struct device *dev = &spisg->pdev->dev;
639 struct clk_init_data init = {};
640 struct clk_divider *div;
641 struct clk_div_table *tbl;
642 char name[32];
643 int ret, i;
644
645 spisg->core = devm_clk_get_enabled(dev, "core");
646 if (IS_ERR(spisg->core)) {
647 dev_err(dev, "core clock request failed\n");
648 return PTR_ERR(spisg->core);
649 }
650
651 spisg->pclk = devm_clk_get_enabled(dev, "pclk");
652 if (IS_ERR(spisg->pclk)) {
653 dev_err(dev, "pclk clock request failed\n");
654 return PTR_ERR(spisg->pclk);
655 }
656
657 clk_set_min_rate(spisg->pclk, SPISG_PCLK_RATE_MIN);
658
659 clk_disable_unprepare(spisg->pclk);
660
661 tbl = devm_kcalloc(dev, (DIV_NUM + 1), sizeof(*tbl), GFP_KERNEL);
662 if (!tbl)
663 return -ENOMEM;
664
665 for (i = 0; i < DIV_NUM; i++) {
666 tbl[i].val = i + SPISG_CLK_DIV_MIN - 1;
667 tbl[i].div = i + SPISG_CLK_DIV_MIN;
668 }
669 spisg->tbl = tbl;
670
671 div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
672 if (!div)
673 return -ENOMEM;
674
675 div->flags = CLK_DIVIDER_ROUND_CLOSEST;
676 div->reg = base + SPISG_REG_CFG_BUS;
677 div->shift = __bf_shf(CFG_CLK_DIV);
678 div->width = CLK_DIV_WIDTH;
679 div->table = tbl;
680
681 /* Register value should not be outside of the table */
682 regmap_update_bits(spisg->map, SPISG_REG_CFG_BUS, CFG_CLK_DIV,
683 FIELD_PREP(CFG_CLK_DIV, SPISG_CLK_DIV_MIN - 1));
684
685 /* Register clk-divider */
686 snprintf(name, sizeof(name), "%s_div", dev_name(dev));
687 init.name = name;
688 init.ops = &clk_divider_ops;
689 init.flags = CLK_SET_RATE_PARENT;
690 init.parent_data = &(const struct clk_parent_data) {
691 .fw_name = "pclk",
692 };
693 init.num_parents = 1;
694 div->hw.init = &init;
695 ret = devm_clk_hw_register(dev, &div->hw);
696 if (ret) {
697 dev_err(dev, "clock registration failed\n");
698 return ret;
699 }
700
701 spisg->sclk = devm_clk_hw_get_clk(dev, &div->hw, NULL);
702 if (IS_ERR(spisg->sclk)) {
703 dev_err(dev, "get clock failed\n");
704 return PTR_ERR(spisg->sclk);
705 }
706
707 clk_prepare_enable(spisg->sclk);
708
709 return 0;
710}
711
712static int aml_spisg_probe(struct platform_device *pdev)
713{
714 struct spi_controller *ctlr;
715 struct spisg_device *spisg;
716 struct device *dev = &pdev->dev;
717 void __iomem *base;
718 int ret, irq;
719
720 const struct regmap_config aml_regmap_config = {
721 .reg_bits = 32,
722 .val_bits = 32,
723 .reg_stride = 4,
724 .max_register = SPISG_MAX_REG,
725 };
726
727 if (of_property_read_bool(dev->of_node, "spi-slave"))
728 ctlr = devm_spi_alloc_target(dev, sizeof(*spisg));
729 else
730 ctlr = devm_spi_alloc_host(dev, sizeof(*spisg));
731 if (!ctlr)
732 return -ENOMEM;
733
734 spisg = spi_controller_get_devdata(ctlr);
735 spisg->controller = ctlr;
736
737 spisg->pdev = pdev;
738 platform_set_drvdata(pdev, spisg);
739
740 base = devm_platform_ioremap_resource(pdev, 0);
741 if (IS_ERR(base))
742 return dev_err_probe(dev, PTR_ERR(base), "resource ioremap failed\n");
743
744 spisg->map = devm_regmap_init_mmio(dev, base, &aml_regmap_config);
745 if (IS_ERR(spisg->map))
746 return dev_err_probe(dev, PTR_ERR(spisg->map), "regmap init failed\n");
747
748 irq = platform_get_irq(pdev, 0);
749 if (irq < 0)
750 return irq;
751
752 ret = device_reset_optional(dev);
753 if (ret)
754 return dev_err_probe(dev, ret, "reset dev failed\n");
755
756 ret = aml_spisg_clk_init(spisg, base);
757 if (ret)
758 return dev_err_probe(dev, ret, "clock init failed\n");
759
760 spisg->cfg_spi = 0;
761 spisg->cfg_start = 0;
762 spisg->cfg_bus = 0;
763
764 spisg->cfg_spi = FIELD_PREP(CFG_SFLASH_WP, 1) |
765 FIELD_PREP(CFG_SFLASH_HD, 1);
766 if (spi_controller_is_target(ctlr)) {
767 spisg->cfg_spi |= FIELD_PREP(CFG_SLAVE_EN, 1);
768 spisg->cfg_bus = FIELD_PREP(CFG_TX_TUNING, 0xf);
769 }
770 /* default pending */
771 spisg->cfg_start = FIELD_PREP(CFG_PEND, 1);
772
773 pm_runtime_set_active(&spisg->pdev->dev);
774 pm_runtime_enable(&spisg->pdev->dev);
775 pm_runtime_resume_and_get(&spisg->pdev->dev);
776
777 ctlr->num_chipselect = 4;
778 ctlr->mode_bits = SPI_CPHA | SPI_CPOL | SPI_LSB_FIRST |
779 SPI_3WIRE | SPI_TX_QUAD | SPI_RX_QUAD;
780 ctlr->max_speed_hz = 1000 * 1000 * 100;
781 ctlr->min_speed_hz = 1000 * 10;
782 ctlr->setup = aml_spisg_setup;
783 ctlr->cleanup = aml_spisg_cleanup;
784 ctlr->prepare_message = aml_spisg_prepare_message;
785 ctlr->transfer_one_message = aml_spisg_transfer_one_message;
786 ctlr->target_abort = aml_spisg_target_abort;
787 ctlr->can_dma = aml_spisg_can_dma;
788 ctlr->max_dma_len = SPISG_BLOCK_MAX;
789 ctlr->auto_runtime_pm = true;
790
791 dma_set_max_seg_size(&pdev->dev, SPISG_BLOCK_MAX);
792
793 init_completion(&spisg->completion);
794 ret = devm_request_irq(&pdev->dev, irq, aml_spisg_irq, 0, NULL, spisg);
795 if (ret) {
796 dev_err(&pdev->dev, "irq request failed\n");
797 goto out_clk;
798 }
799
800 ret = spi_register_controller(ctlr);
801 if (ret) {
802 dev_err(&pdev->dev, "spi controller registration failed\n");
803 goto out_clk;
804 }
805
806 pm_runtime_put(&spisg->pdev->dev);
807
808 return 0;
809out_clk:
810 if (spisg->core)
811 clk_disable_unprepare(spisg->core);
812 clk_disable_unprepare(spisg->pclk);
813
814 return ret;
815}
816
817static void aml_spisg_remove(struct platform_device *pdev)
818{
819 struct spisg_device *spisg = platform_get_drvdata(pdev);
820
821 spi_unregister_controller(spisg->controller);
822
823 if (!pm_runtime_suspended(&pdev->dev)) {
824 pinctrl_pm_select_sleep_state(&spisg->pdev->dev);
825 clk_disable_unprepare(spisg->core);
826 clk_disable_unprepare(spisg->pclk);
827 }
828}
829
830static int spisg_suspend_runtime(struct device *dev)
831{
832 struct spisg_device *spisg = dev_get_drvdata(dev);
833
834 pinctrl_pm_select_sleep_state(&spisg->pdev->dev);
835 clk_disable_unprepare(spisg->sclk);
836 clk_disable_unprepare(spisg->core);
837
838 return 0;
839}
840
841static int spisg_resume_runtime(struct device *dev)
842{
843 struct spisg_device *spisg = dev_get_drvdata(dev);
844
845 clk_prepare_enable(spisg->core);
846 clk_prepare_enable(spisg->sclk);
847 pinctrl_pm_select_default_state(&spisg->pdev->dev);
848
849 return 0;
850}
851
852static const struct dev_pm_ops amlogic_spisg_pm_ops = {
853 .runtime_suspend = spisg_suspend_runtime,
854 .runtime_resume = spisg_resume_runtime,
855};
856
857static const struct of_device_id amlogic_spisg_of_match[] = {
858 {
859 .compatible = "amlogic,a4-spisg",
860 },
861
862 { /* sentinel */ }
863};
864MODULE_DEVICE_TABLE(of, amlogic_spisg_of_match);
865
866static struct platform_driver amlogic_spisg_driver = {
867 .probe = aml_spisg_probe,
868 .remove = aml_spisg_remove,
869 .driver = {
870 .name = "amlogic-spisg",
871 .of_match_table = amlogic_spisg_of_match,
872 .pm = &amlogic_spisg_pm_ops,
873 },
874};
875
876module_platform_driver(amlogic_spisg_driver);
877
878MODULE_DESCRIPTION("Amlogic SPI Scatter-Gather Controller driver");
879MODULE_AUTHOR("Sunny Luo <[email protected]>");
880MODULE_LICENSE("GPL");