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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Driver for Andes ATCSPI200 SPI Controller
4 *
5 * Copyright (C) 2025 Andes Technology Corporation.
6 */
7
8#include <linux/bitfield.h>
9#include <linux/clk.h>
10#include <linux/completion.h>
11#include <linux/dev_printk.h>
12#include <linux/dmaengine.h>
13#include <linux/err.h>
14#include <linux/errno.h>
15#include <linux/jiffies.h>
16#include <linux/minmax.h>
17#include <linux/module.h>
18#include <linux/mutex.h>
19#include <linux/platform_device.h>
20#include <linux/regmap.h>
21#include <linux/spi/spi.h>
22#include <linux/spi/spi-mem.h>
23
24/* Register definitions */
25#define ATCSPI_TRANS_FMT 0x10 /* SPI transfer format register */
26#define ATCSPI_TRANS_CTRL 0x20 /* SPI transfer control register */
27#define ATCSPI_CMD 0x24 /* SPI command register */
28#define ATCSPI_ADDR 0x28 /* SPI address register */
29#define ATCSPI_DATA 0x2C /* SPI data register */
30#define ATCSPI_CTRL 0x30 /* SPI control register */
31#define ATCSPI_STATUS 0x34 /* SPI status register */
32#define ATCSPI_TIMING 0x40 /* SPI interface timing register */
33#define ATCSPI_CONFIG 0x7C /* SPI configuration register */
34
35/* Transfer format register */
36#define TRANS_FMT_CPHA BIT(0)
37#define TRANS_FMT_CPOL BIT(1)
38#define TRANS_FMT_DATA_MERGE_EN BIT(7)
39#define TRANS_FMT_DATA_LEN_MASK GENMASK(12, 8)
40#define TRANS_FMT_ADDR_LEN_MASK GENMASK(17, 16)
41#define TRANS_FMT_DATA_LEN(x) FIELD_PREP(TRANS_FMT_DATA_LEN_MASK, (x) - 1)
42#define TRANS_FMT_ADDR_LEN(x) FIELD_PREP(TRANS_FMT_ADDR_LEN_MASK, (x) - 1)
43
44/* Transfer control register */
45#define TRANS_MODE_MASK GENMASK(27, 24)
46#define TRANS_MODE_W_ONLY FIELD_PREP(TRANS_MODE_MASK, 1)
47#define TRANS_MODE_R_ONLY FIELD_PREP(TRANS_MODE_MASK, 2)
48#define TRANS_MODE_NONE_DATA FIELD_PREP(TRANS_MODE_MASK, 7)
49#define TRANS_MODE_DMY_READ FIELD_PREP(TRANS_MODE_MASK, 9)
50#define TRANS_FIELD_DECNZ(m, x) ((x) ? FIELD_PREP(m, (x) - 1) : 0)
51#define TRANS_RD_TRANS_CNT(x) TRANS_FIELD_DECNZ(GENMASK(8, 0), x)
52#define TRANS_DUMMY_CNT(x) TRANS_FIELD_DECNZ(GENMASK(10, 9), x)
53#define TRANS_WR_TRANS_CNT(x) TRANS_FIELD_DECNZ(GENMASK(20, 12), x)
54#define TRANS_DUAL_QUAD(x) FIELD_PREP(GENMASK(23, 22), (x))
55#define TRANS_ADDR_FMT BIT(28)
56#define TRANS_ADDR_EN BIT(29)
57#define TRANS_CMD_EN BIT(30)
58
59/* Control register */
60#define CTRL_SPI_RST BIT(0)
61#define CTRL_RX_FIFO_RST BIT(1)
62#define CTRL_TX_FIFO_RST BIT(2)
63#define CTRL_RX_DMA_EN BIT(3)
64#define CTRL_TX_DMA_EN BIT(4)
65
66/* Status register */
67#define ATCSPI_ACTIVE BIT(0)
68#define ATCSPI_RX_EMPTY BIT(14)
69#define ATCSPI_TX_FULL BIT(23)
70
71/* Interface timing setting */
72#define TIMING_SCLK_DIV_MASK GENMASK(7, 0)
73#define TIMING_SCLK_DIV_MAX 0xFE
74
75/* Configuration register */
76#define RXFIFO_SIZE(x) FIELD_GET(GENMASK(3, 0), (x))
77#define TXFIFO_SIZE(x) FIELD_GET(GENMASK(7, 4), (x))
78
79/* driver configurations */
80#define ATCSPI_MAX_TRANS_LEN 512
81#define ATCSPI_MAX_SPEED_HZ 50000000
82#define ATCSPI_RDY_TIMEOUT_US 1000000
83#define ATCSPI_XFER_TIMEOUT(n) ((n) * 10)
84#define ATCSPI_MAX_CS_NUM 1
85#define ATCSPI_DMA_THRESHOLD 256
86#define ATCSPI_BITS_PER_UINT 8
87#define ATCSPI_DATA_MERGE_EN 1
88#define ATCSPI_DMA_SUPPORT 1
89
90/**
91 * struct atcspi_dev - Andes ATCSPI200 SPI controller private data
92 * @host: Pointer to the SPI controller structure.
93 * @mutex_lock: A mutex to protect concurrent access to the controller.
94 * @dma_completion: A completion to signal the end of a DMA transfer.
95 * @dev: Pointer to the device structure.
96 * @regmap: Register map for accessing controller registers.
97 * @clk: Pointer to the controller's functional clock.
98 * @dma_addr: The physical address of the SPI data register for DMA.
99 * @clk_rate: The cached frequency of the functional clock.
100 * @sclk_rate: The target frequency for the SPI clock (SCLK).
101 * @txfifo_size: The size of the transmit FIFO in bytes.
102 * @rxfifo_size: The size of the receive FIFO in bytes.
103 * @data_merge: A flag indicating if the data merge mode is enabled for
104 * the current transfer.
105 * @use_dma: Enable DMA mode if ATCSPI_DMA_SUPPORT is set and DMA is
106 * successfully configured.
107 */
108struct atcspi_dev {
109 struct spi_controller *host;
110 struct mutex mutex_lock;
111 struct completion dma_completion;
112 struct device *dev;
113 struct regmap *regmap;
114 struct clk *clk;
115 dma_addr_t dma_addr;
116 unsigned int clk_rate;
117 unsigned int sclk_rate;
118 unsigned int txfifo_size;
119 unsigned int rxfifo_size;
120 bool data_merge;
121 bool use_dma;
122};
123
124static int atcspi_wait_fifo_ready(struct atcspi_dev *spi,
125 enum spi_mem_data_dir dir)
126{
127 unsigned int val;
128 unsigned int mask;
129 int ret;
130
131 mask = (dir == SPI_MEM_DATA_OUT) ? ATCSPI_TX_FULL : ATCSPI_RX_EMPTY;
132 ret = regmap_read_poll_timeout(spi->regmap,
133 ATCSPI_STATUS,
134 val,
135 !(val & mask),
136 0,
137 ATCSPI_RDY_TIMEOUT_US);
138 if (ret)
139 dev_info(spi->dev, "Timed out waiting for FIFO ready\n");
140
141 return ret;
142}
143
144static int atcspi_xfer_data_poll(struct atcspi_dev *spi,
145 const struct spi_mem_op *op)
146{
147 void *rx_buf = op->data.buf.in;
148 const void *tx_buf = op->data.buf.out;
149 unsigned int val;
150 int trans_bytes = op->data.nbytes;
151 int num_byte;
152 int ret = 0;
153
154 num_byte = spi->data_merge ? 4 : 1;
155 while (trans_bytes) {
156 if (op->data.dir == SPI_MEM_DATA_OUT) {
157 ret = atcspi_wait_fifo_ready(spi, SPI_MEM_DATA_OUT);
158 if (ret)
159 return ret;
160
161 if (spi->data_merge)
162 val = *(unsigned int *)tx_buf;
163 else
164 val = *(unsigned char *)tx_buf;
165 regmap_write(spi->regmap, ATCSPI_DATA, val);
166 tx_buf = (unsigned char *)tx_buf + num_byte;
167 } else {
168 ret = atcspi_wait_fifo_ready(spi, SPI_MEM_DATA_IN);
169 if (ret)
170 return ret;
171
172 regmap_read(spi->regmap, ATCSPI_DATA, &val);
173 if (spi->data_merge)
174 *(unsigned int *)rx_buf = val;
175 else
176 *(unsigned char *)rx_buf = (unsigned char)val;
177 rx_buf = (unsigned char *)rx_buf + num_byte;
178 }
179 trans_bytes -= num_byte;
180 }
181
182 return ret;
183}
184
185static void atcspi_set_trans_ctl(struct atcspi_dev *spi,
186 const struct spi_mem_op *op)
187{
188 unsigned int tc = 0;
189
190 if (op->cmd.nbytes)
191 tc |= TRANS_CMD_EN;
192 if (op->addr.nbytes)
193 tc |= TRANS_ADDR_EN;
194 if (op->addr.buswidth > 1)
195 tc |= TRANS_ADDR_FMT;
196 if (op->data.nbytes) {
197 unsigned int width_code;
198
199 width_code = ffs(op->data.buswidth) - 1;
200 if (unlikely(width_code > 3)) {
201 WARN_ON_ONCE(1);
202 width_code = 0;
203 }
204 tc |= TRANS_DUAL_QUAD(width_code);
205
206 if (op->data.dir == SPI_MEM_DATA_IN) {
207 if (op->dummy.nbytes)
208 tc |= TRANS_MODE_DMY_READ |
209 TRANS_DUMMY_CNT(op->dummy.nbytes);
210 else
211 tc |= TRANS_MODE_R_ONLY;
212 tc |= TRANS_RD_TRANS_CNT(op->data.nbytes);
213 } else {
214 tc |= TRANS_MODE_W_ONLY |
215 TRANS_WR_TRANS_CNT(op->data.nbytes);
216 }
217 } else {
218 tc |= TRANS_MODE_NONE_DATA;
219 }
220 regmap_write(spi->regmap, ATCSPI_TRANS_CTRL, tc);
221}
222
223static void atcspi_set_trans_fmt(struct atcspi_dev *spi,
224 const struct spi_mem_op *op)
225{
226 unsigned int val;
227
228 regmap_read(spi->regmap, ATCSPI_TRANS_FMT, &val);
229 if (op->data.nbytes) {
230 if (ATCSPI_DATA_MERGE_EN && ATCSPI_BITS_PER_UINT == 8 &&
231 !(op->data.nbytes % 4)) {
232 val |= TRANS_FMT_DATA_MERGE_EN;
233 spi->data_merge = true;
234 } else {
235 val &= ~TRANS_FMT_DATA_MERGE_EN;
236 spi->data_merge = false;
237 }
238 }
239
240 val = (val & ~TRANS_FMT_ADDR_LEN_MASK) |
241 TRANS_FMT_ADDR_LEN(op->addr.nbytes);
242 regmap_write(spi->regmap, ATCSPI_TRANS_FMT, val);
243}
244
245static void atcspi_prepare_trans(struct atcspi_dev *spi,
246 const struct spi_mem_op *op)
247{
248 atcspi_set_trans_fmt(spi, op);
249 atcspi_set_trans_ctl(spi, op);
250 if (op->addr.nbytes)
251 regmap_write(spi->regmap, ATCSPI_ADDR, op->addr.val);
252 regmap_write(spi->regmap, ATCSPI_CMD, op->cmd.opcode);
253}
254
255static int atcspi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op)
256{
257 struct atcspi_dev *spi;
258
259 spi = spi_controller_get_devdata(mem->spi->controller);
260 op->data.nbytes = min(op->data.nbytes, ATCSPI_MAX_TRANS_LEN);
261
262 /* DMA needs to be aligned to 4 byte */
263 if (spi->use_dma && op->data.nbytes >= ATCSPI_DMA_THRESHOLD)
264 op->data.nbytes = ALIGN_DOWN(op->data.nbytes, 4);
265
266 return 0;
267}
268
269static int atcspi_dma_config(struct atcspi_dev *spi, bool is_rx)
270{
271 struct dma_slave_config conf = { 0 };
272 struct dma_chan *chan;
273
274 if (is_rx) {
275 chan = spi->host->dma_rx;
276 conf.direction = DMA_DEV_TO_MEM;
277 conf.src_addr = spi->dma_addr;
278 } else {
279 chan = spi->host->dma_tx;
280 conf.direction = DMA_MEM_TO_DEV;
281 conf.dst_addr = spi->dma_addr;
282 }
283 conf.dst_maxburst = spi->rxfifo_size / 2;
284 conf.src_maxburst = spi->txfifo_size / 2;
285
286 if (spi->data_merge) {
287 conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
288 conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
289 } else {
290 conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
291 conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
292 }
293
294 return dmaengine_slave_config(chan, &conf);
295}
296
297static void atcspi_dma_callback(void *arg)
298{
299 struct completion *dma_completion = arg;
300
301 complete(dma_completion);
302}
303
304static int atcspi_dma_trans(struct atcspi_dev *spi,
305 const struct spi_mem_op *op)
306{
307 struct dma_async_tx_descriptor *desc;
308 struct dma_chan *dma_ch;
309 struct sg_table sgt;
310 enum dma_transfer_direction dma_dir;
311 dma_cookie_t cookie;
312 unsigned int ctrl;
313 int timeout;
314 int ret;
315
316 regmap_read(spi->regmap, ATCSPI_CTRL, &ctrl);
317 ctrl |= CTRL_TX_DMA_EN | CTRL_RX_DMA_EN;
318 regmap_write(spi->regmap, ATCSPI_CTRL, ctrl);
319 if (op->data.dir == SPI_MEM_DATA_IN) {
320 ret = atcspi_dma_config(spi, TRUE);
321 dma_dir = DMA_DEV_TO_MEM;
322 dma_ch = spi->host->dma_rx;
323 } else {
324 ret = atcspi_dma_config(spi, FALSE);
325 dma_dir = DMA_MEM_TO_DEV;
326 dma_ch = spi->host->dma_tx;
327 }
328 if (ret)
329 return ret;
330
331 ret = spi_controller_dma_map_mem_op_data(spi->host, op, &sgt);
332 if (ret)
333 return ret;
334
335 desc = dmaengine_prep_slave_sg(dma_ch, sgt.sgl, sgt.nents, dma_dir,
336 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
337 if (!desc) {
338 ret = -ENOMEM;
339 goto exit_unmap;
340 }
341
342 reinit_completion(&spi->dma_completion);
343 desc->callback = atcspi_dma_callback;
344 desc->callback_param = &spi->dma_completion;
345 cookie = dmaengine_submit(desc);
346 ret = dma_submit_error(cookie);
347 if (ret)
348 goto exit_unmap;
349
350 dma_async_issue_pending(dma_ch);
351 timeout = msecs_to_jiffies(ATCSPI_XFER_TIMEOUT(op->data.nbytes));
352 if (!wait_for_completion_timeout(&spi->dma_completion, timeout)) {
353 ret = -ETIMEDOUT;
354 dmaengine_terminate_all(dma_ch);
355 }
356
357exit_unmap:
358 spi_controller_dma_unmap_mem_op_data(spi->host, op, &sgt);
359
360 return ret;
361}
362
363static int atcspi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op)
364{
365 struct spi_device *spi_dev = mem->spi;
366 struct atcspi_dev *spi;
367 unsigned int val;
368 int ret;
369
370 spi = spi_controller_get_devdata(spi_dev->controller);
371 mutex_lock(&spi->mutex_lock);
372 atcspi_prepare_trans(spi, op);
373 if (op->data.nbytes) {
374 if (spi->use_dma && op->data.nbytes >= ATCSPI_DMA_THRESHOLD)
375 ret = atcspi_dma_trans(spi, op);
376 else
377 ret = atcspi_xfer_data_poll(spi, op);
378 if (ret) {
379 dev_info(spi->dev, "SPI transmission failed\n");
380 goto exec_mem_exit;
381 }
382 }
383
384 ret = regmap_read_poll_timeout(spi->regmap,
385 ATCSPI_STATUS,
386 val,
387 !(val & ATCSPI_ACTIVE),
388 0,
389 ATCSPI_RDY_TIMEOUT_US);
390 if (ret)
391 dev_info(spi->dev, "Timed out waiting for ATCSPI_ACTIVE\n");
392
393exec_mem_exit:
394 mutex_unlock(&spi->mutex_lock);
395
396 return ret;
397}
398
399static const struct spi_controller_mem_ops atcspi_mem_ops = {
400 .exec_op = atcspi_exec_mem_op,
401 .adjust_op_size = atcspi_adjust_op_size,
402};
403
404static int atcspi_setup(struct atcspi_dev *spi)
405{
406 unsigned int ctrl_val;
407 unsigned int val;
408 int actual_spi_sclk_f;
409 int ret;
410 unsigned char div;
411
412 ctrl_val = CTRL_TX_FIFO_RST | CTRL_RX_FIFO_RST | CTRL_SPI_RST;
413 regmap_write(spi->regmap, ATCSPI_CTRL, ctrl_val);
414 ret = regmap_read_poll_timeout(spi->regmap,
415 ATCSPI_CTRL,
416 val,
417 !(val & ctrl_val),
418 0,
419 ATCSPI_RDY_TIMEOUT_US);
420 if (ret)
421 return dev_err_probe(spi->dev, ret,
422 "Timed out waiting for ATCSPI_CTRL\n");
423
424 val = TRANS_FMT_DATA_LEN(ATCSPI_BITS_PER_UINT) |
425 TRANS_FMT_CPHA | TRANS_FMT_CPOL;
426 regmap_write(spi->regmap, ATCSPI_TRANS_FMT, val);
427
428 regmap_read(spi->regmap, ATCSPI_CONFIG, &val);
429 spi->txfifo_size = BIT(TXFIFO_SIZE(val) + 1);
430 spi->rxfifo_size = BIT(RXFIFO_SIZE(val) + 1);
431
432 regmap_read(spi->regmap, ATCSPI_TIMING, &val);
433 val &= ~TIMING_SCLK_DIV_MASK;
434
435 /*
436 * The SCLK_DIV value 0xFF is special and indicates that the
437 * SCLK rate should be the same as the SPI clock rate.
438 */
439 if (spi->sclk_rate >= spi->clk_rate) {
440 div = TIMING_SCLK_DIV_MASK;
441 } else {
442 /*
443 * The divider value is determined as follows:
444 * 1. If the divider can generate the exact target frequency,
445 * use that setting.
446 * 2. If an exact match is not possible, select the closest
447 * available setting that is lower than the target frequency.
448 */
449 div = (spi->clk_rate + (spi->sclk_rate * 2 - 1)) /
450 (spi->sclk_rate * 2) - 1;
451
452 /* Check if the actual SPI clock is lower than the target */
453 actual_spi_sclk_f = spi->clk_rate / ((div + 1) * 2);
454 if (actual_spi_sclk_f < spi->sclk_rate)
455 dev_info(spi->dev,
456 "Clock adjusted %d to %d due to divider limitation",
457 spi->sclk_rate, actual_spi_sclk_f);
458
459 if (div > TIMING_SCLK_DIV_MAX)
460 return dev_err_probe(spi->dev, -EINVAL,
461 "Unsupported SPI clock %d\n",
462 spi->sclk_rate);
463 }
464 val |= div;
465 regmap_write(spi->regmap, ATCSPI_TIMING, val);
466
467 return ret;
468}
469
470static int atcspi_init_resources(struct platform_device *pdev,
471 struct atcspi_dev *spi,
472 struct resource **mem_res)
473{
474 void __iomem *base;
475 const struct regmap_config atcspi_regmap_cfg = {
476 .name = "atcspi",
477 .reg_bits = 32,
478 .val_bits = 32,
479 .cache_type = REGCACHE_NONE,
480 .reg_stride = 4,
481 .pad_bits = 0,
482 .max_register = ATCSPI_CONFIG
483 };
484
485 base = devm_platform_get_and_ioremap_resource(pdev, 0, mem_res);
486 if (IS_ERR(base))
487 return dev_err_probe(spi->dev, PTR_ERR(base),
488 "Failed to get ioremap resource\n");
489
490 spi->regmap = devm_regmap_init_mmio(spi->dev, base,
491 &atcspi_regmap_cfg);
492 if (IS_ERR(spi->regmap))
493 return dev_err_probe(spi->dev, PTR_ERR(spi->regmap),
494 "Failed to init regmap\n");
495
496 spi->sclk_rate = ATCSPI_MAX_SPEED_HZ;
497 return 0;
498}
499
500static int atcspi_configure_dma(struct atcspi_dev *spi)
501{
502 spi->host->dma_rx = devm_dma_request_chan(spi->dev, "rx");
503 if (IS_ERR(spi->host->dma_rx))
504 return PTR_ERR(spi->host->dma_rx);
505
506 spi->host->dma_tx = devm_dma_request_chan(spi->dev, "tx");
507 if (IS_ERR(spi->host->dma_tx))
508 return PTR_ERR(spi->host->dma_tx);
509
510 init_completion(&spi->dma_completion);
511
512 return 0;
513}
514
515static int atcspi_enable_clk(struct atcspi_dev *spi)
516{
517 spi->clk = devm_clk_get_enabled(spi->dev, NULL);
518 if (IS_ERR(spi->clk))
519 return dev_err_probe(spi->dev, PTR_ERR(spi->clk),
520 "Failed to get SPI clock\n");
521 spi->clk_rate = clk_get_rate(spi->clk);
522 if (!spi->clk_rate)
523 return dev_err_probe(spi->dev, -EINVAL,
524 "Failed to get SPI clock rate\n");
525
526 return 0;
527}
528
529static void atcspi_init_controller(struct platform_device *pdev,
530 struct atcspi_dev *spi,
531 struct spi_controller *host,
532 struct resource *mem_res)
533{
534 /* Get the physical address of the data register for DMA transfers. */
535 spi->dma_addr = (dma_addr_t)(mem_res->start + ATCSPI_DATA);
536
537 /* Initialize controller properties */
538 host->bus_num = pdev->id;
539 host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_QUAD | SPI_TX_QUAD;
540 host->num_chipselect = ATCSPI_MAX_CS_NUM;
541 host->mem_ops = &atcspi_mem_ops;
542 host->max_speed_hz = spi->sclk_rate;
543}
544
545static int atcspi_probe(struct platform_device *pdev)
546{
547 struct spi_controller *host;
548 struct atcspi_dev *spi;
549 struct resource *mem_res;
550 int ret;
551
552 host = devm_spi_alloc_host(&pdev->dev, sizeof(*spi));
553 if (!host)
554 return -ENOMEM;
555
556 spi = spi_controller_get_devdata(host);
557 spi->host = host;
558 spi->dev = &pdev->dev;
559 dev_set_drvdata(&pdev->dev, host);
560
561 ret = devm_mutex_init(&pdev->dev, &spi->mutex_lock);
562 if (ret)
563 return ret;
564
565 ret = atcspi_init_resources(pdev, spi, &mem_res);
566 if (ret)
567 return ret;
568
569 ret = atcspi_enable_clk(spi);
570 if (ret)
571 return ret;
572
573 atcspi_init_controller(pdev, spi, host, mem_res);
574
575 ret = atcspi_setup(spi);
576 if (ret)
577 return ret;
578
579 spi->use_dma = false;
580 if (ATCSPI_DMA_SUPPORT) {
581 ret = atcspi_configure_dma(spi);
582 if (ret)
583 dev_info(spi->dev,
584 "Failed to init DMA, fallback to PIO mode\n");
585 else
586 spi->use_dma = true;
587 }
588
589 ret = devm_spi_register_controller(&pdev->dev, host);
590 if (ret)
591 return dev_err_probe(spi->dev, ret,
592 "Failed to register SPI controller\n");
593
594 return 0;
595}
596
597static int atcspi_suspend(struct device *dev)
598{
599 struct spi_controller *host = dev_get_drvdata(dev);
600 struct atcspi_dev *spi = spi_controller_get_devdata(host);
601 int ret;
602
603 ret = spi_controller_suspend(host);
604 if (ret)
605 return ret;
606
607 clk_disable_unprepare(spi->clk);
608
609 return 0;
610}
611
612static int atcspi_resume(struct device *dev)
613{
614 struct spi_controller *host = dev_get_drvdata(dev);
615 struct atcspi_dev *spi = spi_controller_get_devdata(host);
616 int ret;
617
618 ret = clk_prepare_enable(spi->clk);
619 if (ret)
620 return ret;
621
622 ret = atcspi_setup(spi);
623 if (ret)
624 goto disable_clk;
625
626 ret = spi_controller_resume(host);
627 if (ret)
628 goto disable_clk;
629
630 return ret;
631
632disable_clk:
633 clk_disable_unprepare(spi->clk);
634
635 return ret;
636}
637
638static DEFINE_SIMPLE_DEV_PM_OPS(atcspi_pm_ops, atcspi_suspend, atcspi_resume);
639
640static const struct of_device_id atcspi_of_match[] = {
641 { .compatible = "andestech,ae350-spi", },
642 { /* sentinel */ }
643};
644
645MODULE_DEVICE_TABLE(of, atcspi_of_match);
646
647static struct platform_driver atcspi_driver = {
648 .probe = atcspi_probe,
649 .driver = {
650 .name = "atcspi200",
651 .of_match_table = atcspi_of_match,
652 .pm = pm_sleep_ptr(&atcspi_pm_ops)
653 }
654};
655module_platform_driver(atcspi_driver);
656
657MODULE_AUTHOR("CL Wang <[email protected]>");
658MODULE_DESCRIPTION("Andes ATCSPI200 SPI controller driver");
659MODULE_LICENSE("GPL");