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| 2 | |
| 3 | * Cavium ThunderX SPI driver.
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| 4 | *
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| 5 | * Copyright (C) 2016 Cavium Inc.
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| 6 | * Authors: Jan Glauber <[email protected]>
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| 7 |
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| 8 |
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| 9 | #include <linux/module.h>
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| 10 | #include <linux/pci.h>
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| 11 | #include <linux/spi/spi.h>
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| 12 |
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| 13 | #include "spi-cavium.h"
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| 14 |
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| 15 | #define DRV_NAME "spi-thunderx"
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| 16 |
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| 17 | #define SYS_FREQ_DEFAULT 700000000
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| 18 |
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| 19 | static int thunderx_spi_probe(struct pci_dev *pdev,
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| 20 | const struct pci_device_id *ent)
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| 21 | {
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| 22 | struct device *dev = &pdev->dev;
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| 23 | struct spi_controller *host;
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| 24 | struct octeon_spi *p;
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| 25 | int ret;
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| 26 |
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| 27 | host = devm_spi_alloc_host(dev, sizeof(struct octeon_spi));
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| 28 | if (!host)
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| 29 | return -ENOMEM;
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| 30 |
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| 31 | p = spi_controller_get_devdata(host);
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| 32 |
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| 33 | ret = pcim_enable_device(pdev);
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| 34 | if (ret)
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| 35 | return ret;
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| 36 |
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| 37 | ret = pcim_request_all_regions(pdev, DRV_NAME);
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| 38 | if (ret)
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| 39 | return ret;
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| 40 |
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| 41 | p->register_base = pcim_iomap(pdev, 0, pci_resource_len(pdev, 0));
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| 42 | if (!p->register_base)
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| 43 | return -EINVAL;
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| 44 |
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| 45 | p->regs.config = 0x1000;
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| 46 | p->regs.status = 0x1008;
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| 47 | p->regs.tx = 0x1010;
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| 48 | p->regs.data = 0x1080;
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| 49 |
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| 50 | p->clk = devm_clk_get_enabled(dev, NULL);
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| 51 | if (IS_ERR(p->clk))
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| 52 | return PTR_ERR(p->clk);
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| 53 |
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| 54 | p->sys_freq = clk_get_rate(p->clk);
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| 55 | if (!p->sys_freq)
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| 56 | p->sys_freq = SYS_FREQ_DEFAULT;
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| 57 | dev_info(dev, "Set system clock to %u\n", p->sys_freq);
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| 58 |
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| 59 | host->flags = SPI_CONTROLLER_HALF_DUPLEX;
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| 60 | host->num_chipselect = 4;
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| 61 | host->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH |
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| 62 | SPI_LSB_FIRST | SPI_3WIRE;
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| 63 | host->transfer_one_message = octeon_spi_transfer_one_message;
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| 64 | host->bits_per_word_mask = SPI_BPW_MASK(8);
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| 65 | host->max_speed_hz = OCTEON_SPI_MAX_CLOCK_HZ;
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| 66 |
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| 67 | pci_set_drvdata(pdev, host);
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| 68 |
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| 69 | return spi_register_controller(host);
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| 70 | }
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| 71 |
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| 72 | static void thunderx_spi_remove(struct pci_dev *pdev)
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| 73 | {
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| 74 | struct spi_controller *host = pci_get_drvdata(pdev);
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| 75 | struct octeon_spi *p;
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| 76 |
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| 77 | p = spi_controller_get_devdata(host);
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| 78 | if (!p)
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| 79 | return;
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| 80 |
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| 81 | spi_unregister_controller(host);
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| 82 |
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| 83 |
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| 84 | writeq(0, p->register_base + OCTEON_SPI_CFG(p));
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| 85 | }
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| 86 |
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| 87 | static const struct pci_device_id thunderx_spi_pci_id_table[] = {
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| 88 | { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, 0xa00b) },
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| 89 | { 0, }
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| 90 | };
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| 91 |
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| 92 | MODULE_DEVICE_TABLE(pci, thunderx_spi_pci_id_table);
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| 93 |
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| 94 | static struct pci_driver thunderx_spi_driver = {
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| 95 | .name = DRV_NAME,
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| 96 | .id_table = thunderx_spi_pci_id_table,
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| 97 | .probe = thunderx_spi_probe,
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| 98 | .remove = thunderx_spi_remove,
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| 99 | };
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| 100 |
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| 101 | module_pci_driver(thunderx_spi_driver);
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| 102 |
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| 103 | MODULE_DESCRIPTION("Cavium, Inc. ThunderX SPI bus driver");
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| 104 | MODULE_AUTHOR("Jan Glauber");
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| 105 | MODULE_LICENSE("GPL");
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