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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Memory-mapped interface driver for DW SPI Core
4 *
5 * Copyright (c) 2010, Octasic semiconductor.
6 */
7
8#include <linux/clk.h>
9#include <linux/err.h>
10#include <linux/platform_device.h>
11#include <linux/pm_runtime.h>
12#include <linux/slab.h>
13#include <linux/spi/spi.h>
14#include <linux/scatterlist.h>
15#include <linux/mfd/syscon.h>
16#include <linux/module.h>
17#include <linux/of.h>
18#include <linux/of_platform.h>
19#include <linux/acpi.h>
20#include <linux/property.h>
21#include <linux/regmap.h>
22#include <linux/reset.h>
23
24#include "spi-dw.h"
25
26#define DRIVER_NAME "dw_spi_mmio"
27
28struct dw_spi_mmio {
29 struct dw_spi dws;
30 struct clk *clk;
31 struct clk *pclk;
32 void *priv;
33 struct reset_control *rstc;
34 void (*platform_suspend)(struct dw_spi_mmio *dwsmmio);
35 int (*platform_resume)(struct dw_spi_mmio *dwsmmio);
36};
37
38#define MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL 0x24
39#define OCELOT_IF_SI_OWNER_OFFSET 4
40#define JAGUAR2_IF_SI_OWNER_OFFSET 6
41#define MSCC_IF_SI_OWNER_MASK GENMASK(1, 0)
42#define MSCC_IF_SI_OWNER_SISL 0
43#define MSCC_IF_SI_OWNER_SIBM 1
44#define MSCC_IF_SI_OWNER_SIMC 2
45
46#define MSCC_SPI_MST_SW_MODE 0x14
47#define MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE BIT(13)
48#define MSCC_SPI_MST_SW_MODE_SW_SPI_CS(x) (x << 5)
49
50#define SPARX5_FORCE_ENA 0xa4
51#define SPARX5_FORCE_VAL 0xa8
52
53#define JHB100_ADDRMODE_CS 0x00
54
55struct dw_spi_mscc {
56 struct regmap *syscon;
57 void __iomem *spi_mst; /* Not sparx5 */
58};
59
60/*
61 * Elba SoC does not use ssi, pin override is used for cs 0,1 and
62 * gpios for cs 2,3 as defined in the device tree.
63 *
64 * cs: | 1 0
65 * bit: |---3-------2-------1-------0
66 * | cs1 cs1_ovr cs0 cs0_ovr
67 */
68#define ELBA_SPICS_REG 0x2468
69#define ELBA_SPICS_OFFSET(cs) ((cs) << 1)
70#define ELBA_SPICS_MASK(cs) (GENMASK(1, 0) << ELBA_SPICS_OFFSET(cs))
71#define ELBA_SPICS_SET(cs, val) \
72 ((((val) << 1) | BIT(0)) << ELBA_SPICS_OFFSET(cs))
73
74/*
75 * The Designware SPI controller (referred to as master in the documentation)
76 * automatically deasserts chip select when the tx fifo is empty. The chip
77 * selects then needs to be either driven as GPIOs or, for the first 4 using
78 * the SPI boot controller registers. the final chip select is an OR gate
79 * between the Designware SPI controller and the SPI boot controller.
80 */
81static void dw_spi_mscc_set_cs(struct spi_device *spi, bool enable)
82{
83 struct dw_spi *dws = spi_controller_get_devdata(spi->controller);
84 struct dw_spi_mmio *dwsmmio = container_of(dws, struct dw_spi_mmio, dws);
85 struct dw_spi_mscc *dwsmscc = dwsmmio->priv;
86 u32 cs = spi_get_chipselect(spi, 0);
87
88 if (cs < 4) {
89 u32 sw_mode = MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE;
90
91 if (!enable)
92 sw_mode |= MSCC_SPI_MST_SW_MODE_SW_SPI_CS(BIT(cs));
93
94 writel(sw_mode, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE);
95 }
96
97 dw_spi_set_cs(spi, enable);
98}
99
100static int dw_spi_mscc_init(struct platform_device *pdev,
101 struct dw_spi_mmio *dwsmmio,
102 const char *cpu_syscon, u32 if_si_owner_offset)
103{
104 struct dw_spi_mscc *dwsmscc;
105
106 dwsmscc = devm_kzalloc(&pdev->dev, sizeof(*dwsmscc), GFP_KERNEL);
107 if (!dwsmscc)
108 return -ENOMEM;
109
110 dwsmscc->spi_mst = devm_platform_ioremap_resource(pdev, 1);
111 if (IS_ERR(dwsmscc->spi_mst))
112 return PTR_ERR(dwsmscc->spi_mst);
113
114 dwsmscc->syscon = syscon_regmap_lookup_by_compatible(cpu_syscon);
115 if (IS_ERR(dwsmscc->syscon))
116 return PTR_ERR(dwsmscc->syscon);
117
118 /* Deassert all CS */
119 writel(0, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE);
120
121 /* Select the owner of the SI interface */
122 regmap_update_bits(dwsmscc->syscon, MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL,
123 MSCC_IF_SI_OWNER_MASK << if_si_owner_offset,
124 MSCC_IF_SI_OWNER_SIMC << if_si_owner_offset);
125
126 dwsmmio->dws.set_cs = dw_spi_mscc_set_cs;
127 dwsmmio->priv = dwsmscc;
128
129 return 0;
130}
131
132static int dw_spi_mscc_ocelot_init(struct platform_device *pdev,
133 struct dw_spi_mmio *dwsmmio)
134{
135 return dw_spi_mscc_init(pdev, dwsmmio, "mscc,ocelot-cpu-syscon",
136 OCELOT_IF_SI_OWNER_OFFSET);
137}
138
139static int dw_spi_mscc_jaguar2_init(struct platform_device *pdev,
140 struct dw_spi_mmio *dwsmmio)
141{
142 return dw_spi_mscc_init(pdev, dwsmmio, "mscc,jaguar2-cpu-syscon",
143 JAGUAR2_IF_SI_OWNER_OFFSET);
144}
145
146/*
147 * The Designware SPI controller (referred to as master in the
148 * documentation) automatically deasserts chip select when the tx fifo
149 * is empty. The chip selects then needs to be driven by a CS override
150 * register. enable is an active low signal.
151 */
152static void dw_spi_sparx5_set_cs(struct spi_device *spi, bool enable)
153{
154 struct dw_spi *dws = spi_controller_get_devdata(spi->controller);
155 struct dw_spi_mmio *dwsmmio = container_of(dws, struct dw_spi_mmio, dws);
156 struct dw_spi_mscc *dwsmscc = dwsmmio->priv;
157 u8 cs = spi_get_chipselect(spi, 0);
158
159 if (!enable) {
160 /* CS override drive enable */
161 regmap_write(dwsmscc->syscon, SPARX5_FORCE_ENA, 1);
162 /* Now set CSx enabled */
163 regmap_write(dwsmscc->syscon, SPARX5_FORCE_VAL, ~BIT(cs));
164 /* Allow settle */
165 usleep_range(1, 5);
166 } else {
167 /* CS value */
168 regmap_write(dwsmscc->syscon, SPARX5_FORCE_VAL, ~0);
169 /* Allow settle */
170 usleep_range(1, 5);
171 /* CS override drive disable */
172 regmap_write(dwsmscc->syscon, SPARX5_FORCE_ENA, 0);
173 }
174
175 dw_spi_set_cs(spi, enable);
176}
177
178static int dw_spi_mscc_sparx5_init(struct platform_device *pdev,
179 struct dw_spi_mmio *dwsmmio)
180{
181 const char *syscon_name = "microchip,sparx5-cpu-syscon";
182 struct device *dev = &pdev->dev;
183 struct dw_spi_mscc *dwsmscc;
184
185 if (!IS_ENABLED(CONFIG_SPI_MUX)) {
186 dev_err(dev, "This driver needs CONFIG_SPI_MUX\n");
187 return -EOPNOTSUPP;
188 }
189
190 dwsmscc = devm_kzalloc(dev, sizeof(*dwsmscc), GFP_KERNEL);
191 if (!dwsmscc)
192 return -ENOMEM;
193
194 dwsmscc->syscon =
195 syscon_regmap_lookup_by_compatible(syscon_name);
196 if (IS_ERR(dwsmscc->syscon)) {
197 dev_err(dev, "No syscon map %s\n", syscon_name);
198 return PTR_ERR(dwsmscc->syscon);
199 }
200
201 dwsmmio->dws.set_cs = dw_spi_sparx5_set_cs;
202 dwsmmio->priv = dwsmscc;
203
204 return 0;
205}
206
207static int dw_spi_alpine_init(struct platform_device *pdev,
208 struct dw_spi_mmio *dwsmmio)
209{
210 dwsmmio->dws.caps = DW_SPI_CAP_CS_OVERRIDE;
211
212 return 0;
213}
214
215static int dw_spi_pssi_init(struct platform_device *pdev,
216 struct dw_spi_mmio *dwsmmio)
217{
218 dw_spi_dma_setup_generic(&dwsmmio->dws);
219
220 return 0;
221}
222
223static int dw_spi_hssi_init(struct platform_device *pdev,
224 struct dw_spi_mmio *dwsmmio)
225{
226 dwsmmio->dws.ip = DW_HSSI_ID;
227
228 dw_spi_dma_setup_generic(&dwsmmio->dws);
229
230 return 0;
231}
232
233static int dw_spi_hssi_no_dma_init(struct platform_device *pdev,
234 struct dw_spi_mmio *dwsmmio)
235{
236 dwsmmio->dws.ip = DW_HSSI_ID;
237
238 return 0;
239}
240
241/*
242 * DMA-based mem ops are not configured for this device and are not tested.
243 */
244static int dw_spi_mountevans_imc_init(struct platform_device *pdev,
245 struct dw_spi_mmio *dwsmmio)
246{
247 /*
248 * The Intel Mount Evans SoC's Integrated Management Complex DW
249 * apb_ssi_v4.02a controller has an errata where a full TX FIFO can
250 * result in data corruption. The suggested workaround is to never
251 * completely fill the FIFO. The TX FIFO has a size of 32 so the
252 * fifo_len is set to 31.
253 */
254 dwsmmio->dws.fifo_len = 31;
255
256 return 0;
257}
258
259static int dw_spi_canaan_k210_init(struct platform_device *pdev,
260 struct dw_spi_mmio *dwsmmio)
261{
262 /*
263 * The Canaan Kendryte K210 SoC DW apb_ssi v4 spi controller is
264 * documented to have a 32 word deep TX and RX FIFO, which
265 * spi_hw_init() detects. However, when the RX FIFO is filled up to
266 * 32 entries (RXFLR = 32), an RX FIFO overrun error occurs. Avoid this
267 * problem by force setting fifo_len to 31.
268 */
269 dwsmmio->dws.fifo_len = 31;
270
271 return 0;
272}
273
274static void dw_spi_elba_override_cs(struct regmap *syscon, int cs, int enable)
275{
276 regmap_update_bits(syscon, ELBA_SPICS_REG, ELBA_SPICS_MASK(cs),
277 ELBA_SPICS_SET(cs, enable));
278}
279
280static void dw_spi_elba_set_cs(struct spi_device *spi, bool enable)
281{
282 struct dw_spi *dws = spi_controller_get_devdata(spi->controller);
283 struct dw_spi_mmio *dwsmmio = container_of(dws, struct dw_spi_mmio, dws);
284 struct regmap *syscon = dwsmmio->priv;
285 u8 cs;
286
287 cs = spi_get_chipselect(spi, 0);
288 if (cs < 2)
289 dw_spi_elba_override_cs(syscon, spi_get_chipselect(spi, 0), enable);
290
291 /*
292 * The DW SPI controller needs a native CS bit selected to start
293 * the serial engine.
294 */
295 spi_set_chipselect(spi, 0, 0);
296 dw_spi_set_cs(spi, enable);
297 spi_set_chipselect(spi, 0, cs);
298}
299
300static int dw_spi_elba_init(struct platform_device *pdev,
301 struct dw_spi_mmio *dwsmmio)
302{
303 struct regmap *syscon;
304
305 syscon = syscon_regmap_lookup_by_phandle(dev_of_node(&pdev->dev),
306 "amd,pensando-elba-syscon");
307 if (IS_ERR(syscon))
308 return dev_err_probe(&pdev->dev, PTR_ERR(syscon),
309 "syscon regmap lookup failed\n");
310
311 dwsmmio->priv = syscon;
312 dwsmmio->dws.set_cs = dw_spi_elba_set_cs;
313
314 return 0;
315}
316
317static int dw_spi_jhb100_set_addr_nbyte(struct spi_device *spi, u8 nbyte)
318{
319 struct dw_spi *dws = spi_controller_get_devdata(spi->controller);
320 struct dw_spi_mmio *dwsmmio = container_of(dws, struct dw_spi_mmio, dws);
321 struct regmap *syscon = dwsmmio->priv;
322
323 if (nbyte == 3) {
324 regmap_update_bits(syscon, JHB100_ADDRMODE_CS,
325 BIT(spi_get_chipselect(spi, 0)),
326 0);
327 } else if (nbyte == 4) {
328 regmap_update_bits(syscon, JHB100_ADDRMODE_CS,
329 BIT(spi_get_chipselect(spi, 0)),
330 BIT(spi_get_chipselect(spi, 0)));
331 } else {
332 dev_err(&spi->dev, "Unsupported address nbyte %d\n", nbyte);
333 return -EINVAL;
334 }
335
336 return 0;
337}
338
339static int dw_spi_jhb100_resume(struct dw_spi_mmio *dwsmmio)
340{
341 dw_spi_jhb100_mask_intr(&dwsmmio->dws, 0xff);
342
343 return 0;
344}
345
346static int dw_spi_jhb100_init(struct platform_device *pdev,
347 struct dw_spi_mmio *dwsmmio)
348{
349 struct regmap *syscon;
350
351 syscon = syscon_regmap_lookup_by_phandle(dev_of_node(&pdev->dev),
352 "starfive,sfc-filter-syscon");
353 if (IS_ERR(syscon))
354 return dev_err_probe(&pdev->dev, PTR_ERR(syscon),
355 "syscon regmap lookup failed\n");
356
357 dwsmmio->priv = syscon;
358 dwsmmio->platform_resume = dw_spi_jhb100_resume;
359
360 dwsmmio->dws.set_addr_nbyte = dw_spi_jhb100_set_addr_nbyte;
361 dwsmmio->dws.ip = DW_HSSI_ID;
362 dwsmmio->dws.quirk_flags = DW_SPI_QUIRK_JHB100;
363
364 dw_spi_jhb100_mask_intr(&dwsmmio->dws, 0xff);
365
366 return 0;
367}
368
369static int dw_spi_mmio_probe(struct platform_device *pdev)
370{
371 int (*init_func)(struct platform_device *pdev,
372 struct dw_spi_mmio *dwsmmio);
373 struct dw_spi_mmio *dwsmmio;
374 struct resource *mem;
375 struct dw_spi *dws;
376 int ret;
377
378 dwsmmio = devm_kzalloc(&pdev->dev, sizeof(struct dw_spi_mmio),
379 GFP_KERNEL);
380 if (!dwsmmio)
381 return -ENOMEM;
382
383 dws = &dwsmmio->dws;
384
385 /* Get basic io resource and map it */
386 dws->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
387 if (IS_ERR(dws->regs))
388 return PTR_ERR(dws->regs);
389
390 dws->paddr = mem->start;
391
392 dws->irq = platform_get_irq(pdev, 0);
393 if (dws->irq < 0)
394 return dws->irq; /* -ENXIO */
395
396 dwsmmio->clk = devm_clk_get_enabled(&pdev->dev, NULL);
397 if (IS_ERR(dwsmmio->clk))
398 return PTR_ERR(dwsmmio->clk);
399
400 /* Optional clock needed to access the registers */
401 dwsmmio->pclk = devm_clk_get_optional_enabled(&pdev->dev, "pclk");
402 if (IS_ERR(dwsmmio->pclk))
403 return PTR_ERR(dwsmmio->pclk);
404
405 /* find an optional reset controller */
406 dwsmmio->rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, "spi");
407 if (IS_ERR(dwsmmio->rstc))
408 return PTR_ERR(dwsmmio->rstc);
409
410 ret = reset_control_deassert(dwsmmio->rstc);
411 if (ret)
412 return dev_err_probe(&pdev->dev, ret, "Failed to deassert resets\n");
413
414 dws->bus_num = pdev->id;
415
416 dws->max_freq = clk_get_rate(dwsmmio->clk);
417
418 if (device_property_read_u32(&pdev->dev, "reg-io-width",
419 &dws->reg_io_width))
420 dws->reg_io_width = 4;
421
422 /* Rely on the auto-detection if no property specified */
423 device_property_read_u32(&pdev->dev, "num-cs", &dws->num_cs);
424
425 init_func = device_get_match_data(&pdev->dev);
426 if (init_func) {
427 ret = init_func(pdev, dwsmmio);
428 if (ret)
429 goto out_reset;
430 }
431
432 pm_runtime_enable(&pdev->dev);
433
434 ret = dw_spi_add_controller(&pdev->dev, dws);
435 if (ret)
436 goto out;
437
438 platform_set_drvdata(pdev, dwsmmio);
439 return 0;
440
441out:
442 pm_runtime_disable(&pdev->dev);
443out_reset:
444 reset_control_assert(dwsmmio->rstc);
445
446 return ret;
447}
448
449static int dw_spi_mmio_suspend(struct device *dev)
450{
451 struct dw_spi_mmio *dwsmmio = dev_get_drvdata(dev);
452 int ret;
453
454 ret = dw_spi_suspend_controller(&dwsmmio->dws);
455 if (ret)
456 return ret;
457
458 if (dwsmmio->platform_suspend)
459 dwsmmio->platform_suspend(dwsmmio);
460
461 reset_control_assert(dwsmmio->rstc);
462
463 clk_disable_unprepare(dwsmmio->pclk);
464 clk_disable_unprepare(dwsmmio->clk);
465
466 return 0;
467}
468
469static int dw_spi_mmio_resume(struct device *dev)
470{
471 struct dw_spi_mmio *dwsmmio = dev_get_drvdata(dev);
472 int ret;
473
474 clk_prepare_enable(dwsmmio->clk);
475 clk_prepare_enable(dwsmmio->pclk);
476
477 reset_control_deassert(dwsmmio->rstc);
478
479 if (dwsmmio->platform_resume) {
480 ret = dwsmmio->platform_resume(dwsmmio);
481 if (ret) {
482 reset_control_assert(dwsmmio->rstc);
483
484 clk_disable_unprepare(dwsmmio->pclk);
485 clk_disable_unprepare(dwsmmio->clk);
486 return ret;
487 }
488 }
489
490 return dw_spi_resume_controller(&dwsmmio->dws);
491}
492
493static DEFINE_SIMPLE_DEV_PM_OPS(dw_spi_mmio_pm_ops,
494 dw_spi_mmio_suspend, dw_spi_mmio_resume);
495
496static void dw_spi_mmio_remove(struct platform_device *pdev)
497{
498 struct dw_spi_mmio *dwsmmio = platform_get_drvdata(pdev);
499
500 dw_spi_remove_controller(&dwsmmio->dws);
501 pm_runtime_disable(&pdev->dev);
502 reset_control_assert(dwsmmio->rstc);
503}
504
505static const struct of_device_id dw_spi_mmio_of_match[] = {
506 { .compatible = "snps,dw-apb-ssi", .data = dw_spi_pssi_init},
507 { .compatible = "mscc,ocelot-spi", .data = dw_spi_mscc_ocelot_init},
508 { .compatible = "mscc,jaguar2-spi", .data = dw_spi_mscc_jaguar2_init},
509 { .compatible = "amazon,alpine-dw-apb-ssi", .data = dw_spi_alpine_init},
510 { .compatible = "renesas,rzn1-spi", .data = dw_spi_pssi_init},
511 { .compatible = "snps,dwc-ssi-1.01a", .data = dw_spi_hssi_init},
512 { .compatible = "snps,dwc-ssi-2.00a", .data = dw_spi_hssi_init},
513 { .compatible = "intel,keembay-ssi", .data = dw_spi_hssi_no_dma_init},
514 {
515 .compatible = "intel,mountevans-imc-ssi",
516 .data = dw_spi_mountevans_imc_init,
517 },
518 { .compatible = "microchip,sparx5-spi", dw_spi_mscc_sparx5_init},
519 { .compatible = "canaan,k210-spi", dw_spi_canaan_k210_init},
520 { .compatible = "amd,pensando-elba-spi", .data = dw_spi_elba_init},
521 { .compatible = "starfive,jhb100-sfc", .data = dw_spi_jhb100_init},
522 { /* end of table */}
523};
524MODULE_DEVICE_TABLE(of, dw_spi_mmio_of_match);
525
526#ifdef CONFIG_ACPI
527static const struct acpi_device_id dw_spi_mmio_acpi_match[] = {
528 {"HISI0173", (kernel_ulong_t)dw_spi_pssi_init},
529 {"LECA0002", (kernel_ulong_t)dw_spi_hssi_no_dma_init},
530 {},
531};
532MODULE_DEVICE_TABLE(acpi, dw_spi_mmio_acpi_match);
533#endif
534
535static struct platform_driver dw_spi_mmio_driver = {
536 .probe = dw_spi_mmio_probe,
537 .remove = dw_spi_mmio_remove,
538 .driver = {
539 .name = DRIVER_NAME,
540 .of_match_table = dw_spi_mmio_of_match,
541 .acpi_match_table = ACPI_PTR(dw_spi_mmio_acpi_match),
542 .pm = pm_sleep_ptr(&dw_spi_mmio_pm_ops),
543 },
544};
545module_platform_driver(dw_spi_mmio_driver);
546
547MODULE_AUTHOR("Jean-Hugues Deschenes <[email protected]>");
548MODULE_DESCRIPTION("Memory-mapped I/O interface driver for DW SPI Core");
549MODULE_LICENSE("GPL v2");
550MODULE_IMPORT_NS("SPI_DW_CORE");