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1// SPDX-License-Identifier: GPL-2.0+
2
3/*
4 * Freescale QuadSPI driver.
5 *
6 * Copyright (C) 2013 Freescale Semiconductor, Inc.
7 * Copyright (C) 2018 Bootlin
8 * Copyright (C) 2018 exceet electronics GmbH
9 * Copyright (C) 2018 Kontron Electronics GmbH
10 *
11 * Transition to SPI MEM interface:
12 * Authors:
13 * Boris Brezillon <[email protected]>
14 * Frieder Schrempf <[email protected]>
15 * Yogesh Gaur <[email protected]>
16 * Suresh Gupta <[email protected]>
17 *
18 * Based on the original fsl-quadspi.c SPI NOR driver:
19 * Author: Freescale Semiconductor, Inc.
20 *
21 */
22
23#include <linux/bitops.h>
24#include <linux/clk.h>
25#include <linux/completion.h>
26#include <linux/delay.h>
27#include <linux/err.h>
28#include <linux/errno.h>
29#include <linux/interrupt.h>
30#include <linux/io.h>
31#include <linux/iopoll.h>
32#include <linux/jiffies.h>
33#include <linux/kernel.h>
34#include <linux/module.h>
35#include <linux/mutex.h>
36#include <linux/of.h>
37#include <linux/platform_device.h>
38#include <linux/pm_qos.h>
39#include <linux/reset.h>
40#include <linux/sizes.h>
41
42#include <linux/spi/spi.h>
43#include <linux/spi/spi-mem.h>
44
45/*
46 * The driver only uses one single LUT entry, that is updated on
47 * each call of exec_op(). Index 0 is preset at boot with a basic
48 * read operation, so let's use the last entry (15).
49 */
50#define SEQID_LUT 15
51
52/* Registers used by the driver */
53#define QUADSPI_MCR 0x00
54#define QUADSPI_MCR_RESERVED_MASK GENMASK(19, 16)
55#define QUADSPI_MCR_MDIS_MASK BIT(14)
56#define QUADSPI_MCR_CLR_TXF_MASK BIT(11)
57#define QUADSPI_MCR_CLR_RXF_MASK BIT(10)
58#define QUADSPI_MCR_DDR_EN_MASK BIT(7)
59#define QUADSPI_MCR_END_CFG_MASK GENMASK(3, 2)
60#define QUADSPI_MCR_SWRSTHD_MASK BIT(1)
61#define QUADSPI_MCR_SWRSTSD_MASK BIT(0)
62
63#define QUADSPI_IPCR 0x08
64#define QUADSPI_IPCR_SEQID(x) ((x) << 24)
65
66#define QUADSPI_FLSHCR 0x0c
67#define QUADSPI_FLSHCR_TCSS_MASK GENMASK(3, 0)
68#define QUADSPI_FLSHCR_TCSH_MASK GENMASK(11, 8)
69#define QUADSPI_FLSHCR_TDH_MASK GENMASK(17, 16)
70
71#define QUADSPI_BUF0CR 0x10
72#define QUADSPI_BUF1CR 0x14
73#define QUADSPI_BUF2CR 0x18
74#define QUADSPI_BUFXCR_INVALID_MSTRID 0xe
75
76#define QUADSPI_BUF3CR 0x1c
77#define QUADSPI_BUF3CR_ALLMST_MASK BIT(31)
78#define QUADSPI_BUF3CR_ADATSZ(x) ((x) << 8)
79#define QUADSPI_BUF3CR_ADATSZ_MASK GENMASK(15, 8)
80
81#define QUADSPI_BFGENCR 0x20
82#define QUADSPI_BFGENCR_SEQID(x) ((x) << 12)
83
84#define QUADSPI_BUF0IND 0x30
85#define QUADSPI_BUF1IND 0x34
86#define QUADSPI_BUF2IND 0x38
87#define QUADSPI_SFAR 0x100
88
89#define QUADSPI_SMPR 0x108
90#define QUADSPI_SMPR_DDRSMP_MASK GENMASK(18, 16)
91#define QUADSPI_SMPR_FSDLY_MASK BIT(6)
92#define QUADSPI_SMPR_FSPHS_MASK BIT(5)
93#define QUADSPI_SMPR_HSENA_MASK BIT(0)
94
95#define QUADSPI_RBCT 0x110
96#define QUADSPI_RBCT_WMRK_MASK GENMASK(4, 0)
97#define QUADSPI_RBCT_RXBRD_USEIPS BIT(8)
98
99#define QUADSPI_TBDR 0x154
100
101#define QUADSPI_SR 0x15c
102#define QUADSPI_SR_IP_ACC_MASK BIT(1)
103#define QUADSPI_SR_AHB_ACC_MASK BIT(2)
104
105#define QUADSPI_FR 0x160
106#define QUADSPI_FR_TFF_MASK BIT(0)
107
108#define QUADSPI_RSER 0x164
109#define QUADSPI_RSER_TFIE BIT(0)
110
111#define QUADSPI_SPTRCLR 0x16c
112#define QUADSPI_SPTRCLR_IPPTRC BIT(8)
113#define QUADSPI_SPTRCLR_BFPTRC BIT(0)
114
115#define QUADSPI_SFA1AD 0x180
116#define QUADSPI_SFA2AD 0x184
117#define QUADSPI_SFB1AD 0x188
118#define QUADSPI_SFB2AD 0x18c
119#define QUADSPI_RBDR(x) (0x200 + ((x) * 4))
120
121#define QUADSPI_LUTKEY 0x300
122#define QUADSPI_LUTKEY_VALUE 0x5AF05AF0
123
124#define QUADSPI_LCKCR 0x304
125#define QUADSPI_LCKER_LOCK BIT(0)
126#define QUADSPI_LCKER_UNLOCK BIT(1)
127
128#define QUADSPI_LUT_BASE 0x310
129#define QUADSPI_LUT_OFFSET (SEQID_LUT * 4 * 4)
130#define QUADSPI_LUT_REG(idx) \
131 (QUADSPI_LUT_BASE + QUADSPI_LUT_OFFSET + (idx) * 4)
132
133/* Instruction set for the LUT register */
134#define LUT_STOP 0
135#define LUT_CMD 1
136#define LUT_ADDR 2
137#define LUT_DUMMY 3
138#define LUT_MODE 4
139#define LUT_MODE2 5
140#define LUT_MODE4 6
141#define LUT_FSL_READ 7
142#define LUT_FSL_WRITE 8
143#define LUT_JMP_ON_CS 9
144#define LUT_ADDR_DDR 10
145#define LUT_MODE_DDR 11
146#define LUT_MODE2_DDR 12
147#define LUT_MODE4_DDR 13
148#define LUT_FSL_READ_DDR 14
149#define LUT_FSL_WRITE_DDR 15
150#define LUT_DATA_LEARN 16
151
152/*
153 * The PAD definitions for LUT register.
154 *
155 * The pad stands for the number of IO lines [0:3].
156 * For example, the quad read needs four IO lines,
157 * so you should use LUT_PAD(4).
158 */
159#define LUT_PAD(x) (fls(x) - 1)
160
161/*
162 * Macro for constructing the LUT entries with the following
163 * register layout:
164 *
165 * ---------------------------------------------------
166 * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
167 * ---------------------------------------------------
168 */
169#define LUT_DEF(idx, ins, pad, opr) \
170 ((((ins) << 10) | ((pad) << 8) | (opr)) << (((idx) % 2) * 16))
171
172/* Controller needs driver to swap endianness */
173#define QUADSPI_QUIRK_SWAP_ENDIAN BIT(0)
174
175/* Controller needs 4x internal clock */
176#define QUADSPI_QUIRK_4X_INT_CLK BIT(1)
177
178/*
179 * TKT253890, the controller needs the driver to fill the txfifo with
180 * 16 bytes at least to trigger a data transfer, even though the extra
181 * data won't be transferred.
182 */
183#define QUADSPI_QUIRK_TKT253890 BIT(2)
184
185/* TKT245618, the controller cannot wake up from wait mode */
186#define QUADSPI_QUIRK_TKT245618 BIT(3)
187
188/*
189 * Controller adds QSPI_AMBA_BASE (base address of the mapped memory)
190 * internally. No need to add it when setting SFXXAD and SFAR registers
191 */
192#define QUADSPI_QUIRK_BASE_INTERNAL BIT(4)
193
194/*
195 * Controller uses TDH bits in register QUADSPI_FLSHCR.
196 * They need to be set in accordance with the DDR/SDR mode.
197 */
198#define QUADSPI_QUIRK_USE_TDH_SETTING BIT(5)
199
200/*
201 * Do not disable the "qspi" clock when changing its rate.
202 */
203#define QUADSPI_QUIRK_SKIP_CLK_DISABLE BIT(6)
204
205struct fsl_qspi_devtype_data {
206 unsigned int rxfifo;
207 unsigned int txfifo;
208 int invalid_mstrid;
209 unsigned int ahb_buf_size;
210 unsigned int sfa_size;
211 unsigned int quirks;
212 bool little_endian;
213};
214
215static const struct fsl_qspi_devtype_data vybrid_data = {
216 .rxfifo = SZ_128,
217 .txfifo = SZ_64,
218 .invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID,
219 .ahb_buf_size = SZ_1K,
220 .quirks = QUADSPI_QUIRK_SWAP_ENDIAN,
221 .little_endian = true,
222};
223
224static const struct fsl_qspi_devtype_data imx6sx_data = {
225 .rxfifo = SZ_128,
226 .txfifo = SZ_512,
227 .invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID,
228 .ahb_buf_size = SZ_1K,
229 .quirks = QUADSPI_QUIRK_4X_INT_CLK | QUADSPI_QUIRK_TKT245618,
230 .little_endian = true,
231};
232
233static const struct fsl_qspi_devtype_data imx7d_data = {
234 .rxfifo = SZ_128,
235 .txfifo = SZ_512,
236 .invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID,
237 .ahb_buf_size = SZ_1K,
238 .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK |
239 QUADSPI_QUIRK_USE_TDH_SETTING,
240 .little_endian = true,
241};
242
243static const struct fsl_qspi_devtype_data imx6ul_data = {
244 .rxfifo = SZ_128,
245 .txfifo = SZ_512,
246 .invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID,
247 .ahb_buf_size = SZ_1K,
248 .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK |
249 QUADSPI_QUIRK_USE_TDH_SETTING,
250 .little_endian = true,
251};
252
253static const struct fsl_qspi_devtype_data ls1021a_data = {
254 .rxfifo = SZ_128,
255 .txfifo = SZ_64,
256 .invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID,
257 .ahb_buf_size = SZ_1K,
258 .quirks = 0,
259 .little_endian = false,
260};
261
262static const struct fsl_qspi_devtype_data ls2080a_data = {
263 .rxfifo = SZ_128,
264 .txfifo = SZ_64,
265 .ahb_buf_size = SZ_1K,
266 .invalid_mstrid = 0x0,
267 .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_BASE_INTERNAL,
268 .little_endian = true,
269};
270
271static const struct fsl_qspi_devtype_data spacemit_k1_data = {
272 .rxfifo = SZ_128,
273 .txfifo = SZ_256,
274 .ahb_buf_size = SZ_512,
275 .sfa_size = SZ_1K,
276 .invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID,
277 .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_SKIP_CLK_DISABLE,
278 .little_endian = true,
279};
280
281struct fsl_qspi {
282 void __iomem *iobase;
283 void __iomem *ahb_addr;
284 const struct fsl_qspi_devtype_data *devtype_data;
285 struct mutex lock;
286 struct completion c;
287 struct reset_control *resets;
288 struct clk *clk, *clk_en;
289 struct pm_qos_request pm_qos_req;
290 struct device *dev;
291 int selected;
292 u32 selected_freq;
293 u32 memmap_phy;
294};
295
296static bool needs_swap_endian(struct fsl_qspi *q)
297{
298 return !!(q->devtype_data->quirks & QUADSPI_QUIRK_SWAP_ENDIAN);
299}
300
301static bool needs_4x_clock(struct fsl_qspi *q)
302{
303 return !!(q->devtype_data->quirks & QUADSPI_QUIRK_4X_INT_CLK);
304}
305
306static bool needs_fill_txfifo(struct fsl_qspi *q)
307{
308 return !!(q->devtype_data->quirks & QUADSPI_QUIRK_TKT253890);
309}
310
311static bool needs_wakeup_wait_mode(struct fsl_qspi *q)
312{
313 return !!(q->devtype_data->quirks & QUADSPI_QUIRK_TKT245618);
314}
315
316static bool needs_amba_base_offset(struct fsl_qspi *q)
317{
318 return !(q->devtype_data->quirks & QUADSPI_QUIRK_BASE_INTERNAL);
319}
320
321static bool needs_tdh_setting(struct fsl_qspi *q)
322{
323 return !!(q->devtype_data->quirks & QUADSPI_QUIRK_USE_TDH_SETTING);
324}
325
326static bool needs_clk_disable(struct fsl_qspi *q)
327{
328 return !(q->devtype_data->quirks & QUADSPI_QUIRK_SKIP_CLK_DISABLE);
329}
330
331/*
332 * An IC bug makes it necessary to rearrange the 32-bit data.
333 * Later chips, such as IMX6SLX, have fixed this bug.
334 */
335static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi *q, u32 a)
336{
337 return needs_swap_endian(q) ? __swab32(a) : a;
338}
339
340/*
341 * R/W functions for big- or little-endian registers:
342 * The QSPI controller's endianness is independent of
343 * the CPU core's endianness. So far, although the CPU
344 * core is little-endian the QSPI controller can use
345 * big-endian or little-endian.
346 */
347static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem *addr)
348{
349 if (q->devtype_data->little_endian)
350 iowrite32(val, addr);
351 else
352 iowrite32be(val, addr);
353}
354
355static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr)
356{
357 if (q->devtype_data->little_endian)
358 return ioread32(addr);
359
360 return ioread32be(addr);
361}
362
363static irqreturn_t fsl_qspi_irq_handler(int irq, void *dev_id)
364{
365 struct fsl_qspi *q = dev_id;
366 u32 reg;
367
368 /* clear interrupt */
369 reg = qspi_readl(q, q->iobase + QUADSPI_FR);
370 qspi_writel(q, reg, q->iobase + QUADSPI_FR);
371
372 if (reg & QUADSPI_FR_TFF_MASK)
373 complete(&q->c);
374
375 dev_dbg(q->dev, "QUADSPI_FR : 0x%.8x:0x%.8x\n", 0, reg);
376 return IRQ_HANDLED;
377}
378
379static int fsl_qspi_check_buswidth(struct fsl_qspi *q, u8 width)
380{
381 switch (width) {
382 case 1:
383 case 2:
384 case 4:
385 return 0;
386 }
387
388 return -ENOTSUPP;
389}
390
391static bool fsl_qspi_supports_op(struct spi_mem *mem,
392 const struct spi_mem_op *op)
393{
394 struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->controller);
395 int ret;
396
397 ret = fsl_qspi_check_buswidth(q, op->cmd.buswidth);
398
399 if (op->addr.nbytes)
400 ret |= fsl_qspi_check_buswidth(q, op->addr.buswidth);
401
402 if (op->dummy.nbytes)
403 ret |= fsl_qspi_check_buswidth(q, op->dummy.buswidth);
404
405 if (op->data.nbytes)
406 ret |= fsl_qspi_check_buswidth(q, op->data.buswidth);
407
408 if (ret)
409 return false;
410
411 /*
412 * The number of instructions needed for the op, needs
413 * to fit into a single LUT entry.
414 */
415 if (op->addr.nbytes +
416 (op->dummy.nbytes ? 1:0) +
417 (op->data.nbytes ? 1:0) > 6)
418 return false;
419
420 /* Max 64 dummy clock cycles supported */
421 if (op->dummy.nbytes &&
422 (op->dummy.nbytes * 8 / op->dummy.buswidth > 64))
423 return false;
424
425 /* Max data length, check controller limits and alignment */
426 if (op->data.dir == SPI_MEM_DATA_IN &&
427 (op->data.nbytes > q->devtype_data->ahb_buf_size ||
428 (op->data.nbytes > q->devtype_data->rxfifo - 4 &&
429 !IS_ALIGNED(op->data.nbytes, 8))))
430 return false;
431
432 if (op->data.dir == SPI_MEM_DATA_OUT &&
433 op->data.nbytes > q->devtype_data->txfifo)
434 return false;
435
436 return spi_mem_default_supports_op(mem, op);
437}
438
439static void fsl_qspi_prepare_lut(struct fsl_qspi *q,
440 const struct spi_mem_op *op)
441{
442 void __iomem *base = q->iobase;
443 u32 lutval[4] = {};
444 int lutidx = 1, i;
445
446 lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth),
447 op->cmd.opcode);
448
449 /*
450 * For some unknown reason, using LUT_ADDR doesn't work in some
451 * cases (at least with only one byte long addresses), so
452 * let's use LUT_MODE to write the address bytes one by one
453 */
454 for (i = 0; i < op->addr.nbytes; i++) {
455 u8 addrbyte = op->addr.val >> (8 * (op->addr.nbytes - i - 1));
456
457 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_MODE,
458 LUT_PAD(op->addr.buswidth),
459 addrbyte);
460 lutidx++;
461 }
462
463 if (op->dummy.nbytes) {
464 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_DUMMY,
465 LUT_PAD(op->dummy.buswidth),
466 op->dummy.nbytes * 8 /
467 op->dummy.buswidth);
468 lutidx++;
469 }
470
471 if (op->data.nbytes) {
472 lutval[lutidx / 2] |= LUT_DEF(lutidx,
473 op->data.dir == SPI_MEM_DATA_IN ?
474 LUT_FSL_READ : LUT_FSL_WRITE,
475 LUT_PAD(op->data.buswidth),
476 0);
477 lutidx++;
478 }
479
480 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_STOP, 0, 0);
481
482 /* unlock LUT */
483 qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
484 qspi_writel(q, QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
485
486 /* fill LUT */
487 for (i = 0; i < ARRAY_SIZE(lutval); i++)
488 qspi_writel(q, lutval[i], base + QUADSPI_LUT_REG(i));
489
490 /* lock LUT */
491 qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
492 qspi_writel(q, QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
493}
494
495static int fsl_qspi_clk_prep_enable(struct fsl_qspi *q)
496{
497 int ret;
498
499 ret = clk_prepare_enable(q->clk_en);
500 if (ret)
501 return ret;
502
503 ret = clk_prepare_enable(q->clk);
504 if (ret) {
505 clk_disable_unprepare(q->clk_en);
506 return ret;
507 }
508
509 if (needs_wakeup_wait_mode(q))
510 cpu_latency_qos_add_request(&q->pm_qos_req, 0);
511
512 return 0;
513}
514
515static void fsl_qspi_clk_disable_unprep(struct fsl_qspi *q)
516{
517 if (needs_wakeup_wait_mode(q))
518 cpu_latency_qos_remove_request(&q->pm_qos_req);
519
520 clk_disable_unprepare(q->clk);
521 clk_disable_unprepare(q->clk_en);
522}
523
524/*
525 * If we have changed the content of the flash by writing or erasing, or if we
526 * read from flash with a different offset into the page buffer, we need to
527 * invalidate the AHB buffer. If we do not do so, we may read out the wrong
528 * data. The spec tells us reset the AHB domain and Serial Flash domain at
529 * the same time.
530 */
531static void fsl_qspi_invalidate(struct fsl_qspi *q)
532{
533 u32 reg;
534
535 reg = qspi_readl(q, q->iobase + QUADSPI_MCR);
536 reg |= QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK;
537 qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
538
539 /*
540 * The minimum delay : 1 AHB + 2 SFCK clocks.
541 * Delay 1 us is enough.
542 */
543 udelay(1);
544
545 reg &= ~(QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK);
546 qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
547}
548
549static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_device *spi,
550 const struct spi_mem_op *op)
551{
552 unsigned long rate = op->max_freq;
553 int ret;
554
555 if (q->selected == spi_get_chipselect(spi, 0) &&
556 q->selected_freq == op->max_freq)
557 return;
558
559 if (needs_4x_clock(q))
560 rate *= 4;
561
562 if (needs_clk_disable(q))
563 fsl_qspi_clk_disable_unprep(q);
564
565 ret = clk_set_rate(q->clk, rate);
566 if (ret)
567 return;
568
569 if (needs_clk_disable(q)) {
570 ret = fsl_qspi_clk_prep_enable(q);
571 if (ret)
572 return;
573 }
574
575 q->selected = spi_get_chipselect(spi, 0);
576 q->selected_freq = op->max_freq;
577
578 fsl_qspi_invalidate(q);
579}
580
581static void fsl_qspi_read_ahb(struct fsl_qspi *q, const struct spi_mem_op *op)
582{
583 memcpy_fromio(op->data.buf.in,
584 q->ahb_addr + q->selected * q->devtype_data->ahb_buf_size,
585 op->data.nbytes);
586}
587
588static void fsl_qspi_fill_txfifo(struct fsl_qspi *q,
589 const struct spi_mem_op *op)
590{
591 void __iomem *base = q->iobase;
592 int i;
593 u32 val;
594
595 for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 4); i += 4) {
596 memcpy(&val, op->data.buf.out + i, 4);
597 val = fsl_qspi_endian_xchg(q, val);
598 qspi_writel(q, val, base + QUADSPI_TBDR);
599 }
600
601 if (i < op->data.nbytes) {
602 memcpy(&val, op->data.buf.out + i, op->data.nbytes - i);
603 val = fsl_qspi_endian_xchg(q, val);
604 qspi_writel(q, val, base + QUADSPI_TBDR);
605 }
606
607 if (needs_fill_txfifo(q)) {
608 for (i = op->data.nbytes; i < 16; i += 4)
609 qspi_writel(q, 0, base + QUADSPI_TBDR);
610 }
611}
612
613static void fsl_qspi_read_rxfifo(struct fsl_qspi *q,
614 const struct spi_mem_op *op)
615{
616 void __iomem *base = q->iobase;
617 int i;
618 u8 *buf = op->data.buf.in;
619 u32 val;
620
621 for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 4); i += 4) {
622 val = qspi_readl(q, base + QUADSPI_RBDR(i / 4));
623 val = fsl_qspi_endian_xchg(q, val);
624 memcpy(buf + i, &val, 4);
625 }
626
627 if (i < op->data.nbytes) {
628 val = qspi_readl(q, base + QUADSPI_RBDR(i / 4));
629 val = fsl_qspi_endian_xchg(q, val);
630 memcpy(buf + i, &val, op->data.nbytes - i);
631 }
632}
633
634static int fsl_qspi_do_op(struct fsl_qspi *q, const struct spi_mem_op *op)
635{
636 void __iomem *base = q->iobase;
637 int err = 0;
638
639 reinit_completion(&q->c);
640
641 /*
642 * Always start the sequence at the same index since we update
643 * the LUT at each exec_op() call. And also specify the DATA
644 * length, since it's has not been specified in the LUT.
645 */
646 qspi_writel(q, op->data.nbytes | QUADSPI_IPCR_SEQID(SEQID_LUT),
647 base + QUADSPI_IPCR);
648
649 /* Wait for the interrupt. */
650 if (!wait_for_completion_timeout(&q->c, msecs_to_jiffies(1000)))
651 err = -ETIMEDOUT;
652
653 if (!err && op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN)
654 fsl_qspi_read_rxfifo(q, op);
655
656 return err;
657}
658
659static int fsl_qspi_readl_poll_tout(struct fsl_qspi *q, void __iomem *base,
660 u32 mask, u32 delay_us, u32 timeout_us)
661{
662 u32 reg;
663
664 if (!q->devtype_data->little_endian)
665 mask = (u32)cpu_to_be32(mask);
666
667 return readl_poll_timeout(base, reg, !(reg & mask), delay_us,
668 timeout_us);
669}
670
671static int fsl_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
672{
673 struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->controller);
674 void __iomem *base = q->iobase;
675 u32 addr_offset = 0;
676 int err = 0;
677 int invalid_mstrid = q->devtype_data->invalid_mstrid;
678
679 mutex_lock(&q->lock);
680
681 /* wait for the controller being ready */
682 fsl_qspi_readl_poll_tout(q, base + QUADSPI_SR, (QUADSPI_SR_IP_ACC_MASK |
683 QUADSPI_SR_AHB_ACC_MASK), 10, 1000);
684
685 fsl_qspi_select_mem(q, mem->spi, op);
686
687 if (needs_amba_base_offset(q))
688 addr_offset = q->memmap_phy;
689
690 qspi_writel(q,
691 q->selected * q->devtype_data->ahb_buf_size + addr_offset,
692 base + QUADSPI_SFAR);
693
694 qspi_writel(q, qspi_readl(q, base + QUADSPI_MCR) |
695 QUADSPI_MCR_CLR_RXF_MASK | QUADSPI_MCR_CLR_TXF_MASK,
696 base + QUADSPI_MCR);
697
698 qspi_writel(q, QUADSPI_SPTRCLR_BFPTRC | QUADSPI_SPTRCLR_IPPTRC,
699 base + QUADSPI_SPTRCLR);
700
701 qspi_writel(q, invalid_mstrid, base + QUADSPI_BUF0CR);
702 qspi_writel(q, invalid_mstrid, base + QUADSPI_BUF1CR);
703 qspi_writel(q, invalid_mstrid, base + QUADSPI_BUF2CR);
704
705 fsl_qspi_prepare_lut(q, op);
706
707 /*
708 * If we have large chunks of data, we read them through the AHB bus
709 * by accessing the mapped memory. In all other cases we use
710 * IP commands to access the flash.
711 */
712 if (op->data.nbytes > (q->devtype_data->rxfifo - 4) &&
713 op->data.dir == SPI_MEM_DATA_IN) {
714 fsl_qspi_read_ahb(q, op);
715 } else {
716 qspi_writel(q, QUADSPI_RBCT_WMRK_MASK |
717 QUADSPI_RBCT_RXBRD_USEIPS, base + QUADSPI_RBCT);
718
719 if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT)
720 fsl_qspi_fill_txfifo(q, op);
721
722 err = fsl_qspi_do_op(q, op);
723 }
724
725 /* Invalidate the data in the AHB buffer. */
726 fsl_qspi_invalidate(q);
727
728 mutex_unlock(&q->lock);
729
730 return err;
731}
732
733static int fsl_qspi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op)
734{
735 struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->controller);
736
737 if (op->data.dir == SPI_MEM_DATA_OUT) {
738 if (op->data.nbytes > q->devtype_data->txfifo)
739 op->data.nbytes = q->devtype_data->txfifo;
740 } else {
741 if (op->data.nbytes > q->devtype_data->ahb_buf_size)
742 op->data.nbytes = q->devtype_data->ahb_buf_size;
743 else if (op->data.nbytes > (q->devtype_data->rxfifo - 4))
744 op->data.nbytes = ALIGN_DOWN(op->data.nbytes, 8);
745 }
746
747 return 0;
748}
749
750static int fsl_qspi_default_setup(struct fsl_qspi *q)
751{
752 void __iomem *base = q->iobase;
753 u32 reg, addr_offset = 0;
754 u32 sfa_size;
755 int ret;
756
757 /* disable and unprepare clock to avoid glitch pass to controller */
758 fsl_qspi_clk_disable_unprep(q);
759
760 /* the default frequency, we will change it later if necessary. */
761 ret = clk_set_rate(q->clk, 66000000);
762 if (ret)
763 return ret;
764
765 ret = fsl_qspi_clk_prep_enable(q);
766 if (ret)
767 return ret;
768
769 /* Reset the module */
770 qspi_writel(q, QUADSPI_MCR_SWRSTSD_MASK | QUADSPI_MCR_SWRSTHD_MASK,
771 base + QUADSPI_MCR);
772 udelay(1);
773
774 /* Disable the module */
775 qspi_writel(q, QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK,
776 base + QUADSPI_MCR);
777
778 /*
779 * Previous boot stages (BootROM, bootloader) might have used DDR
780 * mode and did not clear the TDH bits. As we currently use SDR mode
781 * only, clear the TDH bits if necessary.
782 */
783 if (needs_tdh_setting(q))
784 qspi_writel(q, qspi_readl(q, base + QUADSPI_FLSHCR) &
785 ~QUADSPI_FLSHCR_TDH_MASK,
786 base + QUADSPI_FLSHCR);
787
788 reg = qspi_readl(q, base + QUADSPI_SMPR);
789 qspi_writel(q, reg & ~(QUADSPI_SMPR_FSDLY_MASK
790 | QUADSPI_SMPR_FSPHS_MASK
791 | QUADSPI_SMPR_HSENA_MASK
792 | QUADSPI_SMPR_DDRSMP_MASK), base + QUADSPI_SMPR);
793
794 /* We only use the buffer3 for AHB read */
795 qspi_writel(q, 0, base + QUADSPI_BUF0IND);
796 qspi_writel(q, 0, base + QUADSPI_BUF1IND);
797 qspi_writel(q, 0, base + QUADSPI_BUF2IND);
798
799 qspi_writel(q, QUADSPI_BFGENCR_SEQID(SEQID_LUT),
800 q->iobase + QUADSPI_BFGENCR);
801 qspi_writel(q, QUADSPI_RBCT_WMRK_MASK, base + QUADSPI_RBCT);
802 qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
803 QUADSPI_BUF3CR_ADATSZ(q->devtype_data->ahb_buf_size / 8),
804 base + QUADSPI_BUF3CR);
805
806 if (needs_amba_base_offset(q))
807 addr_offset = q->memmap_phy;
808
809 /*
810 * In HW there can be a maximum of four chips on two buses with
811 * two chip selects on each bus. We use four chip selects in SW
812 * to differentiate between the four chips.
813 *
814 * By default we write the AHB buffer size to each chip, but
815 * a different size can be specified with devtype_data->sfa_size.
816 * The SFA1AD, SFA2AD, SFB1AD, and SFB2AD registers define the
817 * top (end) of these four regions.
818 */
819 sfa_size = q->devtype_data->sfa_size ? : q->devtype_data->ahb_buf_size;
820 qspi_writel(q, addr_offset + 1 * sfa_size, base + QUADSPI_SFA1AD);
821 qspi_writel(q, addr_offset + 2 * sfa_size, base + QUADSPI_SFA2AD);
822 qspi_writel(q, addr_offset + 3 * sfa_size, base + QUADSPI_SFB1AD);
823 qspi_writel(q, addr_offset + 4 * sfa_size, base + QUADSPI_SFB2AD);
824
825 q->selected = -1;
826
827 /* Enable the module */
828 qspi_writel(q, QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK,
829 base + QUADSPI_MCR);
830
831 /* clear all interrupt status */
832 qspi_writel(q, 0xffffffff, q->iobase + QUADSPI_FR);
833
834 /* enable the interrupt */
835 qspi_writel(q, QUADSPI_RSER_TFIE, q->iobase + QUADSPI_RSER);
836
837 return 0;
838}
839
840static const char *fsl_qspi_get_name(struct spi_mem *mem)
841{
842 struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->controller);
843 struct device *dev = &mem->spi->dev;
844 const char *name;
845
846 /*
847 * In order to keep mtdparts compatible with the old MTD driver at
848 * mtd/spi-nor/fsl-quadspi.c, we set a custom name derived from the
849 * platform_device of the controller.
850 */
851 if (of_get_available_child_count(q->dev->of_node) == 1)
852 return dev_name(q->dev);
853
854 name = devm_kasprintf(dev, GFP_KERNEL,
855 "%s-%d", dev_name(q->dev),
856 spi_get_chipselect(mem->spi, 0));
857
858 if (!name) {
859 dev_err(dev, "failed to get memory for custom flash name\n");
860 return ERR_PTR(-ENOMEM);
861 }
862
863 return name;
864}
865
866static const struct spi_controller_mem_ops fsl_qspi_mem_ops = {
867 .adjust_op_size = fsl_qspi_adjust_op_size,
868 .supports_op = fsl_qspi_supports_op,
869 .exec_op = fsl_qspi_exec_op,
870 .get_name = fsl_qspi_get_name,
871};
872
873static const struct spi_controller_mem_caps fsl_qspi_mem_caps = {
874 .per_op_freq = true,
875};
876
877static void fsl_qspi_disable(void *data)
878{
879 struct fsl_qspi *q = data;
880
881 /* disable the hardware */
882 qspi_writel(q, QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR);
883 qspi_writel(q, 0x0, q->iobase + QUADSPI_RSER);
884}
885
886static void fsl_qspi_cleanup(void *data)
887{
888 struct fsl_qspi *q = data;
889
890 reset_control_assert(q->resets);
891
892 fsl_qspi_clk_disable_unprep(q);
893
894 mutex_destroy(&q->lock);
895}
896
897static int fsl_qspi_probe(struct platform_device *pdev)
898{
899 struct spi_controller *ctlr;
900 struct device *dev = &pdev->dev;
901 struct device_node *np = dev->of_node;
902 struct resource *res;
903 struct fsl_qspi *q;
904 int ret;
905
906 ctlr = devm_spi_alloc_host(&pdev->dev, sizeof(*q));
907 if (!ctlr)
908 return -ENOMEM;
909
910 ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD |
911 SPI_TX_DUAL | SPI_TX_QUAD;
912
913 q = spi_controller_get_devdata(ctlr);
914 q->dev = dev;
915 q->devtype_data = of_device_get_match_data(dev);
916 if (!q->devtype_data)
917 return -ENODEV;
918
919 platform_set_drvdata(pdev, q);
920
921 /* find the resources */
922 q->iobase = devm_platform_ioremap_resource_byname(pdev, "QuadSPI");
923 if (IS_ERR(q->iobase))
924 return PTR_ERR(q->iobase);
925
926 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
927 "QuadSPI-memory");
928 if (!res)
929 return -EINVAL;
930 q->memmap_phy = res->start;
931 /* Since there are 4 cs, map size required is 4 times ahb_buf_size */
932 q->ahb_addr = devm_ioremap(dev, q->memmap_phy,
933 (q->devtype_data->ahb_buf_size * 4));
934 if (!q->ahb_addr)
935 return -ENOMEM;
936
937 q->resets = devm_reset_control_array_get_optional_exclusive(dev);
938 if (IS_ERR(q->resets))
939 return PTR_ERR(q->resets);
940
941 /* find the clocks */
942 q->clk_en = devm_clk_get(dev, "qspi_en");
943 if (IS_ERR(q->clk_en))
944 return PTR_ERR(q->clk_en);
945
946 q->clk = devm_clk_get(dev, "qspi");
947 if (IS_ERR(q->clk))
948 return PTR_ERR(q->clk);
949
950 mutex_init(&q->lock);
951
952 ret = fsl_qspi_clk_prep_enable(q);
953 if (ret) {
954 dev_err(dev, "can not enable the clock\n");
955 return ret;
956 }
957
958 ret = devm_add_action_or_reset(dev, fsl_qspi_cleanup, q);
959 if (ret)
960 return ret;
961
962 ret = reset_control_deassert(q->resets);
963 if (ret)
964 return ret;
965
966 /* find the irq */
967 ret = platform_get_irq(pdev, 0);
968 if (ret < 0)
969 return ret;
970
971 init_completion(&q->c);
972 ret = devm_request_irq(dev, ret,
973 fsl_qspi_irq_handler, 0, pdev->name, q);
974 if (ret) {
975 dev_err(dev, "failed to request irq: %d\n", ret);
976 return ret;
977 }
978
979 ctlr->bus_num = -1;
980 ctlr->num_chipselect = 4;
981 ctlr->mem_ops = &fsl_qspi_mem_ops;
982 ctlr->mem_caps = &fsl_qspi_mem_caps;
983
984 fsl_qspi_default_setup(q);
985
986 ctlr->dev.of_node = np;
987
988 ret = devm_add_action_or_reset(dev, fsl_qspi_disable, q);
989 if (ret)
990 return ret;
991
992 ret = devm_spi_register_controller(dev, ctlr);
993 if (ret)
994 return ret;
995
996 return 0;
997}
998
999static int fsl_qspi_suspend(struct device *dev)
1000{
1001 return 0;
1002}
1003
1004static int fsl_qspi_resume(struct device *dev)
1005{
1006 struct fsl_qspi *q = dev_get_drvdata(dev);
1007
1008 fsl_qspi_default_setup(q);
1009
1010 return 0;
1011}
1012
1013static const struct of_device_id fsl_qspi_dt_ids[] = {
1014 { .compatible = "fsl,vf610-qspi", .data = &vybrid_data, },
1015 { .compatible = "fsl,imx6sx-qspi", .data = &imx6sx_data, },
1016 { .compatible = "fsl,imx7d-qspi", .data = &imx7d_data, },
1017 { .compatible = "fsl,imx6ul-qspi", .data = &imx6ul_data, },
1018 { .compatible = "fsl,ls1021a-qspi", .data = &ls1021a_data, },
1019 { .compatible = "fsl,ls2080a-qspi", .data = &ls2080a_data, },
1020 { .compatible = "spacemit,k1-qspi", .data = &spacemit_k1_data, },
1021 { /* sentinel */ }
1022};
1023MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);
1024
1025static const struct dev_pm_ops fsl_qspi_pm_ops = {
1026 .suspend = fsl_qspi_suspend,
1027 .resume = fsl_qspi_resume,
1028};
1029
1030static struct platform_driver fsl_qspi_driver = {
1031 .driver = {
1032 .name = "fsl-quadspi",
1033 .of_match_table = fsl_qspi_dt_ids,
1034 .pm = &fsl_qspi_pm_ops,
1035 },
1036 .probe = fsl_qspi_probe,
1037};
1038module_platform_driver(fsl_qspi_driver);
1039
1040MODULE_DESCRIPTION("Freescale QuadSPI Controller Driver");
1041MODULE_AUTHOR("Freescale Semiconductor Inc.");
1042MODULE_AUTHOR("Boris Brezillon <[email protected]>");
1043MODULE_AUTHOR("Frieder Schrempf <[email protected]>");
1044MODULE_AUTHOR("Yogesh Gaur <[email protected]>");
1045MODULE_AUTHOR("Suresh Gupta <[email protected]>");
1046MODULE_LICENSE("GPL v2");