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1// SPDX-License-Identifier: GPL-2.0
2// Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
3
4#include <trace/events/qcom_geni_se.h>
5
6#define CREATE_TRACE_POINTS
7#include <trace/events/qcom_geni_spi.h>
8
9#include <linux/clk.h>
10#include <linux/dmaengine.h>
11#include <linux/dma-mapping.h>
12#include <linux/dma/qcom-gpi-dma.h>
13#include <linux/interrupt.h>
14#include <linux/io.h>
15#include <linux/log2.h>
16#include <linux/module.h>
17#include <linux/platform_device.h>
18#include <linux/pm_opp.h>
19#include <linux/pm_runtime.h>
20#include <linux/property.h>
21#include <linux/soc/qcom/geni-se.h>
22#include <linux/spi/spi.h>
23#include <linux/spinlock.h>
24
25/* SPI SE specific registers and respective register fields */
26#define SE_SPI_CPHA 0x224
27#define CPHA BIT(0)
28
29#define SE_SPI_LOOPBACK 0x22c
30#define LOOPBACK_ENABLE 0x1
31#define NORMAL_MODE 0x0
32#define LOOPBACK_MSK GENMASK(1, 0)
33
34#define SE_SPI_CPOL 0x230
35#define CPOL BIT(2)
36
37#define SE_SPI_DEMUX_OUTPUT_INV 0x24c
38#define CS_DEMUX_OUTPUT_INV_MSK GENMASK(3, 0)
39
40#define SE_SPI_DEMUX_SEL 0x250
41#define CS_DEMUX_OUTPUT_SEL GENMASK(3, 0)
42
43#define SE_SPI_TRANS_CFG 0x25c
44#define CS_TOGGLE BIT(1)
45
46#define SE_SPI_WORD_LEN 0x268
47#define WORD_LEN_MSK GENMASK(9, 0)
48#define MIN_WORD_LEN 4
49
50#define SE_SPI_TX_TRANS_LEN 0x26c
51#define SE_SPI_RX_TRANS_LEN 0x270
52#define TRANS_LEN_MSK GENMASK(23, 0)
53
54#define SE_SPI_PRE_POST_CMD_DLY 0x274
55
56#define SE_SPI_DELAY_COUNTERS 0x278
57#define SPI_INTER_WORDS_DELAY_MSK GENMASK(9, 0)
58#define SPI_CS_CLK_DELAY_MSK GENMASK(19, 10)
59#define SPI_CS_CLK_DELAY_SHFT 10
60
61#define SE_SPI_SLAVE_EN (0x2BC)
62#define SPI_SLAVE_EN BIT(0)
63
64/* M_CMD OP codes for SPI */
65#define SPI_TX_ONLY 1
66#define SPI_RX_ONLY 2
67#define SPI_TX_RX 7
68#define SPI_CS_ASSERT 8
69#define SPI_CS_DEASSERT 9
70#define SPI_SCK_ONLY 10
71/* M_CMD params for SPI */
72#define SPI_PRE_CMD_DELAY BIT(0)
73#define TIMESTAMP_BEFORE BIT(1)
74#define FRAGMENTATION BIT(2)
75#define TIMESTAMP_AFTER BIT(3)
76#define POST_CMD_DELAY BIT(4)
77
78#define GSI_LOOPBACK_EN BIT(0)
79#define GSI_CS_TOGGLE BIT(3)
80#define GSI_CPHA BIT(4)
81#define GSI_CPOL BIT(5)
82
83struct geni_spi_desc {
84 int (*resources_init)(struct geni_se *se);
85 int (*set_rate)(struct geni_se *se, unsigned long clk_freq);
86 int (*power_on)(struct geni_se *se);
87 int (*power_off)(struct geni_se *se);
88};
89
90struct spi_geni_master {
91 struct geni_se se;
92 struct device *dev;
93 u32 tx_fifo_depth;
94 u32 fifo_width_bits;
95 u32 tx_wm;
96 u32 last_mode;
97 u8 last_cs;
98 unsigned long cur_speed_hz;
99 unsigned long cur_sclk_hz;
100 unsigned int cur_bits_per_word;
101 unsigned int tx_rem_bytes;
102 unsigned int rx_rem_bytes;
103 const struct spi_transfer *cur_xfer;
104 struct completion cs_done;
105 struct completion cancel_done;
106 struct completion abort_done;
107 struct completion tx_reset_done;
108 struct completion rx_reset_done;
109 unsigned int oversampling;
110 spinlock_t lock;
111 int irq;
112 bool cs_flag;
113 bool abort_failed;
114 struct dma_chan *tx;
115 struct dma_chan *rx;
116 int cur_xfer_mode;
117 const struct geni_spi_desc *dev_data;
118};
119
120static void spi_slv_setup(struct spi_geni_master *mas)
121{
122 struct geni_se *se = &mas->se;
123
124 writel(SPI_SLAVE_EN, se->base + SE_SPI_SLAVE_EN);
125 writel(GENI_IO_MUX_0_EN, se->base + GENI_OUTPUT_CTRL);
126 writel(START_TRIGGER, se->base + SE_GENI_CFG_SEQ_START);
127 dev_dbg(mas->dev, "spi slave setup done\n");
128}
129
130static int get_spi_clk_cfg(unsigned int speed_hz,
131 struct spi_geni_master *mas,
132 unsigned int *clk_idx,
133 unsigned int *clk_div)
134{
135 unsigned long sclk_freq;
136 unsigned int actual_hz;
137 int ret;
138
139 ret = geni_se_clk_freq_match(&mas->se,
140 speed_hz * mas->oversampling,
141 clk_idx, &sclk_freq, false);
142 if (ret) {
143 dev_err(mas->dev, "Failed(%d) to find src clk for %dHz\n",
144 ret, speed_hz);
145 return ret;
146 }
147
148 *clk_div = DIV_ROUND_UP(sclk_freq, mas->oversampling * speed_hz);
149 actual_hz = sclk_freq / (mas->oversampling * *clk_div);
150
151 dev_dbg(mas->dev, "req %u=>%u sclk %lu, idx %d, div %d\n", speed_hz,
152 actual_hz, sclk_freq, *clk_idx, *clk_div);
153 ret = dev_pm_opp_set_rate(mas->dev, sclk_freq);
154 if (ret)
155 dev_err(mas->dev, "dev_pm_opp_set_rate failed %d\n", ret);
156 else
157 mas->cur_sclk_hz = sclk_freq;
158
159 return ret;
160}
161
162static void handle_se_timeout(struct spi_controller *spi)
163{
164 struct spi_geni_master *mas = spi_controller_get_devdata(spi);
165 unsigned long time_left;
166 struct geni_se *se = &mas->se;
167 const struct spi_transfer *xfer;
168
169 spin_lock_irq(&mas->lock);
170 if (mas->cur_xfer_mode == GENI_SE_FIFO)
171 writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
172
173 xfer = mas->cur_xfer;
174 mas->cur_xfer = NULL;
175
176 /* The controller doesn't support the Cancel commnand in target mode */
177 if (!spi->target) {
178 reinit_completion(&mas->cancel_done);
179 geni_se_cancel_m_cmd(se);
180
181 spin_unlock_irq(&mas->lock);
182
183 time_left = wait_for_completion_timeout(&mas->cancel_done, HZ);
184 if (time_left)
185 goto reset_if_dma;
186
187 spin_lock_irq(&mas->lock);
188 }
189
190 reinit_completion(&mas->abort_done);
191 geni_se_abort_m_cmd(se);
192 spin_unlock_irq(&mas->lock);
193
194 time_left = wait_for_completion_timeout(&mas->abort_done, HZ);
195 if (!time_left) {
196 dev_err(mas->dev, "Failed to cancel/abort m_cmd\n");
197 trace_geni_se_regs(se);
198
199 /*
200 * No need for a lock since SPI core has a lock and we never
201 * access this from an interrupt.
202 */
203 mas->abort_failed = true;
204 }
205
206reset_if_dma:
207 if (mas->cur_xfer_mode == GENI_SE_DMA) {
208 if (xfer) {
209 if (xfer->tx_buf) {
210 spin_lock_irq(&mas->lock);
211 reinit_completion(&mas->tx_reset_done);
212 writel(1, se->base + SE_DMA_TX_FSM_RST);
213 spin_unlock_irq(&mas->lock);
214 time_left = wait_for_completion_timeout(&mas->tx_reset_done, HZ);
215 if (!time_left) {
216 dev_err(mas->dev, "DMA TX RESET failed\n");
217 trace_geni_se_regs(se);
218 }
219 }
220 if (xfer->rx_buf) {
221 spin_lock_irq(&mas->lock);
222 reinit_completion(&mas->rx_reset_done);
223 writel(1, se->base + SE_DMA_RX_FSM_RST);
224 spin_unlock_irq(&mas->lock);
225 time_left = wait_for_completion_timeout(&mas->rx_reset_done, HZ);
226 if (!time_left) {
227 dev_err(mas->dev, "DMA RX RESET failed\n");
228 trace_geni_se_regs(se);
229 }
230 }
231 } else {
232 /*
233 * This can happen if a timeout happened and we had to wait
234 * for lock in this function because isr was holding the lock
235 * and handling transfer completion at that time.
236 */
237 dev_warn(mas->dev, "Cancel/Abort on completed SPI transfer\n");
238 }
239 }
240}
241
242static void handle_gpi_timeout(struct spi_controller *spi)
243{
244 struct spi_geni_master *mas = spi_controller_get_devdata(spi);
245
246 dmaengine_terminate_sync(mas->tx);
247 dmaengine_terminate_sync(mas->rx);
248}
249
250static void spi_geni_handle_err(struct spi_controller *spi, struct spi_message *msg)
251{
252 struct spi_geni_master *mas = spi_controller_get_devdata(spi);
253
254 switch (mas->cur_xfer_mode) {
255 case GENI_SE_FIFO:
256 case GENI_SE_DMA:
257 handle_se_timeout(spi);
258 break;
259 case GENI_GPI_DMA:
260 handle_gpi_timeout(spi);
261 break;
262 default:
263 dev_err(mas->dev, "Abort on Mode:%d not supported", mas->cur_xfer_mode);
264 }
265}
266
267static bool spi_geni_is_abort_still_pending(struct spi_geni_master *mas)
268{
269 struct geni_se *se = &mas->se;
270 u32 m_irq, m_irq_en;
271
272 if (!mas->abort_failed)
273 return false;
274
275 /*
276 * The only known case where a transfer times out and then a cancel
277 * times out then an abort times out is if something is blocking our
278 * interrupt handler from running. Avoid starting any new transfers
279 * until that sorts itself out.
280 */
281 spin_lock_irq(&mas->lock);
282 m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS);
283 m_irq_en = readl(se->base + SE_GENI_M_IRQ_EN);
284 spin_unlock_irq(&mas->lock);
285
286 if (m_irq & m_irq_en) {
287 dev_err(mas->dev, "Interrupts pending after abort: %#010x\n",
288 m_irq & m_irq_en);
289 return true;
290 }
291
292 /*
293 * If we're here the problem resolved itself so no need to check more
294 * on future transfers.
295 */
296 mas->abort_failed = false;
297
298 return false;
299}
300
301static void spi_setup_word_len(struct spi_geni_master *mas, u16 mode,
302 unsigned int bits_per_word)
303{
304 unsigned int pack_words;
305 bool msb_first = (mode & SPI_LSB_FIRST) ? false : true;
306 struct geni_se *se = &mas->se;
307 u32 word_len;
308
309 /*
310 * If bits_per_word isn't a byte aligned value, set the packing to be
311 * 1 SPI word per FIFO word.
312 */
313 if (!(mas->fifo_width_bits % bits_per_word))
314 pack_words = mas->fifo_width_bits / bits_per_word;
315 else
316 pack_words = 1;
317 geni_se_config_packing(&mas->se, bits_per_word, pack_words, msb_first,
318 true, true);
319 word_len = (bits_per_word - MIN_WORD_LEN) & WORD_LEN_MSK;
320 writel(word_len, se->base + SE_SPI_WORD_LEN);
321}
322
323static int geni_spi_set_clock_and_bw(struct geni_se *se,
324 unsigned long clk_hz)
325{
326 struct spi_controller *spi = dev_get_drvdata(se->dev);
327 struct spi_geni_master *mas = spi_controller_get_devdata(spi);
328 u32 clk_sel, m_clk_cfg, idx, div;
329 int ret;
330
331 if (clk_hz == mas->cur_speed_hz)
332 return 0;
333
334 ret = get_spi_clk_cfg(clk_hz, mas, &idx, &div);
335 if (ret) {
336 dev_err(mas->dev, "Err setting clk to %lu: %d\n", clk_hz, ret);
337 return ret;
338 }
339
340 /*
341 * SPI core clock gets configured with the requested frequency
342 * or the frequency closer to the requested frequency.
343 * For that reason requested frequency is stored in the
344 * cur_speed_hz and referred in the consecutive transfer instead
345 * of calling clk_get_rate() API.
346 */
347 mas->cur_speed_hz = clk_hz;
348
349 clk_sel = idx & CLK_SEL_MSK;
350 m_clk_cfg = (div << CLK_DIV_SHFT) | SER_CLK_EN;
351 writel(clk_sel, se->base + SE_GENI_CLK_SEL);
352 writel(m_clk_cfg, se->base + GENI_SER_M_CLK_CFG);
353
354 trace_geni_spi_clk_cfg(mas->dev, clk_hz, mas->cur_sclk_hz, idx, div,
355 mas->cur_bits_per_word);
356
357 /* Set BW quota for CPU as driver supports FIFO mode only. */
358 se->icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(mas->cur_speed_hz);
359 ret = geni_icc_set_bw(se);
360 if (ret)
361 return ret;
362
363 return 0;
364}
365
366static int setup_fifo_params(struct spi_device *spi_slv,
367 struct spi_controller *spi)
368{
369 struct spi_geni_master *mas = spi_controller_get_devdata(spi);
370 struct geni_se *se = &mas->se;
371 u8 chipselect = spi_get_chipselect(spi_slv, 0);
372 bool cs_changed = (mas->last_cs != chipselect);
373 u32 mode_changed = mas->last_mode ^ spi_slv->mode;
374
375 mas->last_cs = chipselect;
376 mas->last_mode = spi_slv->mode;
377
378 if (mode_changed & SPI_LSB_FIRST)
379 mas->cur_bits_per_word = 0; /* force next setup_se_xfer to call spi_setup_word_len */
380 if (mode_changed & SPI_LOOP)
381 writel((spi_slv->mode & SPI_LOOP) ? LOOPBACK_ENABLE : 0, se->base + SE_SPI_LOOPBACK);
382 if (cs_changed)
383 writel(chipselect, se->base + SE_SPI_DEMUX_SEL);
384 if (mode_changed & SPI_CPHA)
385 writel((spi_slv->mode & SPI_CPHA) ? CPHA : 0, se->base + SE_SPI_CPHA);
386 if (mode_changed & SPI_CPOL)
387 writel((spi_slv->mode & SPI_CPOL) ? CPOL : 0, se->base + SE_SPI_CPOL);
388 if ((mode_changed & SPI_CS_HIGH) || (cs_changed && (spi_slv->mode & SPI_CS_HIGH)))
389 writel((spi_slv->mode & SPI_CS_HIGH) ? BIT(chipselect) : 0, se->base + SE_SPI_DEMUX_OUTPUT_INV);
390
391 trace_geni_spi_setup_params(mas->dev, chipselect, spi_slv->mode,
392 mode_changed, cs_changed);
393
394 return 0;
395}
396
397static void
398spi_gsi_callback_result(void *cb, const struct dmaengine_result *result)
399{
400 struct spi_controller *spi = cb;
401 struct spi_geni_master *mas = spi_controller_get_devdata(spi);
402
403 spi->cur_msg->status = -EIO;
404 if (result->result != DMA_TRANS_NOERROR) {
405 dev_err(&spi->dev, "DMA txn failed: %d\n", result->result);
406 trace_geni_se_regs(&mas->se);
407 spi_finalize_current_transfer(spi);
408 return;
409 }
410
411 if (!result->residue) {
412 spi->cur_msg->status = 0;
413 dev_dbg(&spi->dev, "DMA txn completed\n");
414 } else {
415 dev_err(&spi->dev, "DMA xfer has pending: %d\n", result->residue);
416 trace_geni_se_regs(&mas->se);
417 }
418
419 spi_finalize_current_transfer(spi);
420}
421
422static int setup_gsi_xfer(struct spi_transfer *xfer, struct spi_geni_master *mas,
423 struct spi_device *spi_slv, struct spi_controller *spi)
424{
425 unsigned long flags = DMA_PREP_INTERRUPT | DMA_CTRL_ACK;
426 struct dma_slave_config config = {};
427 struct gpi_spi_config peripheral = {};
428 struct dma_async_tx_descriptor *tx_desc, *rx_desc;
429 int ret;
430
431 config.peripheral_config = &peripheral;
432 config.peripheral_size = sizeof(peripheral);
433 peripheral.set_config = true;
434
435 if (xfer->bits_per_word != mas->cur_bits_per_word ||
436 xfer->speed_hz != mas->cur_speed_hz) {
437 mas->cur_bits_per_word = xfer->bits_per_word;
438 mas->cur_speed_hz = xfer->speed_hz;
439 }
440
441 if (xfer->tx_buf && xfer->rx_buf) {
442 peripheral.cmd = SPI_DUPLEX;
443 } else if (xfer->tx_buf) {
444 peripheral.cmd = SPI_TX;
445 peripheral.rx_len = 0;
446 } else if (xfer->rx_buf) {
447 peripheral.cmd = SPI_RX;
448 if (!(mas->cur_bits_per_word % MIN_WORD_LEN)) {
449 peripheral.rx_len = ((xfer->len << 3) / mas->cur_bits_per_word);
450 } else {
451 int bytes_per_word = (mas->cur_bits_per_word / BITS_PER_BYTE) + 1;
452
453 peripheral.rx_len = (xfer->len / bytes_per_word);
454 }
455 }
456
457 peripheral.loopback_en = !!(spi_slv->mode & SPI_LOOP);
458 peripheral.clock_pol_high = !!(spi_slv->mode & SPI_CPOL);
459 peripheral.data_pol_high = !!(spi_slv->mode & SPI_CPHA);
460 peripheral.cs = spi_get_chipselect(spi_slv, 0);
461 peripheral.pack_en = true;
462 peripheral.word_len = xfer->bits_per_word - MIN_WORD_LEN;
463
464 ret = get_spi_clk_cfg(mas->cur_speed_hz, mas,
465 &peripheral.clk_src, &peripheral.clk_div);
466 if (ret) {
467 dev_err(mas->dev, "Err in get_spi_clk_cfg() :%d\n", ret);
468 return ret;
469 }
470
471 /*
472 * Set fragmentation to keep CS asserted after this transfer when:
473 * - non-last transfer with cs_change=0: keep CS asserted between chained transfers
474 * - last transfer with cs_change=1: keep CS asserted after the message
475 * (e.g. TPM TIS SPI uses cs_change=1 on single-transfer messages to
476 * keep CS asserted across header, wait-state and data phases)
477 */
478 peripheral.fragmentation = list_is_last(&xfer->transfer_list, &spi->cur_msg->transfers) ?
479 xfer->cs_change : !xfer->cs_change;
480
481 if (peripheral.cmd & SPI_RX) {
482 dmaengine_slave_config(mas->rx, &config);
483 rx_desc = dmaengine_prep_slave_sg(mas->rx, xfer->rx_sg.sgl, xfer->rx_sg.nents,
484 DMA_DEV_TO_MEM, flags);
485 if (!rx_desc) {
486 dev_err(mas->dev, "Err setting up rx desc\n");
487 return -EIO;
488 }
489 }
490
491 /*
492 * Prepare the TX always, even for RX or tx_buf being null, we would
493 * need TX to be prepared per GSI spec
494 */
495 dmaengine_slave_config(mas->tx, &config);
496 tx_desc = dmaengine_prep_slave_sg(mas->tx, xfer->tx_sg.sgl, xfer->tx_sg.nents,
497 DMA_MEM_TO_DEV, flags);
498 if (!tx_desc) {
499 dev_err(mas->dev, "Err setting up tx desc\n");
500 return -EIO;
501 }
502
503 tx_desc->callback_result = spi_gsi_callback_result;
504 tx_desc->callback_param = spi;
505
506 if (peripheral.cmd & SPI_RX)
507 dmaengine_submit(rx_desc);
508 dmaengine_submit(tx_desc);
509
510 if (peripheral.cmd & SPI_RX)
511 dma_async_issue_pending(mas->rx);
512
513 dma_async_issue_pending(mas->tx);
514 return 1;
515}
516
517static u32 get_xfer_len_in_words(struct spi_transfer *xfer,
518 struct spi_geni_master *mas)
519{
520 u32 len;
521
522 if (!(xfer->bits_per_word % MIN_WORD_LEN))
523 len = xfer->len * BITS_PER_BYTE / xfer->bits_per_word;
524 else
525 len = xfer->len / (xfer->bits_per_word / BITS_PER_BYTE + 1);
526 len &= TRANS_LEN_MSK;
527
528 return len;
529}
530
531static bool geni_can_dma(struct spi_controller *ctlr,
532 struct spi_device *slv, struct spi_transfer *xfer)
533{
534 struct spi_geni_master *mas = spi_controller_get_devdata(slv->controller);
535 u32 len, fifo_size;
536
537 if (mas->cur_xfer_mode == GENI_GPI_DMA)
538 return true;
539
540 /* Set SE DMA mode for SPI target. */
541 if (ctlr->target)
542 return true;
543
544 len = get_xfer_len_in_words(xfer, mas);
545 fifo_size = mas->tx_fifo_depth * mas->fifo_width_bits / xfer->bits_per_word;
546
547 if (len > fifo_size)
548 return true;
549 else
550 return false;
551}
552
553static int spi_geni_prepare_message(struct spi_controller *spi,
554 struct spi_message *spi_msg)
555{
556 struct spi_geni_master *mas = spi_controller_get_devdata(spi);
557 int ret;
558
559 switch (mas->cur_xfer_mode) {
560 case GENI_SE_FIFO:
561 case GENI_SE_DMA:
562 if (spi_geni_is_abort_still_pending(mas))
563 return -EBUSY;
564 ret = setup_fifo_params(spi_msg->spi, spi);
565 if (ret)
566 dev_err(mas->dev, "Couldn't select mode %d\n", ret);
567 return ret;
568
569 case GENI_GPI_DMA:
570 /* nothing to do for GPI DMA */
571 return 0;
572 }
573
574 dev_err(mas->dev, "Mode not supported %d", mas->cur_xfer_mode);
575 return -EINVAL;
576}
577
578static void spi_geni_release_dma_chan(void *data)
579{
580 struct spi_geni_master *mas = data;
581
582 if (mas->rx) {
583 dma_release_channel(mas->rx);
584 mas->rx = NULL;
585 }
586
587 if (mas->tx) {
588 dma_release_channel(mas->tx);
589 mas->tx = NULL;
590 }
591}
592
593static int spi_geni_grab_gpi_chan(struct spi_geni_master *mas)
594{
595 int ret;
596
597 mas->tx = dma_request_chan(mas->dev, "tx");
598 if (IS_ERR(mas->tx)) {
599 ret = dev_err_probe(mas->dev, PTR_ERR(mas->tx),
600 "Failed to get tx DMA ch\n");
601 goto err_tx;
602 }
603
604 mas->rx = dma_request_chan(mas->dev, "rx");
605 if (IS_ERR(mas->rx)) {
606 ret = dev_err_probe(mas->dev, PTR_ERR(mas->rx),
607 "Failed to get rx DMA ch\n");
608 goto err_rx;
609 }
610
611 ret = devm_add_action_or_reset(mas->dev, spi_geni_release_dma_chan, mas);
612 if (ret) {
613 dev_err(mas->dev, "Unable to add action.\n");
614 return ret;
615 }
616
617 return 0;
618
619err_rx:
620 mas->rx = NULL;
621 dma_release_channel(mas->tx);
622err_tx:
623 mas->tx = NULL;
624 return ret;
625}
626
627static int spi_geni_init(struct spi_geni_master *mas)
628{
629 struct spi_controller *spi = dev_get_drvdata(mas->dev);
630 struct geni_se *se = &mas->se;
631 unsigned int proto, major, minor, ver;
632 u32 spi_tx_cfg, fifo_disable;
633 int ret = -ENXIO;
634
635 PM_RUNTIME_ACQUIRE_IF_ENABLED(mas->dev, pm);
636 ret = PM_RUNTIME_ACQUIRE_ERR(&pm);
637 if (ret < 0) {
638 dev_err(mas->dev, "Failed to resume and get %d\n", ret);
639 return ret;
640 }
641
642 proto = geni_se_read_proto(se);
643
644 if (spi->target) {
645 if (proto != GENI_SE_SPI_SLAVE) {
646 dev_err(mas->dev, "Invalid proto %d\n", proto);
647 return -EINVAL;
648 }
649 spi_slv_setup(mas);
650 } else if (proto == GENI_SE_INVALID_PROTO) {
651 ret = geni_load_se_firmware(se, GENI_SE_SPI);
652 if (ret) {
653 dev_err(mas->dev, "spi master firmware load failed ret: %d\n", ret);
654 return ret;
655 }
656 } else if (proto != GENI_SE_SPI) {
657 dev_err(mas->dev, "Invalid proto %d\n", proto);
658 return -EINVAL;
659 }
660 mas->tx_fifo_depth = geni_se_get_tx_fifo_depth(se);
661
662 /* Width of Tx and Rx FIFO is same */
663 mas->fifo_width_bits = geni_se_get_tx_fifo_width(se);
664
665 /*
666 * Hardware programming guide suggests to configure
667 * RX FIFO RFR level to fifo_depth-2.
668 */
669 geni_se_init(se, mas->tx_fifo_depth - 3, mas->tx_fifo_depth - 2);
670 /* Transmit an entire FIFO worth of data per IRQ */
671 mas->tx_wm = 1;
672 ver = geni_se_get_qup_hw_version(se);
673 major = GENI_SE_VERSION_MAJOR(ver);
674 minor = GENI_SE_VERSION_MINOR(ver);
675
676 if (major == 1 && minor == 0)
677 mas->oversampling = 2;
678 else
679 mas->oversampling = 1;
680
681 fifo_disable = readl(se->base + GENI_IF_DISABLE_RO) & FIFO_IF_DISABLE;
682 switch (fifo_disable) {
683 case 1:
684 ret = spi_geni_grab_gpi_chan(mas);
685 if (!ret) { /* success case */
686 mas->cur_xfer_mode = GENI_GPI_DMA;
687 geni_se_select_mode(se, GENI_GPI_DMA);
688 dev_dbg(mas->dev, "Using GPI DMA mode for SPI\n");
689 break;
690 } else if (ret == -EPROBE_DEFER) {
691 return ret;
692 }
693 /*
694 * in case of failure to get gpi dma channel, we can still do the
695 * FIFO mode, so fallthrough
696 */
697 dev_warn(mas->dev, "FIFO mode disabled, but couldn't get DMA, fall back to FIFO mode\n");
698 fallthrough;
699
700 case 0:
701 mas->cur_xfer_mode = GENI_SE_FIFO;
702 geni_se_select_mode(se, GENI_SE_FIFO);
703 /* setup_fifo_params assumes that these registers start with a zero value */
704 writel(0, se->base + SE_SPI_LOOPBACK);
705 writel(0, se->base + SE_SPI_DEMUX_SEL);
706 writel(0, se->base + SE_SPI_CPHA);
707 writel(0, se->base + SE_SPI_CPOL);
708 writel(0, se->base + SE_SPI_DEMUX_OUTPUT_INV);
709 ret = 0;
710 break;
711 }
712
713 /* We never control CS manually */
714 if (!spi->target) {
715 spi_tx_cfg = readl(se->base + SE_SPI_TRANS_CFG);
716 spi_tx_cfg &= ~CS_TOGGLE;
717 writel(spi_tx_cfg, se->base + SE_SPI_TRANS_CFG);
718 }
719
720 return ret;
721}
722
723static unsigned int geni_byte_per_fifo_word(struct spi_geni_master *mas)
724{
725 /*
726 * Calculate how many bytes we'll put in each FIFO word. If the
727 * transfer words don't pack cleanly into a FIFO word we'll just put
728 * one transfer word in each FIFO word. If they do pack we'll pack 'em.
729 */
730 if (mas->fifo_width_bits % mas->cur_bits_per_word)
731 return roundup_pow_of_two(DIV_ROUND_UP(mas->cur_bits_per_word,
732 BITS_PER_BYTE));
733
734 return mas->fifo_width_bits / BITS_PER_BYTE;
735}
736
737static bool geni_spi_handle_tx(struct spi_geni_master *mas)
738{
739 struct geni_se *se = &mas->se;
740 unsigned int max_bytes;
741 const u8 *tx_buf;
742 unsigned int bytes_per_fifo_word = geni_byte_per_fifo_word(mas);
743 unsigned int i = 0;
744
745 /* Stop the watermark IRQ if nothing to send */
746 if (!mas->cur_xfer) {
747 writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
748 return false;
749 }
750
751 max_bytes = (mas->tx_fifo_depth - mas->tx_wm) * bytes_per_fifo_word;
752 if (mas->tx_rem_bytes < max_bytes)
753 max_bytes = mas->tx_rem_bytes;
754
755 tx_buf = mas->cur_xfer->tx_buf + mas->cur_xfer->len - mas->tx_rem_bytes;
756 while (i < max_bytes) {
757 unsigned int j;
758 unsigned int bytes_to_write;
759 u32 fifo_word = 0;
760 u8 *fifo_byte = (u8 *)&fifo_word;
761
762 bytes_to_write = min(bytes_per_fifo_word, max_bytes - i);
763 for (j = 0; j < bytes_to_write; j++)
764 fifo_byte[j] = tx_buf[i++];
765 iowrite32_rep(se->base + SE_GENI_TX_FIFOn, &fifo_word, 1);
766 }
767 mas->tx_rem_bytes -= max_bytes;
768 if (!mas->tx_rem_bytes) {
769 writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
770 return false;
771 }
772 return true;
773}
774
775static void geni_spi_handle_rx(struct spi_geni_master *mas)
776{
777 struct geni_se *se = &mas->se;
778 u32 rx_fifo_status;
779 unsigned int rx_bytes;
780 unsigned int rx_last_byte_valid;
781 u8 *rx_buf;
782 unsigned int bytes_per_fifo_word = geni_byte_per_fifo_word(mas);
783 unsigned int i = 0;
784
785 rx_fifo_status = readl(se->base + SE_GENI_RX_FIFO_STATUS);
786 rx_bytes = (rx_fifo_status & RX_FIFO_WC_MSK) * bytes_per_fifo_word;
787 if (rx_fifo_status & RX_LAST) {
788 rx_last_byte_valid = rx_fifo_status & RX_LAST_BYTE_VALID_MSK;
789 rx_last_byte_valid >>= RX_LAST_BYTE_VALID_SHFT;
790 if (rx_last_byte_valid && rx_last_byte_valid < 4)
791 rx_bytes -= bytes_per_fifo_word - rx_last_byte_valid;
792 }
793
794 /* Clear out the FIFO and bail if nowhere to put it */
795 if (!mas->cur_xfer) {
796 for (i = 0; i < DIV_ROUND_UP(rx_bytes, bytes_per_fifo_word); i++)
797 readl(se->base + SE_GENI_RX_FIFOn);
798 return;
799 }
800
801 if (mas->rx_rem_bytes < rx_bytes)
802 rx_bytes = mas->rx_rem_bytes;
803
804 rx_buf = mas->cur_xfer->rx_buf + mas->cur_xfer->len - mas->rx_rem_bytes;
805 while (i < rx_bytes) {
806 u32 fifo_word = 0;
807 u8 *fifo_byte = (u8 *)&fifo_word;
808 unsigned int bytes_to_read;
809 unsigned int j;
810
811 bytes_to_read = min(bytes_per_fifo_word, rx_bytes - i);
812 ioread32_rep(se->base + SE_GENI_RX_FIFOn, &fifo_word, 1);
813 for (j = 0; j < bytes_to_read; j++)
814 rx_buf[i++] = fifo_byte[j];
815 }
816 mas->rx_rem_bytes -= rx_bytes;
817}
818
819static int setup_se_xfer(struct spi_transfer *xfer,
820 struct spi_geni_master *mas,
821 u16 mode, struct spi_controller *spi)
822{
823 u32 m_cmd = 0;
824 u32 m_params = 0;
825 u32 len;
826 struct geni_se *se = &mas->se;
827 int ret;
828
829 /*
830 * Ensure that our interrupt handler isn't still running from some
831 * prior command before we start messing with the hardware behind
832 * its back. We don't need to _keep_ the lock here since we're only
833 * worried about racing with out interrupt handler. The SPI core
834 * already handles making sure that we're not trying to do two
835 * transfers at once or setting a chip select and doing a transfer
836 * concurrently.
837 *
838 * NOTE: we actually _can't_ hold the lock here because possibly we
839 * might call clk_set_rate() which needs to be able to sleep.
840 */
841 spin_lock_irq(&mas->lock);
842 spin_unlock_irq(&mas->lock);
843
844 if (xfer->bits_per_word != mas->cur_bits_per_word) {
845 spi_setup_word_len(mas, mode, xfer->bits_per_word);
846 mas->cur_bits_per_word = xfer->bits_per_word;
847 }
848
849 /* Speed and bits per word can be overridden per transfer */
850 ret = mas->dev_data->set_rate(&mas->se, xfer->speed_hz);
851 if (ret)
852 return ret;
853
854 mas->tx_rem_bytes = 0;
855 mas->rx_rem_bytes = 0;
856
857 len = get_xfer_len_in_words(xfer, mas);
858
859 mas->cur_xfer = xfer;
860 if (xfer->tx_buf) {
861 m_cmd |= SPI_TX_ONLY;
862 mas->tx_rem_bytes = xfer->len;
863 writel(len, se->base + SE_SPI_TX_TRANS_LEN);
864 }
865
866 if (xfer->rx_buf) {
867 m_cmd |= SPI_RX_ONLY;
868 writel(len, se->base + SE_SPI_RX_TRANS_LEN);
869 mas->rx_rem_bytes = xfer->len;
870 }
871
872 /*
873 * Select DMA mode if sgt are present; and with only 1 entry
874 * This is not a serious limitation because the xfer buffers are
875 * expected to fit into in 1 entry almost always, and if any
876 * doesn't for any reason we fall back to FIFO mode anyway
877 */
878 if (!xfer->tx_sg.nents && !xfer->rx_sg.nents)
879 mas->cur_xfer_mode = GENI_SE_FIFO;
880 else if (xfer->tx_sg.nents > 1 || xfer->rx_sg.nents > 1) {
881 dev_warn_once(mas->dev, "Doing FIFO, cannot handle tx_nents-%d, rx_nents-%d\n",
882 xfer->tx_sg.nents, xfer->rx_sg.nents);
883 mas->cur_xfer_mode = GENI_SE_FIFO;
884 } else
885 mas->cur_xfer_mode = GENI_SE_DMA;
886 geni_se_select_mode(se, mas->cur_xfer_mode);
887
888 /*
889 * Set FRAGMENTATION to keep CS asserted after this transfer when:
890 * - non-last transfer with cs_change=0: keep CS asserted between chained transfers
891 * - last transfer with cs_change=1: keep CS asserted after the message
892 * (e.g. TPM TIS SPI uses cs_change=1 on single-transfer messages to
893 * keep CS asserted across header, wait-state and data phases)
894 */
895 if (list_is_last(&xfer->transfer_list, &spi->cur_msg->transfers) ?
896 xfer->cs_change : !xfer->cs_change)
897 m_params = FRAGMENTATION;
898
899 /*
900 * Lock around right before we start the transfer since our
901 * interrupt could come in at any time now.
902 */
903 spin_lock_irq(&mas->lock);
904 geni_se_setup_m_cmd(se, m_cmd, m_params);
905
906 trace_geni_spi_transfer(mas->dev, len, m_cmd);
907
908 if (mas->cur_xfer_mode == GENI_SE_DMA) {
909 if (m_cmd & SPI_RX_ONLY)
910 geni_se_rx_init_dma(se, sg_dma_address(xfer->rx_sg.sgl),
911 sg_dma_len(xfer->rx_sg.sgl));
912 if (m_cmd & SPI_TX_ONLY)
913 geni_se_tx_init_dma(se, sg_dma_address(xfer->tx_sg.sgl),
914 sg_dma_len(xfer->tx_sg.sgl));
915 } else if (m_cmd & SPI_TX_ONLY) {
916 if (geni_spi_handle_tx(mas))
917 writel(mas->tx_wm, se->base + SE_GENI_TX_WATERMARK_REG);
918 }
919
920 spin_unlock_irq(&mas->lock);
921 return ret;
922}
923
924static int spi_geni_transfer_one(struct spi_controller *spi,
925 struct spi_device *slv,
926 struct spi_transfer *xfer)
927{
928 struct spi_geni_master *mas = spi_controller_get_devdata(spi);
929 int ret;
930
931 if (spi_geni_is_abort_still_pending(mas))
932 return -EBUSY;
933
934 /* Terminate and return success for 0 byte length transfer */
935 if (!xfer->len)
936 return 0;
937
938 if (mas->cur_xfer_mode == GENI_SE_FIFO || mas->cur_xfer_mode == GENI_SE_DMA) {
939 ret = setup_se_xfer(xfer, mas, slv->mode, spi);
940 /* SPI framework expects +ve ret code to wait for transfer complete */
941 if (!ret)
942 ret = 1;
943 return ret;
944 }
945 return setup_gsi_xfer(xfer, mas, slv, spi);
946}
947
948static irqreturn_t geni_spi_isr(int irq, void *data)
949{
950 struct spi_controller *spi = data;
951 struct spi_geni_master *mas = spi_controller_get_devdata(spi);
952 struct geni_se *se = &mas->se;
953 u32 m_irq, dma_tx_status, dma_rx_status;
954
955 m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS);
956 dma_tx_status = readl_relaxed(se->base + SE_DMA_TX_IRQ_STAT);
957 dma_rx_status = readl_relaxed(se->base + SE_DMA_RX_IRQ_STAT);
958
959 if (!m_irq && !dma_tx_status && !dma_rx_status)
960 return IRQ_NONE;
961
962 trace_geni_spi_irq(mas->dev, m_irq, dma_tx_status, dma_rx_status);
963
964 if (m_irq & (M_CMD_OVERRUN_EN | M_ILLEGAL_CMD_EN | M_CMD_FAILURE_EN |
965 M_RX_FIFO_RD_ERR_EN | M_RX_FIFO_WR_ERR_EN |
966 M_TX_FIFO_RD_ERR_EN | M_TX_FIFO_WR_ERR_EN)) {
967 dev_warn(mas->dev, "Unexpected IRQ err status %#010x\n", m_irq);
968 trace_geni_se_regs(se);
969 }
970
971 spin_lock(&mas->lock);
972
973 if (mas->cur_xfer_mode == GENI_SE_FIFO) {
974 if ((m_irq & M_RX_FIFO_WATERMARK_EN) || (m_irq & M_RX_FIFO_LAST_EN))
975 geni_spi_handle_rx(mas);
976
977 if (m_irq & M_TX_FIFO_WATERMARK_EN)
978 geni_spi_handle_tx(mas);
979
980 if (m_irq & M_CMD_DONE_EN) {
981 if (mas->cur_xfer) {
982 spi_finalize_current_transfer(spi);
983 mas->cur_xfer = NULL;
984 /*
985 * If this happens, then a CMD_DONE came before all the
986 * Tx buffer bytes were sent out. This is unusual, log
987 * this condition and disable the WM interrupt to
988 * prevent the system from stalling due an interrupt
989 * storm.
990 *
991 * If this happens when all Rx bytes haven't been
992 * received, log the condition. The only known time
993 * this can happen is if bits_per_word != 8 and some
994 * registers that expect xfer lengths in num spi_words
995 * weren't written correctly.
996 */
997 if (mas->tx_rem_bytes) {
998 trace_geni_se_regs(se);
999 writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
1000 dev_err(mas->dev, "Premature done. tx_rem = %d bpw%d\n",
1001 mas->tx_rem_bytes, mas->cur_bits_per_word);
1002 }
1003 if (mas->rx_rem_bytes) {
1004 dev_err(mas->dev, "Premature done. rx_rem = %d bpw%d\n",
1005 mas->rx_rem_bytes, mas->cur_bits_per_word);
1006 trace_geni_se_regs(se);
1007 }
1008 } else {
1009 complete(&mas->cs_done);
1010 }
1011 }
1012 } else if (mas->cur_xfer_mode == GENI_SE_DMA) {
1013 const struct spi_transfer *xfer = mas->cur_xfer;
1014
1015 if (dma_tx_status)
1016 writel(dma_tx_status, se->base + SE_DMA_TX_IRQ_CLR);
1017 if (dma_rx_status)
1018 writel(dma_rx_status, se->base + SE_DMA_RX_IRQ_CLR);
1019 if (dma_tx_status & TX_DMA_DONE)
1020 mas->tx_rem_bytes = 0;
1021 if (dma_rx_status & RX_DMA_DONE)
1022 mas->rx_rem_bytes = 0;
1023 if (dma_tx_status & TX_RESET_DONE)
1024 complete(&mas->tx_reset_done);
1025 if (dma_rx_status & RX_RESET_DONE)
1026 complete(&mas->rx_reset_done);
1027 if (!mas->tx_rem_bytes && !mas->rx_rem_bytes && xfer) {
1028 spi_finalize_current_transfer(spi);
1029 mas->cur_xfer = NULL;
1030 }
1031 }
1032
1033 if (m_irq & M_CMD_CANCEL_EN)
1034 complete(&mas->cancel_done);
1035 if (m_irq & M_CMD_ABORT_EN)
1036 complete(&mas->abort_done);
1037
1038 /*
1039 * It's safe or a good idea to Ack all of our interrupts at the end
1040 * of the function. Specifically:
1041 * - M_CMD_DONE_EN / M_RX_FIFO_LAST_EN: Edge triggered interrupts and
1042 * clearing Acks. Clearing at the end relies on nobody else having
1043 * started a new transfer yet or else we could be clearing _their_
1044 * done bit, but everyone grabs the spinlock before starting a new
1045 * transfer.
1046 * - M_RX_FIFO_WATERMARK_EN / M_TX_FIFO_WATERMARK_EN: These appear
1047 * to be "latched level" interrupts so it's important to clear them
1048 * _after_ you've handled the condition and always safe to do so
1049 * since they'll re-assert if they're still happening.
1050 */
1051 writel(m_irq, se->base + SE_GENI_M_IRQ_CLEAR);
1052
1053 spin_unlock(&mas->lock);
1054
1055 return IRQ_HANDLED;
1056}
1057
1058static int spi_geni_target_abort(struct spi_controller *spi)
1059{
1060 if (!spi->cur_msg)
1061 return 0;
1062
1063 handle_se_timeout(spi);
1064 spi_finalize_current_transfer(spi);
1065
1066 return 0;
1067}
1068
1069static int spi_geni_probe(struct platform_device *pdev)
1070{
1071 int ret, irq;
1072 struct spi_controller *spi;
1073 struct spi_geni_master *mas;
1074 void __iomem *base;
1075 struct device *dev = &pdev->dev;
1076
1077 irq = platform_get_irq(pdev, 0);
1078 if (irq < 0)
1079 return irq;
1080
1081 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
1082 if (ret)
1083 return dev_err_probe(dev, ret, "could not set DMA mask\n");
1084
1085 base = devm_platform_ioremap_resource(pdev, 0);
1086 if (IS_ERR(base))
1087 return PTR_ERR(base);
1088
1089 if (device_property_read_bool(dev, "spi-slave"))
1090 spi = devm_spi_alloc_target(dev, sizeof(*mas));
1091 else
1092 spi = devm_spi_alloc_host(dev, sizeof(*mas));
1093
1094 if (!spi)
1095 return -ENOMEM;
1096
1097 platform_set_drvdata(pdev, spi);
1098 mas = spi_controller_get_devdata(spi);
1099 mas->irq = irq;
1100 mas->dev = dev;
1101 mas->se.dev = dev;
1102 mas->se.wrapper = dev_get_drvdata(dev->parent);
1103 mas->se.base = base;
1104
1105 mas->dev_data = device_get_match_data(&pdev->dev);
1106 if (!mas->dev_data)
1107 return -EINVAL;
1108
1109 ret = mas->dev_data->resources_init(&mas->se);
1110 if (ret)
1111 return ret;
1112
1113 spi->bus_num = -1;
1114 spi->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_CS_HIGH;
1115 spi->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1116 spi->num_chipselect = 4;
1117 spi->max_speed_hz = 50000000;
1118 spi->max_dma_len = 0xffff0; /* 24 bits for tx/rx dma length */
1119 spi->prepare_message = spi_geni_prepare_message;
1120 spi->transfer_one = spi_geni_transfer_one;
1121 spi->can_dma = geni_can_dma;
1122 spi->dma_map_dev = dev->parent;
1123 spi->auto_runtime_pm = true;
1124 spi->handle_err = spi_geni_handle_err;
1125 spi->use_gpio_descriptors = true;
1126
1127 init_completion(&mas->cs_done);
1128 init_completion(&mas->cancel_done);
1129 init_completion(&mas->abort_done);
1130 init_completion(&mas->tx_reset_done);
1131 init_completion(&mas->rx_reset_done);
1132 spin_lock_init(&mas->lock);
1133
1134 if (spi->target)
1135 spi->target_abort = spi_geni_target_abort;
1136
1137 pm_runtime_use_autosuspend(&pdev->dev);
1138 pm_runtime_set_autosuspend_delay(&pdev->dev, 250);
1139 ret = devm_pm_runtime_enable(dev);
1140 if (ret)
1141 return ret;
1142
1143 ret = spi_geni_init(mas);
1144 if (ret)
1145 return ret;
1146
1147 /*
1148 * TX is required per GSI spec, see setup_gsi_xfer().
1149 */
1150 if (mas->cur_xfer_mode == GENI_GPI_DMA)
1151 spi->flags = SPI_CONTROLLER_MUST_TX;
1152
1153 ret = devm_request_irq(dev, mas->irq, geni_spi_isr, 0, dev_name(dev), spi);
1154 if (ret)
1155 return ret;
1156
1157 return devm_spi_register_controller(dev, spi);
1158}
1159
1160static int spi_geni_runtime_suspend(struct device *dev)
1161{
1162 struct spi_controller *spi = dev_get_drvdata(dev);
1163 struct spi_geni_master *mas = spi_controller_get_devdata(spi);
1164
1165 return mas->dev_data->power_off ?
1166 mas->dev_data->power_off(&mas->se) : 0;
1167}
1168
1169static int spi_geni_runtime_resume(struct device *dev)
1170{
1171 struct spi_controller *spi = dev_get_drvdata(dev);
1172 struct spi_geni_master *mas = spi_controller_get_devdata(spi);
1173 int ret;
1174
1175 if (mas->dev_data->power_on) {
1176 ret = mas->dev_data->power_on(&mas->se);
1177 if (ret)
1178 return ret;
1179 }
1180
1181 if (mas->se.has_opp)
1182 return dev_pm_opp_set_rate(mas->dev, mas->cur_sclk_hz);
1183
1184 return 0;
1185}
1186
1187static int spi_geni_suspend(struct device *dev)
1188{
1189 struct spi_controller *spi = dev_get_drvdata(dev);
1190 int ret;
1191
1192 ret = spi_controller_suspend(spi);
1193 if (ret)
1194 return ret;
1195
1196 ret = pm_runtime_force_suspend(dev);
1197 if (ret)
1198 spi_controller_resume(spi);
1199
1200 return ret;
1201}
1202
1203static int spi_geni_resume(struct device *dev)
1204{
1205 struct spi_controller *spi = dev_get_drvdata(dev);
1206 int ret;
1207
1208 ret = pm_runtime_force_resume(dev);
1209 if (ret)
1210 return ret;
1211
1212 ret = spi_controller_resume(spi);
1213 if (ret)
1214 pm_runtime_force_suspend(dev);
1215
1216 return ret;
1217}
1218
1219static const struct dev_pm_ops spi_geni_pm_ops = {
1220 RUNTIME_PM_OPS(spi_geni_runtime_suspend, spi_geni_runtime_resume, NULL)
1221 SYSTEM_SLEEP_PM_OPS(spi_geni_suspend, spi_geni_resume)
1222};
1223
1224static const struct geni_spi_desc geni_spi = {
1225 .resources_init = geni_se_resources_init,
1226 .set_rate = geni_spi_set_clock_and_bw,
1227 .power_on = geni_se_resources_activate,
1228 .power_off = geni_se_resources_deactivate,
1229};
1230
1231static const struct geni_spi_desc sa8255p_geni_spi = {
1232 .resources_init = geni_se_domain_attach,
1233 .set_rate = geni_se_set_perf_opp,
1234};
1235
1236static const struct of_device_id spi_geni_dt_match[] = {
1237 { .compatible = "qcom,geni-spi", .data = &geni_spi },
1238 { .compatible = "qcom,sa8255p-geni-spi", .data = &sa8255p_geni_spi },
1239 {}
1240};
1241MODULE_DEVICE_TABLE(of, spi_geni_dt_match);
1242
1243static struct platform_driver spi_geni_driver = {
1244 .probe = spi_geni_probe,
1245 .driver = {
1246 .name = "geni_spi",
1247 .pm = pm_ptr(&spi_geni_pm_ops),
1248 .of_match_table = spi_geni_dt_match,
1249 },
1250};
1251module_platform_driver(spi_geni_driver);
1252
1253MODULE_DESCRIPTION("SPI driver for GENI based QUP cores");
1254MODULE_LICENSE("GPL v2");