| 1 | |
| 2 | |
| 3 | * Copyright (C) 2018 Exceet Electronics GmbH
|
| 4 | * Copyright (C) 2018 Bootlin
|
| 5 | *
|
| 6 | * Author: Boris Brezillon <[email protected]>
|
| 7 |
|
| 8 | #include <linux/dmaengine.h>
|
| 9 | #include <linux/iopoll.h>
|
| 10 | #include <linux/pm_runtime.h>
|
| 11 | #include <linux/spi/spi.h>
|
| 12 | #include <linux/spi/spi-mem.h>
|
| 13 | #include <linux/sched/task_stack.h>
|
| 14 |
|
| 15 | #define CREATE_TRACE_POINTS
|
| 16 | #include <trace/events/spi-mem.h>
|
| 17 |
|
| 18 | #include "internals.h"
|
| 19 |
|
| 20 | #define SPI_MEM_MAX_BUSWIDTH 8
|
| 21 |
|
| 22 | |
| 23 | * spi_controller_dma_map_mem_op_data() - DMA-map the buffer attached to a
|
| 24 | * memory operation
|
| 25 | * @ctlr: the SPI controller requesting this dma_map()
|
| 26 | * @op: the memory operation containing the buffer to map
|
| 27 | * @sgt: a pointer to a non-initialized sg_table that will be filled by this
|
| 28 | * function
|
| 29 | *
|
| 30 | * Some controllers might want to do DMA on the data buffer embedded in @op.
|
| 31 | * This helper prepares everything for you and provides a ready-to-use
|
| 32 | * sg_table. This function is not intended to be called from spi drivers.
|
| 33 | * Only SPI controller drivers should use it.
|
| 34 | * Note that the caller must ensure the memory region pointed by
|
| 35 | * op->data.buf.{in,out} is DMA-able before calling this function.
|
| 36 | *
|
| 37 | * Return: 0 in case of success, a negative error code otherwise.
|
| 38 |
|
| 39 | int spi_controller_dma_map_mem_op_data(struct spi_controller *ctlr,
|
| 40 | const struct spi_mem_op *op,
|
| 41 | struct sg_table *sgt)
|
| 42 | {
|
| 43 | struct device *dmadev;
|
| 44 |
|
| 45 | if (!op->data.nbytes)
|
| 46 | return -EINVAL;
|
| 47 |
|
| 48 | if (op->data.dir == SPI_MEM_DATA_OUT && ctlr->dma_tx)
|
| 49 | dmadev = ctlr->dma_tx->device->dev;
|
| 50 | else if (op->data.dir == SPI_MEM_DATA_IN && ctlr->dma_rx)
|
| 51 | dmadev = ctlr->dma_rx->device->dev;
|
| 52 | else
|
| 53 | dmadev = ctlr->dev.parent;
|
| 54 |
|
| 55 | if (!dmadev)
|
| 56 | return -EINVAL;
|
| 57 |
|
| 58 | return spi_map_buf(ctlr, dmadev, sgt, op->data.buf.in, op->data.nbytes,
|
| 59 | op->data.dir == SPI_MEM_DATA_IN ?
|
| 60 | DMA_FROM_DEVICE : DMA_TO_DEVICE);
|
| 61 | }
|
| 62 | EXPORT_SYMBOL_GPL(spi_controller_dma_map_mem_op_data);
|
| 63 |
|
| 64 | |
| 65 | * spi_controller_dma_unmap_mem_op_data() - DMA-unmap the buffer attached to a
|
| 66 | * memory operation
|
| 67 | * @ctlr: the SPI controller requesting this dma_unmap()
|
| 68 | * @op: the memory operation containing the buffer to unmap
|
| 69 | * @sgt: a pointer to an sg_table previously initialized by
|
| 70 | * spi_controller_dma_map_mem_op_data()
|
| 71 | *
|
| 72 | * Some controllers might want to do DMA on the data buffer embedded in @op.
|
| 73 | * This helper prepares things so that the CPU can access the
|
| 74 | * op->data.buf.{in,out} buffer again.
|
| 75 | *
|
| 76 | * This function is not intended to be called from SPI drivers. Only SPI
|
| 77 | * controller drivers should use it.
|
| 78 | *
|
| 79 | * This function should be called after the DMA operation has finished and is
|
| 80 | * only valid if the previous spi_controller_dma_map_mem_op_data() call
|
| 81 | * returned 0.
|
| 82 | *
|
| 83 | * Return: 0 in case of success, a negative error code otherwise.
|
| 84 |
|
| 85 | void spi_controller_dma_unmap_mem_op_data(struct spi_controller *ctlr,
|
| 86 | const struct spi_mem_op *op,
|
| 87 | struct sg_table *sgt)
|
| 88 | {
|
| 89 | struct device *dmadev;
|
| 90 |
|
| 91 | if (!op->data.nbytes)
|
| 92 | return;
|
| 93 |
|
| 94 | if (op->data.dir == SPI_MEM_DATA_OUT && ctlr->dma_tx)
|
| 95 | dmadev = ctlr->dma_tx->device->dev;
|
| 96 | else if (op->data.dir == SPI_MEM_DATA_IN && ctlr->dma_rx)
|
| 97 | dmadev = ctlr->dma_rx->device->dev;
|
| 98 | else
|
| 99 | dmadev = ctlr->dev.parent;
|
| 100 |
|
| 101 | spi_unmap_buf(ctlr, dmadev, sgt,
|
| 102 | op->data.dir == SPI_MEM_DATA_IN ?
|
| 103 | DMA_FROM_DEVICE : DMA_TO_DEVICE);
|
| 104 | }
|
| 105 | EXPORT_SYMBOL_GPL(spi_controller_dma_unmap_mem_op_data);
|
| 106 |
|
| 107 | static int spi_check_buswidth_req(struct spi_mem *mem, u8 buswidth, bool tx)
|
| 108 | {
|
| 109 | u32 mode = mem->spi->mode;
|
| 110 |
|
| 111 | switch (buswidth) {
|
| 112 | case 1:
|
| 113 | return 0;
|
| 114 |
|
| 115 | case 2:
|
| 116 | if ((tx &&
|
| 117 | (mode & (SPI_TX_DUAL | SPI_TX_QUAD | SPI_TX_OCTAL))) ||
|
| 118 | (!tx &&
|
| 119 | (mode & (SPI_RX_DUAL | SPI_RX_QUAD | SPI_RX_OCTAL))))
|
| 120 | return 0;
|
| 121 |
|
| 122 | break;
|
| 123 |
|
| 124 | case 4:
|
| 125 | if ((tx && (mode & (SPI_TX_QUAD | SPI_TX_OCTAL))) ||
|
| 126 | (!tx && (mode & (SPI_RX_QUAD | SPI_RX_OCTAL))))
|
| 127 | return 0;
|
| 128 |
|
| 129 | break;
|
| 130 |
|
| 131 | case 8:
|
| 132 | if ((tx && (mode & SPI_TX_OCTAL)) ||
|
| 133 | (!tx && (mode & SPI_RX_OCTAL)))
|
| 134 | return 0;
|
| 135 |
|
| 136 | break;
|
| 137 |
|
| 138 | default:
|
| 139 | break;
|
| 140 | }
|
| 141 |
|
| 142 | return -ENOTSUPP;
|
| 143 | }
|
| 144 |
|
| 145 | static bool spi_mem_check_buswidth(struct spi_mem *mem,
|
| 146 | const struct spi_mem_op *op)
|
| 147 | {
|
| 148 | if (spi_check_buswidth_req(mem, op->cmd.buswidth, true))
|
| 149 | return false;
|
| 150 |
|
| 151 | if (op->addr.nbytes &&
|
| 152 | spi_check_buswidth_req(mem, op->addr.buswidth, true))
|
| 153 | return false;
|
| 154 |
|
| 155 | if (op->dummy.nbytes &&
|
| 156 | spi_check_buswidth_req(mem, op->dummy.buswidth, true))
|
| 157 | return false;
|
| 158 |
|
| 159 | if (op->data.dir != SPI_MEM_NO_DATA &&
|
| 160 | spi_check_buswidth_req(mem, op->data.buswidth,
|
| 161 | op->data.dir == SPI_MEM_DATA_OUT))
|
| 162 | return false;
|
| 163 |
|
| 164 | return true;
|
| 165 | }
|
| 166 |
|
| 167 | bool spi_mem_default_supports_op(struct spi_mem *mem,
|
| 168 | const struct spi_mem_op *op)
|
| 169 | {
|
| 170 | struct spi_controller *ctlr = mem->spi->controller;
|
| 171 | bool op_is_dtr =
|
| 172 | op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr;
|
| 173 |
|
| 174 | if (op_is_dtr) {
|
| 175 | if (!spi_mem_controller_is_capable(ctlr, dtr))
|
| 176 | return false;
|
| 177 |
|
| 178 | if (op->data.swap16 && !spi_mem_controller_is_capable(ctlr, swap16))
|
| 179 | return false;
|
| 180 |
|
| 181 |
|
| 182 | if (op->cmd.dtr && op->cmd.buswidth == 8) {
|
| 183 | if (op->cmd.nbytes != 2)
|
| 184 | return false;
|
| 185 |
|
| 186 | if ((op->addr.nbytes % 2) ||
|
| 187 | (op->dummy.nbytes % 2) ||
|
| 188 | (op->data.nbytes % 2)) {
|
| 189 | dev_err(&ctlr->dev,
|
| 190 | "Even byte numbers not allowed in octal DTR operations\n");
|
| 191 | return false;
|
| 192 | }
|
| 193 | }
|
| 194 | } else {
|
| 195 | if (op->cmd.nbytes != 1)
|
| 196 | return false;
|
| 197 | }
|
| 198 |
|
| 199 | if (op->data.ecc) {
|
| 200 | if (!spi_mem_controller_is_capable(ctlr, ecc))
|
| 201 | return false;
|
| 202 | }
|
| 203 |
|
| 204 | if (op->max_freq && mem->spi->controller->min_speed_hz &&
|
| 205 | op->max_freq < mem->spi->controller->min_speed_hz)
|
| 206 | return false;
|
| 207 |
|
| 208 | if (op->max_freq &&
|
| 209 | op->max_freq < mem->spi->max_speed_hz) {
|
| 210 | if (!spi_mem_controller_is_capable(ctlr, per_op_freq))
|
| 211 | return false;
|
| 212 | }
|
| 213 |
|
| 214 | return spi_mem_check_buswidth(mem, op);
|
| 215 | }
|
| 216 | EXPORT_SYMBOL_GPL(spi_mem_default_supports_op);
|
| 217 |
|
| 218 | static bool spi_mem_buswidth_is_valid(u8 buswidth)
|
| 219 | {
|
| 220 | if (hweight8(buswidth) > 1 || buswidth > SPI_MEM_MAX_BUSWIDTH)
|
| 221 | return false;
|
| 222 |
|
| 223 | return true;
|
| 224 | }
|
| 225 |
|
| 226 | static int spi_mem_check_op(const struct spi_mem_op *op)
|
| 227 | {
|
| 228 | if (!op->cmd.buswidth || !op->cmd.nbytes)
|
| 229 | return -EINVAL;
|
| 230 |
|
| 231 | if ((op->addr.nbytes && !op->addr.buswidth) ||
|
| 232 | (op->dummy.nbytes && !op->dummy.buswidth) ||
|
| 233 | (op->data.nbytes && !op->data.buswidth))
|
| 234 | return -EINVAL;
|
| 235 |
|
| 236 | if (!spi_mem_buswidth_is_valid(op->cmd.buswidth) ||
|
| 237 | !spi_mem_buswidth_is_valid(op->addr.buswidth) ||
|
| 238 | !spi_mem_buswidth_is_valid(op->dummy.buswidth) ||
|
| 239 | !spi_mem_buswidth_is_valid(op->data.buswidth))
|
| 240 | return -EINVAL;
|
| 241 |
|
| 242 |
|
| 243 | if (WARN_ON_ONCE(op->data.dir == SPI_MEM_DATA_IN &&
|
| 244 | object_is_on_stack(op->data.buf.in)))
|
| 245 | return -EINVAL;
|
| 246 |
|
| 247 | if (WARN_ON_ONCE(op->data.dir == SPI_MEM_DATA_OUT &&
|
| 248 | object_is_on_stack(op->data.buf.out)))
|
| 249 | return -EINVAL;
|
| 250 |
|
| 251 | return 0;
|
| 252 | }
|
| 253 |
|
| 254 | static bool spi_mem_internal_supports_op(struct spi_mem *mem,
|
| 255 | const struct spi_mem_op *op)
|
| 256 | {
|
| 257 | struct spi_controller *ctlr = mem->spi->controller;
|
| 258 |
|
| 259 | if (ctlr->mem_ops && ctlr->mem_ops->supports_op)
|
| 260 | return ctlr->mem_ops->supports_op(mem, op);
|
| 261 |
|
| 262 | return spi_mem_default_supports_op(mem, op);
|
| 263 | }
|
| 264 |
|
| 265 | |
| 266 | * spi_mem_supports_op() - Check if a memory device and the controller it is
|
| 267 | * connected to support a specific memory operation
|
| 268 | * @mem: the SPI memory
|
| 269 | * @op: the memory operation to check
|
| 270 | *
|
| 271 | * Some controllers are only supporting Single or Dual IOs, others might only
|
| 272 | * support specific opcodes, or it can even be that the controller and device
|
| 273 | * both support Quad IOs but the hardware prevents you from using it because
|
| 274 | * only 2 IO lines are connected.
|
| 275 | *
|
| 276 | * This function checks whether a specific operation is supported.
|
| 277 | *
|
| 278 | * Return: true if @op is supported, false otherwise.
|
| 279 |
|
| 280 | bool spi_mem_supports_op(struct spi_mem *mem, const struct spi_mem_op *op)
|
| 281 | {
|
| 282 | struct spi_mem_op eval_op = *op;
|
| 283 |
|
| 284 | |
| 285 | * Work on a local copy; this is a pure capability check and must
|
| 286 | * not modify the caller's op. Stored templates with max_freq == 0
|
| 287 | * must remain unset so their frequency is always re-capped to the
|
| 288 | * current device maximum at execution time.
|
| 289 |
|
| 290 | spi_mem_adjust_op_freq(mem, &eval_op);
|
| 291 |
|
| 292 | if (spi_mem_check_op(&eval_op))
|
| 293 | return false;
|
| 294 |
|
| 295 | return spi_mem_internal_supports_op(mem, &eval_op);
|
| 296 | }
|
| 297 | EXPORT_SYMBOL_GPL(spi_mem_supports_op);
|
| 298 |
|
| 299 | static int spi_mem_access_start(struct spi_mem *mem)
|
| 300 | {
|
| 301 | struct spi_controller *ctlr = mem->spi->controller;
|
| 302 |
|
| 303 | |
| 304 | * Flush the message queue before executing our SPI memory
|
| 305 | * operation to prevent preemption of regular SPI transfers.
|
| 306 |
|
| 307 | spi_flush_queue(ctlr);
|
| 308 |
|
| 309 | if (ctlr->auto_runtime_pm) {
|
| 310 | int ret;
|
| 311 |
|
| 312 | ret = pm_runtime_resume_and_get(ctlr->dev.parent);
|
| 313 | if (ret < 0) {
|
| 314 | dev_err(&ctlr->dev, "Failed to power device: %d\n",
|
| 315 | ret);
|
| 316 | return ret;
|
| 317 | }
|
| 318 | }
|
| 319 |
|
| 320 | mutex_lock(&ctlr->bus_lock_mutex);
|
| 321 | mutex_lock(&ctlr->io_mutex);
|
| 322 |
|
| 323 | return 0;
|
| 324 | }
|
| 325 |
|
| 326 | static void spi_mem_access_end(struct spi_mem *mem)
|
| 327 | {
|
| 328 | struct spi_controller *ctlr = mem->spi->controller;
|
| 329 |
|
| 330 | mutex_unlock(&ctlr->io_mutex);
|
| 331 | mutex_unlock(&ctlr->bus_lock_mutex);
|
| 332 |
|
| 333 | if (ctlr->auto_runtime_pm)
|
| 334 | pm_runtime_put(ctlr->dev.parent);
|
| 335 | }
|
| 336 |
|
| 337 | static void spi_mem_add_op_stats(struct spi_statistics __percpu *pcpu_stats,
|
| 338 | const struct spi_mem_op *op, int exec_op_ret)
|
| 339 | {
|
| 340 | struct spi_statistics *stats;
|
| 341 | u64 len, l2len;
|
| 342 |
|
| 343 | get_cpu();
|
| 344 | stats = this_cpu_ptr(pcpu_stats);
|
| 345 | u64_stats_update_begin(&stats->syncp);
|
| 346 |
|
| 347 | |
| 348 | * We do not have the concept of messages or transfers. Let's consider
|
| 349 | * that one operation is equivalent to one message and one transfer.
|
| 350 |
|
| 351 | u64_stats_inc(&stats->messages);
|
| 352 | u64_stats_inc(&stats->transfers);
|
| 353 |
|
| 354 |
|
| 355 | len = op->cmd.nbytes + op->addr.nbytes;
|
| 356 | len += op->dummy.nbytes + op->data.nbytes;
|
| 357 | u64_stats_add(&stats->bytes, len);
|
| 358 | l2len = min(fls(len), SPI_STATISTICS_HISTO_SIZE) - 1;
|
| 359 | u64_stats_inc(&stats->transfer_bytes_histo[l2len]);
|
| 360 |
|
| 361 |
|
| 362 | if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT)
|
| 363 | u64_stats_add(&stats->bytes_tx, op->data.nbytes);
|
| 364 | if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN)
|
| 365 | u64_stats_add(&stats->bytes_rx, op->data.nbytes);
|
| 366 |
|
| 367 | |
| 368 | * A timeout is not an error, following the same behavior as
|
| 369 | * spi_transfer_one_message().
|
| 370 |
|
| 371 | if (exec_op_ret == -ETIMEDOUT)
|
| 372 | u64_stats_inc(&stats->timedout);
|
| 373 | else if (exec_op_ret)
|
| 374 | u64_stats_inc(&stats->errors);
|
| 375 |
|
| 376 | u64_stats_update_end(&stats->syncp);
|
| 377 | put_cpu();
|
| 378 | }
|
| 379 |
|
| 380 | |
| 381 | * spi_mem_exec_op() - Execute a memory operation
|
| 382 | * @mem: the SPI memory
|
| 383 | * @op: the memory operation to execute
|
| 384 | *
|
| 385 | * Executes a memory operation.
|
| 386 | *
|
| 387 | * This function first checks that @op is supported and then tries to execute
|
| 388 | * it.
|
| 389 | *
|
| 390 | * Return: 0 in case of success, a negative error code otherwise.
|
| 391 |
|
| 392 | int spi_mem_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
|
| 393 | {
|
| 394 | unsigned int tmpbufsize, xferpos = 0, totalxferlen = 0;
|
| 395 | struct spi_controller *ctlr = mem->spi->controller;
|
| 396 | struct spi_transfer xfers[4] = { };
|
| 397 | struct spi_message msg;
|
| 398 | u8 *tmpbuf;
|
| 399 | int ret;
|
| 400 |
|
| 401 |
|
| 402 | spi_mem_adjust_op_freq(mem, (struct spi_mem_op *)op);
|
| 403 |
|
| 404 | dev_vdbg(&mem->spi->dev, "[cmd: 0x%02x][%dB addr: %#8llx][%2dB dummy][%4dB data %s] %d%c-%d%c-%d%c-%d%c @ %uHz\n",
|
| 405 | op->cmd.opcode,
|
| 406 | op->addr.nbytes, (op->addr.nbytes ? op->addr.val : 0),
|
| 407 | op->dummy.nbytes,
|
| 408 | op->data.nbytes, (op->data.nbytes ? (op->data.dir == SPI_MEM_DATA_IN ? " read" : "write") : " "),
|
| 409 | op->cmd.buswidth, op->cmd.dtr ? 'D' : 'S',
|
| 410 | op->addr.buswidth, op->addr.dtr ? 'D' : 'S',
|
| 411 | op->dummy.buswidth, op->dummy.dtr ? 'D' : 'S',
|
| 412 | op->data.buswidth, op->data.dtr ? 'D' : 'S',
|
| 413 | op->max_freq ? op->max_freq : mem->spi->max_speed_hz);
|
| 414 |
|
| 415 | ret = spi_mem_check_op(op);
|
| 416 | if (ret)
|
| 417 | return ret;
|
| 418 |
|
| 419 | if (!spi_mem_internal_supports_op(mem, op))
|
| 420 | return -EOPNOTSUPP;
|
| 421 |
|
| 422 | if (ctlr->mem_ops && ctlr->mem_ops->exec_op && !spi_get_csgpiod(mem->spi, 0)) {
|
| 423 | ret = spi_mem_access_start(mem);
|
| 424 | if (ret)
|
| 425 | return ret;
|
| 426 |
|
| 427 | trace_spi_mem_start_op(mem, op);
|
| 428 | ret = ctlr->mem_ops->exec_op(mem, op);
|
| 429 | trace_spi_mem_stop_op(mem, op);
|
| 430 |
|
| 431 | spi_mem_access_end(mem);
|
| 432 |
|
| 433 | |
| 434 | * Some controllers only optimize specific paths (typically the
|
| 435 | * read path) and expect the core to use the regular SPI
|
| 436 | * interface in other cases.
|
| 437 |
|
| 438 | if (!ret || (ret != -ENOTSUPP && ret != -EOPNOTSUPP)) {
|
| 439 | spi_mem_add_op_stats(ctlr->pcpu_statistics, op, ret);
|
| 440 | spi_mem_add_op_stats(mem->spi->pcpu_statistics, op, ret);
|
| 441 |
|
| 442 | return ret;
|
| 443 | }
|
| 444 | }
|
| 445 |
|
| 446 | tmpbufsize = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes;
|
| 447 |
|
| 448 | |
| 449 | * Allocate a buffer to transmit the CMD, ADDR cycles with kmalloc() so
|
| 450 | * we're guaranteed that this buffer is DMA-able, as required by the
|
| 451 | * SPI layer.
|
| 452 |
|
| 453 | tmpbuf = kzalloc(tmpbufsize, GFP_KERNEL | GFP_DMA);
|
| 454 | if (!tmpbuf)
|
| 455 | return -ENOMEM;
|
| 456 |
|
| 457 | spi_message_init(&msg);
|
| 458 |
|
| 459 | tmpbuf[0] = op->cmd.opcode;
|
| 460 | xfers[xferpos].tx_buf = tmpbuf;
|
| 461 | xfers[xferpos].len = op->cmd.nbytes;
|
| 462 | xfers[xferpos].tx_nbits = op->cmd.buswidth;
|
| 463 | xfers[xferpos].speed_hz = op->max_freq;
|
| 464 | spi_message_add_tail(&xfers[xferpos], &msg);
|
| 465 | xferpos++;
|
| 466 | totalxferlen++;
|
| 467 |
|
| 468 | if (op->addr.nbytes) {
|
| 469 | int i;
|
| 470 |
|
| 471 | for (i = 0; i < op->addr.nbytes; i++)
|
| 472 | tmpbuf[i + 1] = op->addr.val >>
|
| 473 | (8 * (op->addr.nbytes - i - 1));
|
| 474 |
|
| 475 | xfers[xferpos].tx_buf = tmpbuf + 1;
|
| 476 | xfers[xferpos].len = op->addr.nbytes;
|
| 477 | xfers[xferpos].tx_nbits = op->addr.buswidth;
|
| 478 | xfers[xferpos].speed_hz = op->max_freq;
|
| 479 | spi_message_add_tail(&xfers[xferpos], &msg);
|
| 480 | xferpos++;
|
| 481 | totalxferlen += op->addr.nbytes;
|
| 482 | }
|
| 483 |
|
| 484 | if (op->dummy.nbytes) {
|
| 485 | memset(tmpbuf + op->addr.nbytes + 1, 0xff, op->dummy.nbytes);
|
| 486 | xfers[xferpos].tx_buf = tmpbuf + op->addr.nbytes + 1;
|
| 487 | xfers[xferpos].len = op->dummy.nbytes;
|
| 488 | xfers[xferpos].tx_nbits = op->dummy.buswidth;
|
| 489 | xfers[xferpos].dummy_data = 1;
|
| 490 | xfers[xferpos].speed_hz = op->max_freq;
|
| 491 | spi_message_add_tail(&xfers[xferpos], &msg);
|
| 492 | xferpos++;
|
| 493 | totalxferlen += op->dummy.nbytes;
|
| 494 | }
|
| 495 |
|
| 496 | if (op->data.nbytes) {
|
| 497 | if (op->data.dir == SPI_MEM_DATA_IN) {
|
| 498 | xfers[xferpos].rx_buf = op->data.buf.in;
|
| 499 | xfers[xferpos].rx_nbits = op->data.buswidth;
|
| 500 | } else {
|
| 501 | xfers[xferpos].tx_buf = op->data.buf.out;
|
| 502 | xfers[xferpos].tx_nbits = op->data.buswidth;
|
| 503 | }
|
| 504 |
|
| 505 | xfers[xferpos].len = op->data.nbytes;
|
| 506 | xfers[xferpos].speed_hz = op->max_freq;
|
| 507 | spi_message_add_tail(&xfers[xferpos], &msg);
|
| 508 | xferpos++;
|
| 509 | totalxferlen += op->data.nbytes;
|
| 510 | }
|
| 511 |
|
| 512 | ret = spi_sync(mem->spi, &msg);
|
| 513 |
|
| 514 | kfree(tmpbuf);
|
| 515 |
|
| 516 | if (ret)
|
| 517 | return ret;
|
| 518 |
|
| 519 | if (msg.actual_length != totalxferlen)
|
| 520 | return -EIO;
|
| 521 |
|
| 522 | return 0;
|
| 523 | }
|
| 524 | EXPORT_SYMBOL_GPL(spi_mem_exec_op);
|
| 525 |
|
| 526 | |
| 527 | * spi_mem_get_name() - Return the SPI mem device name to be used by the
|
| 528 | * upper layer if necessary
|
| 529 | * @mem: the SPI memory
|
| 530 | *
|
| 531 | * This function allows SPI mem users to retrieve the SPI mem device name.
|
| 532 | * It is useful if the upper layer needs to expose a custom name for
|
| 533 | * compatibility reasons.
|
| 534 | *
|
| 535 | * Return: a string containing the name of the memory device to be used
|
| 536 | * by the SPI mem user
|
| 537 |
|
| 538 | const char *spi_mem_get_name(struct spi_mem *mem)
|
| 539 | {
|
| 540 | return mem->name;
|
| 541 | }
|
| 542 | EXPORT_SYMBOL_GPL(spi_mem_get_name);
|
| 543 |
|
| 544 | |
| 545 | * spi_mem_set_dqs() - Mark DQS as being available
|
| 546 | * @mem: the SPI memory
|
| 547 | *
|
| 548 | * When reading at high frequencies (> 100MHz), especially when DTR is enabled,
|
| 549 | * transfer speed is limited due to clock skews. In particular, the controller
|
| 550 | * does not know the board propagation delay nor the memory chip internal delay
|
| 551 | * (clock in to data out) and thus cannot optimize its sampling points.
|
| 552 | * Mitigating this limitation is possible with the addition of a data strobe
|
| 553 | * signal, commonly named DQS.
|
| 554 | *
|
| 555 | * Set the DQS boolean if the feature is available and configured at the chip
|
| 556 | * level. Controllers may query this value.
|
| 557 |
|
| 558 | void spi_mem_set_dqs(struct spi_mem *mem)
|
| 559 | {
|
| 560 | mem->dqs = true;
|
| 561 | }
|
| 562 | EXPORT_SYMBOL_GPL(spi_mem_set_dqs);
|
| 563 |
|
| 564 | |
| 565 | * spi_mem_has_dqs() - Query whether the DQS is available or not
|
| 566 | * @mem: the SPI memory
|
| 567 | *
|
| 568 | * Return: a boolean indicating whether the DQS signal is available or not.
|
| 569 |
|
| 570 | bool spi_mem_has_dqs(struct spi_mem *mem)
|
| 571 | {
|
| 572 | return mem->dqs;
|
| 573 | }
|
| 574 | EXPORT_SYMBOL_GPL(spi_mem_has_dqs);
|
| 575 |
|
| 576 | |
| 577 | * spi_mem_adjust_op_size() - Adjust the data size of a SPI mem operation to
|
| 578 | * match controller limitations
|
| 579 | * @mem: the SPI memory
|
| 580 | * @op: the operation to adjust
|
| 581 | *
|
| 582 | * Some controllers have FIFO limitations and must split a data transfer
|
| 583 | * operation into multiple ones, others require a specific alignment for
|
| 584 | * optimized accesses. This function allows SPI mem drivers to split a single
|
| 585 | * operation into multiple sub-operations when required.
|
| 586 | *
|
| 587 | * Return: a negative error code if the controller can't properly adjust @op,
|
| 588 | * 0 otherwise. Note that @op->data.nbytes will be updated if @op
|
| 589 | * can't be handled in a single step.
|
| 590 |
|
| 591 | int spi_mem_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op)
|
| 592 | {
|
| 593 | struct spi_controller *ctlr = mem->spi->controller;
|
| 594 | size_t len;
|
| 595 |
|
| 596 | if (ctlr->mem_ops && ctlr->mem_ops->adjust_op_size)
|
| 597 | return ctlr->mem_ops->adjust_op_size(mem, op);
|
| 598 |
|
| 599 | if (!ctlr->mem_ops || !ctlr->mem_ops->exec_op) {
|
| 600 | len = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes;
|
| 601 |
|
| 602 | if (len > spi_max_transfer_size(mem->spi))
|
| 603 | return -EINVAL;
|
| 604 |
|
| 605 | op->data.nbytes = min3((size_t)op->data.nbytes,
|
| 606 | spi_max_transfer_size(mem->spi),
|
| 607 | spi_max_message_size(mem->spi) -
|
| 608 | len);
|
| 609 | if (!op->data.nbytes)
|
| 610 | return -EINVAL;
|
| 611 | }
|
| 612 |
|
| 613 | return 0;
|
| 614 | }
|
| 615 | EXPORT_SYMBOL_GPL(spi_mem_adjust_op_size);
|
| 616 |
|
| 617 | |
| 618 | * spi_mem_adjust_op_freq() - Adjust the frequency of a SPI mem operation to
|
| 619 | * match controller, PCB and chip limitations
|
| 620 | * @mem: the SPI memory
|
| 621 | * @op: the operation to adjust
|
| 622 | *
|
| 623 | * Some chips have per-op frequency limitations and must adapt the maximum
|
| 624 | * speed. This function allows SPI mem drivers to set @op->max_freq to the
|
| 625 | * maximum supported value.
|
| 626 |
|
| 627 | void spi_mem_adjust_op_freq(struct spi_mem *mem, struct spi_mem_op *op)
|
| 628 | {
|
| 629 | if (!op->max_freq || op->max_freq > mem->spi->max_speed_hz)
|
| 630 | op->max_freq = mem->spi->max_speed_hz;
|
| 631 | }
|
| 632 | EXPORT_SYMBOL_GPL(spi_mem_adjust_op_freq);
|
| 633 |
|
| 634 | |
| 635 | * spi_mem_calc_op_duration() - Derives the theoretical length (in ns) of an
|
| 636 | * operation. This helps finding the best variant
|
| 637 | * among a list of possible choices.
|
| 638 | * @mem: the SPI memory
|
| 639 | * @op: the operation to benchmark
|
| 640 | *
|
| 641 | * Some chips have per-op frequency limitations, PCBs usually have their own
|
| 642 | * limitations as well, and controllers can support dual, quad or even octal
|
| 643 | * modes, sometimes in DTR. All these combinations make it impossible to
|
| 644 | * statically list the best combination for all situations. If we want something
|
| 645 | * accurate, all these combinations should be rated (eg. with a time estimate)
|
| 646 | * and the best pick should be taken based on these calculations.
|
| 647 | *
|
| 648 | * Returns a ns estimate for the time this op would take, except if no
|
| 649 | * frequency limit has been set, in this case we return the number of
|
| 650 | * cycles nevertheless to allow callers to distinguish which operation
|
| 651 | * would be the fastest at iso-frequency.
|
| 652 |
|
| 653 | u64 spi_mem_calc_op_duration(struct spi_mem *mem, struct spi_mem_op *op)
|
| 654 | {
|
| 655 | u64 ncycles = 0;
|
| 656 | u64 ps_per_cycles, duration;
|
| 657 |
|
| 658 | spi_mem_adjust_op_freq(mem, op);
|
| 659 |
|
| 660 | if (op->max_freq) {
|
| 661 | ps_per_cycles = 1000000000000ULL;
|
| 662 | do_div(ps_per_cycles, op->max_freq);
|
| 663 | } else {
|
| 664 |
|
| 665 | ps_per_cycles = 1;
|
| 666 | }
|
| 667 |
|
| 668 | ncycles += ((op->cmd.nbytes * 8) / op->cmd.buswidth) / (op->cmd.dtr ? 2 : 1);
|
| 669 | ncycles += ((op->addr.nbytes * 8) / op->addr.buswidth) / (op->addr.dtr ? 2 : 1);
|
| 670 |
|
| 671 |
|
| 672 | if (op->dummy.nbytes)
|
| 673 | ncycles += ((op->dummy.nbytes * 8) / op->dummy.buswidth) / (op->dummy.dtr ? 2 : 1);
|
| 674 |
|
| 675 | ncycles += ((op->data.nbytes * 8) / op->data.buswidth) / (op->data.dtr ? 2 : 1);
|
| 676 |
|
| 677 |
|
| 678 | duration = ncycles * ps_per_cycles;
|
| 679 |
|
| 680 | do_div(duration, 1000);
|
| 681 |
|
| 682 | return duration;
|
| 683 | }
|
| 684 | EXPORT_SYMBOL_GPL(spi_mem_calc_op_duration);
|
| 685 |
|
| 686 | static ssize_t spi_mem_no_dirmap_read(struct spi_mem_dirmap_desc *desc,
|
| 687 | u64 offs, size_t len, void *buf)
|
| 688 | {
|
| 689 | struct spi_mem_op op = *desc->info.op_tmpl;
|
| 690 | int ret;
|
| 691 |
|
| 692 | op.addr.val = desc->info.offset + offs;
|
| 693 | op.data.buf.in = buf;
|
| 694 | op.data.nbytes = len;
|
| 695 | ret = spi_mem_adjust_op_size(desc->mem, &op);
|
| 696 | if (ret)
|
| 697 | return ret;
|
| 698 |
|
| 699 | ret = spi_mem_exec_op(desc->mem, &op);
|
| 700 | if (ret)
|
| 701 | return ret;
|
| 702 |
|
| 703 | return op.data.nbytes;
|
| 704 | }
|
| 705 |
|
| 706 | static ssize_t spi_mem_no_dirmap_write(struct spi_mem_dirmap_desc *desc,
|
| 707 | u64 offs, size_t len, const void *buf)
|
| 708 | {
|
| 709 | struct spi_mem_op op = *desc->info.op_tmpl;
|
| 710 | int ret;
|
| 711 |
|
| 712 | op.addr.val = desc->info.offset + offs;
|
| 713 | op.data.buf.out = buf;
|
| 714 | op.data.nbytes = len;
|
| 715 | ret = spi_mem_adjust_op_size(desc->mem, &op);
|
| 716 | if (ret)
|
| 717 | return ret;
|
| 718 |
|
| 719 | ret = spi_mem_exec_op(desc->mem, &op);
|
| 720 | if (ret)
|
| 721 | return ret;
|
| 722 |
|
| 723 | return op.data.nbytes;
|
| 724 | }
|
| 725 |
|
| 726 | |
| 727 | * spi_mem_dirmap_create() - Create a direct mapping descriptor
|
| 728 | * @mem: SPI mem device this direct mapping should be created for
|
| 729 | * @info: direct mapping information
|
| 730 | *
|
| 731 | * This function is creating a direct mapping descriptor which can then be used
|
| 732 | * to access the memory using spi_mem_dirmap_read() or spi_mem_dirmap_write().
|
| 733 | * If the SPI controller driver does not support direct mapping, this function
|
| 734 | * falls back to an implementation using spi_mem_exec_op(), so that the caller
|
| 735 | * doesn't have to bother implementing a fallback on his own.
|
| 736 | *
|
| 737 | * Return: a valid pointer in case of success, and ERR_PTR() otherwise.
|
| 738 |
|
| 739 | struct spi_mem_dirmap_desc *
|
| 740 | spi_mem_dirmap_create(struct spi_mem *mem,
|
| 741 | const struct spi_mem_dirmap_info *info)
|
| 742 | {
|
| 743 | struct spi_controller *ctlr = mem->spi->controller;
|
| 744 | struct spi_mem_dirmap_desc *desc;
|
| 745 | int ret = -ENOTSUPP;
|
| 746 |
|
| 747 |
|
| 748 | if (!info->primary_op_tmpl.addr.nbytes || info->primary_op_tmpl.addr.nbytes > 8)
|
| 749 | return ERR_PTR(-EINVAL);
|
| 750 |
|
| 751 |
|
| 752 | if (info->primary_op_tmpl.data.dir == SPI_MEM_NO_DATA)
|
| 753 | return ERR_PTR(-EINVAL);
|
| 754 |
|
| 755 |
|
| 756 | if (info->secondary_op_tmpl.cmd.opcode) {
|
| 757 | if (!info->secondary_op_tmpl.addr.nbytes ||
|
| 758 | info->secondary_op_tmpl.addr.nbytes > 8)
|
| 759 | return ERR_PTR(-EINVAL);
|
| 760 |
|
| 761 | if (info->secondary_op_tmpl.data.dir == SPI_MEM_NO_DATA)
|
| 762 | return ERR_PTR(-EINVAL);
|
| 763 |
|
| 764 | if (!spi_mem_supports_op(mem, &info->secondary_op_tmpl))
|
| 765 | return ERR_PTR(-EOPNOTSUPP);
|
| 766 |
|
| 767 | if (ctlr->mem_ops && ctlr->mem_ops->dirmap_create &&
|
| 768 | !spi_mem_controller_is_capable(ctlr, secondary_op_tmpl))
|
| 769 | return ERR_PTR(-EOPNOTSUPP);
|
| 770 | }
|
| 771 |
|
| 772 | desc = kzalloc_obj(*desc);
|
| 773 | if (!desc)
|
| 774 | return ERR_PTR(-ENOMEM);
|
| 775 |
|
| 776 | desc->mem = mem;
|
| 777 | desc->info = *info;
|
| 778 | desc->info.op_tmpl = &desc->info.primary_op_tmpl;
|
| 779 | if (ctlr->mem_ops && ctlr->mem_ops->dirmap_create) {
|
| 780 | ret = spi_mem_access_start(mem);
|
| 781 | if (ret) {
|
| 782 | kfree(desc);
|
| 783 | return ERR_PTR(ret);
|
| 784 | }
|
| 785 |
|
| 786 | ret = ctlr->mem_ops->dirmap_create(desc);
|
| 787 |
|
| 788 | spi_mem_access_end(mem);
|
| 789 | }
|
| 790 |
|
| 791 | if (ret) {
|
| 792 | desc->nodirmap = true;
|
| 793 | if (!spi_mem_supports_op(desc->mem, &desc->info.primary_op_tmpl))
|
| 794 | ret = -EOPNOTSUPP;
|
| 795 | else
|
| 796 | ret = 0;
|
| 797 | }
|
| 798 |
|
| 799 | if (ret) {
|
| 800 | kfree(desc);
|
| 801 | return ERR_PTR(ret);
|
| 802 | }
|
| 803 |
|
| 804 | return desc;
|
| 805 | }
|
| 806 | EXPORT_SYMBOL_GPL(spi_mem_dirmap_create);
|
| 807 |
|
| 808 | |
| 809 | * spi_mem_dirmap_destroy() - Destroy a direct mapping descriptor
|
| 810 | * @desc: the direct mapping descriptor to destroy
|
| 811 | *
|
| 812 | * This function destroys a direct mapping descriptor previously created by
|
| 813 | * spi_mem_dirmap_create().
|
| 814 |
|
| 815 | void spi_mem_dirmap_destroy(struct spi_mem_dirmap_desc *desc)
|
| 816 | {
|
| 817 | struct spi_controller *ctlr = desc->mem->spi->controller;
|
| 818 |
|
| 819 | if (!desc->nodirmap && ctlr->mem_ops && ctlr->mem_ops->dirmap_destroy)
|
| 820 | ctlr->mem_ops->dirmap_destroy(desc);
|
| 821 |
|
| 822 | kfree(desc);
|
| 823 | }
|
| 824 | EXPORT_SYMBOL_GPL(spi_mem_dirmap_destroy);
|
| 825 |
|
| 826 | static void devm_spi_mem_dirmap_release(struct device *dev, void *res)
|
| 827 | {
|
| 828 | struct spi_mem_dirmap_desc *desc = *(struct spi_mem_dirmap_desc **)res;
|
| 829 |
|
| 830 | spi_mem_dirmap_destroy(desc);
|
| 831 | }
|
| 832 |
|
| 833 | |
| 834 | * devm_spi_mem_dirmap_create() - Create a direct mapping descriptor and attach
|
| 835 | * it to a device
|
| 836 | * @dev: device the dirmap desc will be attached to
|
| 837 | * @mem: SPI mem device this direct mapping should be created for
|
| 838 | * @info: direct mapping information
|
| 839 | *
|
| 840 | * devm_ variant of the spi_mem_dirmap_create() function. See
|
| 841 | * spi_mem_dirmap_create() for more details.
|
| 842 | *
|
| 843 | * Return: a valid pointer in case of success, and ERR_PTR() otherwise.
|
| 844 |
|
| 845 | struct spi_mem_dirmap_desc *
|
| 846 | devm_spi_mem_dirmap_create(struct device *dev, struct spi_mem *mem,
|
| 847 | const struct spi_mem_dirmap_info *info)
|
| 848 | {
|
| 849 | struct spi_mem_dirmap_desc **ptr, *desc;
|
| 850 |
|
| 851 | ptr = devres_alloc(devm_spi_mem_dirmap_release, sizeof(*ptr),
|
| 852 | GFP_KERNEL);
|
| 853 | if (!ptr)
|
| 854 | return ERR_PTR(-ENOMEM);
|
| 855 |
|
| 856 | desc = spi_mem_dirmap_create(mem, info);
|
| 857 | if (IS_ERR(desc)) {
|
| 858 | devres_free(ptr);
|
| 859 | } else {
|
| 860 | *ptr = desc;
|
| 861 | devres_add(dev, ptr);
|
| 862 | }
|
| 863 |
|
| 864 | return desc;
|
| 865 | }
|
| 866 | EXPORT_SYMBOL_GPL(devm_spi_mem_dirmap_create);
|
| 867 |
|
| 868 | static int devm_spi_mem_dirmap_match(struct device *dev, void *res, void *data)
|
| 869 | {
|
| 870 | struct spi_mem_dirmap_desc **ptr = res;
|
| 871 |
|
| 872 | if (WARN_ON(!ptr || !*ptr))
|
| 873 | return 0;
|
| 874 |
|
| 875 | return *ptr == data;
|
| 876 | }
|
| 877 |
|
| 878 | |
| 879 | * devm_spi_mem_dirmap_destroy() - Destroy a direct mapping descriptor attached
|
| 880 | * to a device
|
| 881 | * @dev: device the dirmap desc is attached to
|
| 882 | * @desc: the direct mapping descriptor to destroy
|
| 883 | *
|
| 884 | * devm_ variant of the spi_mem_dirmap_destroy() function. See
|
| 885 | * spi_mem_dirmap_destroy() for more details.
|
| 886 |
|
| 887 | void devm_spi_mem_dirmap_destroy(struct device *dev,
|
| 888 | struct spi_mem_dirmap_desc *desc)
|
| 889 | {
|
| 890 | devres_release(dev, devm_spi_mem_dirmap_release,
|
| 891 | devm_spi_mem_dirmap_match, desc);
|
| 892 | }
|
| 893 | EXPORT_SYMBOL_GPL(devm_spi_mem_dirmap_destroy);
|
| 894 |
|
| 895 | |
| 896 | * spi_mem_dirmap_read() - Read data through a direct mapping
|
| 897 | * @desc: direct mapping descriptor
|
| 898 | * @offs: offset to start reading from. Note that this is not an absolute
|
| 899 | * offset, but the offset within the direct mapping which already has
|
| 900 | * its own offset
|
| 901 | * @len: length in bytes
|
| 902 | * @buf: destination buffer. This buffer must be DMA-able
|
| 903 | *
|
| 904 | * This function reads data from a memory device using a direct mapping
|
| 905 | * previously instantiated with spi_mem_dirmap_create().
|
| 906 | *
|
| 907 | * Return: the amount of data read from the memory device or a negative error
|
| 908 | * code. Note that the returned size might be smaller than @len, and the caller
|
| 909 | * is responsible for calling spi_mem_dirmap_read() again when that happens.
|
| 910 |
|
| 911 | ssize_t spi_mem_dirmap_read(struct spi_mem_dirmap_desc *desc,
|
| 912 | u64 offs, size_t len, void *buf)
|
| 913 | {
|
| 914 | struct spi_controller *ctlr = desc->mem->spi->controller;
|
| 915 | ssize_t ret;
|
| 916 |
|
| 917 | if (desc->info.op_tmpl->data.dir != SPI_MEM_DATA_IN)
|
| 918 | return -EINVAL;
|
| 919 |
|
| 920 | if (!len)
|
| 921 | return 0;
|
| 922 |
|
| 923 | if (desc->nodirmap) {
|
| 924 | ret = spi_mem_no_dirmap_read(desc, offs, len, buf);
|
| 925 | } else if (ctlr->mem_ops && ctlr->mem_ops->dirmap_read) {
|
| 926 | ret = spi_mem_access_start(desc->mem);
|
| 927 | if (ret)
|
| 928 | return ret;
|
| 929 |
|
| 930 | ret = ctlr->mem_ops->dirmap_read(desc, offs, len, buf);
|
| 931 |
|
| 932 | spi_mem_access_end(desc->mem);
|
| 933 | } else {
|
| 934 | ret = -ENOTSUPP;
|
| 935 | }
|
| 936 |
|
| 937 | return ret;
|
| 938 | }
|
| 939 | EXPORT_SYMBOL_GPL(spi_mem_dirmap_read);
|
| 940 |
|
| 941 | |
| 942 | * spi_mem_dirmap_write() - Write data through a direct mapping
|
| 943 | * @desc: direct mapping descriptor
|
| 944 | * @offs: offset to start writing from. Note that this is not an absolute
|
| 945 | * offset, but the offset within the direct mapping which already has
|
| 946 | * its own offset
|
| 947 | * @len: length in bytes
|
| 948 | * @buf: source buffer. This buffer must be DMA-able
|
| 949 | *
|
| 950 | * This function writes data to a memory device using a direct mapping
|
| 951 | * previously instantiated with spi_mem_dirmap_create().
|
| 952 | *
|
| 953 | * Return: the amount of data written to the memory device or a negative error
|
| 954 | * code. Note that the returned size might be smaller than @len, and the caller
|
| 955 | * is responsible for calling spi_mem_dirmap_write() again when that happens.
|
| 956 |
|
| 957 | ssize_t spi_mem_dirmap_write(struct spi_mem_dirmap_desc *desc,
|
| 958 | u64 offs, size_t len, const void *buf)
|
| 959 | {
|
| 960 | struct spi_controller *ctlr = desc->mem->spi->controller;
|
| 961 | ssize_t ret;
|
| 962 |
|
| 963 | if (desc->info.op_tmpl->data.dir != SPI_MEM_DATA_OUT)
|
| 964 | return -EINVAL;
|
| 965 |
|
| 966 | if (!len)
|
| 967 | return 0;
|
| 968 |
|
| 969 | if (desc->nodirmap) {
|
| 970 | ret = spi_mem_no_dirmap_write(desc, offs, len, buf);
|
| 971 | } else if (ctlr->mem_ops && ctlr->mem_ops->dirmap_write) {
|
| 972 | ret = spi_mem_access_start(desc->mem);
|
| 973 | if (ret)
|
| 974 | return ret;
|
| 975 |
|
| 976 | ret = ctlr->mem_ops->dirmap_write(desc, offs, len, buf);
|
| 977 |
|
| 978 | spi_mem_access_end(desc->mem);
|
| 979 | } else {
|
| 980 | ret = -ENOTSUPP;
|
| 981 | }
|
| 982 |
|
| 983 | return ret;
|
| 984 | }
|
| 985 | EXPORT_SYMBOL_GPL(spi_mem_dirmap_write);
|
| 986 |
|
| 987 | static inline struct spi_mem_driver *to_spi_mem_drv(struct device_driver *drv)
|
| 988 | {
|
| 989 | return container_of(drv, struct spi_mem_driver, spidrv.driver);
|
| 990 | }
|
| 991 |
|
| 992 | static int spi_mem_read_status(struct spi_mem *mem,
|
| 993 | const struct spi_mem_op *op,
|
| 994 | u16 *status)
|
| 995 | {
|
| 996 | const u8 *bytes = (u8 *)op->data.buf.in;
|
| 997 | int ret;
|
| 998 |
|
| 999 | ret = spi_mem_exec_op(mem, op);
|
| 1000 | if (ret)
|
| 1001 | return ret;
|
| 1002 |
|
| 1003 | if (op->data.nbytes > 1)
|
| 1004 | *status = ((u16)bytes[0] << 8) | bytes[1];
|
| 1005 | else
|
| 1006 | *status = bytes[0];
|
| 1007 |
|
| 1008 | return 0;
|
| 1009 | }
|
| 1010 |
|
| 1011 | |
| 1012 | * spi_mem_poll_status() - Poll memory device status
|
| 1013 | * @mem: SPI memory device
|
| 1014 | * @op: the memory operation to execute
|
| 1015 | * @mask: status bitmask to ckeck
|
| 1016 | * @match: (status & mask) expected value
|
| 1017 | * @initial_delay_us: delay in us before starting to poll
|
| 1018 | * @polling_delay_us: time to sleep between reads in us
|
| 1019 | * @timeout_ms: timeout in milliseconds
|
| 1020 | *
|
| 1021 | * This function polls a status register and returns when
|
| 1022 | * (status & mask) == match or when the timeout has expired.
|
| 1023 | *
|
| 1024 | * Return: 0 in case of success, -ETIMEDOUT in case of error,
|
| 1025 | * -EOPNOTSUPP if not supported.
|
| 1026 |
|
| 1027 | int spi_mem_poll_status(struct spi_mem *mem,
|
| 1028 | const struct spi_mem_op *op,
|
| 1029 | u16 mask, u16 match,
|
| 1030 | unsigned long initial_delay_us,
|
| 1031 | unsigned long polling_delay_us,
|
| 1032 | u16 timeout_ms)
|
| 1033 | {
|
| 1034 | struct spi_controller *ctlr = mem->spi->controller;
|
| 1035 | int ret = -EOPNOTSUPP;
|
| 1036 | int read_status_ret;
|
| 1037 | u16 status;
|
| 1038 |
|
| 1039 | if (op->data.nbytes < 1 || op->data.nbytes > 2 ||
|
| 1040 | op->data.dir != SPI_MEM_DATA_IN)
|
| 1041 | return -EINVAL;
|
| 1042 |
|
| 1043 | if (ctlr->mem_ops && ctlr->mem_ops->poll_status && !spi_get_csgpiod(mem->spi, 0)) {
|
| 1044 | ret = spi_mem_access_start(mem);
|
| 1045 | if (ret)
|
| 1046 | return ret;
|
| 1047 |
|
| 1048 | ret = ctlr->mem_ops->poll_status(mem, op, mask, match,
|
| 1049 | initial_delay_us, polling_delay_us,
|
| 1050 | timeout_ms);
|
| 1051 |
|
| 1052 | spi_mem_access_end(mem);
|
| 1053 | }
|
| 1054 |
|
| 1055 | if (ret == -EOPNOTSUPP) {
|
| 1056 | if (!spi_mem_supports_op(mem, op))
|
| 1057 | return ret;
|
| 1058 |
|
| 1059 | if (initial_delay_us < 10)
|
| 1060 | udelay(initial_delay_us);
|
| 1061 | else
|
| 1062 | usleep_range((initial_delay_us >> 2) + 1,
|
| 1063 | initial_delay_us);
|
| 1064 |
|
| 1065 | ret = read_poll_timeout(spi_mem_read_status, read_status_ret,
|
| 1066 | (read_status_ret || ((status) & mask) == match),
|
| 1067 | polling_delay_us, timeout_ms * 1000, false, mem,
|
| 1068 | op, &status);
|
| 1069 | if (read_status_ret)
|
| 1070 | return read_status_ret;
|
| 1071 | }
|
| 1072 |
|
| 1073 | return ret;
|
| 1074 | }
|
| 1075 | EXPORT_SYMBOL_GPL(spi_mem_poll_status);
|
| 1076 |
|
| 1077 | static int spi_mem_probe(struct spi_device *spi)
|
| 1078 | {
|
| 1079 | struct spi_mem_driver *memdrv = to_spi_mem_drv(spi->dev.driver);
|
| 1080 | struct spi_controller *ctlr = spi->controller;
|
| 1081 | struct spi_mem *mem;
|
| 1082 |
|
| 1083 | mem = devm_kzalloc(&spi->dev, sizeof(*mem), GFP_KERNEL);
|
| 1084 | if (!mem)
|
| 1085 | return -ENOMEM;
|
| 1086 |
|
| 1087 | mem->spi = spi;
|
| 1088 |
|
| 1089 | if (ctlr->mem_ops && ctlr->mem_ops->get_name)
|
| 1090 | mem->name = ctlr->mem_ops->get_name(mem);
|
| 1091 | else
|
| 1092 | mem->name = dev_name(&spi->dev);
|
| 1093 |
|
| 1094 | if (IS_ERR_OR_NULL(mem->name))
|
| 1095 | return PTR_ERR_OR_ZERO(mem->name);
|
| 1096 |
|
| 1097 | spi_set_drvdata(spi, mem);
|
| 1098 |
|
| 1099 | return memdrv->probe(mem);
|
| 1100 | }
|
| 1101 |
|
| 1102 | static void spi_mem_remove(struct spi_device *spi)
|
| 1103 | {
|
| 1104 | struct spi_mem_driver *memdrv = to_spi_mem_drv(spi->dev.driver);
|
| 1105 | struct spi_mem *mem = spi_get_drvdata(spi);
|
| 1106 |
|
| 1107 | if (memdrv->remove)
|
| 1108 | memdrv->remove(mem);
|
| 1109 | }
|
| 1110 |
|
| 1111 | static void spi_mem_shutdown(struct spi_device *spi)
|
| 1112 | {
|
| 1113 | struct spi_mem_driver *memdrv = to_spi_mem_drv(spi->dev.driver);
|
| 1114 | struct spi_mem *mem = spi_get_drvdata(spi);
|
| 1115 |
|
| 1116 | if (memdrv->shutdown)
|
| 1117 | memdrv->shutdown(mem);
|
| 1118 | }
|
| 1119 |
|
| 1120 | |
| 1121 | * spi_mem_driver_register_with_owner() - Register a SPI memory driver
|
| 1122 | * @memdrv: the SPI memory driver to register
|
| 1123 | * @owner: the owner of this driver
|
| 1124 | *
|
| 1125 | * Registers a SPI memory driver.
|
| 1126 | *
|
| 1127 | * Return: 0 in case of success, a negative error core otherwise.
|
| 1128 |
|
| 1129 |
|
| 1130 | int spi_mem_driver_register_with_owner(struct spi_mem_driver *memdrv,
|
| 1131 | struct module *owner)
|
| 1132 | {
|
| 1133 | memdrv->spidrv.probe = spi_mem_probe;
|
| 1134 | memdrv->spidrv.remove = spi_mem_remove;
|
| 1135 | memdrv->spidrv.shutdown = spi_mem_shutdown;
|
| 1136 |
|
| 1137 | return __spi_register_driver(owner, &memdrv->spidrv);
|
| 1138 | }
|
| 1139 | EXPORT_SYMBOL_GPL(spi_mem_driver_register_with_owner);
|
| 1140 |
|
| 1141 | |
| 1142 | * spi_mem_driver_unregister() - Unregister a SPI memory driver
|
| 1143 | * @memdrv: the SPI memory driver to unregister
|
| 1144 | *
|
| 1145 | * Unregisters a SPI memory driver.
|
| 1146 |
|
| 1147 | void spi_mem_driver_unregister(struct spi_mem_driver *memdrv)
|
| 1148 | {
|
| 1149 | spi_unregister_driver(&memdrv->spidrv);
|
| 1150 | }
|
| 1151 | EXPORT_SYMBOL_GPL(spi_mem_driver_unregister);
|