projects/linux·blob master · refs

1726 lines · 47.9 KiB

1/*
2 * SPDX-License-Identifier: GPL-2.0
3 *
4 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
5 *
6 * Authors:
7 * Md Sadre Alam <[email protected]>
8 * Sricharan R <[email protected]>
9 * Varadarajan Narayanan <[email protected]>
10 */
11#include <linux/bitops.h>
12#include <linux/clk.h>
13#include <linux/delay.h>
14#include <linux/dmaengine.h>
15#include <linux/dma-mapping.h>
16#include <linux/dma/qcom_adm.h>
17#include <linux/dma/qcom_bam_dma.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/platform_device.h>
21#include <linux/slab.h>
22#include <linux/mtd/nand-qpic-common.h>
23#include <linux/mtd/spinand.h>
24#include <linux/bitfield.h>
25
26#define NAND_FLASH_SPI_CFG 0xc0
27#define NAND_NUM_ADDR_CYCLES 0xc4
28#define NAND_BUSY_CHECK_WAIT_CNT 0xc8
29#define NAND_FLASH_FEATURES 0xf64
30
31/* QSPI NAND config reg bits */
32#define LOAD_CLK_CNTR_INIT_EN BIT(28)
33#define CLK_CNTR_INIT_VAL_VEC 0x924
34#define CLK_CNTR_INIT_VAL_VEC_MASK GENMASK(27, 16)
35#define FEA_STATUS_DEV_ADDR 0xc0
36#define FEA_STATUS_DEV_ADDR_MASK GENMASK(15, 8)
37#define SPI_CFG BIT(0)
38#define SPI_NUM_ADDR 0xDA4DB
39#define SPI_WAIT_CNT 0x10
40#define QPIC_QSPI_NUM_CS 1
41#define SPI_TRANSFER_MODE_x1 BIT(29)
42#define SPI_TRANSFER_MODE_x4 (3 << 29)
43#define SPI_WP BIT(28)
44#define SPI_HOLD BIT(27)
45#define QPIC_SET_FEATURE BIT(31)
46
47#define SPINAND_RESET 0xff
48#define SPINAND_READID 0x9f
49#define SPINAND_FEATURE_ADDR 0xb0
50#define SPINAND_GET_FEATURE 0x0f
51#define SPINAND_SET_FEATURE 0x1f
52#define SPINAND_READ_CACHE 0x0b
53#define SPINAND_READ 0x13
54#define SPINAND_READ_QUAD 0xeb
55#define SPINAND_READ_MACRONIX 0x6b
56#define SPINAND_ERASE 0xd8
57#define SPINAND_WRITE_EN 0x06
58#define SPINAND_PROGRAM_EXECUTE 0x10
59#define SPINAND_PROGRAM_LOAD 0x84
60#define SPINAND_PROGRAM_LOAD_QUAD 0x34
61
62#define QUAD_WIDTH 0x4
63#define ACC_FEATURE 0xe
64#define BAD_BLOCK_MARKER_SIZE 0x2
65#define OOB_BUF_SIZE 128
66#define ecceng_to_qspi(eng) container_of(eng, struct qpic_spi_nand, ecc_eng)
67
68struct snandc_read_status {
69 __le32 snandc_flash;
70 __le32 snandc_buffer;
71 __le32 snandc_erased_cw;
72};
73
74/*
75 * ECC state struct
76 * @corrected: ECC corrected
77 * @bitflips: Max bit flip
78 * @failed: ECC failed
79 */
80struct qcom_ecc_stats {
81 u32 corrected;
82 u32 bitflips;
83 u32 failed;
84};
85
86struct qpic_ecc {
87 int ecc_bytes_hw;
88 int spare_bytes;
89 int bbm_size;
90 int ecc_mode;
91 int bytes;
92 int steps;
93 int step_size;
94 int strength;
95 int cw_size;
96 int cw_data;
97 u32 cfg0;
98 u32 cfg1;
99 u32 cfg0_raw;
100 u32 cfg1_raw;
101 u32 ecc_buf_cfg;
102 u32 ecc_bch_cfg;
103 bool bch_enabled;
104};
105
106struct qpic_spi_nand {
107 struct qcom_nand_controller *snandc;
108 struct spi_controller *ctlr;
109 struct mtd_info *mtd;
110 struct clk *iomacro_clk;
111 struct qpic_ecc *ecc;
112 struct qcom_ecc_stats ecc_stats;
113 struct nand_ecc_engine ecc_eng;
114 u8 *data_buf;
115 u8 *oob_buf;
116 __le32 addr1;
117 __le32 addr2;
118 __le32 cmd;
119 u32 num_cw;
120 bool oob_rw;
121 bool page_rw;
122 bool raw_rw;
123 bool quad_mode;
124};
125
126static void qcom_spi_set_read_loc_first(struct qcom_nand_controller *snandc,
127 int reg, int cw_offset, int read_size,
128 int is_last_read_loc)
129{
130 __le32 locreg_val;
131 u32 val = FIELD_PREP(READ_LOCATION_OFFSET_MASK, cw_offset) |
132 FIELD_PREP(READ_LOCATION_SIZE_MASK, read_size) |
133 FIELD_PREP(READ_LOCATION_LAST_MASK, is_last_read_loc);
134
135 locreg_val = cpu_to_le32(val);
136
137 if (reg == NAND_READ_LOCATION_0)
138 snandc->regs->read_location0 = locreg_val;
139 else if (reg == NAND_READ_LOCATION_1)
140 snandc->regs->read_location1 = locreg_val;
141 else if (reg == NAND_READ_LOCATION_2)
142 snandc->regs->read_location2 = locreg_val;
143 else if (reg == NAND_READ_LOCATION_3)
144 snandc->regs->read_location3 = locreg_val;
145}
146
147static void qcom_spi_set_read_loc_last(struct qcom_nand_controller *snandc,
148 int reg, int cw_offset, int read_size,
149 int is_last_read_loc)
150{
151 __le32 locreg_val;
152 u32 val = FIELD_PREP(READ_LOCATION_OFFSET_MASK, cw_offset) |
153 FIELD_PREP(READ_LOCATION_SIZE_MASK, read_size) |
154 FIELD_PREP(READ_LOCATION_LAST_MASK, is_last_read_loc);
155
156 locreg_val = cpu_to_le32(val);
157
158 if (reg == NAND_READ_LOCATION_LAST_CW_0)
159 snandc->regs->read_location_last0 = locreg_val;
160 else if (reg == NAND_READ_LOCATION_LAST_CW_1)
161 snandc->regs->read_location_last1 = locreg_val;
162 else if (reg == NAND_READ_LOCATION_LAST_CW_2)
163 snandc->regs->read_location_last2 = locreg_val;
164 else if (reg == NAND_READ_LOCATION_LAST_CW_3)
165 snandc->regs->read_location_last3 = locreg_val;
166}
167
168static struct qcom_nand_controller *nand_to_qcom_snand(struct nand_device *nand)
169{
170 struct nand_ecc_engine *eng = nand->ecc.engine;
171 struct qpic_spi_nand *qspi = ecceng_to_qspi(eng);
172
173 return qspi->snandc;
174}
175
176static int qcom_spi_init(struct qcom_nand_controller *snandc)
177{
178 u32 snand_cfg_val = 0x0;
179 int ret;
180
181 snand_cfg_val = FIELD_PREP(CLK_CNTR_INIT_VAL_VEC_MASK, CLK_CNTR_INIT_VAL_VEC) |
182 FIELD_PREP(LOAD_CLK_CNTR_INIT_EN, 0) |
183 FIELD_PREP(FEA_STATUS_DEV_ADDR_MASK, FEA_STATUS_DEV_ADDR) |
184 FIELD_PREP(SPI_CFG, 0);
185
186 snandc->regs->spi_cfg = cpu_to_le32(snand_cfg_val);
187 snandc->regs->num_addr_cycle = cpu_to_le32(SPI_NUM_ADDR);
188 snandc->regs->busy_wait_cnt = cpu_to_le32(SPI_WAIT_CNT);
189
190 qcom_write_reg_dma(snandc, &snandc->regs->spi_cfg, NAND_FLASH_SPI_CFG, 1, 0);
191
192 snand_cfg_val &= ~LOAD_CLK_CNTR_INIT_EN;
193 snandc->regs->spi_cfg = cpu_to_le32(snand_cfg_val);
194
195 qcom_write_reg_dma(snandc, &snandc->regs->spi_cfg, NAND_FLASH_SPI_CFG, 1, 0);
196
197 qcom_write_reg_dma(snandc, &snandc->regs->num_addr_cycle, NAND_NUM_ADDR_CYCLES, 1, 0);
198 qcom_write_reg_dma(snandc, &snandc->regs->busy_wait_cnt, NAND_BUSY_CHECK_WAIT_CNT, 1,
199 NAND_BAM_NEXT_SGL);
200
201 ret = qcom_submit_descs(snandc);
202 if (ret) {
203 dev_err(snandc->dev, "failure in submitting spi init descriptor\n");
204 return ret;
205 }
206
207 return ret;
208}
209
210static int qcom_spi_ooblayout_ecc(struct mtd_info *mtd, int section,
211 struct mtd_oob_region *oobregion)
212{
213 struct nand_device *nand = mtd_to_nanddev(mtd);
214 struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand);
215 struct qpic_ecc *qecc = snandc->qspi->ecc;
216
217 switch (section) {
218 case 0:
219 oobregion->offset = 0;
220 oobregion->length = qecc->bytes * (qecc->steps - 1) +
221 qecc->bbm_size;
222 return 0;
223 case 1:
224 oobregion->offset = qecc->bytes * (qecc->steps - 1) +
225 qecc->bbm_size +
226 qecc->steps * 4;
227 oobregion->length = mtd->oobsize - oobregion->offset;
228 return 0;
229 }
230
231 return -ERANGE;
232}
233
234static int qcom_spi_ooblayout_free(struct mtd_info *mtd, int section,
235 struct mtd_oob_region *oobregion)
236{
237 struct nand_device *nand = mtd_to_nanddev(mtd);
238 struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand);
239 struct qpic_ecc *qecc = snandc->qspi->ecc;
240
241 if (section)
242 return -ERANGE;
243
244 oobregion->length = qecc->steps * 4;
245 oobregion->offset = ((qecc->steps - 1) * qecc->bytes) + qecc->bbm_size;
246
247 return 0;
248}
249
250static const struct mtd_ooblayout_ops qcom_spi_ooblayout = {
251 .ecc = qcom_spi_ooblayout_ecc,
252 .free = qcom_spi_ooblayout_free,
253};
254
255static int qcom_spi_ecc_init_ctx_pipelined(struct nand_device *nand)
256{
257 struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand);
258 struct nand_ecc_props *reqs = &nand->ecc.requirements;
259 struct nand_ecc_props *user = &nand->ecc.user_conf;
260 struct nand_ecc_props *conf = &nand->ecc.ctx.conf;
261 struct mtd_info *mtd = nanddev_to_mtd(nand);
262 int cwperpage, bad_block_byte, ret;
263 struct qpic_ecc *ecc_cfg;
264
265 cwperpage = mtd->writesize / NANDC_STEP_SIZE;
266 snandc->qspi->num_cw = cwperpage;
267
268 ecc_cfg = kzalloc_obj(*ecc_cfg);
269 if (!ecc_cfg)
270 return -ENOMEM;
271
272 if (user->step_size && user->strength) {
273 ecc_cfg->step_size = user->step_size;
274 ecc_cfg->strength = user->strength;
275 } else if (reqs->step_size && reqs->strength) {
276 ecc_cfg->step_size = reqs->step_size;
277 ecc_cfg->strength = reqs->strength;
278 } else {
279 /* use defaults */
280 ecc_cfg->step_size = NANDC_STEP_SIZE;
281 ecc_cfg->strength = 4;
282 }
283
284 /*
285 * Override ECC strength based on OOB size to avoid weak ECC warning.
286 * If OOB size is more than 128 bytes, use 8-bit ECC for better
287 * error correction capability, which is required by chips with
288 * larger OOB areas like Macronix SPI NAND with 256 bytes OOB.
289 */
290 if (mtd->oobsize >= 128 && ecc_cfg->strength < 8) {
291 dev_info(snandc->dev,
292 "Upgrading ECC strength from %d to 8 bits (OOB size: %d bytes)\n",
293 ecc_cfg->strength, mtd->oobsize);
294 ecc_cfg->strength = 8;
295 }
296
297 if (ecc_cfg->step_size != NANDC_STEP_SIZE) {
298 dev_err(snandc->dev,
299 "only %u bytes ECC step size is supported\n",
300 NANDC_STEP_SIZE);
301 ret = -EOPNOTSUPP;
302 goto err_free_ecc_cfg;
303 }
304
305 switch (ecc_cfg->strength) {
306 case 4:
307 ecc_cfg->ecc_mode = ECC_MODE_4BIT;
308 ecc_cfg->ecc_bytes_hw = 7;
309 ecc_cfg->spare_bytes = 4;
310 break;
311
312 case 8:
313 ecc_cfg->ecc_mode = ECC_MODE_8BIT;
314 ecc_cfg->ecc_bytes_hw = 13;
315 ecc_cfg->spare_bytes = 2;
316 break;
317
318 default:
319 dev_err(snandc->dev,
320 "only 4 or 8 bits ECC strength is supported\n");
321 ret = -EOPNOTSUPP;
322 goto err_free_ecc_cfg;
323 }
324
325 snandc->qspi->oob_buf = kmalloc(mtd->writesize + mtd->oobsize,
326 GFP_KERNEL);
327 if (!snandc->qspi->oob_buf) {
328 ret = -ENOMEM;
329 goto err_free_ecc_cfg;
330 }
331
332 memset(snandc->qspi->oob_buf, 0xff, mtd->writesize + mtd->oobsize);
333
334 nand->ecc.ctx.priv = ecc_cfg;
335 snandc->qspi->mtd = mtd;
336
337 ecc_cfg->bbm_size = 1;
338 ecc_cfg->bch_enabled = true;
339 ecc_cfg->bytes = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes + ecc_cfg->bbm_size;
340
341 ecc_cfg->steps = cwperpage;
342 ecc_cfg->cw_data = 516;
343 ecc_cfg->cw_size = ecc_cfg->cw_data + ecc_cfg->bytes;
344 bad_block_byte = mtd->writesize - ecc_cfg->cw_size * (cwperpage - 1) + 1;
345
346 mtd_set_ooblayout(mtd, &qcom_spi_ooblayout);
347
348 /*
349 * Free the temporary BAM transaction allocated initially by
350 * qcom_nandc_alloc(), and allocate a new one based on the
351 * updated max_cwperpage value.
352 */
353 qcom_free_bam_transaction(snandc);
354
355 snandc->max_cwperpage = cwperpage;
356
357 snandc->bam_txn = qcom_alloc_bam_transaction(snandc);
358 if (!snandc->bam_txn) {
359 dev_err(snandc->dev, "failed to allocate BAM transaction\n");
360 ret = -ENOMEM;
361 goto err_free_ecc_cfg;
362 }
363
364 ecc_cfg->cfg0 = FIELD_PREP(CW_PER_PAGE_MASK, (cwperpage - 1)) |
365 FIELD_PREP(UD_SIZE_BYTES_MASK, ecc_cfg->cw_data) |
366 FIELD_PREP(DISABLE_STATUS_AFTER_WRITE, 1) |
367 FIELD_PREP(NUM_ADDR_CYCLES_MASK, 3) |
368 FIELD_PREP(ECC_PARITY_SIZE_BYTES_RS, ecc_cfg->ecc_bytes_hw) |
369 FIELD_PREP(STATUS_BFR_READ, 0) |
370 FIELD_PREP(SET_RD_MODE_AFTER_STATUS, 1) |
371 FIELD_PREP(SPARE_SIZE_BYTES_MASK, ecc_cfg->spare_bytes);
372
373 ecc_cfg->cfg1 = FIELD_PREP(NAND_RECOVERY_CYCLES_MASK, 0) |
374 FIELD_PREP(CS_ACTIVE_BSY, 0) |
375 FIELD_PREP(BAD_BLOCK_BYTE_NUM_MASK, bad_block_byte) |
376 FIELD_PREP(BAD_BLOCK_IN_SPARE_AREA, 0) |
377 FIELD_PREP(WR_RD_BSY_GAP_MASK, 20) |
378 FIELD_PREP(WIDE_FLASH, 0) |
379 FIELD_PREP(ENABLE_BCH_ECC, ecc_cfg->bch_enabled);
380
381 ecc_cfg->cfg0_raw = FIELD_PREP(CW_PER_PAGE_MASK, (cwperpage - 1)) |
382 FIELD_PREP(NUM_ADDR_CYCLES_MASK, 3) |
383 FIELD_PREP(UD_SIZE_BYTES_MASK, ecc_cfg->cw_size) |
384 FIELD_PREP(SPARE_SIZE_BYTES_MASK, 0);
385
386 ecc_cfg->cfg1_raw = FIELD_PREP(NAND_RECOVERY_CYCLES_MASK, 0) |
387 FIELD_PREP(CS_ACTIVE_BSY, 0) |
388 FIELD_PREP(BAD_BLOCK_BYTE_NUM_MASK, 17) |
389 FIELD_PREP(BAD_BLOCK_IN_SPARE_AREA, 1) |
390 FIELD_PREP(WR_RD_BSY_GAP_MASK, 20) |
391 FIELD_PREP(WIDE_FLASH, 0) |
392 FIELD_PREP(DEV0_CFG1_ECC_DISABLE, 1);
393
394 ecc_cfg->ecc_bch_cfg = FIELD_PREP(ECC_CFG_ECC_DISABLE, !ecc_cfg->bch_enabled) |
395 FIELD_PREP(ECC_SW_RESET, 0) |
396 FIELD_PREP(ECC_NUM_DATA_BYTES_MASK, ecc_cfg->cw_data) |
397 FIELD_PREP(ECC_FORCE_CLK_OPEN, 1) |
398 FIELD_PREP(ECC_MODE_MASK, ecc_cfg->ecc_mode) |
399 FIELD_PREP(ECC_PARITY_SIZE_BYTES_BCH_MASK, ecc_cfg->ecc_bytes_hw);
400
401 ecc_cfg->ecc_buf_cfg = FIELD_PREP(NUM_STEPS_MASK, 0x203);
402
403 conf->step_size = ecc_cfg->step_size;
404 conf->strength = ecc_cfg->strength;
405
406 snandc->regs->clrflashstatus = cpu_to_le32(FS_READY_BSY_N);
407 snandc->regs->clrreadstatus = cpu_to_le32(0xc0);
408 snandc->regs->erased_cw_detect_cfg_clr = cpu_to_le32(CLR_ERASED_PAGE_DET);
409 snandc->regs->erased_cw_detect_cfg_set = cpu_to_le32(SET_ERASED_PAGE_DET);
410
411 dev_dbg(snandc->dev, "ECC strength: %u bits per %u bytes\n",
412 ecc_cfg->strength, ecc_cfg->step_size);
413
414 return 0;
415
416err_free_ecc_cfg:
417 kfree(snandc->qspi->oob_buf);
418 snandc->qspi->oob_buf = NULL;
419 kfree(ecc_cfg);
420 return ret;
421}
422
423static void qcom_spi_ecc_cleanup_ctx_pipelined(struct nand_device *nand)
424{
425 struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand);
426 struct qpic_ecc *ecc_cfg = nand_to_ecc_ctx(nand);
427
428 kfree(snandc->qspi->oob_buf);
429 snandc->qspi->oob_buf = NULL;
430 kfree(ecc_cfg);
431}
432
433static int qcom_spi_ecc_prepare_io_req_pipelined(struct nand_device *nand,
434 struct nand_page_io_req *req)
435{
436 struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand);
437 struct qpic_ecc *ecc_cfg = nand_to_ecc_ctx(nand);
438
439 snandc->qspi->ecc = ecc_cfg;
440 snandc->qspi->raw_rw = false;
441 snandc->qspi->oob_rw = false;
442 snandc->qspi->page_rw = false;
443
444 if (req->datalen)
445 snandc->qspi->page_rw = true;
446
447 if (req->ooblen)
448 snandc->qspi->oob_rw = true;
449
450 if (req->mode == MTD_OPS_RAW)
451 snandc->qspi->raw_rw = true;
452
453 return 0;
454}
455
456static int qcom_spi_ecc_finish_io_req_pipelined(struct nand_device *nand,
457 struct nand_page_io_req *req)
458{
459 struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand);
460 struct mtd_info *mtd = nanddev_to_mtd(nand);
461
462 if (req->mode == MTD_OPS_RAW || req->type != NAND_PAGE_READ)
463 return 0;
464
465 if (snandc->qspi->ecc_stats.failed)
466 mtd->ecc_stats.failed += snandc->qspi->ecc_stats.failed;
467 else
468 mtd->ecc_stats.corrected += snandc->qspi->ecc_stats.corrected;
469
470 if (snandc->qspi->ecc_stats.failed)
471 return -EBADMSG;
472 else
473 return snandc->qspi->ecc_stats.bitflips;
474}
475
476static const struct nand_ecc_engine_ops qcom_spi_ecc_engine_ops_pipelined = {
477 .init_ctx = qcom_spi_ecc_init_ctx_pipelined,
478 .cleanup_ctx = qcom_spi_ecc_cleanup_ctx_pipelined,
479 .prepare_io_req = qcom_spi_ecc_prepare_io_req_pipelined,
480 .finish_io_req = qcom_spi_ecc_finish_io_req_pipelined,
481};
482
483/* helper to configure location register values */
484static void qcom_spi_set_read_loc(struct qcom_nand_controller *snandc, int cw, int reg,
485 int cw_offset, int read_size, int is_last_read_loc)
486{
487 int reg_base = NAND_READ_LOCATION_0;
488 int num_cw = snandc->qspi->num_cw;
489
490 if (cw == (num_cw - 1))
491 reg_base = NAND_READ_LOCATION_LAST_CW_0;
492
493 reg_base += reg * 4;
494
495 if (cw == (num_cw - 1))
496 return qcom_spi_set_read_loc_last(snandc, reg_base, cw_offset,
497 read_size, is_last_read_loc);
498 else
499 return qcom_spi_set_read_loc_first(snandc, reg_base, cw_offset,
500 read_size, is_last_read_loc);
501}
502
503static void
504qcom_spi_config_cw_read(struct qcom_nand_controller *snandc, bool use_ecc, int cw)
505{
506 __le32 *reg = &snandc->regs->read_location0;
507 int num_cw = snandc->qspi->num_cw;
508
509 qcom_write_reg_dma(snandc, reg, NAND_READ_LOCATION_0, 4, NAND_BAM_NEXT_SGL);
510 if (cw == (num_cw - 1)) {
511 reg = &snandc->regs->read_location_last0;
512 qcom_write_reg_dma(snandc, reg, NAND_READ_LOCATION_LAST_CW_0, 4,
513 NAND_BAM_NEXT_SGL);
514 }
515
516 qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
517 qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
518
519 if (use_ecc) {
520 qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 2, 0);
521 qcom_read_reg_dma(snandc, NAND_ERASED_CW_DETECT_STATUS, 1,
522 NAND_BAM_NEXT_SGL);
523 } else {
524 qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 1,
525 NAND_BAM_NEXT_SGL);
526 }
527}
528
529static int qcom_spi_block_erase(struct qcom_nand_controller *snandc)
530{
531 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
532 int ret;
533
534 snandc->buf_count = 0;
535 snandc->buf_start = 0;
536 qcom_clear_read_regs(snandc);
537 qcom_clear_bam_transaction(snandc);
538
539 snandc->regs->cmd = snandc->qspi->cmd;
540 snandc->regs->addr0 = snandc->qspi->addr1;
541 snandc->regs->addr1 = snandc->qspi->addr2;
542 snandc->regs->cfg0 = cpu_to_le32((ecc_cfg->cfg0_raw & ~CW_PER_PAGE_MASK) |
543 FIELD_PREP(CW_PER_PAGE_MASK, 0));
544 snandc->regs->cfg1 = cpu_to_le32(ecc_cfg->cfg1_raw);
545 snandc->regs->exec = cpu_to_le32(1);
546
547 qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 3, NAND_BAM_NEXT_SGL);
548 qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 2, NAND_BAM_NEXT_SGL);
549 qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
550
551 ret = qcom_submit_descs(snandc);
552 if (ret) {
553 dev_err(snandc->dev, "failure to erase block\n");
554 return ret;
555 }
556
557 return 0;
558}
559
560static void qcom_spi_config_single_cw_page_read(struct qcom_nand_controller *snandc,
561 bool use_ecc, int cw)
562{
563 __le32 *reg = &snandc->regs->read_location0;
564 int num_cw = snandc->qspi->num_cw;
565
566 qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0);
567 qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0);
568 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr,
569 NAND_ERASED_CW_DETECT_CFG, 1, 0);
570 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set,
571 NAND_ERASED_CW_DETECT_CFG, 1,
572 NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
573
574 if (cw == (num_cw - 1)) {
575 reg = &snandc->regs->read_location_last0;
576 qcom_write_reg_dma(snandc, reg, NAND_READ_LOCATION_LAST_CW_0, 4, NAND_BAM_NEXT_SGL);
577 }
578 qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
579 qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
580
581 qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 1, 0);
582}
583
584static int qcom_spi_check_raw_flash_errors(struct qcom_nand_controller *snandc, int cw_cnt)
585{
586 int i;
587
588 qcom_nandc_dev_to_mem(snandc, true);
589
590 for (i = 0; i < cw_cnt; i++) {
591 u32 flash = le32_to_cpu(snandc->reg_read_buf[i]);
592
593 if (flash & (FS_OP_ERR | FS_MPU_ERR))
594 return -EIO;
595 }
596
597 return 0;
598}
599
600static int qcom_spi_read_last_cw(struct qcom_nand_controller *snandc,
601 const struct spi_mem_op *op)
602{
603 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
604 struct mtd_info *mtd = snandc->qspi->mtd;
605 int size, ret = 0;
606 int col, bbpos;
607 u32 cfg0, cfg1, ecc_bch_cfg;
608 u32 num_cw = snandc->qspi->num_cw;
609
610 qcom_clear_bam_transaction(snandc);
611 qcom_clear_read_regs(snandc);
612
613 size = ecc_cfg->cw_size;
614 col = ecc_cfg->cw_size * (num_cw - 1);
615
616 memset(snandc->data_buffer, 0xff, size);
617 snandc->regs->addr0 = (snandc->qspi->addr1 | cpu_to_le32(col));
618 snandc->regs->addr1 = snandc->qspi->addr2;
619
620 cfg0 = (ecc_cfg->cfg0_raw & ~CW_PER_PAGE_MASK) |
621 FIELD_PREP(CW_PER_PAGE_MASK, 0);
622 cfg1 = ecc_cfg->cfg1_raw;
623 ecc_bch_cfg = ECC_CFG_ECC_DISABLE;
624
625 snandc->regs->cmd = snandc->qspi->cmd;
626 snandc->regs->cfg0 = cpu_to_le32(cfg0);
627 snandc->regs->cfg1 = cpu_to_le32(cfg1);
628 snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
629 snandc->regs->exec = cpu_to_le32(1);
630
631 qcom_spi_set_read_loc(snandc, num_cw - 1, 0, 0, ecc_cfg->cw_size, 1);
632
633 qcom_spi_config_single_cw_page_read(snandc, false, num_cw - 1);
634
635 qcom_read_data_dma(snandc, FLASH_BUF_ACC, snandc->data_buffer, size, 0);
636
637 ret = qcom_submit_descs(snandc);
638 if (ret) {
639 dev_err(snandc->dev, "failed to read last cw\n");
640 return ret;
641 }
642
643 ret = qcom_spi_check_raw_flash_errors(snandc, 1);
644 if (ret)
645 return ret;
646
647 bbpos = mtd->writesize - ecc_cfg->cw_size * (num_cw - 1);
648
649 /*
650 * TODO: The SPINAND code expects two bad block marker bytes
651 * at the beginning of the OOB area, but the OOB layout used by
652 * the driver has only one. Duplicate that for now in order to
653 * avoid certain blocks to be marked as bad.
654 *
655 * This can be removed once single-byte bad block marker support
656 * gets implemented in the SPINAND code.
657 */
658 snandc->data_buffer[bbpos + 1] = snandc->data_buffer[bbpos];
659
660 memcpy(op->data.buf.in, snandc->data_buffer + bbpos, op->data.nbytes);
661
662 return ret;
663}
664
665static int qcom_spi_check_error(struct qcom_nand_controller *snandc)
666{
667 struct snandc_read_status *buf;
668 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
669 int i, num_cw = snandc->qspi->num_cw;
670 bool flash_op_err = false, erased;
671 unsigned int max_bitflips = 0;
672 unsigned int uncorrectable_cws = 0;
673
674 snandc->qspi->ecc_stats.failed = 0;
675 snandc->qspi->ecc_stats.corrected = 0;
676
677 qcom_nandc_dev_to_mem(snandc, true);
678 buf = (struct snandc_read_status *)snandc->reg_read_buf;
679
680 for (i = 0; i < num_cw; i++, buf++) {
681 u32 flash, buffer, erased_cw;
682
683 flash = le32_to_cpu(buf->snandc_flash);
684 buffer = le32_to_cpu(buf->snandc_buffer);
685 erased_cw = le32_to_cpu(buf->snandc_erased_cw);
686
687 if ((flash & FS_OP_ERR) && (buffer & BS_UNCORRECTABLE_BIT)) {
688 if (ecc_cfg->bch_enabled)
689 erased = (erased_cw & ERASED_CW) == ERASED_CW;
690 else
691 erased = false;
692
693 if (!erased)
694 uncorrectable_cws |= BIT(i);
695
696 } else if (flash & (FS_OP_ERR | FS_MPU_ERR)) {
697 flash_op_err = true;
698 } else {
699 unsigned int stat;
700
701 stat = buffer & BS_CORRECTABLE_ERR_MSK;
702
703 /*
704 * The exact number of the corrected bits is
705 * unknown because the hardware only reports the
706 * number of the corrected bytes.
707 *
708 * Since we have no better solution at the moment,
709 * report that value as the number of bit errors
710 * despite that it is inaccurate in most cases.
711 */
712 if (stat && stat != ecc_cfg->strength)
713 dev_warn_once(snandc->dev,
714 "Warning: due to hw limitation, the reported number of the corrected bits may be inaccurate\n");
715
716 snandc->qspi->ecc_stats.corrected += stat;
717 max_bitflips = max(max_bitflips, stat);
718 }
719 }
720
721 if (flash_op_err)
722 return -EIO;
723
724 if (!uncorrectable_cws)
725 snandc->qspi->ecc_stats.bitflips = max_bitflips;
726 else
727 snandc->qspi->ecc_stats.failed++;
728
729 return 0;
730}
731
732static int qcom_spi_read_cw_raw(struct qcom_nand_controller *snandc, u8 *data_buf,
733 u8 *oob_buf, int cw)
734{
735 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
736 struct mtd_info *mtd = snandc->qspi->mtd;
737 int data_size1, data_size2, oob_size1, oob_size2;
738 int ret, reg_off = FLASH_BUF_ACC, read_loc = 0;
739 int raw_cw = cw;
740 u32 cfg0, cfg1, ecc_bch_cfg, num_cw = snandc->qspi->num_cw;
741 int col;
742
743 snandc->buf_count = 0;
744 snandc->buf_start = 0;
745 qcom_clear_read_regs(snandc);
746 qcom_clear_bam_transaction(snandc);
747 raw_cw = num_cw - 1;
748
749 cfg0 = (ecc_cfg->cfg0_raw & ~CW_PER_PAGE_MASK) |
750 FIELD_PREP(CW_PER_PAGE_MASK, 0);
751 cfg1 = ecc_cfg->cfg1_raw;
752 ecc_bch_cfg = ECC_CFG_ECC_DISABLE;
753
754 col = ecc_cfg->cw_size * cw;
755
756 snandc->regs->addr0 = (snandc->qspi->addr1 | cpu_to_le32(col));
757 snandc->regs->addr1 = snandc->qspi->addr2;
758 snandc->regs->cmd = snandc->qspi->cmd;
759 snandc->regs->cfg0 = cpu_to_le32(cfg0);
760 snandc->regs->cfg1 = cpu_to_le32(cfg1);
761 snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
762 snandc->regs->exec = cpu_to_le32(1);
763
764 qcom_spi_set_read_loc(snandc, raw_cw, 0, 0, ecc_cfg->cw_size, 1);
765
766 qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0);
767 qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0);
768 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr,
769 NAND_ERASED_CW_DETECT_CFG, 1, 0);
770 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set,
771 NAND_ERASED_CW_DETECT_CFG, 1,
772 NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
773
774 data_size1 = mtd->writesize - ecc_cfg->cw_size * (num_cw - 1);
775 oob_size1 = ecc_cfg->bbm_size;
776
777 if (cw == (num_cw - 1)) {
778 data_size2 = NANDC_STEP_SIZE - data_size1 -
779 ((num_cw - 1) * 4);
780 oob_size2 = (num_cw * 4) + ecc_cfg->ecc_bytes_hw +
781 ecc_cfg->spare_bytes;
782 } else {
783 data_size2 = ecc_cfg->cw_data - data_size1;
784 oob_size2 = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes;
785 }
786
787 qcom_spi_set_read_loc(snandc, cw, 0, read_loc, data_size1, 0);
788 read_loc += data_size1;
789
790 qcom_spi_set_read_loc(snandc, cw, 1, read_loc, oob_size1, 0);
791 read_loc += oob_size1;
792
793 qcom_spi_set_read_loc(snandc, cw, 2, read_loc, data_size2, 0);
794 read_loc += data_size2;
795
796 qcom_spi_set_read_loc(snandc, cw, 3, read_loc, oob_size2, 1);
797
798 qcom_spi_config_cw_read(snandc, false, raw_cw);
799
800 qcom_read_data_dma(snandc, reg_off, data_buf, data_size1, 0);
801 reg_off += data_size1;
802
803 qcom_read_data_dma(snandc, reg_off, oob_buf, oob_size1, 0);
804 reg_off += oob_size1;
805
806 qcom_read_data_dma(snandc, reg_off, data_buf + data_size1, data_size2, 0);
807 reg_off += data_size2;
808
809 qcom_read_data_dma(snandc, reg_off, oob_buf + oob_size1, oob_size2, 0);
810
811 ret = qcom_submit_descs(snandc);
812 if (ret) {
813 dev_err(snandc->dev, "failure to read raw cw %d\n", cw);
814 return ret;
815 }
816
817 return qcom_spi_check_raw_flash_errors(snandc, 1);
818}
819
820static int qcom_spi_read_page_raw(struct qcom_nand_controller *snandc,
821 const struct spi_mem_op *op)
822{
823 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
824 u8 *data_buf = NULL, *oob_buf = NULL;
825 int ret, cw;
826 u32 num_cw = snandc->qspi->num_cw;
827
828 if (snandc->qspi->page_rw)
829 data_buf = op->data.buf.in;
830
831 oob_buf = snandc->qspi->oob_buf;
832 memset(oob_buf, 0xff, OOB_BUF_SIZE);
833
834 for (cw = 0; cw < num_cw; cw++) {
835 ret = qcom_spi_read_cw_raw(snandc, data_buf, oob_buf, cw);
836 if (ret)
837 return ret;
838
839 if (data_buf)
840 data_buf += ecc_cfg->cw_data;
841 if (oob_buf)
842 oob_buf += ecc_cfg->bytes;
843 }
844
845 return 0;
846}
847
848static int qcom_spi_read_page_ecc(struct qcom_nand_controller *snandc,
849 const struct spi_mem_op *op)
850{
851 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
852 u8 *data_buf = NULL, *oob_buf = NULL;
853 int ret, i;
854 u32 cfg0, cfg1, ecc_bch_cfg, num_cw = snandc->qspi->num_cw;
855
856 data_buf = op->data.buf.in;
857 oob_buf = snandc->qspi->oob_buf;
858
859 snandc->buf_count = 0;
860 snandc->buf_start = 0;
861 qcom_clear_read_regs(snandc);
862
863 cfg0 = (ecc_cfg->cfg0 & ~CW_PER_PAGE_MASK) |
864 FIELD_PREP(CW_PER_PAGE_MASK, num_cw - 1);
865 cfg1 = ecc_cfg->cfg1;
866 ecc_bch_cfg = ecc_cfg->ecc_bch_cfg;
867
868 snandc->regs->addr0 = snandc->qspi->addr1;
869 snandc->regs->addr1 = snandc->qspi->addr2;
870 snandc->regs->cmd = snandc->qspi->cmd;
871 snandc->regs->cfg0 = cpu_to_le32(cfg0);
872 snandc->regs->cfg1 = cpu_to_le32(cfg1);
873 snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
874 snandc->regs->exec = cpu_to_le32(1);
875
876 qcom_clear_bam_transaction(snandc);
877
878 qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0);
879 qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0);
880 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr,
881 NAND_ERASED_CW_DETECT_CFG, 1, 0);
882 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set,
883 NAND_ERASED_CW_DETECT_CFG, 1,
884 NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
885
886 for (i = 0; i < num_cw; i++) {
887 int data_size, oob_size;
888
889 if (i == (num_cw - 1)) {
890 data_size = NANDC_STEP_SIZE - ((num_cw - 1) << 2);
891 oob_size = (num_cw << 2) + ecc_cfg->ecc_bytes_hw +
892 ecc_cfg->spare_bytes;
893 } else {
894 data_size = ecc_cfg->cw_data;
895 oob_size = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes;
896 }
897
898 if (data_buf && oob_buf) {
899 qcom_spi_set_read_loc(snandc, i, 0, 0, data_size, 0);
900 qcom_spi_set_read_loc(snandc, i, 1, data_size, oob_size, 1);
901 } else if (data_buf) {
902 qcom_spi_set_read_loc(snandc, i, 0, 0, data_size, 1);
903 } else {
904 qcom_spi_set_read_loc(snandc, i, 0, data_size, oob_size, 1);
905 }
906
907 qcom_spi_config_cw_read(snandc, true, i);
908
909 if (data_buf)
910 qcom_read_data_dma(snandc, FLASH_BUF_ACC, data_buf,
911 data_size, 0);
912 if (oob_buf) {
913 int j;
914
915 for (j = 0; j < ecc_cfg->bbm_size; j++)
916 *oob_buf++ = 0xff;
917
918 qcom_read_data_dma(snandc, FLASH_BUF_ACC + data_size,
919 oob_buf, oob_size, 0);
920 }
921
922 if (data_buf)
923 data_buf += data_size;
924 if (oob_buf)
925 oob_buf += oob_size;
926 }
927
928 ret = qcom_submit_descs(snandc);
929 if (ret) {
930 dev_err(snandc->dev, "failure to read page\n");
931 return ret;
932 }
933
934 return qcom_spi_check_error(snandc);
935}
936
937static int qcom_spi_read_page_oob(struct qcom_nand_controller *snandc,
938 const struct spi_mem_op *op)
939{
940 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
941 u8 *oob_buf = NULL;
942 int ret, i;
943 u32 cfg0, cfg1, ecc_bch_cfg, num_cw = snandc->qspi->num_cw;
944
945 oob_buf = op->data.buf.in;
946
947 snandc->buf_count = 0;
948 snandc->buf_start = 0;
949 qcom_clear_read_regs(snandc);
950 qcom_clear_bam_transaction(snandc);
951
952 cfg0 = (ecc_cfg->cfg0 & ~CW_PER_PAGE_MASK) |
953 FIELD_PREP(CW_PER_PAGE_MASK, num_cw - 1);
954 cfg1 = ecc_cfg->cfg1;
955 ecc_bch_cfg = ecc_cfg->ecc_bch_cfg;
956
957 snandc->regs->addr0 = snandc->qspi->addr1;
958 snandc->regs->addr1 = snandc->qspi->addr2;
959 snandc->regs->cmd = snandc->qspi->cmd;
960 snandc->regs->cfg0 = cpu_to_le32(cfg0);
961 snandc->regs->cfg1 = cpu_to_le32(cfg1);
962 snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
963 snandc->regs->exec = cpu_to_le32(1);
964
965 qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0);
966 qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0);
967 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr,
968 NAND_ERASED_CW_DETECT_CFG, 1, 0);
969 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set,
970 NAND_ERASED_CW_DETECT_CFG, 1,
971 NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
972
973 for (i = 0; i < num_cw; i++) {
974 int data_size, oob_size;
975
976 if (i == (num_cw - 1)) {
977 data_size = NANDC_STEP_SIZE - ((num_cw - 1) << 2);
978 oob_size = (num_cw << 2) + ecc_cfg->ecc_bytes_hw +
979 ecc_cfg->spare_bytes;
980 } else {
981 data_size = ecc_cfg->cw_data;
982 oob_size = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes;
983 }
984
985 qcom_spi_set_read_loc(snandc, i, 0, data_size, oob_size, 1);
986
987 qcom_spi_config_cw_read(snandc, true, i);
988
989 if (oob_buf) {
990 int j;
991
992 for (j = 0; j < ecc_cfg->bbm_size; j++)
993 *oob_buf++ = 0xff;
994
995 qcom_read_data_dma(snandc, FLASH_BUF_ACC + data_size,
996 oob_buf, oob_size, 0);
997 }
998
999 if (oob_buf)
1000 oob_buf += oob_size;
1001 }
1002
1003 ret = qcom_submit_descs(snandc);
1004 if (ret) {
1005 dev_err(snandc->dev, "failure to read oob\n");
1006 return ret;
1007 }
1008
1009 return qcom_spi_check_error(snandc);
1010}
1011
1012static int qcom_spi_cmd_mapping(struct qcom_nand_controller *snandc,
1013 const struct spi_mem_op *op, u32 *cmd)
1014{
1015 u32 opcode = op->cmd.opcode;
1016 u32 transfer_mode = SPI_TRANSFER_MODE_x1;
1017
1018 if (snandc->qspi->quad_mode && op->data.buswidth == QUAD_WIDTH)
1019 transfer_mode = SPI_TRANSFER_MODE_x4;
1020
1021 switch (opcode) {
1022 case SPINAND_RESET:
1023 *cmd = (SPI_WP | SPI_HOLD | SPI_TRANSFER_MODE_x1 | OP_RESET_DEVICE);
1024 break;
1025 case SPINAND_READID:
1026 *cmd = (SPI_WP | SPI_HOLD | SPI_TRANSFER_MODE_x1 | OP_FETCH_ID);
1027 break;
1028 case SPINAND_GET_FEATURE:
1029 *cmd = (SPI_TRANSFER_MODE_x1 | SPI_WP | SPI_HOLD | ACC_FEATURE);
1030 break;
1031 case SPINAND_SET_FEATURE:
1032 *cmd = (SPI_TRANSFER_MODE_x1 | SPI_WP | SPI_HOLD | ACC_FEATURE |
1033 QPIC_SET_FEATURE);
1034 break;
1035 case SPINAND_READ:
1036 case SPINAND_READ_QUAD:
1037 case SPINAND_READ_CACHE:
1038 case SPINAND_READ_MACRONIX:
1039 if (snandc->qspi->raw_rw) {
1040 *cmd = (PAGE_ACC | LAST_PAGE | transfer_mode |
1041 SPI_WP | SPI_HOLD | OP_PAGE_READ);
1042 } else {
1043 *cmd = (PAGE_ACC | LAST_PAGE | transfer_mode |
1044 SPI_WP | SPI_HOLD | OP_PAGE_READ_WITH_ECC);
1045 }
1046
1047 break;
1048 case SPINAND_ERASE:
1049 *cmd = OP_BLOCK_ERASE | PAGE_ACC | LAST_PAGE | SPI_WP |
1050 SPI_HOLD | SPI_TRANSFER_MODE_x1;
1051 break;
1052 case SPINAND_WRITE_EN:
1053 *cmd = SPINAND_WRITE_EN;
1054 break;
1055 case SPINAND_PROGRAM_EXECUTE:
1056 *cmd = (PAGE_ACC | LAST_PAGE | transfer_mode |
1057 SPI_WP | SPI_HOLD | OP_PROGRAM_PAGE);
1058 break;
1059 case SPINAND_PROGRAM_LOAD:
1060 *cmd = SPINAND_PROGRAM_LOAD;
1061 break;
1062 case SPINAND_PROGRAM_LOAD_QUAD:
1063 *cmd = SPINAND_PROGRAM_LOAD_QUAD;
1064 break;
1065 default:
1066 dev_err(snandc->dev, "Opcode not supported: %u\n", opcode);
1067 return -EOPNOTSUPP;
1068 }
1069
1070 return 0;
1071}
1072
1073static int qcom_spi_read_page(struct qcom_nand_controller *snandc,
1074 const struct spi_mem_op *op)
1075{
1076 int ret;
1077 u32 cmd;
1078
1079 /* Update the cached command for the cache-read opcode and bus width. */
1080 ret = qcom_spi_cmd_mapping(snandc, op, &cmd);
1081 if (ret < 0)
1082 return ret;
1083
1084 snandc->qspi->cmd = cpu_to_le32(cmd);
1085
1086 if (snandc->qspi->page_rw && snandc->qspi->raw_rw)
1087 return qcom_spi_read_page_raw(snandc, op);
1088
1089 if (snandc->qspi->page_rw)
1090 return qcom_spi_read_page_ecc(snandc, op);
1091
1092 if (snandc->qspi->oob_rw && snandc->qspi->raw_rw)
1093 return qcom_spi_read_last_cw(snandc, op);
1094
1095 if (snandc->qspi->oob_rw)
1096 return qcom_spi_read_page_oob(snandc, op);
1097
1098 return 0;
1099}
1100
1101static void qcom_spi_config_page_write(struct qcom_nand_controller *snandc)
1102{
1103 qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0);
1104 qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0);
1105}
1106
1107static void qcom_spi_config_cw_write(struct qcom_nand_controller *snandc)
1108{
1109 qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
1110 qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
1111 qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
1112
1113 qcom_write_reg_dma(snandc, &snandc->regs->clrflashstatus, NAND_FLASH_STATUS, 1, 0);
1114 qcom_write_reg_dma(snandc, &snandc->regs->clrreadstatus, NAND_READ_STATUS, 1,
1115 NAND_BAM_NEXT_SGL);
1116}
1117
1118static int qcom_spi_program_raw(struct qcom_nand_controller *snandc,
1119 const struct spi_mem_op *op)
1120{
1121 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
1122 struct mtd_info *mtd = snandc->qspi->mtd;
1123 u8 *data_buf = NULL, *oob_buf = NULL;
1124 int i, ret;
1125 int num_cw = snandc->qspi->num_cw;
1126 u32 cfg0, cfg1, ecc_bch_cfg;
1127
1128 cfg0 = (ecc_cfg->cfg0_raw & ~CW_PER_PAGE_MASK) |
1129 FIELD_PREP(CW_PER_PAGE_MASK, num_cw - 1);
1130 cfg1 = ecc_cfg->cfg1_raw;
1131 ecc_bch_cfg = ECC_CFG_ECC_DISABLE;
1132
1133 data_buf = snandc->qspi->data_buf;
1134
1135 oob_buf = snandc->qspi->oob_buf;
1136 memset(oob_buf, 0xff, OOB_BUF_SIZE);
1137
1138 snandc->buf_count = 0;
1139 snandc->buf_start = 0;
1140 qcom_clear_read_regs(snandc);
1141 qcom_clear_bam_transaction(snandc);
1142
1143 snandc->regs->addr0 = snandc->qspi->addr1;
1144 snandc->regs->addr1 = snandc->qspi->addr2;
1145 snandc->regs->cmd = snandc->qspi->cmd;
1146 snandc->regs->cfg0 = cpu_to_le32(cfg0);
1147 snandc->regs->cfg1 = cpu_to_le32(cfg1);
1148 snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
1149 snandc->regs->exec = cpu_to_le32(1);
1150
1151 qcom_spi_config_page_write(snandc);
1152
1153 for (i = 0; i < num_cw; i++) {
1154 int data_size1, data_size2, oob_size1, oob_size2;
1155 int reg_off = FLASH_BUF_ACC;
1156
1157 data_size1 = mtd->writesize - ecc_cfg->cw_size * (num_cw - 1);
1158 oob_size1 = ecc_cfg->bbm_size;
1159
1160 if (i == (num_cw - 1)) {
1161 data_size2 = NANDC_STEP_SIZE - data_size1 -
1162 ((num_cw - 1) << 2);
1163 oob_size2 = (num_cw << 2) + ecc_cfg->ecc_bytes_hw +
1164 ecc_cfg->spare_bytes;
1165 } else {
1166 data_size2 = ecc_cfg->cw_data - data_size1;
1167 oob_size2 = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes;
1168 }
1169
1170 qcom_write_data_dma(snandc, reg_off, data_buf, data_size1,
1171 NAND_BAM_NO_EOT);
1172 reg_off += data_size1;
1173 data_buf += data_size1;
1174
1175 qcom_write_data_dma(snandc, reg_off, oob_buf, oob_size1,
1176 NAND_BAM_NO_EOT);
1177 oob_buf += oob_size1;
1178 reg_off += oob_size1;
1179
1180 qcom_write_data_dma(snandc, reg_off, data_buf, data_size2,
1181 NAND_BAM_NO_EOT);
1182 reg_off += data_size2;
1183 data_buf += data_size2;
1184
1185 qcom_write_data_dma(snandc, reg_off, oob_buf, oob_size2, 0);
1186 oob_buf += oob_size2;
1187
1188 qcom_spi_config_cw_write(snandc);
1189 }
1190
1191 ret = qcom_submit_descs(snandc);
1192 if (ret) {
1193 dev_err(snandc->dev, "failure to write raw page\n");
1194 return ret;
1195 }
1196
1197 return 0;
1198}
1199
1200static int qcom_spi_program_ecc(struct qcom_nand_controller *snandc,
1201 const struct spi_mem_op *op)
1202{
1203 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
1204 u8 *data_buf = NULL, *oob_buf = NULL;
1205 int i, ret;
1206 int num_cw = snandc->qspi->num_cw;
1207 u32 cfg0, cfg1, ecc_bch_cfg, ecc_buf_cfg;
1208
1209 cfg0 = (ecc_cfg->cfg0 & ~CW_PER_PAGE_MASK) |
1210 FIELD_PREP(CW_PER_PAGE_MASK, num_cw - 1);
1211 cfg1 = ecc_cfg->cfg1;
1212 ecc_bch_cfg = ecc_cfg->ecc_bch_cfg;
1213 ecc_buf_cfg = ecc_cfg->ecc_buf_cfg;
1214
1215 if (snandc->qspi->data_buf)
1216 data_buf = snandc->qspi->data_buf;
1217
1218 oob_buf = snandc->qspi->oob_buf;
1219
1220 snandc->buf_count = 0;
1221 snandc->buf_start = 0;
1222 qcom_clear_read_regs(snandc);
1223 qcom_clear_bam_transaction(snandc);
1224
1225 snandc->regs->addr0 = snandc->qspi->addr1;
1226 snandc->regs->addr1 = snandc->qspi->addr2;
1227 snandc->regs->cmd = snandc->qspi->cmd;
1228 snandc->regs->cfg0 = cpu_to_le32(cfg0);
1229 snandc->regs->cfg1 = cpu_to_le32(cfg1);
1230 snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
1231 snandc->regs->ecc_buf_cfg = cpu_to_le32(ecc_buf_cfg);
1232 snandc->regs->exec = cpu_to_le32(1);
1233
1234 qcom_spi_config_page_write(snandc);
1235
1236 for (i = 0; i < num_cw; i++) {
1237 int data_size, oob_size;
1238
1239 if (i == (num_cw - 1)) {
1240 data_size = NANDC_STEP_SIZE - ((num_cw - 1) << 2);
1241 oob_size = (num_cw << 2) + ecc_cfg->ecc_bytes_hw +
1242 ecc_cfg->spare_bytes;
1243 } else {
1244 data_size = ecc_cfg->cw_data;
1245 oob_size = ecc_cfg->bytes;
1246 }
1247
1248 if (data_buf)
1249 qcom_write_data_dma(snandc, FLASH_BUF_ACC, data_buf, data_size,
1250 i == (num_cw - 1) ? NAND_BAM_NO_EOT : 0);
1251
1252 if (i == (num_cw - 1)) {
1253 if (oob_buf) {
1254 oob_buf += ecc_cfg->bbm_size;
1255 qcom_write_data_dma(snandc, FLASH_BUF_ACC + data_size,
1256 oob_buf, oob_size, 0);
1257 }
1258 }
1259
1260 qcom_spi_config_cw_write(snandc);
1261
1262 if (data_buf)
1263 data_buf += data_size;
1264 if (oob_buf)
1265 oob_buf += oob_size;
1266 }
1267
1268 ret = qcom_submit_descs(snandc);
1269 if (ret) {
1270 dev_err(snandc->dev, "failure to write page\n");
1271 return ret;
1272 }
1273
1274 return 0;
1275}
1276
1277static int qcom_spi_program_oob(struct qcom_nand_controller *snandc,
1278 const struct spi_mem_op *op)
1279{
1280 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
1281 u8 *oob_buf = NULL;
1282 int ret, col, data_size, oob_size;
1283 int num_cw = snandc->qspi->num_cw;
1284 u32 cfg0, cfg1, ecc_bch_cfg, ecc_buf_cfg;
1285
1286 cfg0 = (ecc_cfg->cfg0 & ~CW_PER_PAGE_MASK) |
1287 FIELD_PREP(CW_PER_PAGE_MASK, 0);
1288 cfg1 = ecc_cfg->cfg1;
1289 ecc_bch_cfg = ecc_cfg->ecc_bch_cfg;
1290 ecc_buf_cfg = ecc_cfg->ecc_buf_cfg;
1291
1292 col = ecc_cfg->cw_size * (num_cw - 1);
1293
1294 oob_buf = snandc->qspi->data_buf;
1295
1296 snandc->buf_count = 0;
1297 snandc->buf_start = 0;
1298 qcom_clear_read_regs(snandc);
1299 qcom_clear_bam_transaction(snandc);
1300 snandc->regs->addr0 = (snandc->qspi->addr1 | cpu_to_le32(col));
1301 snandc->regs->addr1 = snandc->qspi->addr2;
1302 snandc->regs->cmd = snandc->qspi->cmd;
1303 snandc->regs->cfg0 = cpu_to_le32(cfg0);
1304 snandc->regs->cfg1 = cpu_to_le32(cfg1);
1305 snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
1306 snandc->regs->ecc_buf_cfg = cpu_to_le32(ecc_buf_cfg);
1307 snandc->regs->exec = cpu_to_le32(1);
1308
1309 /* calculate the data and oob size for the last codeword/step */
1310 data_size = NANDC_STEP_SIZE - ((num_cw - 1) << 2);
1311 oob_size = snandc->qspi->mtd->oobavail;
1312
1313 memset(snandc->data_buffer, 0xff, ecc_cfg->cw_data);
1314 /* override new oob content to last codeword */
1315 mtd_ooblayout_get_databytes(snandc->qspi->mtd, snandc->data_buffer + data_size,
1316 oob_buf, 0, snandc->qspi->mtd->oobavail);
1317 qcom_spi_config_page_write(snandc);
1318 qcom_write_data_dma(snandc, FLASH_BUF_ACC, snandc->data_buffer, data_size + oob_size, 0);
1319 qcom_spi_config_cw_write(snandc);
1320
1321 ret = qcom_submit_descs(snandc);
1322 if (ret) {
1323 dev_err(snandc->dev, "failure to write oob\n");
1324 return ret;
1325 }
1326
1327 return 0;
1328}
1329
1330static int qcom_spi_program_execute(struct qcom_nand_controller *snandc,
1331 const struct spi_mem_op *op)
1332{
1333 if (snandc->qspi->page_rw && snandc->qspi->raw_rw)
1334 return qcom_spi_program_raw(snandc, op);
1335
1336 if (snandc->qspi->page_rw)
1337 return qcom_spi_program_ecc(snandc, op);
1338
1339 if (snandc->qspi->oob_rw)
1340 return qcom_spi_program_oob(snandc, op);
1341
1342 return 0;
1343}
1344
1345static int qcom_spi_write_page(struct qcom_nand_controller *snandc,
1346 const struct spi_mem_op *op)
1347{
1348 int ret;
1349 u32 cmd;
1350
1351 ret = qcom_spi_cmd_mapping(snandc, op, &cmd);
1352 if (ret < 0)
1353 return ret;
1354
1355 if (op->cmd.opcode == SPINAND_PROGRAM_LOAD ||
1356 op->cmd.opcode == SPINAND_PROGRAM_LOAD_QUAD)
1357 snandc->qspi->data_buf = (u8 *)op->data.buf.out;
1358
1359 return 0;
1360}
1361
1362static int qcom_spi_send_cmdaddr(struct qcom_nand_controller *snandc,
1363 const struct spi_mem_op *op)
1364{
1365 u32 cmd;
1366 int ret, opcode;
1367
1368 ret = qcom_spi_cmd_mapping(snandc, op, &cmd);
1369 if (ret < 0)
1370 return ret;
1371
1372 opcode = op->cmd.opcode;
1373
1374 switch (opcode) {
1375 case SPINAND_WRITE_EN:
1376 return 0;
1377 case SPINAND_PROGRAM_EXECUTE:
1378 snandc->qspi->addr1 = cpu_to_le32(op->addr.val << 16);
1379 snandc->qspi->addr2 = cpu_to_le32(op->addr.val >> 16 & 0xff);
1380 snandc->qspi->cmd = cpu_to_le32(cmd);
1381 return qcom_spi_program_execute(snandc, op);
1382 case SPINAND_READ:
1383 snandc->qspi->addr1 = cpu_to_le32(op->addr.val << 16);
1384 snandc->qspi->addr2 = cpu_to_le32(op->addr.val >> 16 & 0xff);
1385 snandc->qspi->cmd = cpu_to_le32(cmd);
1386 return 0;
1387 case SPINAND_ERASE:
1388 snandc->qspi->addr1 = cpu_to_le32(op->addr.val << 16);
1389 snandc->qspi->addr2 = cpu_to_le32(op->addr.val >> 16 & 0xffff);
1390 snandc->qspi->cmd = cpu_to_le32(cmd);
1391 return qcom_spi_block_erase(snandc);
1392 default:
1393 break;
1394 }
1395
1396 snandc->buf_count = 0;
1397 snandc->buf_start = 0;
1398 qcom_clear_read_regs(snandc);
1399 qcom_clear_bam_transaction(snandc);
1400
1401 snandc->regs->cmd = cpu_to_le32(cmd);
1402 snandc->regs->exec = cpu_to_le32(1);
1403 snandc->regs->addr0 = cpu_to_le32(op->addr.val);
1404 snandc->regs->addr1 = cpu_to_le32(0);
1405
1406 /*
1407 * The feature value has to reach NAND_FLASH_FEATURES before the
1408 * command is executed, otherwise the controller programs the chip
1409 * with whatever the register happened to hold from a previous
1410 * operation.
1411 */
1412 if (opcode == SPINAND_SET_FEATURE) {
1413 u32 ftr = 0;
1414
1415 memcpy(&ftr, op->data.buf.out,
1416 min_t(size_t, op->data.nbytes, sizeof(ftr)));
1417 snandc->regs->flash_feature = cpu_to_le32(ftr);
1418 qcom_write_reg_dma(snandc, &snandc->regs->flash_feature,
1419 NAND_FLASH_FEATURES, 1, NAND_BAM_NEXT_SGL);
1420 }
1421
1422 qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 3, NAND_BAM_NEXT_SGL);
1423 qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
1424
1425 ret = qcom_submit_descs(snandc);
1426 if (ret)
1427 dev_err(snandc->dev, "failure in submitting cmd descriptor\n");
1428
1429 return ret;
1430}
1431
1432static int qcom_spi_io_op(struct qcom_nand_controller *snandc, const struct spi_mem_op *op)
1433{
1434 int ret, val, opcode;
1435 bool copy = false, copy_ftr = false;
1436
1437 ret = qcom_spi_send_cmdaddr(snandc, op);
1438 if (ret)
1439 return ret;
1440
1441 snandc->buf_count = 0;
1442 snandc->buf_start = 0;
1443 qcom_clear_read_regs(snandc);
1444 qcom_clear_bam_transaction(snandc);
1445 opcode = op->cmd.opcode;
1446
1447 switch (opcode) {
1448 case SPINAND_READID:
1449 snandc->buf_count = 4;
1450 qcom_read_reg_dma(snandc, NAND_READ_ID, 1, NAND_BAM_NEXT_SGL);
1451 copy = true;
1452 break;
1453 case SPINAND_GET_FEATURE:
1454 snandc->buf_count = 4;
1455 qcom_read_reg_dma(snandc, NAND_FLASH_FEATURES, 1, NAND_BAM_NEXT_SGL);
1456 copy_ftr = true;
1457 break;
1458 case SPINAND_SET_FEATURE:
1459 /* fully handled by qcom_spi_send_cmdaddr() */
1460 return 0;
1461 case SPINAND_PROGRAM_EXECUTE:
1462 case SPINAND_WRITE_EN:
1463 case SPINAND_RESET:
1464 case SPINAND_ERASE:
1465 case SPINAND_READ:
1466 return 0;
1467 default:
1468 return -EOPNOTSUPP;
1469 }
1470
1471 ret = qcom_submit_descs(snandc);
1472 if (ret) {
1473 dev_err(snandc->dev, "failure in submitting descriptor for:%d\n", opcode);
1474 return ret;
1475 }
1476
1477 if (copy) {
1478 qcom_nandc_dev_to_mem(snandc, true);
1479 memcpy(op->data.buf.in, snandc->reg_read_buf, snandc->buf_count);
1480 }
1481
1482 if (copy_ftr) {
1483 qcom_nandc_dev_to_mem(snandc, true);
1484 val = le32_to_cpu(*(__le32 *)snandc->reg_read_buf);
1485 val >>= 8;
1486 memcpy(op->data.buf.in, &val, snandc->buf_count);
1487
1488 /*
1489 * Track QUAD mode state from configuration register.
1490 * When core layer reads register 0xB0 (CFG), check if
1491 * QUAD enable bit (bit 0) is set and update our state
1492 * accordingly for future READ/WRITE operations.
1493 */
1494 if (op->addr.val == SPINAND_FEATURE_ADDR) {
1495 bool quad_enabled = !!((u8)val & BIT(0));
1496
1497 if (snandc->qspi->quad_mode != quad_enabled) {
1498 snandc->qspi->quad_mode = quad_enabled;
1499 dev_info(snandc->dev, "SPI NAND QUAD mode: %s\n",
1500 quad_enabled ? "enabled" : "disabled");
1501 }
1502 }
1503 }
1504
1505 return 0;
1506}
1507
1508static bool qcom_spi_is_page_op(const struct spi_mem_op *op)
1509{
1510 if (op->addr.buswidth != 1 && op->addr.buswidth != 2 && op->addr.buswidth != 4)
1511 return false;
1512
1513 if (op->data.dir == SPI_MEM_DATA_IN) {
1514 if (op->addr.buswidth == 4 && op->data.buswidth == 4)
1515 return true;
1516
1517 if (op->addr.nbytes == 2 && op->addr.buswidth == 1)
1518 return true;
1519
1520 } else if (op->data.dir == SPI_MEM_DATA_OUT) {
1521 if (op->data.buswidth == 4)
1522 return true;
1523 if (op->addr.nbytes == 2 && op->addr.buswidth == 1)
1524 return true;
1525 }
1526
1527 return false;
1528}
1529
1530static bool qcom_spi_supports_op(struct spi_mem *mem, const struct spi_mem_op *op)
1531{
1532 if (!spi_mem_default_supports_op(mem, op))
1533 return false;
1534
1535 if (op->cmd.nbytes != 1 || op->cmd.buswidth != 1)
1536 return false;
1537
1538 if (qcom_spi_is_page_op(op))
1539 return true;
1540
1541 return ((!op->addr.nbytes || op->addr.buswidth == 1) &&
1542 (!op->dummy.nbytes || op->dummy.buswidth == 1) &&
1543 (!op->data.nbytes || op->data.buswidth == 1 ||
1544 op->data.buswidth == 4));
1545}
1546
1547static int qcom_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
1548{
1549 struct qcom_nand_controller *snandc = spi_controller_get_devdata(mem->spi->controller);
1550
1551 dev_dbg(snandc->dev, "OP %02x ADDR %08llX@%d:%u DATA %d:%u", op->cmd.opcode,
1552 op->addr.val, op->addr.buswidth, op->addr.nbytes,
1553 op->data.buswidth, op->data.nbytes);
1554
1555 if (qcom_spi_is_page_op(op)) {
1556 if (op->data.dir == SPI_MEM_DATA_IN)
1557 return qcom_spi_read_page(snandc, op);
1558 if (op->data.dir == SPI_MEM_DATA_OUT)
1559 return qcom_spi_write_page(snandc, op);
1560 } else {
1561 return qcom_spi_io_op(snandc, op);
1562 }
1563
1564 return 0;
1565}
1566
1567static const struct spi_controller_mem_ops qcom_spi_mem_ops = {
1568 .supports_op = qcom_spi_supports_op,
1569 .exec_op = qcom_spi_exec_op,
1570};
1571
1572static const struct spi_controller_mem_caps qcom_spi_mem_caps = {
1573 .ecc = true,
1574};
1575
1576static int qcom_spi_probe(struct platform_device *pdev)
1577{
1578 struct device *dev = &pdev->dev;
1579 struct spi_controller *ctlr;
1580 struct qcom_nand_controller *snandc;
1581 struct qpic_spi_nand *qspi;
1582 struct qpic_ecc *ecc;
1583 struct resource *res;
1584 const void *dev_data;
1585 int ret;
1586
1587 ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL);
1588 if (!ecc)
1589 return -ENOMEM;
1590
1591 qspi = devm_kzalloc(dev, sizeof(*qspi), GFP_KERNEL);
1592 if (!qspi)
1593 return -ENOMEM;
1594
1595 /* Initialize QUAD mode state */
1596 qspi->quad_mode = false;
1597
1598 ctlr = __devm_spi_alloc_controller(dev, sizeof(*snandc), false);
1599 if (!ctlr)
1600 return -ENOMEM;
1601
1602 platform_set_drvdata(pdev, ctlr);
1603
1604 snandc = spi_controller_get_devdata(ctlr);
1605 qspi->snandc = snandc;
1606
1607 snandc->dev = dev;
1608 snandc->qspi = qspi;
1609 snandc->qspi->ctlr = ctlr;
1610 snandc->qspi->ecc = ecc;
1611
1612 dev_data = of_device_get_match_data(dev);
1613 if (!dev_data) {
1614 dev_err(&pdev->dev, "failed to get device data\n");
1615 return -ENODEV;
1616 }
1617
1618 snandc->props = dev_data;
1619
1620 snandc->core_clk = devm_clk_get_enabled(dev, "core");
1621 if (IS_ERR(snandc->core_clk))
1622 return PTR_ERR(snandc->core_clk);
1623
1624 snandc->aon_clk = devm_clk_get_enabled(dev, "aon");
1625 if (IS_ERR(snandc->aon_clk))
1626 return PTR_ERR(snandc->aon_clk);
1627
1628 snandc->qspi->iomacro_clk = devm_clk_get_enabled(dev, "iom");
1629 if (IS_ERR(snandc->qspi->iomacro_clk))
1630 return PTR_ERR(snandc->qspi->iomacro_clk);
1631
1632 snandc->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1633 if (IS_ERR(snandc->base))
1634 return PTR_ERR(snandc->base);
1635
1636 snandc->base_phys = res->start;
1637 snandc->base_dma = dma_map_resource(dev, res->start, resource_size(res),
1638 DMA_BIDIRECTIONAL, 0);
1639 if (dma_mapping_error(dev, snandc->base_dma))
1640 return -ENXIO;
1641
1642 ret = qcom_nandc_alloc(snandc);
1643 if (ret)
1644 goto err_snand_alloc;
1645
1646 ret = qcom_spi_init(snandc);
1647 if (ret)
1648 goto err_spi_init;
1649
1650 /* setup ECC engine */
1651 snandc->qspi->ecc_eng.dev = &pdev->dev;
1652 snandc->qspi->ecc_eng.integration = NAND_ECC_ENGINE_INTEGRATION_PIPELINED;
1653 snandc->qspi->ecc_eng.ops = &qcom_spi_ecc_engine_ops_pipelined;
1654 snandc->qspi->ecc_eng.priv = snandc;
1655
1656 ret = nand_ecc_register_on_host_hw_engine(&snandc->qspi->ecc_eng);
1657 if (ret) {
1658 dev_err(&pdev->dev, "failed to register ecc engine:%d\n", ret);
1659 goto err_spi_init;
1660 }
1661
1662 ctlr->num_chipselect = QPIC_QSPI_NUM_CS;
1663 ctlr->mem_ops = &qcom_spi_mem_ops;
1664 ctlr->mem_caps = &qcom_spi_mem_caps;
1665 ctlr->mode_bits = SPI_TX_DUAL | SPI_RX_DUAL |
1666 SPI_TX_QUAD | SPI_RX_QUAD;
1667
1668 ret = spi_register_controller(ctlr);
1669 if (ret) {
1670 dev_err(&pdev->dev, "spi_register_controller failed.\n");
1671 goto err_register_controller;
1672 }
1673
1674 return 0;
1675
1676err_register_controller:
1677 nand_ecc_unregister_on_host_hw_engine(&snandc->qspi->ecc_eng);
1678err_spi_init:
1679 qcom_nandc_unalloc(snandc);
1680err_snand_alloc:
1681 dma_unmap_resource(dev, res->start, resource_size(res),
1682 DMA_BIDIRECTIONAL, 0);
1683 return ret;
1684}
1685
1686static void qcom_spi_remove(struct platform_device *pdev)
1687{
1688 struct spi_controller *ctlr = platform_get_drvdata(pdev);
1689 struct qcom_nand_controller *snandc = spi_controller_get_devdata(ctlr);
1690 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1691
1692 spi_unregister_controller(ctlr);
1693 nand_ecc_unregister_on_host_hw_engine(&snandc->qspi->ecc_eng);
1694 qcom_nandc_unalloc(snandc);
1695 dma_unmap_resource(&pdev->dev, snandc->base_dma, resource_size(res),
1696 DMA_BIDIRECTIONAL, 0);
1697}
1698
1699static const struct qcom_nandc_props ipq9574_snandc_props = {
1700 .dev_cmd_reg_start = 0x7000,
1701 .bam_offset = 0x30000,
1702 .supports_bam = true,
1703};
1704
1705static const struct of_device_id qcom_snandc_of_match[] = {
1706 {
1707 .compatible = "qcom,ipq9574-snand",
1708 .data = &ipq9574_snandc_props,
1709 },
1710 {}
1711};
1712MODULE_DEVICE_TABLE(of, qcom_snandc_of_match);
1713
1714static struct platform_driver qcom_spi_driver = {
1715 .driver = {
1716 .name = "qcom_snand",
1717 .of_match_table = qcom_snandc_of_match,
1718 },
1719 .probe = qcom_spi_probe,
1720 .remove = qcom_spi_remove,
1721};
1722module_platform_driver(qcom_spi_driver);
1723
1724MODULE_DESCRIPTION("SPI driver for QPIC QSPI cores");
1725MODULE_AUTHOR("Md Sadre Alam <[email protected]>");
1726MODULE_LICENSE("GPL");