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1// SPDX-License-Identifier: GPL-2.0
2// spi-uniphier.c - Socionext UniPhier SPI controller driver
3// Copyright 2012 Panasonic Corporation
4// Copyright 2016-2018 Socionext Inc.
5
6#include <linux/kernel.h>
7#include <linux/bitfield.h>
8#include <linux/bitops.h>
9#include <linux/clk.h>
10#include <linux/delay.h>
11#include <linux/dmaengine.h>
12#include <linux/interrupt.h>
13#include <linux/io.h>
14#include <linux/module.h>
15#include <linux/platform_device.h>
16#include <linux/spi/spi.h>
17
18#include <linux/unaligned.h>
19
20#define SSI_TIMEOUT_MS 2000
21#define SSI_POLL_TIMEOUT_US 200
22#define SSI_MAX_CLK_DIVIDER 254
23#define SSI_MIN_CLK_DIVIDER 4
24
25struct uniphier_spi_priv {
26 void __iomem *base;
27 dma_addr_t base_dma_addr;
28 struct clk *clk;
29 struct spi_controller *host;
30 struct completion xfer_done;
31
32 int error;
33 unsigned int tx_bytes;
34 unsigned int rx_bytes;
35 const u8 *tx_buf;
36 u8 *rx_buf;
37 atomic_t dma_busy;
38
39 bool is_save_param;
40 u8 bits_per_word;
41 u16 mode;
42 u32 speed_hz;
43};
44
45#define SSI_CTL 0x00
46#define SSI_CTL_EN BIT(0)
47
48#define SSI_CKS 0x04
49#define SSI_CKS_CKRAT_MASK GENMASK(7, 0)
50#define SSI_CKS_CKPHS BIT(14)
51#define SSI_CKS_CKINIT BIT(13)
52#define SSI_CKS_CKDLY BIT(12)
53
54#define SSI_TXWDS 0x08
55#define SSI_TXWDS_WDLEN_MASK GENMASK(13, 8)
56#define SSI_TXWDS_TDTF_MASK GENMASK(7, 6)
57#define SSI_TXWDS_DTLEN_MASK GENMASK(5, 0)
58
59#define SSI_RXWDS 0x0c
60#define SSI_RXWDS_DTLEN_MASK GENMASK(5, 0)
61
62#define SSI_FPS 0x10
63#define SSI_FPS_FSPOL BIT(15)
64#define SSI_FPS_FSTRT BIT(14)
65
66#define SSI_SR 0x14
67#define SSI_SR_BUSY BIT(7)
68#define SSI_SR_RNE BIT(0)
69
70#define SSI_IE 0x18
71#define SSI_IE_TCIE BIT(4)
72#define SSI_IE_RCIE BIT(3)
73#define SSI_IE_TXRE BIT(2)
74#define SSI_IE_RXRE BIT(1)
75#define SSI_IE_RORIE BIT(0)
76#define SSI_IE_ALL_MASK GENMASK(4, 0)
77
78#define SSI_IS 0x1c
79#define SSI_IS_RXRS BIT(9)
80#define SSI_IS_RCID BIT(3)
81#define SSI_IS_RORID BIT(0)
82
83#define SSI_IC 0x1c
84#define SSI_IC_TCIC BIT(4)
85#define SSI_IC_RCIC BIT(3)
86#define SSI_IC_RORIC BIT(0)
87
88#define SSI_FC 0x20
89#define SSI_FC_TXFFL BIT(12)
90#define SSI_FC_TXFTH_MASK GENMASK(11, 8)
91#define SSI_FC_RXFFL BIT(4)
92#define SSI_FC_RXFTH_MASK GENMASK(3, 0)
93
94#define SSI_TXDR 0x24
95#define SSI_RXDR 0x24
96
97#define SSI_FIFO_DEPTH 8U
98#define SSI_FIFO_BURST_NUM 1
99
100#define SSI_DMA_RX_BUSY BIT(1)
101#define SSI_DMA_TX_BUSY BIT(0)
102
103static inline unsigned int bytes_per_word(unsigned int bits)
104{
105 return bits <= 8 ? 1 : (bits <= 16 ? 2 : 4);
106}
107
108static inline void uniphier_spi_irq_enable(struct uniphier_spi_priv *priv,
109 u32 mask)
110{
111 u32 val;
112
113 val = readl(priv->base + SSI_IE);
114 val |= mask;
115 writel(val, priv->base + SSI_IE);
116}
117
118static inline void uniphier_spi_irq_disable(struct uniphier_spi_priv *priv,
119 u32 mask)
120{
121 u32 val;
122
123 val = readl(priv->base + SSI_IE);
124 val &= ~mask;
125 writel(val, priv->base + SSI_IE);
126}
127
128static void uniphier_spi_set_mode(struct spi_device *spi)
129{
130 struct uniphier_spi_priv *priv = spi_controller_get_devdata(spi->controller);
131 u32 val1, val2;
132
133 /*
134 * clock setting
135 * CKPHS capture timing. 0:rising edge, 1:falling edge
136 * CKINIT clock initial level. 0:low, 1:high
137 * CKDLY clock delay. 0:no delay, 1:delay depending on FSTRT
138 * (FSTRT=0: 1 clock, FSTRT=1: 0.5 clock)
139 *
140 * frame setting
141 * FSPOL frame signal porarity. 0: low, 1: high
142 * FSTRT start frame timing
143 * 0: rising edge of clock, 1: falling edge of clock
144 */
145 switch (spi->mode & SPI_MODE_X_MASK) {
146 case SPI_MODE_0:
147 /* CKPHS=1, CKINIT=0, CKDLY=1, FSTRT=0 */
148 val1 = SSI_CKS_CKPHS | SSI_CKS_CKDLY;
149 val2 = 0;
150 break;
151 case SPI_MODE_1:
152 /* CKPHS=0, CKINIT=0, CKDLY=0, FSTRT=1 */
153 val1 = 0;
154 val2 = SSI_FPS_FSTRT;
155 break;
156 case SPI_MODE_2:
157 /* CKPHS=0, CKINIT=1, CKDLY=1, FSTRT=1 */
158 val1 = SSI_CKS_CKINIT | SSI_CKS_CKDLY;
159 val2 = SSI_FPS_FSTRT;
160 break;
161 case SPI_MODE_3:
162 /* CKPHS=1, CKINIT=1, CKDLY=0, FSTRT=0 */
163 val1 = SSI_CKS_CKPHS | SSI_CKS_CKINIT;
164 val2 = 0;
165 break;
166 }
167
168 if (!(spi->mode & SPI_CS_HIGH))
169 val2 |= SSI_FPS_FSPOL;
170
171 writel(val1, priv->base + SSI_CKS);
172 writel(val2, priv->base + SSI_FPS);
173
174 val1 = 0;
175 if (spi->mode & SPI_LSB_FIRST)
176 val1 |= FIELD_PREP(SSI_TXWDS_TDTF_MASK, 1);
177 writel(val1, priv->base + SSI_TXWDS);
178 writel(val1, priv->base + SSI_RXWDS);
179}
180
181static void uniphier_spi_set_transfer_size(struct spi_device *spi, int size)
182{
183 struct uniphier_spi_priv *priv = spi_controller_get_devdata(spi->controller);
184 u32 val;
185
186 val = readl(priv->base + SSI_TXWDS);
187 FIELD_MODIFY(SSI_TXWDS_WDLEN_MASK, &val, size);
188 FIELD_MODIFY(SSI_TXWDS_DTLEN_MASK, &val, size);
189 writel(val, priv->base + SSI_TXWDS);
190
191 val = readl(priv->base + SSI_RXWDS);
192 FIELD_MODIFY(SSI_RXWDS_DTLEN_MASK, &val, size);
193 writel(val, priv->base + SSI_RXWDS);
194}
195
196static void uniphier_spi_set_baudrate(struct spi_device *spi,
197 unsigned int speed)
198{
199 struct uniphier_spi_priv *priv = spi_controller_get_devdata(spi->controller);
200 u32 val, ckdiv;
201
202 /*
203 * the supported rates are even numbers from 4 to 254. (4,6,8...254)
204 * round up as we look for equal or less speed
205 */
206 ckdiv = DIV_ROUND_UP(clk_get_rate(priv->clk), speed);
207 ckdiv = round_up(ckdiv, 2);
208
209 val = readl(priv->base + SSI_CKS);
210 val &= ~SSI_CKS_CKRAT_MASK;
211 val |= ckdiv & SSI_CKS_CKRAT_MASK;
212 writel(val, priv->base + SSI_CKS);
213}
214
215static void uniphier_spi_setup_transfer(struct spi_device *spi,
216 struct spi_transfer *t)
217{
218 struct uniphier_spi_priv *priv = spi_controller_get_devdata(spi->controller);
219 u32 val;
220
221 priv->error = 0;
222 priv->tx_buf = t->tx_buf;
223 priv->rx_buf = t->rx_buf;
224 priv->tx_bytes = priv->rx_bytes = t->len;
225
226 if (!priv->is_save_param || priv->mode != spi->mode) {
227 uniphier_spi_set_mode(spi);
228 priv->mode = spi->mode;
229 priv->is_save_param = false;
230 }
231
232 if (!priv->is_save_param || priv->bits_per_word != t->bits_per_word) {
233 uniphier_spi_set_transfer_size(spi, t->bits_per_word);
234 priv->bits_per_word = t->bits_per_word;
235 }
236
237 if (!priv->is_save_param || priv->speed_hz != t->speed_hz) {
238 uniphier_spi_set_baudrate(spi, t->speed_hz);
239 priv->speed_hz = t->speed_hz;
240 }
241
242 priv->is_save_param = true;
243
244 /* reset FIFOs */
245 val = SSI_FC_TXFFL | SSI_FC_RXFFL;
246 writel(val, priv->base + SSI_FC);
247}
248
249static void uniphier_spi_send(struct uniphier_spi_priv *priv)
250{
251 int wsize;
252 u32 val = 0;
253
254 wsize = min(bytes_per_word(priv->bits_per_word), priv->tx_bytes);
255 priv->tx_bytes -= wsize;
256
257 if (priv->tx_buf) {
258 switch (wsize) {
259 case 1:
260 val = *priv->tx_buf;
261 break;
262 case 2:
263 val = get_unaligned_le16(priv->tx_buf);
264 break;
265 case 4:
266 val = get_unaligned_le32(priv->tx_buf);
267 break;
268 }
269
270 priv->tx_buf += wsize;
271 }
272
273 writel(val, priv->base + SSI_TXDR);
274}
275
276static void uniphier_spi_recv(struct uniphier_spi_priv *priv)
277{
278 int rsize;
279 u32 val;
280
281 rsize = min(bytes_per_word(priv->bits_per_word), priv->rx_bytes);
282 priv->rx_bytes -= rsize;
283
284 val = readl(priv->base + SSI_RXDR);
285
286 if (priv->rx_buf) {
287 switch (rsize) {
288 case 1:
289 *priv->rx_buf = val;
290 break;
291 case 2:
292 put_unaligned_le16(val, priv->rx_buf);
293 break;
294 case 4:
295 put_unaligned_le32(val, priv->rx_buf);
296 break;
297 }
298
299 priv->rx_buf += rsize;
300 }
301}
302
303static void uniphier_spi_set_fifo_threshold(struct uniphier_spi_priv *priv,
304 unsigned int threshold)
305{
306 u32 val;
307
308 val = readl(priv->base + SSI_FC);
309 FIELD_MODIFY(SSI_FC_TXFTH_MASK, &val, SSI_FIFO_DEPTH - threshold);
310 FIELD_MODIFY(SSI_FC_RXFTH_MASK, &val, threshold);
311 writel(val, priv->base + SSI_FC);
312}
313
314static void uniphier_spi_fill_tx_fifo(struct uniphier_spi_priv *priv)
315{
316 unsigned int fifo_threshold, fill_words;
317 unsigned int bpw = bytes_per_word(priv->bits_per_word);
318
319 fifo_threshold = DIV_ROUND_UP(priv->rx_bytes, bpw);
320 fifo_threshold = min(fifo_threshold, SSI_FIFO_DEPTH);
321
322 uniphier_spi_set_fifo_threshold(priv, fifo_threshold);
323
324 fill_words = fifo_threshold -
325 DIV_ROUND_UP(priv->rx_bytes - priv->tx_bytes, bpw);
326
327 while (fill_words--)
328 uniphier_spi_send(priv);
329}
330
331static void uniphier_spi_set_cs(struct spi_device *spi, bool enable)
332{
333 struct uniphier_spi_priv *priv = spi_controller_get_devdata(spi->controller);
334 u32 val;
335
336 val = readl(priv->base + SSI_FPS);
337
338 if (enable)
339 val |= SSI_FPS_FSPOL;
340 else
341 val &= ~SSI_FPS_FSPOL;
342
343 writel(val, priv->base + SSI_FPS);
344}
345
346static bool uniphier_spi_can_dma(struct spi_controller *host,
347 struct spi_device *spi,
348 struct spi_transfer *t)
349{
350 struct uniphier_spi_priv *priv = spi_controller_get_devdata(host);
351 unsigned int bpw = bytes_per_word(priv->bits_per_word);
352
353 if ((!host->dma_tx && !host->dma_rx)
354 || (!host->dma_tx && t->tx_buf)
355 || (!host->dma_rx && t->rx_buf))
356 return false;
357
358 return DIV_ROUND_UP(t->len, bpw) > SSI_FIFO_DEPTH;
359}
360
361static void uniphier_spi_dma_rxcb(void *data)
362{
363 struct spi_controller *host = data;
364 struct uniphier_spi_priv *priv = spi_controller_get_devdata(host);
365 int state = atomic_fetch_andnot(SSI_DMA_RX_BUSY, &priv->dma_busy);
366
367 uniphier_spi_irq_disable(priv, SSI_IE_RXRE);
368
369 if (!(state & SSI_DMA_TX_BUSY))
370 spi_finalize_current_transfer(host);
371}
372
373static void uniphier_spi_dma_txcb(void *data)
374{
375 struct spi_controller *host = data;
376 struct uniphier_spi_priv *priv = spi_controller_get_devdata(host);
377 int state = atomic_fetch_andnot(SSI_DMA_TX_BUSY, &priv->dma_busy);
378
379 uniphier_spi_irq_disable(priv, SSI_IE_TXRE);
380
381 if (!(state & SSI_DMA_RX_BUSY))
382 spi_finalize_current_transfer(host);
383}
384
385static int uniphier_spi_transfer_one_dma(struct spi_controller *host,
386 struct spi_device *spi,
387 struct spi_transfer *t)
388{
389 struct uniphier_spi_priv *priv = spi_controller_get_devdata(host);
390 struct dma_async_tx_descriptor *rxdesc = NULL, *txdesc = NULL;
391 int buswidth;
392
393 atomic_set(&priv->dma_busy, 0);
394
395 uniphier_spi_set_fifo_threshold(priv, SSI_FIFO_BURST_NUM);
396
397 if (priv->bits_per_word <= 8)
398 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
399 else if (priv->bits_per_word <= 16)
400 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
401 else
402 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
403
404 if (priv->rx_buf) {
405 struct dma_slave_config rxconf = {
406 .direction = DMA_DEV_TO_MEM,
407 .src_addr = priv->base_dma_addr + SSI_RXDR,
408 .src_addr_width = buswidth,
409 .src_maxburst = SSI_FIFO_BURST_NUM,
410 };
411
412 dmaengine_slave_config(host->dma_rx, &rxconf);
413
414 rxdesc = dmaengine_prep_slave_sg(
415 host->dma_rx,
416 t->rx_sg.sgl, t->rx_sg.nents,
417 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
418 if (!rxdesc)
419 goto out_err_prep;
420
421 rxdesc->callback = uniphier_spi_dma_rxcb;
422 rxdesc->callback_param = host;
423
424 uniphier_spi_irq_enable(priv, SSI_IE_RXRE);
425 atomic_or(SSI_DMA_RX_BUSY, &priv->dma_busy);
426
427 dmaengine_submit(rxdesc);
428 dma_async_issue_pending(host->dma_rx);
429 }
430
431 if (priv->tx_buf) {
432 struct dma_slave_config txconf = {
433 .direction = DMA_MEM_TO_DEV,
434 .dst_addr = priv->base_dma_addr + SSI_TXDR,
435 .dst_addr_width = buswidth,
436 .dst_maxburst = SSI_FIFO_BURST_NUM,
437 };
438
439 dmaengine_slave_config(host->dma_tx, &txconf);
440
441 txdesc = dmaengine_prep_slave_sg(
442 host->dma_tx,
443 t->tx_sg.sgl, t->tx_sg.nents,
444 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
445 if (!txdesc)
446 goto out_err_prep;
447
448 txdesc->callback = uniphier_spi_dma_txcb;
449 txdesc->callback_param = host;
450
451 uniphier_spi_irq_enable(priv, SSI_IE_TXRE);
452 atomic_or(SSI_DMA_TX_BUSY, &priv->dma_busy);
453
454 dmaengine_submit(txdesc);
455 dma_async_issue_pending(host->dma_tx);
456 }
457
458 /* signal that we need to wait for completion */
459 return (priv->tx_buf || priv->rx_buf);
460
461out_err_prep:
462 if (rxdesc)
463 dmaengine_terminate_sync(host->dma_rx);
464
465 return -EINVAL;
466}
467
468static int uniphier_spi_transfer_one_irq(struct spi_controller *host,
469 struct spi_device *spi,
470 struct spi_transfer *t)
471{
472 struct uniphier_spi_priv *priv = spi_controller_get_devdata(host);
473 struct device *dev = host->dev.parent;
474 unsigned long time_left;
475
476 reinit_completion(&priv->xfer_done);
477
478 uniphier_spi_fill_tx_fifo(priv);
479
480 uniphier_spi_irq_enable(priv, SSI_IE_RCIE | SSI_IE_RORIE);
481
482 time_left = wait_for_completion_timeout(&priv->xfer_done,
483 msecs_to_jiffies(SSI_TIMEOUT_MS));
484
485 uniphier_spi_irq_disable(priv, SSI_IE_RCIE | SSI_IE_RORIE);
486
487 if (!time_left) {
488 dev_err(dev, "transfer timeout.\n");
489 return -ETIMEDOUT;
490 }
491
492 return priv->error;
493}
494
495static int uniphier_spi_transfer_one_poll(struct spi_controller *host,
496 struct spi_device *spi,
497 struct spi_transfer *t)
498{
499 struct uniphier_spi_priv *priv = spi_controller_get_devdata(host);
500 int loop = SSI_POLL_TIMEOUT_US * 10;
501
502 while (priv->tx_bytes) {
503 uniphier_spi_fill_tx_fifo(priv);
504
505 while ((priv->rx_bytes - priv->tx_bytes) > 0) {
506 while (!(readl(priv->base + SSI_SR) & SSI_SR_RNE)
507 && loop--)
508 ndelay(100);
509
510 if (loop == -1)
511 goto irq_transfer;
512
513 uniphier_spi_recv(priv);
514 }
515 }
516
517 return 0;
518
519irq_transfer:
520 return uniphier_spi_transfer_one_irq(host, spi, t);
521}
522
523static int uniphier_spi_transfer_one(struct spi_controller *host,
524 struct spi_device *spi,
525 struct spi_transfer *t)
526{
527 struct uniphier_spi_priv *priv = spi_controller_get_devdata(host);
528 unsigned long threshold;
529 bool use_dma;
530
531 /* Terminate and return success for 0 byte length transfer */
532 if (!t->len)
533 return 0;
534
535 uniphier_spi_setup_transfer(spi, t);
536
537 use_dma = host->can_dma ? host->can_dma(host, spi, t) : false;
538 if (use_dma)
539 return uniphier_spi_transfer_one_dma(host, spi, t);
540
541 /*
542 * If the transfer operation will take longer than
543 * SSI_POLL_TIMEOUT_US, it should use irq.
544 */
545 threshold = DIV_ROUND_UP(SSI_POLL_TIMEOUT_US * priv->speed_hz,
546 USEC_PER_SEC * BITS_PER_BYTE);
547 if (t->len > threshold)
548 return uniphier_spi_transfer_one_irq(host, spi, t);
549 else
550 return uniphier_spi_transfer_one_poll(host, spi, t);
551}
552
553static int uniphier_spi_prepare_transfer_hardware(struct spi_controller *host)
554{
555 struct uniphier_spi_priv *priv = spi_controller_get_devdata(host);
556
557 writel(SSI_CTL_EN, priv->base + SSI_CTL);
558
559 return 0;
560}
561
562static int uniphier_spi_unprepare_transfer_hardware(struct spi_controller *host)
563{
564 struct uniphier_spi_priv *priv = spi_controller_get_devdata(host);
565
566 writel(0, priv->base + SSI_CTL);
567
568 return 0;
569}
570
571static void uniphier_spi_handle_err(struct spi_controller *host,
572 struct spi_message *msg)
573{
574 struct uniphier_spi_priv *priv = spi_controller_get_devdata(host);
575 u32 val;
576
577 /* stop running spi transfer */
578 writel(0, priv->base + SSI_CTL);
579
580 /* reset FIFOs */
581 val = SSI_FC_TXFFL | SSI_FC_RXFFL;
582 writel(val, priv->base + SSI_FC);
583
584 uniphier_spi_irq_disable(priv, SSI_IE_ALL_MASK);
585
586 if (atomic_read(&priv->dma_busy) & SSI_DMA_TX_BUSY) {
587 dmaengine_terminate_async(host->dma_tx);
588 atomic_andnot(SSI_DMA_TX_BUSY, &priv->dma_busy);
589 }
590
591 if (atomic_read(&priv->dma_busy) & SSI_DMA_RX_BUSY) {
592 dmaengine_terminate_async(host->dma_rx);
593 atomic_andnot(SSI_DMA_RX_BUSY, &priv->dma_busy);
594 }
595}
596
597static irqreturn_t uniphier_spi_handler(int irq, void *dev_id)
598{
599 struct uniphier_spi_priv *priv = dev_id;
600 u32 val, stat;
601
602 stat = readl(priv->base + SSI_IS);
603 val = SSI_IC_TCIC | SSI_IC_RCIC | SSI_IC_RORIC;
604 writel(val, priv->base + SSI_IC);
605
606 /* rx fifo overrun */
607 if (stat & SSI_IS_RORID) {
608 priv->error = -EIO;
609 goto done;
610 }
611
612 /* rx complete */
613 if ((stat & SSI_IS_RCID) && (stat & SSI_IS_RXRS)) {
614 while ((readl(priv->base + SSI_SR) & SSI_SR_RNE) &&
615 (priv->rx_bytes - priv->tx_bytes) > 0)
616 uniphier_spi_recv(priv);
617
618 if ((readl(priv->base + SSI_SR) & SSI_SR_RNE) ||
619 (priv->rx_bytes != priv->tx_bytes)) {
620 priv->error = -EIO;
621 goto done;
622 } else if (priv->rx_bytes == 0)
623 goto done;
624
625 /* next tx transfer */
626 uniphier_spi_fill_tx_fifo(priv);
627
628 return IRQ_HANDLED;
629 }
630
631 return IRQ_NONE;
632
633done:
634 complete(&priv->xfer_done);
635 return IRQ_HANDLED;
636}
637
638static int uniphier_spi_probe(struct platform_device *pdev)
639{
640 struct uniphier_spi_priv *priv;
641 struct spi_controller *host;
642 struct resource *res;
643 struct dma_slave_caps caps;
644 u32 dma_tx_burst = 0, dma_rx_burst = 0;
645 unsigned long clk_rate;
646 int irq;
647 int ret;
648
649 host = devm_spi_alloc_host(&pdev->dev, sizeof(*priv));
650 if (!host)
651 return -ENOMEM;
652
653 platform_set_drvdata(pdev, host);
654
655 priv = spi_controller_get_devdata(host);
656 priv->host = host;
657 priv->is_save_param = false;
658
659 init_completion(&priv->xfer_done);
660
661 priv->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
662 if (IS_ERR(priv->base))
663 return PTR_ERR(priv->base);
664
665 priv->base_dma_addr = res->start;
666
667 priv->clk = devm_clk_get_enabled(&pdev->dev, NULL);
668 if (IS_ERR(priv->clk)) {
669 dev_err(&pdev->dev, "failed to get clock\n");
670 return PTR_ERR(priv->clk);
671 }
672
673 irq = platform_get_irq(pdev, 0);
674 if (irq < 0)
675 return irq;
676
677 ret = devm_request_irq(&pdev->dev, irq, uniphier_spi_handler,
678 0, "uniphier-spi", priv);
679 if (ret) {
680 dev_err(&pdev->dev, "failed to request IRQ\n");
681 return ret;
682 }
683
684 clk_rate = clk_get_rate(priv->clk);
685
686 host->max_speed_hz = DIV_ROUND_UP(clk_rate, SSI_MIN_CLK_DIVIDER);
687 host->min_speed_hz = DIV_ROUND_UP(clk_rate, SSI_MAX_CLK_DIVIDER);
688 host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
689 host->bus_num = pdev->id;
690 host->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
691
692 host->set_cs = uniphier_spi_set_cs;
693 host->transfer_one = uniphier_spi_transfer_one;
694 host->prepare_transfer_hardware
695 = uniphier_spi_prepare_transfer_hardware;
696 host->unprepare_transfer_hardware
697 = uniphier_spi_unprepare_transfer_hardware;
698 host->handle_err = uniphier_spi_handle_err;
699 host->can_dma = uniphier_spi_can_dma;
700
701 host->num_chipselect = 1;
702 host->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX;
703
704 host->dma_tx = dma_request_chan(&pdev->dev, "tx");
705 if (IS_ERR_OR_NULL(host->dma_tx)) {
706 if (PTR_ERR(host->dma_tx) == -EPROBE_DEFER)
707 return -EPROBE_DEFER;
708
709 host->dma_tx = NULL;
710 dma_tx_burst = INT_MAX;
711 } else {
712 ret = dma_get_slave_caps(host->dma_tx, &caps);
713 if (ret) {
714 dev_err(&pdev->dev, "failed to get TX DMA capacities: %d\n",
715 ret);
716 goto out_release_dma;
717 }
718 dma_tx_burst = caps.max_burst;
719 }
720
721 host->dma_rx = dma_request_chan(&pdev->dev, "rx");
722 if (IS_ERR_OR_NULL(host->dma_rx)) {
723 if (PTR_ERR(host->dma_rx) == -EPROBE_DEFER) {
724 ret = -EPROBE_DEFER;
725 goto out_release_dma;
726 }
727 host->dma_rx = NULL;
728 dma_rx_burst = INT_MAX;
729 } else {
730 ret = dma_get_slave_caps(host->dma_rx, &caps);
731 if (ret) {
732 dev_err(&pdev->dev, "failed to get RX DMA capacities: %d\n",
733 ret);
734 goto out_release_dma;
735 }
736 dma_rx_burst = caps.max_burst;
737 }
738
739 host->max_dma_len = min(dma_tx_burst, dma_rx_burst);
740
741 ret = spi_register_controller(host);
742 if (ret)
743 goto out_release_dma;
744
745 return 0;
746
747out_release_dma:
748 if (!IS_ERR_OR_NULL(host->dma_rx)) {
749 dma_release_channel(host->dma_rx);
750 host->dma_rx = NULL;
751 }
752 if (!IS_ERR_OR_NULL(host->dma_tx)) {
753 dma_release_channel(host->dma_tx);
754 host->dma_tx = NULL;
755 }
756
757 return ret;
758}
759
760static void uniphier_spi_remove(struct platform_device *pdev)
761{
762 struct spi_controller *host = platform_get_drvdata(pdev);
763
764 spi_unregister_controller(host);
765
766 if (host->dma_tx)
767 dma_release_channel(host->dma_tx);
768 if (host->dma_rx)
769 dma_release_channel(host->dma_rx);
770}
771
772static const struct of_device_id uniphier_spi_match[] = {
773 { .compatible = "socionext,uniphier-scssi" },
774 { /* sentinel */ }
775};
776MODULE_DEVICE_TABLE(of, uniphier_spi_match);
777
778static struct platform_driver uniphier_spi_driver = {
779 .probe = uniphier_spi_probe,
780 .remove = uniphier_spi_remove,
781 .driver = {
782 .name = "uniphier-spi",
783 .of_match_table = uniphier_spi_match,
784 },
785};
786module_platform_driver(uniphier_spi_driver);
787
788MODULE_AUTHOR("Kunihiko Hayashi <[email protected]>");
789MODULE_AUTHOR("Keiji Hayashibara <[email protected]>");
790MODULE_DESCRIPTION("Socionext UniPhier SPI controller driver");
791MODULE_LICENSE("GPL v2");