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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * NVEC: NVIDIA compliant embedded controller interface
4 *
5 * Copyright (C) 2011 The AC100 Kernel Team <[email protected]>
6 *
7 * Authors: Pierre-Hugues Husson <[email protected]>
8 * Ilya Petrov <[email protected]>
9 * Marc Dietrich <[email protected]>
10 * Julian Andres Klode <[email protected]>
11 */
12
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/atomic.h>
16#include <linux/clk.h>
17#include <linux/completion.h>
18#include <linux/delay.h>
19#include <linux/err.h>
20#include <linux/gpio/consumer.h>
21#include <linux/interrupt.h>
22#include <linux/io.h>
23#include <linux/irq.h>
24#include <linux/of.h>
25#include <linux/list.h>
26#include <linux/mfd/core.h>
27#include <linux/mutex.h>
28#include <linux/notifier.h>
29#include <linux/slab.h>
30#include <linux/spinlock.h>
31#include <linux/workqueue.h>
32
33#include "nvec.h"
34
35#define I2C_CNFG 0x00
36#define I2C_CNFG_PACKET_MODE_EN BIT(10)
37#define I2C_CNFG_NEW_MASTER_SFM BIT(11)
38#define I2C_CNFG_DEBOUNCE_CNT_SHIFT 12
39
40#define I2C_SL_CNFG 0x20
41#define I2C_SL_NEWSL BIT(2)
42#define I2C_SL_NACK BIT(1)
43#define I2C_SL_RESP BIT(0)
44#define I2C_SL_IRQ BIT(3)
45#define END_TRANS BIT(4)
46#define RCVD BIT(2)
47#define RNW BIT(1)
48
49#define I2C_SL_RCVD 0x24
50#define I2C_SL_STATUS 0x28
51#define I2C_SL_ADDR1 0x2c
52#define I2C_SL_ADDR2 0x30
53#define I2C_SL_DELAY_COUNT 0x3c
54
55/**
56 * enum nvec_msg_category - Message categories for nvec_msg_alloc()
57 * @NVEC_MSG_RX: The message is an incoming message (from EC)
58 * @NVEC_MSG_TX: The message is an outgoing message (to EC)
59 */
60enum nvec_msg_category {
61 NVEC_MSG_RX,
62 NVEC_MSG_TX,
63};
64
65enum nvec_sleep_subcmds {
66 GLOBAL_EVENTS,
67 AP_PWR_DOWN,
68 AP_SUSPEND,
69};
70
71#define CNF_EVENT_REPORTING 0x01
72#define GET_FIRMWARE_VERSION 0x15
73#define LID_SWITCH BIT(1)
74#define PWR_BUTTON BIT(15)
75
76static struct nvec_chip *nvec_power_handle;
77
78static const struct mfd_cell nvec_devices[] = {
79 {
80 .name = "nvec-kbd",
81 },
82 {
83 .name = "nvec-mouse",
84 },
85 {
86 .name = "nvec-power",
87 .id = 0,
88 },
89 {
90 .name = "nvec-power",
91 .id = 1,
92 },
93 {
94 .name = "nvec-paz00",
95 },
96};
97
98/**
99 * nvec_register_notifier - Register a notifier with nvec
100 * @nvec: A &struct nvec_chip
101 * @nb: The notifier block to register
102 * @events: Unused
103 *
104 * Registers a notifier with @nvec. The notifier will be added to an atomic
105 * notifier chain that is called for all received messages except those that
106 * correspond to a request initiated by nvec_write_sync().
107 */
108int nvec_register_notifier(struct nvec_chip *nvec, struct notifier_block *nb,
109 unsigned int events)
110{
111 return atomic_notifier_chain_register(&nvec->notifier_list, nb);
112}
113EXPORT_SYMBOL_GPL(nvec_register_notifier);
114
115/**
116 * nvec_unregister_notifier - Unregister a notifier with nvec
117 * @nvec: A &struct nvec_chip
118 * @nb: The notifier block to unregister
119 *
120 * Unregisters a notifier with @nvec. The notifier will be removed from the
121 * atomic notifier chain.
122 */
123int nvec_unregister_notifier(struct nvec_chip *nvec, struct notifier_block *nb)
124{
125 return atomic_notifier_chain_unregister(&nvec->notifier_list, nb);
126}
127EXPORT_SYMBOL_GPL(nvec_unregister_notifier);
128
129/*
130 * nvec_status_notifier - The final notifier
131 *
132 * Prints a message about control events not handled in the notifier
133 * chain.
134 */
135static int nvec_status_notifier(struct notifier_block *nb,
136 unsigned long event_type, void *data)
137{
138 struct nvec_chip *nvec = container_of(nb, struct nvec_chip,
139 nvec_status_notifier);
140 unsigned char *msg = data;
141
142 if (event_type != NVEC_CNTL)
143 return NOTIFY_DONE;
144
145 dev_warn(nvec->dev, "unhandled msg type %ld\n", event_type);
146 print_hex_dump(KERN_WARNING, "payload: ", DUMP_PREFIX_NONE, 16, 1,
147 msg, msg[1] + 2, true);
148
149 return NOTIFY_OK;
150}
151
152/**
153 * nvec_msg_alloc:
154 * @nvec: A &struct nvec_chip
155 * @category: Pool category, see &enum nvec_msg_category
156 *
157 * Allocate a single &struct nvec_msg object from the message pool of
158 * @nvec. The result shall be passed to nvec_msg_free() if no longer
159 * used.
160 *
161 * Outgoing messages are placed in the upper 75% of the pool, keeping the
162 * lower 25% available for RX buffers only. The reason is to prevent a
163 * situation where all buffers are full and a message is thus endlessly
164 * retried because the response could never be processed.
165 */
166static struct nvec_msg *nvec_msg_alloc(struct nvec_chip *nvec,
167 enum nvec_msg_category category)
168{
169 int i = (category == NVEC_MSG_TX) ? (NVEC_POOL_SIZE / 4) : 0;
170
171 for (; i < NVEC_POOL_SIZE; i++) {
172 if (atomic_xchg(&nvec->msg_pool[i].used, 1) == 0) {
173 dev_vdbg(nvec->dev, "INFO: Allocate %i\n", i);
174 return &nvec->msg_pool[i];
175 }
176 }
177
178 dev_err(nvec->dev, "Could not allocate %s buffer\n",
179 (category == NVEC_MSG_TX) ? "TX" : "RX");
180
181 return NULL;
182}
183
184/**
185 * nvec_msg_free:
186 * @nvec: A &struct nvec_chip
187 * @msg: A message (must be allocated by nvec_msg_alloc() and belong to @nvec)
188 *
189 * Free the given message
190 */
191void nvec_msg_free(struct nvec_chip *nvec, struct nvec_msg *msg)
192{
193 if (msg != &nvec->tx_scratch)
194 dev_vdbg(nvec->dev, "INFO: Free %ti\n", msg - nvec->msg_pool);
195 atomic_set(&msg->used, 0);
196}
197EXPORT_SYMBOL_GPL(nvec_msg_free);
198
199/**
200 * nvec_msg_is_event - Return %true if @msg is an event
201 * @msg: A message
202 */
203static bool nvec_msg_is_event(struct nvec_msg *msg)
204{
205 return msg->data[0] >> 7;
206}
207
208/**
209 * nvec_msg_size - Get the size of a message
210 * @msg: The message to get the size for
211 *
212 * This only works for received messages, not for outgoing messages.
213 */
214static size_t nvec_msg_size(struct nvec_msg *msg)
215{
216 bool is_event = nvec_msg_is_event(msg);
217 int event_length = (msg->data[0] & 0x60) >> 5;
218
219 /* for variable size, payload size in byte 1 + count (1) + cmd (1) */
220 if (!is_event || event_length == NVEC_VAR_SIZE)
221 return (msg->pos || msg->size) ? (msg->data[1] + 2) : 0;
222 else if (event_length == NVEC_2BYTES)
223 return 2;
224 else if (event_length == NVEC_3BYTES)
225 return 3;
226 return 0;
227}
228
229/**
230 * nvec_gpio_set_value - Set the GPIO value
231 * @nvec: A &struct nvec_chip
232 * @value: The value to write (0 or 1)
233 *
234 * Like gpio_set_value(), but generating debugging information
235 */
236static void nvec_gpio_set_value(struct nvec_chip *nvec, int value)
237{
238 dev_dbg(nvec->dev, "GPIO changed from %u to %u\n",
239 gpiod_get_value(nvec->gpiod), value);
240 gpiod_set_value(nvec->gpiod, value);
241}
242
243/**
244 * nvec_write_async - Asynchronously write a message to NVEC
245 * @nvec: An nvec_chip instance
246 * @data: The message data, starting with the request type
247 * @size: The size of @data
248 *
249 * Queue a single message to be transferred to the embedded controller
250 * and return immediately.
251 *
252 * Returns: 0 on success, a negative error code on failure. If a failure
253 * occurred, the nvec driver may print an error.
254 */
255int nvec_write_async(struct nvec_chip *nvec, const unsigned char *data,
256 short size)
257{
258 struct nvec_msg *msg;
259 unsigned long flags;
260
261 msg = nvec_msg_alloc(nvec, NVEC_MSG_TX);
262
263 if (!msg)
264 return -ENOMEM;
265
266 msg->data[0] = size;
267 memcpy(msg->data + 1, data, size);
268 msg->size = size + 1;
269
270 spin_lock_irqsave(&nvec->tx_lock, flags);
271 list_add_tail(&msg->node, &nvec->tx_data);
272 spin_unlock_irqrestore(&nvec->tx_lock, flags);
273
274 schedule_work(&nvec->tx_work);
275
276 return 0;
277}
278EXPORT_SYMBOL(nvec_write_async);
279
280/**
281 * nvec_write_sync - Write a message to nvec and read the response
282 * @nvec: An &struct nvec_chip
283 * @data: The data to write
284 * @size: The size of @data
285 * @msg: The response message received
286 *
287 * This is similar to nvec_write_async(), but waits for the
288 * request to be answered before returning. This function
289 * uses a mutex and can thus not be called from e.g.
290 * interrupt handlers.
291 *
292 * Returns: 0 on success, a negative error code on failure.
293 * The response message is returned in @msg. Shall be freed
294 * with nvec_msg_free() once no longer used.
295 *
296 */
297int nvec_write_sync(struct nvec_chip *nvec,
298 const unsigned char *data, short size,
299 struct nvec_msg **msg)
300{
301 mutex_lock(&nvec->sync_write_mutex);
302
303 if (msg)
304 *msg = NULL;
305
306 nvec->sync_write_pending = (data[1] << 8) + data[0];
307
308 if (nvec_write_async(nvec, data, size) < 0) {
309 mutex_unlock(&nvec->sync_write_mutex);
310 return -ENOMEM;
311 }
312
313 dev_dbg(nvec->dev, "nvec_sync_write: 0x%04x\n",
314 nvec->sync_write_pending);
315 if (!(wait_for_completion_timeout(&nvec->sync_write,
316 msecs_to_jiffies(2000)))) {
317 dev_warn(nvec->dev,
318 "Timeout waiting for sync write to complete\n");
319 mutex_unlock(&nvec->sync_write_mutex);
320 return -ETIMEDOUT;
321 }
322
323 dev_dbg(nvec->dev, "nvec_sync_write: pong!\n");
324
325 if (msg)
326 *msg = nvec->last_sync_msg;
327 else
328 nvec_msg_free(nvec, nvec->last_sync_msg);
329
330 mutex_unlock(&nvec->sync_write_mutex);
331
332 return 0;
333}
334EXPORT_SYMBOL(nvec_write_sync);
335
336/**
337 * nvec_toggle_global_events - enables or disables global event reporting
338 * @nvec: nvec handle
339 * @state: true for enable, false for disable
340 *
341 * This switches on/off global event reports by the embedded controller.
342 */
343static void nvec_toggle_global_events(struct nvec_chip *nvec, bool state)
344{
345 unsigned char global_events[] = { NVEC_SLEEP, GLOBAL_EVENTS, state };
346
347 nvec_write_async(nvec, global_events, 3);
348}
349
350/**
351 * nvec_event_mask - fill the command string with event bitfield
352 * @ev: points to event command string
353 * @mask: bit to insert into the event mask
354 *
355 * Configure event command expects a 32 bit bitfield which describes
356 * which events to enable. The bitfield has the following structure
357 * (from highest byte to lowest):
358 * system state bits 7-0
359 * system state bits 15-8
360 * oem system state bits 7-0
361 * oem system state bits 15-8
362 */
363static void nvec_event_mask(char *ev, u32 mask)
364{
365 ev[3] = mask >> 16 & 0xff;
366 ev[4] = mask >> 24 & 0xff;
367 ev[5] = mask >> 0 & 0xff;
368 ev[6] = mask >> 8 & 0xff;
369}
370
371/**
372 * nvec_request_master - Process outgoing messages
373 * @work: A &struct work_struct (the tx_worker member of &struct nvec_chip)
374 *
375 * Processes all outgoing requests by sending the request and awaiting the
376 * response, then continuing with the next request. Once a request has a
377 * matching response, it will be freed and removed from the list.
378 */
379static void nvec_request_master(struct work_struct *work)
380{
381 struct nvec_chip *nvec = container_of(work, struct nvec_chip, tx_work);
382 unsigned long flags;
383 long err;
384 struct nvec_msg *msg;
385
386 spin_lock_irqsave(&nvec->tx_lock, flags);
387 while (!list_empty(&nvec->tx_data)) {
388 msg = list_first_entry(&nvec->tx_data, struct nvec_msg, node);
389 spin_unlock_irqrestore(&nvec->tx_lock, flags);
390 nvec_gpio_set_value(nvec, 0);
391 err = wait_for_completion_interruptible_timeout(&nvec->ec_transfer,
392 msecs_to_jiffies(5000));
393
394 if (err == 0) {
395 dev_warn(nvec->dev, "Timeout waiting for ec transfer\n");
396 nvec_gpio_set_value(nvec, 1);
397 msg->pos = 0;
398 }
399
400 spin_lock_irqsave(&nvec->tx_lock, flags);
401
402 if (err > 0) {
403 list_del_init(&msg->node);
404 nvec_msg_free(nvec, msg);
405 }
406 }
407 spin_unlock_irqrestore(&nvec->tx_lock, flags);
408}
409
410/**
411 * parse_msg - Print some information and call the notifiers on an RX message
412 * @nvec: A &struct nvec_chip
413 * @msg: A message received by @nvec
414 *
415 * Paarse some pieces of the message and then call the chain of notifiers
416 * registered via nvec_register_notifier.
417 */
418static int parse_msg(struct nvec_chip *nvec, struct nvec_msg *msg)
419{
420 if ((msg->data[0] & 1 << 7) == 0 && msg->data[3]) {
421 dev_err(nvec->dev, "ec responded %*ph\n", 4, msg->data);
422 return -EINVAL;
423 }
424
425 if ((msg->data[0] >> 7) == 1 && (msg->data[0] & 0x0f) == 5)
426 print_hex_dump(KERN_WARNING, "ec system event ",
427 DUMP_PREFIX_NONE, 16, 1, msg->data,
428 msg->data[1] + 2, true);
429
430 atomic_notifier_call_chain(&nvec->notifier_list, msg->data[0] & 0x8f,
431 msg->data);
432
433 return 0;
434}
435
436/**
437 * nvec_dispatch - Process messages received from the EC
438 * @work: A &struct work_struct (the tx_worker member of &struct nvec_chip)
439 *
440 * Process messages previously received from the EC and put into the RX
441 * queue of the &struct nvec_chip instance associated with @work.
442 */
443static void nvec_dispatch(struct work_struct *work)
444{
445 struct nvec_chip *nvec = container_of(work, struct nvec_chip, rx_work);
446 unsigned long flags;
447 struct nvec_msg *msg;
448
449 spin_lock_irqsave(&nvec->rx_lock, flags);
450 while (!list_empty(&nvec->rx_data)) {
451 msg = list_first_entry(&nvec->rx_data, struct nvec_msg, node);
452 list_del_init(&msg->node);
453 spin_unlock_irqrestore(&nvec->rx_lock, flags);
454
455 if (nvec->sync_write_pending ==
456 (msg->data[2] << 8) + msg->data[0]) {
457 dev_dbg(nvec->dev, "Sync write completed!\n");
458 nvec->sync_write_pending = 0;
459 nvec->last_sync_msg = msg;
460 complete(&nvec->sync_write);
461 } else {
462 parse_msg(nvec, msg);
463 nvec_msg_free(nvec, msg);
464 }
465 spin_lock_irqsave(&nvec->rx_lock, flags);
466 }
467 spin_unlock_irqrestore(&nvec->rx_lock, flags);
468}
469
470/**
471 * nvec_tx_completed - Complete the current transfer
472 * @nvec: A &struct nvec_chip
473 *
474 * This is called when we have received an END_TRANS on a TX transfer.
475 */
476static void nvec_tx_completed(struct nvec_chip *nvec)
477{
478 /* We got an END_TRANS, let's skip this, maybe there's an event */
479 if (nvec->tx->pos != nvec->tx->size) {
480 dev_err(nvec->dev, "Premature END_TRANS, resending\n");
481 nvec->tx->pos = 0;
482 nvec_gpio_set_value(nvec, 0);
483 } else {
484 nvec->state = 0;
485 }
486}
487
488/**
489 * nvec_rx_completed - Complete the current transfer
490 * @nvec: A &struct nvec_chip
491 *
492 * This is called when we have received an END_TRANS on a RX transfer.
493 */
494static void nvec_rx_completed(struct nvec_chip *nvec)
495{
496 if (nvec->rx->pos != nvec_msg_size(nvec->rx)) {
497 unsigned char msg_type = nvec->rx->data[0];
498
499 dev_err(nvec->dev, "RX incomplete: Expected %u bytes, got %u\n",
500 (uint)nvec_msg_size(nvec->rx),
501 (uint)nvec->rx->pos);
502
503 nvec_msg_free(nvec, nvec->rx);
504 nvec->state = 0;
505
506 /* Battery quirk - Often incomplete, and likes to crash */
507 if (msg_type == NVEC_BAT)
508 complete(&nvec->ec_transfer);
509
510 return;
511 }
512
513 spin_lock(&nvec->rx_lock);
514
515 /*
516 * Add the received data to the work list and move the ring buffer
517 * pointer to the next entry.
518 */
519 list_add_tail(&nvec->rx->node, &nvec->rx_data);
520
521 spin_unlock(&nvec->rx_lock);
522
523 nvec->state = 0;
524
525 if (!nvec_msg_is_event(nvec->rx))
526 complete(&nvec->ec_transfer);
527
528 schedule_work(&nvec->rx_work);
529}
530
531/**
532 * nvec_invalid_flags - Send an error message about invalid flags and jump
533 * @nvec: The nvec device
534 * @status: The status flags
535 * @reset: Whether we shall jump to state 0.
536 */
537static void nvec_invalid_flags(struct nvec_chip *nvec, unsigned int status,
538 bool reset)
539{
540 dev_err(nvec->dev, "unexpected status flags 0x%02x during state %i\n",
541 status, nvec->state);
542 if (reset)
543 nvec->state = 0;
544}
545
546/**
547 * nvec_tx_set - Set the message to transfer (nvec->tx)
548 * @nvec: A &struct nvec_chip
549 *
550 * Gets the first entry from the tx_data list of @nvec and sets the
551 * tx member to it. If the tx_data list is empty, this uses the
552 * tx_scratch message to send a no operation message.
553 */
554static void nvec_tx_set(struct nvec_chip *nvec)
555{
556 spin_lock(&nvec->tx_lock);
557 if (list_empty(&nvec->tx_data)) {
558 dev_err(nvec->dev, "empty tx - sending no-op\n");
559 memcpy(nvec->tx_scratch.data, "\x02\x07\x02", 3);
560 nvec->tx_scratch.size = 3;
561 nvec->tx_scratch.pos = 0;
562 nvec->tx = &nvec->tx_scratch;
563 list_add_tail(&nvec->tx->node, &nvec->tx_data);
564 } else {
565 nvec->tx = list_first_entry(&nvec->tx_data, struct nvec_msg,
566 node);
567 nvec->tx->pos = 0;
568 }
569 spin_unlock(&nvec->tx_lock);
570
571 dev_dbg(nvec->dev, "Sending message of length %u, command 0x%x\n",
572 (uint)nvec->tx->size, nvec->tx->data[1]);
573}
574
575/**
576 * tegra_i2c_writel - safely write to an I2C client controller register
577 * @val: value to be written
578 * @reg: register to write to
579 *
580 * A write to an I2C controller register needs to be read back to make sure
581 * that the value has arrived.
582 */
583static void tegra_i2c_writel(u32 val, void *reg)
584{
585 writel_relaxed(val, reg);
586
587 /* read back register to make sure that register writes completed */
588 readl_relaxed(reg);
589}
590
591/**
592 * nvec_interrupt - Interrupt handler
593 * @irq: The IRQ
594 * @dev: The nvec device
595 *
596 * Interrupt handler that fills our RX buffers and empties our TX
597 * buffers. This uses a finite state machine with ridiculous amounts
598 * of error checking, in order to be fairly reliable.
599 */
600static irqreturn_t nvec_interrupt(int irq, void *dev)
601{
602 unsigned long status;
603 unsigned int received = 0;
604 unsigned char to_send = 0xff;
605 const unsigned long irq_mask = I2C_SL_IRQ | END_TRANS | RCVD | RNW;
606 struct nvec_chip *nvec = dev;
607 unsigned int state = nvec->state;
608
609 status = readl(nvec->base + I2C_SL_STATUS);
610
611 /* Filter out some errors */
612 if ((status & irq_mask) == 0 && (status & ~irq_mask) != 0) {
613 dev_err(nvec->dev, "Unexpected irq mask %lx\n", status);
614 return IRQ_HANDLED;
615 }
616 if ((status & I2C_SL_IRQ) == 0) {
617 dev_err(nvec->dev, "Spurious IRQ\n");
618 return IRQ_HANDLED;
619 }
620
621 /* The EC did not request a read, so it send us something, read it */
622 if ((status & RNW) == 0) {
623 received = readl(nvec->base + I2C_SL_RCVD);
624 if (status & RCVD)
625 tegra_i2c_writel(0, nvec->base + I2C_SL_RCVD);
626 }
627
628 if (status == (I2C_SL_IRQ | RCVD))
629 nvec->state = 0;
630
631 switch (nvec->state) {
632 case 0: /* Verify that its a transfer start, the rest later */
633 if (status != (I2C_SL_IRQ | RCVD))
634 nvec_invalid_flags(nvec, status, false);
635 break;
636 case 1: /* Command byte */
637 if (status != I2C_SL_IRQ) {
638 nvec_invalid_flags(nvec, status, true);
639 } else {
640 nvec->rx = nvec_msg_alloc(nvec, NVEC_MSG_RX);
641 /* Should not happen in a normal world */
642 if (unlikely(!nvec->rx)) {
643 nvec->state = 0;
644 break;
645 }
646 nvec->rx->data[0] = received;
647 nvec->rx->pos = 1;
648 nvec->state = 2;
649 }
650 break;
651 case 2: /* first byte after command */
652 if (status == (I2C_SL_IRQ | RNW | RCVD)) {
653 if (nvec->rx->data[0] != 0x01) {
654 dev_err(nvec->dev,
655 "Read without prior read command\n");
656 nvec->state = 0;
657 break;
658 }
659 nvec_msg_free(nvec, nvec->rx);
660 nvec->state = 3;
661 nvec_tx_set(nvec);
662 to_send = nvec->tx->data[0];
663 nvec->tx->pos = 1;
664 /*
665 * delay ACK due to AP20 HW Bug
666 * do not replace by usleep_range
667 */
668 udelay(33);
669 } else if (status == (I2C_SL_IRQ)) {
670 nvec->rx->data[1] = received;
671 nvec->rx->pos = 2;
672 nvec->state = 4;
673 } else {
674 nvec_invalid_flags(nvec, status, true);
675 }
676 break;
677 case 3: /* EC does a block read, we transmit data */
678 if (status & END_TRANS) {
679 nvec_tx_completed(nvec);
680 } else if ((status & RNW) == 0 || (status & RCVD)) {
681 nvec_invalid_flags(nvec, status, true);
682 } else if (nvec->tx && nvec->tx->pos < nvec->tx->size) {
683 to_send = nvec->tx->data[nvec->tx->pos++];
684 } else {
685 dev_err(nvec->dev,
686 "tx buffer underflow on %p (%u > %u)\n",
687 nvec->tx,
688 (uint)(nvec->tx ? nvec->tx->pos : 0),
689 (uint)(nvec->tx ? nvec->tx->size : 0));
690 nvec->state = 0;
691 }
692 break;
693 case 4: /* EC does some write, we read the data */
694 if ((status & (END_TRANS | RNW)) == END_TRANS)
695 nvec_rx_completed(nvec);
696 else if (status & (RNW | RCVD))
697 nvec_invalid_flags(nvec, status, true);
698 else if (nvec->rx && nvec->rx->pos < NVEC_MSG_SIZE)
699 nvec->rx->data[nvec->rx->pos++] = received;
700 else
701 dev_err(nvec->dev,
702 "RX buffer overflow on %p: Trying to write byte %u of %u\n",
703 nvec->rx, nvec->rx ? nvec->rx->pos : 0,
704 NVEC_MSG_SIZE);
705 break;
706 default:
707 nvec->state = 0;
708 }
709
710 /* If we are told that a new transfer starts, verify it */
711 if ((status & (RCVD | RNW)) == RCVD) {
712 if (received != nvec->i2c_addr)
713 dev_err(nvec->dev,
714 "received address 0x%02x, expected 0x%02x\n",
715 received, nvec->i2c_addr);
716 nvec->state = 1;
717 }
718
719 /* Send data if requested, but not on end of transmission */
720 if ((status & (RNW | END_TRANS)) == RNW)
721 tegra_i2c_writel(to_send, nvec->base + I2C_SL_RCVD);
722
723 /* If we have send the first byte */
724 if (status == (I2C_SL_IRQ | RNW | RCVD))
725 nvec_gpio_set_value(nvec, 1);
726
727 dev_dbg(nvec->dev,
728 "Handled: %s 0x%02x, %s 0x%02x in state %u [%s%s%s]\n",
729 (status & RNW) == 0 ? "received" : "R=",
730 received,
731 (status & (RNW | END_TRANS)) ? "sent" : "S=",
732 to_send,
733 state,
734 status & END_TRANS ? " END_TRANS" : "",
735 status & RCVD ? " RCVD" : "",
736 status & RNW ? " RNW" : "");
737
738 return IRQ_HANDLED;
739}
740
741static void tegra_init_i2c_slave(struct nvec_chip *nvec)
742{
743 u32 val;
744
745 clk_prepare_enable(nvec->i2c_clk);
746
747 reset_control_assert(nvec->rst);
748 udelay(2);
749 reset_control_deassert(nvec->rst);
750
751 val = I2C_CNFG_NEW_MASTER_SFM | I2C_CNFG_PACKET_MODE_EN |
752 (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT);
753 tegra_i2c_writel(val, nvec->base + I2C_CNFG);
754
755 clk_set_rate(nvec->i2c_clk, 8 * 80000);
756
757 tegra_i2c_writel(I2C_SL_NEWSL, nvec->base + I2C_SL_CNFG);
758 tegra_i2c_writel(0x1E, nvec->base + I2C_SL_DELAY_COUNT);
759
760 tegra_i2c_writel(nvec->i2c_addr >> 1, nvec->base + I2C_SL_ADDR1);
761 tegra_i2c_writel(0, nvec->base + I2C_SL_ADDR2);
762
763 enable_irq(nvec->irq);
764}
765
766#ifdef CONFIG_PM_SLEEP
767static void nvec_disable_i2c_slave(struct nvec_chip *nvec)
768{
769 disable_irq(nvec->irq);
770 tegra_i2c_writel(I2C_SL_NEWSL | I2C_SL_NACK, nvec->base + I2C_SL_CNFG);
771 clk_disable_unprepare(nvec->i2c_clk);
772}
773#endif
774
775static void nvec_power_off(void)
776{
777 char ap_pwr_down[] = { NVEC_SLEEP, AP_PWR_DOWN };
778
779 nvec_toggle_global_events(nvec_power_handle, false);
780 nvec_write_async(nvec_power_handle, ap_pwr_down, 2);
781}
782
783static int tegra_nvec_probe(struct platform_device *pdev)
784{
785 int err, ret;
786 struct clk *i2c_clk;
787 struct device *dev = &pdev->dev;
788 struct nvec_chip *nvec;
789 struct nvec_msg *msg;
790 void __iomem *base;
791 char get_firmware_version[] = { NVEC_CNTL, GET_FIRMWARE_VERSION },
792 unmute_speakers[] = { NVEC_OEM0, 0x10, 0x59, 0x95 },
793 enable_event[7] = { NVEC_SYS, CNF_EVENT_REPORTING, true };
794
795 if (!dev->of_node) {
796 dev_err(dev, "must be instantiated using device tree\n");
797 return -ENODEV;
798 }
799
800 nvec = devm_kzalloc(dev, sizeof(struct nvec_chip), GFP_KERNEL);
801 if (!nvec)
802 return -ENOMEM;
803
804 platform_set_drvdata(pdev, nvec);
805 nvec->dev = dev;
806
807 if (of_property_read_u32(dev->of_node, "slave-addr", &nvec->i2c_addr)) {
808 dev_err(dev, "no i2c address specified");
809 return -ENODEV;
810 }
811
812 base = devm_platform_ioremap_resource(pdev, 0);
813 if (IS_ERR(base))
814 return PTR_ERR(base);
815
816 nvec->irq = platform_get_irq(pdev, 0);
817 if (nvec->irq < 0)
818 return nvec->irq;
819
820 i2c_clk = devm_clk_get(dev, "div-clk");
821 if (IS_ERR(i2c_clk))
822 return dev_err_probe(dev, PTR_ERR(i2c_clk),
823 "failed to get controller clock\n");
824
825 nvec->rst = devm_reset_control_get_exclusive(dev, "i2c");
826 if (IS_ERR(nvec->rst)) {
827 dev_err(dev, "failed to get controller reset\n");
828 return PTR_ERR(nvec->rst);
829 }
830
831 nvec->base = base;
832 nvec->i2c_clk = i2c_clk;
833 nvec->rx = &nvec->msg_pool[0];
834
835 ATOMIC_INIT_NOTIFIER_HEAD(&nvec->notifier_list);
836
837 init_completion(&nvec->sync_write);
838 init_completion(&nvec->ec_transfer);
839 mutex_init(&nvec->sync_write_mutex);
840 spin_lock_init(&nvec->tx_lock);
841 spin_lock_init(&nvec->rx_lock);
842 INIT_LIST_HEAD(&nvec->rx_data);
843 INIT_LIST_HEAD(&nvec->tx_data);
844 INIT_WORK(&nvec->rx_work, nvec_dispatch);
845 INIT_WORK(&nvec->tx_work, nvec_request_master);
846
847 nvec->gpiod = devm_gpiod_get(dev, "request", GPIOD_OUT_HIGH);
848 if (IS_ERR(nvec->gpiod)) {
849 dev_err(dev, "couldn't request gpio\n");
850 return PTR_ERR(nvec->gpiod);
851 }
852
853 err = devm_request_irq(dev, nvec->irq, nvec_interrupt, IRQF_NO_AUTOEN,
854 "nvec", nvec);
855 if (err)
856 return dev_err_probe(dev, err, "couldn't request irq\n");
857
858 tegra_init_i2c_slave(nvec);
859
860 /* enable event reporting */
861 nvec_toggle_global_events(nvec, true);
862
863 nvec->nvec_status_notifier.notifier_call = nvec_status_notifier;
864 nvec_register_notifier(nvec, &nvec->nvec_status_notifier, 0);
865
866 nvec_power_handle = nvec;
867 pm_power_off = nvec_power_off;
868
869 /* Get Firmware Version */
870 err = nvec_write_sync(nvec, get_firmware_version, 2, &msg);
871
872 if (!err) {
873 dev_warn(dev,
874 "ec firmware version %02x.%02x.%02x / %02x\n",
875 msg->data[4], msg->data[5],
876 msg->data[6], msg->data[7]);
877
878 nvec_msg_free(nvec, msg);
879 }
880
881 ret = mfd_add_devices(dev, 0, nvec_devices,
882 ARRAY_SIZE(nvec_devices), NULL, 0, NULL);
883 if (ret)
884 dev_err(dev, "error adding subdevices\n");
885
886 /* unmute speakers? */
887 nvec_write_async(nvec, unmute_speakers, 4);
888
889 /* enable lid switch event */
890 nvec_event_mask(enable_event, LID_SWITCH);
891 nvec_write_async(nvec, enable_event, 7);
892
893 /* enable power button event */
894 nvec_event_mask(enable_event, PWR_BUTTON);
895 nvec_write_async(nvec, enable_event, 7);
896
897 return 0;
898}
899
900static void tegra_nvec_remove(struct platform_device *pdev)
901{
902 struct nvec_chip *nvec = platform_get_drvdata(pdev);
903
904 nvec_toggle_global_events(nvec, false);
905 mfd_remove_devices(nvec->dev);
906 nvec_unregister_notifier(nvec, &nvec->nvec_status_notifier);
907 cancel_work_sync(&nvec->rx_work);
908 cancel_work_sync(&nvec->tx_work);
909 if (pm_power_off == nvec_power_off)
910 pm_power_off = NULL;
911}
912
913#ifdef CONFIG_PM_SLEEP
914static int nvec_suspend(struct device *dev)
915{
916 int err;
917 struct nvec_chip *nvec = dev_get_drvdata(dev);
918 struct nvec_msg *msg;
919 char ap_suspend[] = { NVEC_SLEEP, AP_SUSPEND };
920
921 dev_dbg(nvec->dev, "suspending\n");
922
923 /* keep these sync or you'll break suspend */
924 nvec_toggle_global_events(nvec, false);
925
926 err = nvec_write_sync(nvec, ap_suspend, sizeof(ap_suspend), &msg);
927 if (!err)
928 nvec_msg_free(nvec, msg);
929
930 nvec_disable_i2c_slave(nvec);
931
932 return 0;
933}
934
935static int nvec_resume(struct device *dev)
936{
937 struct nvec_chip *nvec = dev_get_drvdata(dev);
938
939 dev_dbg(nvec->dev, "resuming\n");
940 tegra_init_i2c_slave(nvec);
941 nvec_toggle_global_events(nvec, true);
942
943 return 0;
944}
945#endif
946
947static SIMPLE_DEV_PM_OPS(nvec_pm_ops, nvec_suspend, nvec_resume);
948
949/* Match table for of_platform binding */
950static const struct of_device_id nvidia_nvec_of_match[] = {
951 { .compatible = "nvidia,nvec", },
952 {},
953};
954MODULE_DEVICE_TABLE(of, nvidia_nvec_of_match);
955
956static struct platform_driver nvec_device_driver = {
957 .probe = tegra_nvec_probe,
958 .remove = tegra_nvec_remove,
959 .driver = {
960 .name = "nvec",
961 .pm = &nvec_pm_ops,
962 .of_match_table = nvidia_nvec_of_match,
963 }
964};
965
966module_platform_driver(nvec_device_driver);
967
968MODULE_ALIAS("platform:nvec");
969MODULE_DESCRIPTION("NVIDIA compliant embedded controller interface");
970MODULE_AUTHOR("Marc Dietrich <[email protected]>");
971MODULE_LICENSE("GPL");