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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Thunderbolt driver - PCI NHI driver
4 *
5 * Copyright (c) 2014 Andreas Noever <[email protected]>
6 * Copyright (C) 2018, Intel Corporation
7 */
8
9#include <linux/pm_runtime.h>
10#include <linux/slab.h>
11#include <linux/errno.h>
12#include <linux/pci.h>
13#include <linux/dma-mapping.h>
14#include <linux/interrupt.h>
15#include <linux/iommu.h>
16#include <linux/module.h>
17#include <linux/delay.h>
18#include <linux/property.h>
19#include <linux/string_helpers.h>
20#include <linux/suspend.h>
21
22#include "nhi.h"
23#include "nhi_regs.h"
24#include "tb.h"
25
26/**
27 * struct tb_nhi_pci - NHI device connected over PCIe
28 * @nhi: NHI device
29 * @msix_ida: Used to allocate MSI-X vectors for rings
30 */
31struct tb_nhi_pci {
32 struct tb_nhi nhi;
33 struct ida msix_ida;
34};
35
36static inline struct tb_nhi_pci *nhi_to_pci(struct tb_nhi *nhi)
37{
38 return container_of(nhi, struct tb_nhi_pci, nhi);
39}
40
41static void nhi_pci_check_quirks(struct tb_nhi_pci *nhi_pci)
42{
43 struct tb_nhi *nhi = &nhi_pci->nhi;
44 struct pci_dev *pdev = to_pci_dev(nhi->dev);
45
46 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
47 /*
48 * Intel hardware supports auto clear of the interrupt
49 * status register right after interrupt is being
50 * issued.
51 */
52 nhi->quirks |= QUIRK_AUTO_CLEAR_INT;
53
54 switch (pdev->device) {
55 case PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI:
56 case PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI:
57 /*
58 * Falcon Ridge controller needs the end-to-end
59 * flow control workaround to avoid losing Rx
60 * packets when RING_FLAG_E2E is set.
61 */
62 nhi->quirks |= QUIRK_E2E;
63 break;
64 }
65 }
66}
67
68static int nhi_pci_check_iommu_pdev(struct pci_dev *pdev, void *data)
69{
70 if (!pdev->external_facing ||
71 !device_iommu_capable(&pdev->dev, IOMMU_CAP_PRE_BOOT_PROTECTION))
72 return 0;
73 *(bool *)data = true;
74 return 1; /* Stop walking */
75}
76
77static void nhi_pci_check_iommu(struct tb_nhi_pci *nhi_pci)
78{
79 struct tb_nhi *nhi = &nhi_pci->nhi;
80 struct pci_dev *pdev = to_pci_dev(nhi->dev);
81 struct pci_bus *bus = pdev->bus;
82 bool port_ok = false;
83
84 /*
85 * Ideally what we'd do here is grab every PCI device that
86 * represents a tunnelling adapter for this NHI and check their
87 * status directly, but unfortunately USB4 seems to make it
88 * obnoxiously difficult to reliably make any correlation.
89 *
90 * So for now we'll have to bodge it... Hoping that the system
91 * is at least sane enough that an adapter is in the same PCI
92 * segment as its NHI, if we can find *something* on that segment
93 * which meets the requirements for Kernel DMA Protection, we'll
94 * take that to imply that firmware is aware and has (hopefully)
95 * done the right thing in general. We need to know that the PCI
96 * layer has seen the ExternalFacingPort property which will then
97 * inform the IOMMU layer to enforce the complete "untrusted DMA"
98 * flow, but also that the IOMMU driver itself can be trusted not
99 * to have been subverted by a pre-boot DMA attack.
100 */
101 while (bus->parent)
102 bus = bus->parent;
103
104 pci_walk_bus(bus, nhi_pci_check_iommu_pdev, &port_ok);
105
106 nhi->iommu_dma_protection = port_ok;
107 dev_dbg(nhi->dev, "IOMMU DMA protection is %s\n",
108 str_enabled_disabled(port_ok));
109}
110
111static int nhi_pci_init_msi(struct tb_nhi *nhi)
112{
113 struct tb_nhi_pci *nhi_pci = nhi_to_pci(nhi);
114 struct pci_dev *pdev = to_pci_dev(nhi->dev);
115 int res, irq, nvec;
116
117 ida_init(&nhi_pci->msix_ida);
118
119 /*
120 * The NHI has 16 MSI-X vectors or a single MSI. We first try to
121 * get all MSI-X vectors and if we succeed, each ring will have
122 * one MSI-X. If for some reason that does not work out, we
123 * fallback to a single MSI.
124 */
125 nvec = pci_alloc_irq_vectors(pdev, MSIX_MIN_VECS, MSIX_MAX_VECS,
126 PCI_IRQ_MSIX);
127 if (nvec < 0) {
128 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
129 if (nvec < 0)
130 return nvec;
131
132 INIT_WORK(&nhi->interrupt_work, nhi_interrupt_work);
133
134 irq = pci_irq_vector(pdev, 0);
135 if (irq < 0)
136 return irq;
137
138 res = devm_request_irq(&pdev->dev, irq, nhi_msi,
139 IRQF_NO_SUSPEND, "thunderbolt", nhi);
140 if (res)
141 return res;
142 }
143
144 return 0;
145}
146
147static bool nhi_pci_imr_valid(struct pci_dev *pdev)
148{
149 u8 val;
150
151 if (!device_property_read_u8(&pdev->dev, "IMR_VALID", &val))
152 return !!val;
153
154 return true;
155}
156
157static void nhi_pci_start_dma_port(struct tb_nhi *nhi)
158{
159 struct pci_dev *pdev = to_pci_dev(nhi->dev);
160 struct pci_dev *root_port;
161
162 /*
163 * During host router NVM upgrade we should not allow root port to
164 * go into D3cold because some root ports cannot trigger PME
165 * itself. To be on the safe side keep the root port in D0 during
166 * the whole upgrade process.
167 */
168 root_port = pcie_find_root_port(pdev);
169 if (root_port)
170 pm_runtime_get_noresume(&root_port->dev);
171}
172
173static void nhi_pci_complete_dma_port(struct tb_nhi *nhi)
174{
175 struct pci_dev *pdev = to_pci_dev(nhi->dev);
176 struct pci_dev *root_port;
177
178 root_port = pcie_find_root_port(pdev);
179 if (root_port)
180 pm_runtime_put(&root_port->dev);
181}
182
183static int nhi_pci_ring_request_msix(struct tb_ring *ring, bool no_suspend)
184{
185 struct tb_nhi *nhi = ring->nhi;
186 struct tb_nhi_pci *nhi_pci = nhi_to_pci(nhi);
187 struct pci_dev *pdev = to_pci_dev(nhi->dev);
188 unsigned long irqflags;
189 int ret;
190
191 if (!pdev->msix_enabled)
192 return 0;
193
194 ret = ida_alloc_max(&nhi_pci->msix_ida, MSIX_MAX_VECS - 1, GFP_KERNEL);
195 if (ret < 0)
196 return ret;
197
198 ring->vector = ret;
199
200 ret = pci_irq_vector(pdev, ring->vector);
201 if (ret < 0)
202 goto err_ida_remove;
203
204 ring->irq = ret;
205
206 irqflags = no_suspend ? IRQF_NO_SUSPEND : 0;
207 ret = request_irq(ring->irq, ring_msix, irqflags, "thunderbolt", ring);
208 if (ret)
209 goto err_ida_remove;
210
211 return 0;
212
213err_ida_remove:
214 ida_free(&nhi_pci->msix_ida, ring->vector);
215
216 return ret;
217}
218
219static void nhi_pci_ring_release_msix(struct tb_ring *ring)
220{
221 struct tb_nhi_pci *nhi_pci = nhi_to_pci(ring->nhi);
222
223 if (ring->irq <= 0)
224 return;
225
226 free_irq(ring->irq, ring);
227 ida_free(&nhi_pci->msix_ida, ring->vector);
228 ring->vector = 0;
229 ring->irq = 0;
230}
231
232static void nhi_pci_release_irq(struct tb_nhi *nhi)
233{
234 struct tb_nhi_pci *nhi_pci = nhi_to_pci(nhi);
235 struct pci_dev *pdev = to_pci_dev(nhi->dev);
236
237 /*
238 * We have to release the irq before calling flush_work. Otherwise an
239 * already executing IRQ handler could call schedule_work again.
240 */
241 if (!pdev->msix_enabled) {
242 devm_free_irq(nhi->dev, pdev->irq, nhi);
243 flush_work(&nhi->interrupt_work);
244 }
245 ida_destroy(&nhi_pci->msix_ida);
246}
247
248static bool nhi_pci_is_present(struct tb_nhi *nhi)
249{
250 return pci_device_is_present(to_pci_dev(nhi->dev));
251}
252
253static const struct tb_nhi_ops pci_nhi_default_ops = {
254 .pre_nvm_auth = nhi_pci_start_dma_port,
255 .post_nvm_auth = nhi_pci_complete_dma_port,
256 .request_ring_irq = nhi_pci_ring_request_msix,
257 .release_ring_irq = nhi_pci_ring_release_msix,
258 .shutdown = nhi_pci_release_irq,
259 .is_present = nhi_pci_is_present,
260 .init_interrupts = nhi_pci_init_msi,
261};
262
263/* Ice Lake specific NHI operations */
264
265#define ICL_LC_MAILBOX_TIMEOUT 500 /* ms */
266
267static int check_for_device(struct device *dev, void *data)
268{
269 return tb_is_switch(dev);
270}
271
272static bool icl_nhi_is_device_connected(struct tb_nhi *nhi)
273{
274 struct tb *tb = dev_get_drvdata(nhi->dev);
275 int ret;
276
277 ret = device_for_each_child(&tb->root_switch->dev, NULL,
278 check_for_device);
279 return ret > 0;
280}
281
282static int icl_nhi_force_power(struct tb_nhi *nhi, bool power)
283{
284 struct pci_dev *pdev = to_pci_dev(nhi->dev);
285 u32 vs_cap;
286
287 /*
288 * The Thunderbolt host controller is present always in Ice Lake
289 * but the firmware may not be loaded and running (depending
290 * whether there is device connected and so on). Each time the
291 * controller is used we need to "Force Power" it first and wait
292 * for the firmware to indicate it is up and running. This "Force
293 * Power" is really not about actually powering on/off the
294 * controller so it is accessible even if "Force Power" is off.
295 *
296 * The actual power management happens inside shared ACPI power
297 * resources using standard ACPI methods.
298 */
299 pci_read_config_dword(pdev, VS_CAP_22, &vs_cap);
300 if (power) {
301 vs_cap &= ~VS_CAP_22_DMA_DELAY_MASK;
302 vs_cap |= 0x22 << VS_CAP_22_DMA_DELAY_SHIFT;
303 vs_cap |= VS_CAP_22_FORCE_POWER;
304 } else {
305 vs_cap &= ~VS_CAP_22_FORCE_POWER;
306 }
307 pci_write_config_dword(pdev, VS_CAP_22, vs_cap);
308
309 if (power) {
310 unsigned int retries = 350;
311 u32 val;
312
313 /* Wait until the firmware tells it is up and running */
314 do {
315 pci_read_config_dword(pdev, VS_CAP_9, &val);
316 if (val & VS_CAP_9_FW_READY)
317 return 0;
318 usleep_range(3000, 3100);
319 } while (--retries);
320
321 return -ETIMEDOUT;
322 }
323
324 return 0;
325}
326
327static void icl_nhi_lc_mailbox_cmd(struct tb_nhi *nhi, enum icl_lc_mailbox_cmd cmd)
328{
329 struct pci_dev *pdev = to_pci_dev(nhi->dev);
330 u32 data;
331
332 data = (cmd << VS_CAP_19_CMD_SHIFT) & VS_CAP_19_CMD_MASK;
333 pci_write_config_dword(pdev, VS_CAP_19, data | VS_CAP_19_VALID);
334}
335
336static int icl_nhi_lc_mailbox_cmd_complete(struct tb_nhi *nhi, int timeout)
337{
338 struct pci_dev *pdev = to_pci_dev(nhi->dev);
339 unsigned long end;
340 u32 data;
341
342 if (!timeout)
343 goto clear;
344
345 end = jiffies + msecs_to_jiffies(timeout);
346 do {
347 pci_read_config_dword(pdev, VS_CAP_18, &data);
348 if (data & VS_CAP_18_DONE)
349 goto clear;
350 usleep_range(1000, 1100);
351 } while (time_before(jiffies, end));
352
353 return -ETIMEDOUT;
354
355clear:
356 /* Clear the valid bit */
357 pci_write_config_dword(pdev, VS_CAP_19, 0);
358 return 0;
359}
360
361static void icl_nhi_set_ltr(struct tb_nhi *nhi)
362{
363 struct pci_dev *pdev = to_pci_dev(nhi->dev);
364 u32 max_ltr, ltr;
365
366 pci_read_config_dword(pdev, VS_CAP_16, &max_ltr);
367 max_ltr &= 0xffff;
368 /* Program the same value for both snoop and no-snoop */
369 ltr = max_ltr << 16 | max_ltr;
370 pci_write_config_dword(pdev, VS_CAP_15, ltr);
371}
372
373static int icl_nhi_suspend(struct tb_nhi *nhi)
374{
375 struct tb *tb = dev_get_drvdata(nhi->dev);
376 int ret;
377
378 if (icl_nhi_is_device_connected(nhi))
379 return 0;
380
381 if (tb_switch_is_icm(tb->root_switch)) {
382 /*
383 * If there is no device connected we need to perform
384 * both: a handshake through LC mailbox and force power
385 * down before entering D3.
386 */
387 icl_nhi_lc_mailbox_cmd(nhi, ICL_LC_PREPARE_FOR_RESET);
388 ret = icl_nhi_lc_mailbox_cmd_complete(nhi, ICL_LC_MAILBOX_TIMEOUT);
389 if (ret)
390 return ret;
391 }
392
393 return icl_nhi_force_power(nhi, false);
394}
395
396static int icl_nhi_suspend_noirq(struct tb_nhi *nhi, bool wakeup)
397{
398 struct tb *tb = dev_get_drvdata(nhi->dev);
399 enum icl_lc_mailbox_cmd cmd;
400
401 if (!pm_suspend_via_firmware())
402 return icl_nhi_suspend(nhi);
403
404 if (!tb_switch_is_icm(tb->root_switch))
405 return 0;
406
407 cmd = wakeup ? ICL_LC_GO2SX : ICL_LC_GO2SX_NO_WAKE;
408 icl_nhi_lc_mailbox_cmd(nhi, cmd);
409 return icl_nhi_lc_mailbox_cmd_complete(nhi, ICL_LC_MAILBOX_TIMEOUT);
410}
411
412static int icl_nhi_resume(struct tb_nhi *nhi)
413{
414 int ret;
415
416 ret = icl_nhi_force_power(nhi, true);
417 if (ret)
418 return ret;
419
420 icl_nhi_set_ltr(nhi);
421 return 0;
422}
423
424static void icl_nhi_shutdown(struct tb_nhi *nhi)
425{
426 nhi_pci_release_irq(nhi);
427
428 icl_nhi_force_power(nhi, false);
429}
430
431static const struct tb_nhi_ops icl_nhi_ops = {
432 .init = icl_nhi_resume,
433 .suspend_noirq = icl_nhi_suspend_noirq,
434 .resume_noirq = icl_nhi_resume,
435 .runtime_suspend = icl_nhi_suspend,
436 .runtime_resume = icl_nhi_resume,
437 .shutdown = icl_nhi_shutdown,
438 .pre_nvm_auth = nhi_pci_start_dma_port,
439 .post_nvm_auth = nhi_pci_complete_dma_port,
440 .request_ring_irq = nhi_pci_ring_request_msix,
441 .release_ring_irq = nhi_pci_ring_release_msix,
442 .is_present = nhi_pci_is_present,
443 .init_interrupts = nhi_pci_init_msi,
444};
445
446static int nhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
447{
448 struct device *dev = &pdev->dev;
449 struct tb_nhi_pci *nhi_pci;
450 struct tb_nhi *nhi;
451 int res;
452
453 if (!nhi_pci_imr_valid(pdev))
454 return dev_err_probe(dev, -ENODEV, "firmware image not valid, aborting\n");
455
456 res = pcim_enable_device(pdev);
457 if (res)
458 return dev_err_probe(dev, res, "cannot enable PCI device, aborting\n");
459
460 nhi_pci = devm_kzalloc(dev, sizeof(*nhi_pci), GFP_KERNEL);
461 if (!nhi_pci)
462 return -ENOMEM;
463
464 nhi = &nhi_pci->nhi;
465 nhi->dev = dev;
466 nhi->ops = (const struct tb_nhi_ops *)id->driver_data ?: &pci_nhi_default_ops;
467
468 nhi->iobase = pcim_iomap_region(pdev, 0, "thunderbolt");
469 res = PTR_ERR_OR_ZERO(nhi->iobase);
470 if (res)
471 return dev_err_probe(dev, res, "cannot obtain PCI resources, aborting\n");
472
473 nhi_pci_check_quirks(nhi_pci);
474 nhi_pci_check_iommu(nhi_pci);
475
476 pci_set_master(pdev);
477
478 return nhi_probe(&nhi_pci->nhi);
479}
480
481static void nhi_pci_do_remove(struct pci_dev *pdev, bool reset)
482{
483 struct tb *tb = pci_get_drvdata(pdev);
484 struct tb_nhi *nhi = tb->nhi;
485
486 /*
487 * On system shutdown/reboot force a host router reset so the
488 * connection manager asserts DPR on connected Thunderbolt 3 devices
489 * before the router tree is removed (see tb_stop()).
490 */
491 if (reset)
492 nhi->host_reset = true;
493
494 pm_runtime_get_sync(&pdev->dev);
495 pm_runtime_dont_use_autosuspend(&pdev->dev);
496 pm_runtime_forbid(&pdev->dev);
497
498 tb_domain_remove(tb);
499 wait_for_completion(&nhi->domain_released);
500 nhi_shutdown(nhi);
501}
502
503static void nhi_pci_remove(struct pci_dev *pdev)
504{
505 nhi_pci_do_remove(pdev, false);
506}
507
508static void nhi_pci_shutdown(struct pci_dev *pdev)
509{
510 nhi_pci_do_remove(pdev, true);
511}
512
513static struct pci_device_id nhi_ids[] = {
514 /*
515 * We have to specify class, the TB bridges use the same device and
516 * vendor (sub)id on gen 1 and gen 2 controllers.
517 */
518 {
519 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0,
520 .vendor = PCI_VENDOR_ID_INTEL,
521 .device = PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
522 .subvendor = 0x2222, .subdevice = 0x1111,
523 },
524 {
525 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0,
526 .vendor = PCI_VENDOR_ID_INTEL,
527 .device = PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
528 .subvendor = 0x2222, .subdevice = 0x1111,
529 },
530 {
531 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0,
532 .vendor = PCI_VENDOR_ID_INTEL,
533 .device = PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI,
534 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID,
535 },
536 {
537 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0,
538 .vendor = PCI_VENDOR_ID_INTEL,
539 .device = PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI,
540 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID,
541 },
542
543 /* Thunderbolt 3 */
544 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_NHI) },
545 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_NHI) },
546 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_USBONLY_NHI) },
547 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_NHI) },
548 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_USBONLY_NHI) },
549 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_NHI) },
550 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_NHI) },
551 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_USBONLY_NHI) },
552 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_NHI) },
553 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_NHI) },
554 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICL_NHI0),
555 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
556 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICL_NHI1),
557 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
558 /* Thunderbolt 4 */
559 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_NHI0),
560 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
561 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_NHI1),
562 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
563 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_H_NHI0),
564 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
565 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_H_NHI1),
566 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
567 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADL_NHI0),
568 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
569 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADL_NHI1),
570 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
571 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_RPL_NHI0),
572 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
573 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_RPL_NHI1),
574 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
575 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MTL_M_NHI0),
576 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
577 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MTL_P_NHI0),
578 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
579 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MTL_P_NHI1),
580 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
581 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_LNL_NHI0),
582 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
583 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_LNL_NHI1),
584 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
585 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_PTL_M_NHI0),
586 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
587 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_PTL_M_NHI1),
588 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
589 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_PTL_P_NHI0),
590 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
591 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_PTL_P_NHI1),
592 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
593 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_WCL_NHI0),
594 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
595 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HOST_80G_NHI) },
596 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HOST_40G_NHI) },
597
598 /* Any USB4 compliant host */
599 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_USB4, ~0) },
600
601 { 0,}
602};
603
604MODULE_DEVICE_TABLE(pci, nhi_ids);
605MODULE_DESCRIPTION("Thunderbolt/USB4 core driver");
606MODULE_LICENSE("GPL");
607
608static struct pci_driver nhi_driver = {
609 .name = "thunderbolt",
610 .id_table = nhi_ids,
611 .probe = nhi_pci_probe,
612 .remove = nhi_pci_remove,
613 .shutdown = nhi_pci_shutdown,
614 .driver.pm = &nhi_pm_ops,
615};
616
617static int __init nhi_init(void)
618{
619 int ret;
620
621 ret = tb_domain_init();
622 if (ret)
623 return ret;
624
625 ret = pci_register_driver(&nhi_driver);
626 if (ret)
627 tb_domain_exit();
628
629 return ret;
630}
631
632static void __exit nhi_unload(void)
633{
634 pci_unregister_driver(&nhi_driver);
635 tb_domain_exit();
636}
637
638rootfs_initcall(nhi_init);
639module_exit(nhi_unload);