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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * mxser.c -- MOXA Smartio/Industio family multiport serial driver.
4 *
5 * Copyright (C) 1999-2006 Moxa Technologies ([email protected]).
6 * Copyright (C) 2006-2008 Jiri Slaby <[email protected]>
7 *
8 * This code is loosely based on the 1.8 moxa driver which is based on
9 * Linux serial driver, written by Linus Torvalds, Theodore T'so and
10 * others.
11 *
12 * Fed through a cleanup, indent and remove of non 2.6 code by Alan Cox
13 * <[email protected]>. The original 1.8 code is available on
14 * www.moxa.com.
15 * - Fixed x86_64 cleanness
16 */
17
18#include <linux/module.h>
19#include <linux/errno.h>
20#include <linux/signal.h>
21#include <linux/sched.h>
22#include <linux/timer.h>
23#include <linux/interrupt.h>
24#include <linux/tty.h>
25#include <linux/tty_flip.h>
26#include <linux/serial.h>
27#include <linux/serial_reg.h>
28#include <linux/major.h>
29#include <linux/string.h>
30#include <linux/fcntl.h>
31#include <linux/ptrace.h>
32#include <linux/ioport.h>
33#include <linux/mm.h>
34#include <linux/delay.h>
35#include <linux/pci.h>
36#include <linux/bitops.h>
37#include <linux/slab.h>
38#include <linux/ratelimit.h>
39
40#include <asm/io.h>
41#include <asm/irq.h>
42#include <linux/uaccess.h>
43
44/*
45 * Semi-public control interfaces
46 */
47
48/*
49 * MOXA ioctls
50 */
51
52#define MOXA 0x400
53#define MOXA_SET_OP_MODE (MOXA + 66)
54#define MOXA_GET_OP_MODE (MOXA + 67)
55
56#define RS232_MODE 0
57#define RS485_2WIRE_MODE 1
58#define RS422_MODE 2
59#define RS485_4WIRE_MODE 3
60#define OP_MODE_MASK 3
61
62/* --------------------------------------------------- */
63
64/*
65 * Follow just what Moxa Must chip defines.
66 *
67 * When LCR register (offset 0x03) is written the following value, the Must chip
68 * will enter enhanced mode. And a write to EFR (offset 0x02) bit 6,7 will
69 * change bank.
70 */
71#define MOXA_MUST_ENTER_ENHANCED 0xBF
72
73/* when enhanced mode is enabled, access to general bank register */
74#define MOXA_MUST_GDL_REGISTER 0x07
75#define MOXA_MUST_GDL_MASK 0x7F
76#define MOXA_MUST_GDL_HAS_BAD_DATA 0x80
77
78#define MOXA_MUST_LSR_RERR 0x80 /* error in receive FIFO */
79/* enhanced register bank select and enhanced mode setting register */
80/* This works only when LCR register equals to 0xBF */
81#define MOXA_MUST_EFR_REGISTER 0x02
82#define MOXA_MUST_EFR_EFRB_ENABLE 0x10 /* enhanced mode enable */
83/* enhanced register bank set 0, 1, 2 */
84#define MOXA_MUST_EFR_BANK0 0x00
85#define MOXA_MUST_EFR_BANK1 0x40
86#define MOXA_MUST_EFR_BANK2 0x80
87#define MOXA_MUST_EFR_BANK3 0xC0
88#define MOXA_MUST_EFR_BANK_MASK 0xC0
89
90/* set XON1 value register, when LCR=0xBF and change to bank0 */
91#define MOXA_MUST_XON1_REGISTER 0x04
92
93/* set XON2 value register, when LCR=0xBF and change to bank0 */
94#define MOXA_MUST_XON2_REGISTER 0x05
95
96/* set XOFF1 value register, when LCR=0xBF and change to bank0 */
97#define MOXA_MUST_XOFF1_REGISTER 0x06
98
99/* set XOFF2 value register, when LCR=0xBF and change to bank0 */
100#define MOXA_MUST_XOFF2_REGISTER 0x07
101
102#define MOXA_MUST_RBRTL_REGISTER 0x04
103#define MOXA_MUST_RBRTH_REGISTER 0x05
104#define MOXA_MUST_RBRTI_REGISTER 0x06
105#define MOXA_MUST_THRTL_REGISTER 0x07
106#define MOXA_MUST_ENUM_REGISTER 0x04
107#define MOXA_MUST_HWID_REGISTER 0x05
108#define MOXA_MUST_ECR_REGISTER 0x06
109#define MOXA_MUST_CSR_REGISTER 0x07
110
111#define MOXA_MUST_FCR_GDA_MODE_ENABLE 0x20 /* good data mode enable */
112#define MOXA_MUST_FCR_GDA_ONLY_ENABLE 0x10 /* only good data put into RxFIFO */
113
114#define MOXA_MUST_IER_ECTSI 0x80 /* enable CTS interrupt */
115#define MOXA_MUST_IER_ERTSI 0x40 /* enable RTS interrupt */
116#define MOXA_MUST_IER_XINT 0x20 /* enable Xon/Xoff interrupt */
117#define MOXA_MUST_IER_EGDAI 0x10 /* enable GDA interrupt */
118
119#define MOXA_MUST_RECV_ISR (UART_IER_RDI | MOXA_MUST_IER_EGDAI)
120
121/* GDA interrupt pending */
122#define MOXA_MUST_IIR_GDA 0x1C
123#define MOXA_MUST_IIR_RDA 0x04
124#define MOXA_MUST_IIR_RTO 0x0C
125#define MOXA_MUST_IIR_LSR 0x06
126
127/* received Xon/Xoff or specical interrupt pending */
128#define MOXA_MUST_IIR_XSC 0x10
129
130/* RTS/CTS change state interrupt pending */
131#define MOXA_MUST_IIR_RTSCTS 0x20
132#define MOXA_MUST_IIR_MASK 0x3E
133
134#define MOXA_MUST_MCR_XON_FLAG 0x40
135#define MOXA_MUST_MCR_XON_ANY 0x80
136#define MOXA_MUST_MCR_TX_XON 0x08
137
138#define MOXA_MUST_EFR_SF_MASK 0x0F /* software flow control on chip mask value */
139#define MOXA_MUST_EFR_SF_TX1 0x08 /* send Xon1/Xoff1 */
140#define MOXA_MUST_EFR_SF_TX2 0x04 /* send Xon2/Xoff2 */
141#define MOXA_MUST_EFR_SF_TX12 0x0C /* send Xon1,Xon2/Xoff1,Xoff2 */
142#define MOXA_MUST_EFR_SF_TX_NO 0x00 /* don't send Xon/Xoff */
143#define MOXA_MUST_EFR_SF_TX_MASK 0x0C /* Tx software flow control mask */
144#define MOXA_MUST_EFR_SF_RX_NO 0x00 /* don't receive Xon/Xoff */
145#define MOXA_MUST_EFR_SF_RX1 0x02 /* receive Xon1/Xoff1 */
146#define MOXA_MUST_EFR_SF_RX2 0x01 /* receive Xon2/Xoff2 */
147#define MOXA_MUST_EFR_SF_RX12 0x03 /* receive Xon1,Xon2/Xoff1,Xoff2 */
148#define MOXA_MUST_EFR_SF_RX_MASK 0x03 /* Rx software flow control mask */
149
150#define MXSERMAJOR 174
151
152#define MXSER_BOARDS 4 /* Max. boards */
153#define MXSER_PORTS_PER_BOARD 8 /* Max. ports per board */
154#define MXSER_PORTS (MXSER_BOARDS * MXSER_PORTS_PER_BOARD)
155#define MXSER_ISR_PASS_LIMIT 100
156
157#define WAKEUP_CHARS 256
158
159#define MXSER_BAUD_BASE 921600
160#define MXSER_CUSTOM_DIVISOR (MXSER_BAUD_BASE * 16)
161
162#define PCI_DEVICE_ID_MOXA_RC7000 0x0001
163#define PCI_DEVICE_ID_MOXA_CP102 0x1020
164#define PCI_DEVICE_ID_MOXA_CP102UL 0x1021
165#define PCI_DEVICE_ID_MOXA_CP102U 0x1022
166#define PCI_DEVICE_ID_MOXA_CP102UF 0x1023
167#define PCI_DEVICE_ID_MOXA_C104 0x1040
168#define PCI_DEVICE_ID_MOXA_CP104U 0x1041
169#define PCI_DEVICE_ID_MOXA_CP104JU 0x1042
170#define PCI_DEVICE_ID_MOXA_CP104EL 0x1043
171#define PCI_DEVICE_ID_MOXA_POS104UL 0x1044
172#define PCI_DEVICE_ID_MOXA_CB108 0x1080
173#define PCI_DEVICE_ID_MOXA_CP112UL 0x1120
174#define PCI_DEVICE_ID_MOXA_CT114 0x1140
175#define PCI_DEVICE_ID_MOXA_CP114 0x1141
176#define PCI_DEVICE_ID_MOXA_CB114 0x1142
177#define PCI_DEVICE_ID_MOXA_CP114UL 0x1143
178#define PCI_DEVICE_ID_MOXA_CP118U 0x1180
179#define PCI_DEVICE_ID_MOXA_CP118EL 0x1181
180#define PCI_DEVICE_ID_MOXA_CP132 0x1320
181#define PCI_DEVICE_ID_MOXA_CP132U 0x1321
182#define PCI_DEVICE_ID_MOXA_CP134U 0x1340
183#define PCI_DEVICE_ID_MOXA_CB134I 0x1341
184#define PCI_DEVICE_ID_MOXA_CP138U 0x1380
185#define PCI_DEVICE_ID_MOXA_C168 0x1680
186#define PCI_DEVICE_ID_MOXA_CP168U 0x1681
187#define PCI_DEVICE_ID_MOXA_CP168EL 0x1682
188
189#define MXSER_NPORTS(ddata) ((ddata) & 0xffU)
190#define MXSER_HIGHBAUD 0x0100
191
192enum mxser_must_hwid {
193 MOXA_OTHER_UART = 0x00,
194 MOXA_MUST_MU150_HWID = 0x01,
195 MOXA_MUST_MU860_HWID = 0x02,
196};
197
198static const struct {
199 u8 type;
200 u8 fifo_size;
201 u8 rx_high_water;
202 u8 rx_low_water;
203 speed_t max_baud;
204} Gpci_uart_info[] = {
205 { MOXA_OTHER_UART, 16, 14, 1, 921600 },
206 { MOXA_MUST_MU150_HWID, 64, 48, 16, 230400 },
207 { MOXA_MUST_MU860_HWID, 128, 96, 32, 921600 }
208};
209#define UART_INFO_NUM ARRAY_SIZE(Gpci_uart_info)
210
211static const struct pci_device_id mxser_pcibrds[] = {
212 { PCI_DEVICE_DATA(MOXA, C168, 8) },
213 { PCI_DEVICE_DATA(MOXA, C104, 4) },
214 { PCI_DEVICE_DATA(MOXA, CP132, 2) },
215 { PCI_DEVICE_DATA(MOXA, CP114, 4) },
216 { PCI_DEVICE_DATA(MOXA, CT114, 4) },
217 { PCI_DEVICE_DATA(MOXA, CP102, 2 | MXSER_HIGHBAUD) },
218 { PCI_DEVICE_DATA(MOXA, CP104U, 4) },
219 { PCI_DEVICE_DATA(MOXA, CP168U, 8) },
220 { PCI_DEVICE_DATA(MOXA, CP132U, 2) },
221 { PCI_DEVICE_DATA(MOXA, CP134U, 4) },
222 { PCI_DEVICE_DATA(MOXA, CP104JU, 4) },
223 { PCI_DEVICE_DATA(MOXA, RC7000, 8) }, /* RC7000 */
224 { PCI_DEVICE_DATA(MOXA, CP118U, 8) },
225 { PCI_DEVICE_DATA(MOXA, CP102UL, 2) },
226 { PCI_DEVICE_DATA(MOXA, CP102U, 2) },
227 { PCI_DEVICE_DATA(MOXA, CP118EL, 8) },
228 { PCI_DEVICE_DATA(MOXA, CP168EL, 8) },
229 { PCI_DEVICE_DATA(MOXA, CP104EL, 4) },
230 { PCI_DEVICE_DATA(MOXA, CB108, 8) },
231 { PCI_DEVICE_DATA(MOXA, CB114, 4) },
232 { PCI_DEVICE_DATA(MOXA, CB134I, 4) },
233 { PCI_DEVICE_DATA(MOXA, CP138U, 8) },
234 { PCI_DEVICE_DATA(MOXA, POS104UL, 4) },
235 { PCI_DEVICE_DATA(MOXA, CP114UL, 4) },
236 { PCI_DEVICE_DATA(MOXA, CP102UF, 2) },
237 { PCI_DEVICE_DATA(MOXA, CP112UL, 2) },
238 { }
239};
240MODULE_DEVICE_TABLE(pci, mxser_pcibrds);
241
242static int ttymajor = MXSERMAJOR;
243
244/* Variables for insmod */
245
246MODULE_AUTHOR("Casper Yang");
247MODULE_DESCRIPTION("MOXA Smartio/Industio Family Multiport Board Device Driver");
248module_param(ttymajor, int, 0);
249MODULE_LICENSE("GPL");
250
251struct mxser_board;
252
253struct mxser_port {
254 struct tty_port port;
255 struct mxser_board *board;
256
257 unsigned long ioaddr;
258 unsigned long opmode_ioaddr;
259
260 u8 rx_high_water;
261 u8 rx_low_water;
262 int type; /* UART type */
263
264 u8 x_char; /* xon/xoff character */
265 u8 IER; /* Interrupt Enable Register */
266 u8 MCR; /* Modem control register */
267 u8 FCR; /* FIFO control register */
268
269 struct async_icount icount; /* kernel counters for 4 input interrupts */
270 unsigned int timeout;
271
272 u8 read_status_mask;
273 u8 ignore_status_mask;
274 u8 xmit_fifo_size;
275
276 spinlock_t slock;
277};
278
279struct mxser_board {
280 unsigned int idx;
281 unsigned short nports;
282 int irq;
283 unsigned long vector;
284
285 enum mxser_must_hwid must_hwid;
286 speed_t max_baud;
287
288 struct mxser_port ports[] /* __counted_by(nports) */;
289};
290
291static DECLARE_BITMAP(mxser_boards, MXSER_BOARDS);
292static struct tty_driver *mxvar_sdriver;
293
294static u8 __mxser_must_set_EFR(unsigned long baseio, u8 clear, u8 set,
295 bool restore_LCR)
296{
297 u8 oldlcr, efr;
298
299 oldlcr = inb(baseio + UART_LCR);
300 outb(MOXA_MUST_ENTER_ENHANCED, baseio + UART_LCR);
301
302 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
303 efr &= ~clear;
304 efr |= set;
305
306 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
307
308 if (restore_LCR)
309 outb(oldlcr, baseio + UART_LCR);
310
311 return oldlcr;
312}
313
314static u8 mxser_must_select_bank(unsigned long baseio, u8 bank)
315{
316 return __mxser_must_set_EFR(baseio, MOXA_MUST_EFR_BANK_MASK, bank,
317 false);
318}
319
320static void mxser_set_must_xon1_value(unsigned long baseio, u8 value)
321{
322 u8 oldlcr = mxser_must_select_bank(baseio, MOXA_MUST_EFR_BANK0);
323 outb(value, baseio + MOXA_MUST_XON1_REGISTER);
324 outb(oldlcr, baseio + UART_LCR);
325}
326
327static void mxser_set_must_xoff1_value(unsigned long baseio, u8 value)
328{
329 u8 oldlcr = mxser_must_select_bank(baseio, MOXA_MUST_EFR_BANK0);
330 outb(value, baseio + MOXA_MUST_XOFF1_REGISTER);
331 outb(oldlcr, baseio + UART_LCR);
332}
333
334static void mxser_set_must_fifo_value(struct mxser_port *info)
335{
336 u8 oldlcr = mxser_must_select_bank(info->ioaddr, MOXA_MUST_EFR_BANK1);
337 outb(info->rx_high_water, info->ioaddr + MOXA_MUST_RBRTH_REGISTER);
338 outb(info->rx_high_water, info->ioaddr + MOXA_MUST_RBRTI_REGISTER);
339 outb(info->rx_low_water, info->ioaddr + MOXA_MUST_RBRTL_REGISTER);
340 outb(oldlcr, info->ioaddr + UART_LCR);
341}
342
343static void mxser_set_must_enum_value(unsigned long baseio, u8 value)
344{
345 u8 oldlcr = mxser_must_select_bank(baseio, MOXA_MUST_EFR_BANK2);
346 outb(value, baseio + MOXA_MUST_ENUM_REGISTER);
347 outb(oldlcr, baseio + UART_LCR);
348}
349
350static u8 mxser_get_must_hardware_id(unsigned long baseio)
351{
352 u8 oldlcr = mxser_must_select_bank(baseio, MOXA_MUST_EFR_BANK2);
353 u8 id = inb(baseio + MOXA_MUST_HWID_REGISTER);
354 outb(oldlcr, baseio + UART_LCR);
355
356 return id;
357}
358
359static void mxser_must_set_EFR(unsigned long baseio, u8 clear, u8 set)
360{
361 __mxser_must_set_EFR(baseio, clear, set, true);
362}
363
364static void mxser_must_set_enhance_mode(unsigned long baseio, bool enable)
365{
366 mxser_must_set_EFR(baseio,
367 enable ? 0 : MOXA_MUST_EFR_EFRB_ENABLE,
368 enable ? MOXA_MUST_EFR_EFRB_ENABLE : 0);
369}
370
371static void mxser_must_no_sw_flow_control(unsigned long baseio)
372{
373 mxser_must_set_EFR(baseio, MOXA_MUST_EFR_SF_MASK, 0);
374}
375
376static void mxser_must_set_tx_sw_flow_control(unsigned long baseio, bool enable)
377{
378 mxser_must_set_EFR(baseio, MOXA_MUST_EFR_SF_TX_MASK,
379 enable ? MOXA_MUST_EFR_SF_TX1 : 0);
380}
381
382static void mxser_must_set_rx_sw_flow_control(unsigned long baseio, bool enable)
383{
384 mxser_must_set_EFR(baseio, MOXA_MUST_EFR_SF_RX_MASK,
385 enable ? MOXA_MUST_EFR_SF_RX1 : 0);
386}
387
388static enum mxser_must_hwid mxser_must_get_hwid(unsigned long io)
389{
390 u8 oldmcr, hwid;
391 int i;
392
393 outb(0, io + UART_LCR);
394 mxser_must_set_enhance_mode(io, false);
395 oldmcr = inb(io + UART_MCR);
396 outb(0, io + UART_MCR);
397 mxser_set_must_xon1_value(io, 0x11);
398 if (inb(io + UART_MCR) != 0) {
399 outb(oldmcr, io + UART_MCR);
400 return MOXA_OTHER_UART;
401 }
402
403 hwid = mxser_get_must_hardware_id(io);
404 for (i = 1; i < UART_INFO_NUM; i++) /* 0 = OTHER_UART */
405 if (hwid == Gpci_uart_info[i].type)
406 return hwid;
407
408 return MOXA_OTHER_UART;
409}
410
411static bool mxser_16550A_or_MUST(struct mxser_port *info)
412{
413 return info->type == PORT_16550A || info->board->must_hwid;
414}
415
416static void mxser_process_txrx_fifo(struct mxser_port *info)
417{
418 unsigned int i;
419
420 if (info->type == PORT_16450 || info->type == PORT_8250) {
421 info->rx_high_water = 1;
422 info->rx_low_water = 1;
423 info->xmit_fifo_size = 1;
424 return;
425 }
426
427 for (i = 0; i < UART_INFO_NUM; i++)
428 if (info->board->must_hwid == Gpci_uart_info[i].type) {
429 info->rx_low_water = Gpci_uart_info[i].rx_low_water;
430 info->rx_high_water = Gpci_uart_info[i].rx_high_water;
431 info->xmit_fifo_size = Gpci_uart_info[i].fifo_size;
432 break;
433 }
434}
435
436static void __mxser_start_tx(struct mxser_port *info)
437{
438 outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER);
439 info->IER |= UART_IER_THRI;
440 outb(info->IER, info->ioaddr + UART_IER);
441}
442
443static void mxser_start_tx(struct mxser_port *info)
444{
445 guard(spinlock_irqsave)(&info->slock);
446 __mxser_start_tx(info);
447}
448
449static void __mxser_stop_tx(struct mxser_port *info)
450{
451 info->IER &= ~UART_IER_THRI;
452 outb(info->IER, info->ioaddr + UART_IER);
453}
454
455static bool mxser_carrier_raised(struct tty_port *port)
456{
457 struct mxser_port *mp = container_of(port, struct mxser_port, port);
458
459 return inb(mp->ioaddr + UART_MSR) & UART_MSR_DCD;
460}
461
462static void mxser_dtr_rts(struct tty_port *port, bool active)
463{
464 struct mxser_port *mp = container_of(port, struct mxser_port, port);
465 u8 mcr;
466
467 guard(spinlock_irqsave)(&mp->slock);
468 mcr = inb(mp->ioaddr + UART_MCR);
469 if (active)
470 mcr |= UART_MCR_DTR | UART_MCR_RTS;
471 else
472 mcr &= ~(UART_MCR_DTR | UART_MCR_RTS);
473 outb(mcr, mp->ioaddr + UART_MCR);
474}
475
476static int mxser_set_baud(struct tty_struct *tty, speed_t newspd)
477{
478 struct mxser_port *info = tty->driver_data;
479 unsigned int quot = 0, baud;
480 unsigned char cval;
481 u64 timeout;
482
483 if (newspd > info->board->max_baud)
484 return -1;
485
486 if (newspd == 134) {
487 quot = 2 * MXSER_BAUD_BASE / 269;
488 tty_encode_baud_rate(tty, 134, 134);
489 } else if (newspd) {
490 quot = MXSER_BAUD_BASE / newspd;
491 if (quot == 0)
492 quot = 1;
493 baud = MXSER_BAUD_BASE / quot;
494 tty_encode_baud_rate(tty, baud, baud);
495 } else {
496 quot = 0;
497 }
498
499 /*
500 * worst case (128 * 1000 * 10 * 18432) needs 35 bits, so divide in the
501 * u64 domain
502 */
503 timeout = (u64)info->xmit_fifo_size * HZ * 10 * quot;
504 do_div(timeout, MXSER_BAUD_BASE);
505 info->timeout = timeout + HZ / 50; /* Add .02 seconds of slop */
506
507 if (quot) {
508 info->MCR |= UART_MCR_DTR;
509 outb(info->MCR, info->ioaddr + UART_MCR);
510 } else {
511 info->MCR &= ~UART_MCR_DTR;
512 outb(info->MCR, info->ioaddr + UART_MCR);
513 return 0;
514 }
515
516 cval = inb(info->ioaddr + UART_LCR);
517
518 outb(cval | UART_LCR_DLAB, info->ioaddr + UART_LCR); /* set DLAB */
519
520 outb(quot & 0xff, info->ioaddr + UART_DLL); /* LS of divisor */
521 outb(quot >> 8, info->ioaddr + UART_DLM); /* MS of divisor */
522 outb(cval, info->ioaddr + UART_LCR); /* reset DLAB */
523
524 if (C_BAUD(tty) == BOTHER) {
525 quot = MXSER_BAUD_BASE % newspd;
526 quot *= 8;
527 if (quot % newspd > newspd / 2) {
528 quot /= newspd;
529 quot++;
530 } else
531 quot /= newspd;
532
533 mxser_set_must_enum_value(info->ioaddr, quot);
534 } else {
535 mxser_set_must_enum_value(info->ioaddr, 0);
536 }
537
538 return 0;
539}
540
541static void mxser_handle_cts(struct tty_struct *tty, struct mxser_port *info,
542 u8 msr)
543{
544 bool cts = msr & UART_MSR_CTS;
545
546 if (tty->hw_stopped) {
547 if (cts) {
548 tty->hw_stopped = false;
549
550 if (!mxser_16550A_or_MUST(info))
551 __mxser_start_tx(info);
552 tty_wakeup(tty);
553 }
554 return;
555 } else if (cts)
556 return;
557
558 tty->hw_stopped = true;
559 if (!mxser_16550A_or_MUST(info))
560 __mxser_stop_tx(info);
561}
562
563/*
564 * This routine is called to set the UART divisor registers to match
565 * the specified baud rate for a serial port.
566 */
567static void mxser_change_speed(struct tty_struct *tty,
568 const struct ktermios *old_termios)
569{
570 struct mxser_port *info = tty->driver_data;
571 unsigned cflag, cval;
572
573 cflag = tty->termios.c_cflag;
574
575 if (mxser_set_baud(tty, tty_get_baud_rate(tty))) {
576 /* Use previous rate on a failure */
577 if (old_termios) {
578 speed_t baud = tty_termios_baud_rate(old_termios);
579 tty_encode_baud_rate(tty, baud, baud);
580 }
581 }
582
583 /* byte size and parity */
584 cval = UART_LCR_WLEN(tty_get_char_size(tty->termios.c_cflag));
585
586 if (cflag & CSTOPB)
587 cval |= UART_LCR_STOP;
588 if (cflag & PARENB)
589 cval |= UART_LCR_PARITY;
590 if (!(cflag & PARODD))
591 cval |= UART_LCR_EPAR;
592 if (cflag & CMSPAR)
593 cval |= UART_LCR_SPAR;
594
595 info->FCR = 0;
596 if (info->board->must_hwid) {
597 info->FCR |= UART_FCR_ENABLE_FIFO |
598 MOXA_MUST_FCR_GDA_MODE_ENABLE;
599 mxser_set_must_fifo_value(info);
600 } else if (info->type != PORT_8250 && info->type != PORT_16450) {
601 info->FCR |= UART_FCR_ENABLE_FIFO;
602 switch (info->rx_high_water) {
603 case 1:
604 info->FCR |= UART_FCR_TRIGGER_1;
605 break;
606 case 4:
607 info->FCR |= UART_FCR_TRIGGER_4;
608 break;
609 case 8:
610 info->FCR |= UART_FCR_TRIGGER_8;
611 break;
612 default:
613 info->FCR |= UART_FCR_TRIGGER_14;
614 break;
615 }
616 }
617
618 /* CTS flow control flag and modem status interrupts */
619 info->IER &= ~UART_IER_MSI;
620 info->MCR &= ~UART_MCR_AFE;
621 tty_port_set_cts_flow(&info->port, cflag & CRTSCTS);
622 if (cflag & CRTSCTS) {
623 info->IER |= UART_IER_MSI;
624 if (mxser_16550A_or_MUST(info)) {
625 info->MCR |= UART_MCR_AFE;
626 } else {
627 mxser_handle_cts(tty, info,
628 inb(info->ioaddr + UART_MSR));
629 }
630 }
631 outb(info->MCR, info->ioaddr + UART_MCR);
632 tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL);
633 if (~cflag & CLOCAL)
634 info->IER |= UART_IER_MSI;
635 outb(info->IER, info->ioaddr + UART_IER);
636
637 /*
638 * Set up parity check flag
639 */
640 info->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
641 if (I_INPCK(tty))
642 info->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
643 if (I_BRKINT(tty) || I_PARMRK(tty))
644 info->read_status_mask |= UART_LSR_BI;
645
646 info->ignore_status_mask = 0;
647
648 if (I_IGNBRK(tty)) {
649 info->ignore_status_mask |= UART_LSR_BI;
650 info->read_status_mask |= UART_LSR_BI;
651 /*
652 * If we're ignore parity and break indicators, ignore
653 * overruns too. (For real raw support).
654 */
655 if (I_IGNPAR(tty)) {
656 info->ignore_status_mask |=
657 UART_LSR_OE |
658 UART_LSR_PE |
659 UART_LSR_FE;
660 info->read_status_mask |=
661 UART_LSR_OE |
662 UART_LSR_PE |
663 UART_LSR_FE;
664 }
665 }
666 if (info->board->must_hwid) {
667 mxser_set_must_xon1_value(info->ioaddr, START_CHAR(tty));
668 mxser_set_must_xoff1_value(info->ioaddr, STOP_CHAR(tty));
669 mxser_must_set_rx_sw_flow_control(info->ioaddr, I_IXON(tty));
670 mxser_must_set_tx_sw_flow_control(info->ioaddr, I_IXOFF(tty));
671 }
672
673
674 outb(info->FCR, info->ioaddr + UART_FCR);
675 outb(cval, info->ioaddr + UART_LCR);
676}
677
678static u8 mxser_check_modem_status(struct tty_struct *tty,
679 struct mxser_port *port)
680{
681 u8 msr = inb(port->ioaddr + UART_MSR);
682
683 if (!(msr & UART_MSR_ANY_DELTA))
684 return msr;
685
686 /* update input line counters */
687 if (msr & UART_MSR_TERI)
688 port->icount.rng++;
689 if (msr & UART_MSR_DDSR)
690 port->icount.dsr++;
691 if (msr & UART_MSR_DDCD)
692 port->icount.dcd++;
693 if (msr & UART_MSR_DCTS)
694 port->icount.cts++;
695 wake_up_interruptible(&port->port.delta_msr_wait);
696
697 if (tty_port_check_carrier(&port->port) && (msr & UART_MSR_DDCD)) {
698 if (msr & UART_MSR_DCD)
699 wake_up_interruptible(&port->port.open_wait);
700 }
701
702 if (tty_port_cts_enabled(&port->port))
703 mxser_handle_cts(tty, port, msr);
704
705 return msr;
706}
707
708static void mxser_disable_and_clear_FIFO(struct mxser_port *info)
709{
710 u8 fcr = UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT;
711
712 if (info->board->must_hwid)
713 fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE;
714
715 outb(fcr, info->ioaddr + UART_FCR);
716}
717
718static int mxser_activate(struct tty_port *port, struct tty_struct *tty)
719{
720 struct mxser_port *info = container_of(port, struct mxser_port, port);
721 unsigned long flags;
722 int ret;
723
724 ret = tty_port_alloc_xmit_buf(port);
725 if (ret < 0)
726 return ret;
727
728 spin_lock_irqsave(&info->slock, flags);
729
730 if (!info->type) {
731 set_bit(TTY_IO_ERROR, &tty->flags);
732 spin_unlock_irqrestore(&info->slock, flags);
733 ret = 0;
734 goto err_free_xmit;
735 }
736
737 /*
738 * Clear the FIFO buffers and disable them
739 * (they will be reenabled in mxser_change_speed())
740 */
741 mxser_disable_and_clear_FIFO(info);
742
743 /*
744 * At this point there's no way the LSR could still be 0xFF;
745 * if it is, then bail out, because there's likely no UART
746 * here.
747 */
748 if (inb(info->ioaddr + UART_LSR) == 0xff) {
749 spin_unlock_irqrestore(&info->slock, flags);
750 if (capable(CAP_SYS_ADMIN)) {
751 set_bit(TTY_IO_ERROR, &tty->flags);
752 return 0;
753 }
754
755 ret = -ENODEV;
756 goto err_free_xmit;
757 }
758
759 /*
760 * Clear the interrupt registers.
761 */
762 (void) inb(info->ioaddr + UART_LSR);
763 (void) inb(info->ioaddr + UART_RX);
764 (void) inb(info->ioaddr + UART_IIR);
765 (void) inb(info->ioaddr + UART_MSR);
766
767 /*
768 * Now, initialize the UART
769 */
770 outb(UART_LCR_WLEN8, info->ioaddr + UART_LCR); /* reset DLAB */
771 info->MCR = UART_MCR_DTR | UART_MCR_RTS;
772 outb(info->MCR, info->ioaddr + UART_MCR);
773
774 /*
775 * Finally, enable interrupts
776 */
777 info->IER = UART_IER_MSI | UART_IER_RLSI | UART_IER_RDI;
778
779 if (info->board->must_hwid)
780 info->IER |= MOXA_MUST_IER_EGDAI;
781 outb(info->IER, info->ioaddr + UART_IER); /* enable interrupts */
782
783 /*
784 * And clear the interrupt registers again for luck.
785 */
786 (void) inb(info->ioaddr + UART_LSR);
787 (void) inb(info->ioaddr + UART_RX);
788 (void) inb(info->ioaddr + UART_IIR);
789 (void) inb(info->ioaddr + UART_MSR);
790
791 clear_bit(TTY_IO_ERROR, &tty->flags);
792 kfifo_reset(&port->xmit_fifo);
793
794 /*
795 * and set the speed of the serial port
796 */
797 mxser_change_speed(tty, NULL);
798 spin_unlock_irqrestore(&info->slock, flags);
799
800 return 0;
801err_free_xmit:
802 tty_port_free_xmit_buf(port);
803 return ret;
804}
805
806/*
807 * To stop accepting input, we disable the receive line status interrupts, and
808 * tell the interrupt driver to stop checking the data ready bit in the line
809 * status register.
810 */
811static void mxser_stop_rx(struct mxser_port *info)
812{
813 info->IER &= ~UART_IER_RLSI;
814 if (info->board->must_hwid)
815 info->IER &= ~MOXA_MUST_RECV_ISR;
816
817 outb(info->IER, info->ioaddr + UART_IER);
818}
819
820/*
821 * This routine will shutdown a serial port
822 */
823static void mxser_shutdown_port(struct tty_port *port)
824{
825 struct mxser_port *info = container_of(port, struct mxser_port, port);
826
827 scoped_guard(spinlock_irqsave, &info->slock) {
828 mxser_stop_rx(info);
829
830 /*
831 * clear delta_msr_wait queue to avoid mem leaks: we may free the irq
832 * here so the queue might never be waken up
833 */
834 wake_up_interruptible(&info->port.delta_msr_wait);
835
836 info->IER = 0;
837 outb(0x00, info->ioaddr + UART_IER);
838
839 /* clear Rx/Tx FIFO's */
840 mxser_disable_and_clear_FIFO(info);
841
842 /* read data port to reset things */
843 (void)inb(info->ioaddr + UART_RX);
844
845 if (info->board->must_hwid)
846 mxser_must_no_sw_flow_control(info->ioaddr);
847 }
848
849 /* make sure ISR is not running while we free the buffer */
850 synchronize_irq(info->board->irq);
851
852 tty_port_free_xmit_buf(port);
853}
854
855/*
856 * This routine is called whenever a serial port is opened. It
857 * enables interrupts for a serial port, linking in its async structure into
858 * the IRQ chain. It also performs the serial-specific
859 * initialization for the tty structure.
860 */
861static int mxser_open(struct tty_struct *tty, struct file *filp)
862{
863 struct tty_port *tport = tty->port;
864 struct mxser_port *port = container_of(tport, struct mxser_port, port);
865
866 tty->driver_data = port;
867
868 return tty_port_open(tport, tty, filp);
869}
870
871static void mxser_flush_buffer(struct tty_struct *tty)
872{
873 struct mxser_port *info = tty->driver_data;
874
875 scoped_guard(spinlock_irqsave, &info->slock) {
876 kfifo_reset(&info->port.xmit_fifo);
877
878 outb(info->FCR | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
879 info->ioaddr + UART_FCR);
880 }
881
882 tty_wakeup(tty);
883}
884
885static void mxser_close(struct tty_struct *tty, struct file *filp)
886{
887 tty_port_close(tty->port, tty, filp);
888}
889
890static ssize_t mxser_write(struct tty_struct *tty, const u8 *buf, size_t count)
891{
892 struct mxser_port *info = tty->driver_data;
893 size_t written;
894 bool is_empty;
895
896 scoped_guard(spinlock_irqsave, &info->slock) {
897 written = kfifo_in(&info->port.xmit_fifo, buf, count);
898 is_empty = kfifo_is_empty(&info->port.xmit_fifo);
899 }
900
901 if (!is_empty && !tty->flow.stopped)
902 if (!tty->hw_stopped || mxser_16550A_or_MUST(info))
903 mxser_start_tx(info);
904
905 return written;
906}
907
908static int mxser_put_char(struct tty_struct *tty, u8 ch)
909{
910 struct mxser_port *info = tty->driver_data;
911
912 guard(spinlock_irqsave)(&info->slock);
913 return kfifo_put(&info->port.xmit_fifo, ch);
914}
915
916
917static void mxser_flush_chars(struct tty_struct *tty)
918{
919 struct mxser_port *info = tty->driver_data;
920
921 if (kfifo_is_empty(&info->port.xmit_fifo) || tty->flow.stopped ||
922 (tty->hw_stopped && !mxser_16550A_or_MUST(info)))
923 return;
924
925 mxser_start_tx(info);
926}
927
928static unsigned int mxser_write_room(struct tty_struct *tty)
929{
930 struct mxser_port *info = tty->driver_data;
931
932 return kfifo_avail(&info->port.xmit_fifo);
933}
934
935static unsigned int mxser_chars_in_buffer(struct tty_struct *tty)
936{
937 struct mxser_port *info = tty->driver_data;
938
939 return kfifo_len(&info->port.xmit_fifo);
940}
941
942/*
943 * ------------------------------------------------------------
944 * friends of mxser_ioctl()
945 * ------------------------------------------------------------
946 */
947static int mxser_get_serial_info(struct tty_struct *tty,
948 struct serial_struct *ss)
949{
950 struct mxser_port *info = tty->driver_data;
951 struct tty_port *port = &info->port;
952 unsigned int closing_wait, close_delay;
953
954 guard(mutex)(&port->mutex);
955
956 close_delay = jiffies_to_msecs(info->port.close_delay) / 10;
957 closing_wait = info->port.closing_wait;
958 if (closing_wait != ASYNC_CLOSING_WAIT_NONE)
959 closing_wait = jiffies_to_msecs(closing_wait) / 10;
960
961 ss->type = info->type;
962 ss->line = tty->index;
963 ss->port = info->ioaddr;
964 ss->irq = info->board->irq;
965 ss->flags = info->port.flags;
966 ss->baud_base = MXSER_BAUD_BASE;
967 ss->close_delay = close_delay;
968 ss->closing_wait = closing_wait;
969 ss->custom_divisor = MXSER_CUSTOM_DIVISOR;
970
971 return 0;
972}
973
974static int mxser_set_serial_info(struct tty_struct *tty,
975 struct serial_struct *ss)
976{
977 struct mxser_port *info = tty->driver_data;
978 struct tty_port *port = &info->port;
979 speed_t baud;
980 unsigned int old_speed, close_delay, closing_wait;
981
982 if (tty_io_error(tty))
983 return -EIO;
984
985 guard(mutex)(&port->mutex);
986
987 if (ss->irq != info->board->irq || ss->port != info->ioaddr)
988 return -EINVAL;
989
990 old_speed = port->flags & ASYNC_SPD_MASK;
991
992 close_delay = msecs_to_jiffies(ss->close_delay * 10);
993 closing_wait = ss->closing_wait;
994 if (closing_wait != ASYNC_CLOSING_WAIT_NONE)
995 closing_wait = msecs_to_jiffies(closing_wait * 10);
996
997 if (!capable(CAP_SYS_ADMIN)) {
998 if ((ss->baud_base != MXSER_BAUD_BASE) ||
999 (close_delay != port->close_delay) ||
1000 (closing_wait != port->closing_wait) ||
1001 ((ss->flags & ~ASYNC_USR_MASK) != (port->flags & ~ASYNC_USR_MASK)))
1002 return -EPERM;
1003
1004 port->flags = (port->flags & ~ASYNC_USR_MASK) |
1005 (ss->flags & ASYNC_USR_MASK);
1006 } else {
1007 /*
1008 * OK, past this point, all the error checking has been done.
1009 * At this point, we start making changes.....
1010 */
1011 port->flags = ((port->flags & ~ASYNC_FLAGS) |
1012 (ss->flags & ASYNC_FLAGS));
1013 port->close_delay = close_delay;
1014 port->closing_wait = closing_wait;
1015 if ((port->flags & ASYNC_SPD_MASK) == ASYNC_SPD_CUST &&
1016 (ss->baud_base != MXSER_BAUD_BASE ||
1017 ss->custom_divisor !=
1018 MXSER_CUSTOM_DIVISOR)) {
1019 if (ss->custom_divisor == 0)
1020 return -EINVAL;
1021
1022 baud = ss->baud_base / ss->custom_divisor;
1023 tty_encode_baud_rate(tty, baud, baud);
1024 }
1025
1026 info->type = ss->type;
1027
1028 mxser_process_txrx_fifo(info);
1029 }
1030
1031 if (tty_port_initialized(port)) {
1032 if (old_speed != (port->flags & ASYNC_SPD_MASK)) {
1033 guard(spinlock_irqsave)(&info->slock);
1034 mxser_change_speed(tty, NULL);
1035 }
1036
1037 return 0;
1038 }
1039
1040 int retval = mxser_activate(port, tty);
1041 if (retval == 0)
1042 tty_port_set_initialized(port, true);
1043
1044 return retval;
1045}
1046
1047/*
1048 * mxser_get_lsr_info - get line status register info
1049 *
1050 * Purpose: Let user call ioctl() to get info when the UART physically
1051 * is emptied. On bus types like RS485, the transmitter must
1052 * release the bus after transmitting. This must be done when
1053 * the transmit shift register is empty, not be done when the
1054 * transmit holding register is empty. This functionality
1055 * allows an RS485 driver to be written in user space.
1056 */
1057static int mxser_get_lsr_info(struct mxser_port *info,
1058 unsigned int __user *value)
1059{
1060 unsigned int result;
1061 u8 status;
1062
1063 scoped_guard(spinlock_irqsave, &info->slock)
1064 status = inb(info->ioaddr + UART_LSR);
1065 result = ((status & UART_LSR_TEMT) ? TIOCSER_TEMT : 0);
1066 return put_user(result, value);
1067}
1068
1069static int mxser_tiocmget(struct tty_struct *tty)
1070{
1071 struct mxser_port *info = tty->driver_data;
1072 unsigned char control;
1073 u8 msr;
1074
1075 if (tty_io_error(tty))
1076 return -EIO;
1077
1078 scoped_guard(spinlock_irqsave, &info->slock) {
1079 control = info->MCR;
1080 msr = mxser_check_modem_status(tty, info);
1081 }
1082
1083 return ((control & UART_MCR_RTS) ? TIOCM_RTS : 0) |
1084 ((control & UART_MCR_DTR) ? TIOCM_DTR : 0) |
1085 ((msr & UART_MSR_DCD) ? TIOCM_CAR : 0) |
1086 ((msr & UART_MSR_RI) ? TIOCM_RNG : 0) |
1087 ((msr & UART_MSR_DSR) ? TIOCM_DSR : 0) |
1088 ((msr & UART_MSR_CTS) ? TIOCM_CTS : 0);
1089}
1090
1091static int mxser_tiocmset(struct tty_struct *tty,
1092 unsigned int set, unsigned int clear)
1093{
1094 struct mxser_port *info = tty->driver_data;
1095
1096 if (tty_io_error(tty))
1097 return -EIO;
1098
1099 guard(spinlock_irqsave)(&info->slock);
1100
1101 if (set & TIOCM_RTS)
1102 info->MCR |= UART_MCR_RTS;
1103 if (set & TIOCM_DTR)
1104 info->MCR |= UART_MCR_DTR;
1105
1106 if (clear & TIOCM_RTS)
1107 info->MCR &= ~UART_MCR_RTS;
1108 if (clear & TIOCM_DTR)
1109 info->MCR &= ~UART_MCR_DTR;
1110
1111 outb(info->MCR, info->ioaddr + UART_MCR);
1112
1113 return 0;
1114}
1115
1116static int mxser_cflags_changed(struct mxser_port *info, unsigned long arg,
1117 struct async_icount *cprev)
1118{
1119 struct async_icount cnow;
1120 int ret;
1121
1122 /* atomic copy */
1123 scoped_guard(spinlock_irqsave, &info->slock)
1124 cnow = info->icount;
1125
1126 ret = ((arg & TIOCM_RNG) && (cnow.rng != cprev->rng)) ||
1127 ((arg & TIOCM_DSR) && (cnow.dsr != cprev->dsr)) ||
1128 ((arg & TIOCM_CD) && (cnow.dcd != cprev->dcd)) ||
1129 ((arg & TIOCM_CTS) && (cnow.cts != cprev->cts));
1130
1131 *cprev = cnow;
1132
1133 return ret;
1134}
1135
1136/* We should likely switch to TIOCGRS485/TIOCSRS485. */
1137static int mxser_ioctl_op_mode(struct mxser_port *port, int index, bool set,
1138 int __user *u_opmode)
1139{
1140 int opmode, p = index % 4;
1141 int shiftbit = p * 2;
1142 u8 val;
1143
1144 if (port->board->must_hwid != MOXA_MUST_MU860_HWID)
1145 return -EFAULT;
1146
1147 if (set) {
1148 if (get_user(opmode, u_opmode))
1149 return -EFAULT;
1150
1151 if (opmode & ~OP_MODE_MASK)
1152 return -EINVAL;
1153
1154 guard(spinlock_irq)(&port->slock);
1155 val = inb(port->opmode_ioaddr);
1156 val &= ~(OP_MODE_MASK << shiftbit);
1157 val |= (opmode << shiftbit);
1158 outb(val, port->opmode_ioaddr);
1159
1160 return 0;
1161 }
1162
1163 scoped_guard(spinlock_irq, &port->slock)
1164 opmode = inb(port->opmode_ioaddr) >> shiftbit;
1165
1166 return put_user(opmode & OP_MODE_MASK, u_opmode);
1167}
1168
1169static int mxser_ioctl(struct tty_struct *tty,
1170 unsigned int cmd, unsigned long arg)
1171{
1172 struct mxser_port *info = tty->driver_data;
1173 struct async_icount cnow;
1174 void __user *argp = (void __user *)arg;
1175
1176 if (cmd == MOXA_SET_OP_MODE || cmd == MOXA_GET_OP_MODE)
1177 return mxser_ioctl_op_mode(info, tty->index,
1178 cmd == MOXA_SET_OP_MODE, argp);
1179
1180 if (cmd != TIOCMIWAIT && tty_io_error(tty))
1181 return -EIO;
1182
1183 switch (cmd) {
1184 case TIOCSERGETLSR: /* Get line status register */
1185 return mxser_get_lsr_info(info, argp);
1186 /*
1187 * Wait for any of the 4 modem inputs (DCD,RI,DSR,CTS) to change
1188 * - mask passed in arg for lines of interest
1189 * (use |'ed TIOCM_RNG/DSR/CD/CTS for masking)
1190 * Caller should use TIOCGICOUNT to see which one it was
1191 */
1192 case TIOCMIWAIT:
1193 /* note the counters on entry */
1194 scoped_guard(spinlock_irqsave, &info->slock)
1195 cnow = info->icount;
1196
1197 return wait_event_interruptible(info->port.delta_msr_wait,
1198 mxser_cflags_changed(info, arg, &cnow));
1199 default:
1200 return -ENOIOCTLCMD;
1201 }
1202 return 0;
1203}
1204
1205 /*
1206 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1207 * Return: write counters to the user passed counter struct
1208 * NB: both 1->0 and 0->1 transitions are counted except for
1209 * RI where only 0->1 is counted.
1210 */
1211
1212static int mxser_get_icount(struct tty_struct *tty,
1213 struct serial_icounter_struct *icount)
1214
1215{
1216 struct mxser_port *info = tty->driver_data;
1217 struct async_icount cnow;
1218
1219 scoped_guard(spinlock_irqsave, &info->slock)
1220 cnow = info->icount;
1221
1222 icount->frame = cnow.frame;
1223 icount->brk = cnow.brk;
1224 icount->overrun = cnow.overrun;
1225 icount->buf_overrun = cnow.buf_overrun;
1226 icount->parity = cnow.parity;
1227 icount->rx = cnow.rx;
1228 icount->tx = cnow.tx;
1229 icount->cts = cnow.cts;
1230 icount->dsr = cnow.dsr;
1231 icount->rng = cnow.rng;
1232 icount->dcd = cnow.dcd;
1233 return 0;
1234}
1235
1236/*
1237 * This routine is called by the upper-layer tty layer to signal that
1238 * incoming characters should be throttled.
1239 */
1240static void mxser_throttle(struct tty_struct *tty)
1241{
1242 struct mxser_port *info = tty->driver_data;
1243
1244 if (I_IXOFF(tty)) {
1245 if (info->board->must_hwid) {
1246 info->IER &= ~MOXA_MUST_RECV_ISR;
1247 outb(info->IER, info->ioaddr + UART_IER);
1248 } else {
1249 info->x_char = STOP_CHAR(tty);
1250 outb(0, info->ioaddr + UART_IER);
1251 info->IER |= UART_IER_THRI;
1252 outb(info->IER, info->ioaddr + UART_IER);
1253 }
1254 }
1255
1256 if (C_CRTSCTS(tty)) {
1257 info->MCR &= ~UART_MCR_RTS;
1258 outb(info->MCR, info->ioaddr + UART_MCR);
1259 }
1260}
1261
1262static void mxser_unthrottle(struct tty_struct *tty)
1263{
1264 struct mxser_port *info = tty->driver_data;
1265
1266 /* startrx */
1267 if (I_IXOFF(tty)) {
1268 if (info->x_char)
1269 info->x_char = 0;
1270 else {
1271 if (info->board->must_hwid) {
1272 info->IER |= MOXA_MUST_RECV_ISR;
1273 outb(info->IER, info->ioaddr + UART_IER);
1274 } else {
1275 info->x_char = START_CHAR(tty);
1276 outb(0, info->ioaddr + UART_IER);
1277 info->IER |= UART_IER_THRI;
1278 outb(info->IER, info->ioaddr + UART_IER);
1279 }
1280 }
1281 }
1282
1283 if (C_CRTSCTS(tty)) {
1284 info->MCR |= UART_MCR_RTS;
1285 outb(info->MCR, info->ioaddr + UART_MCR);
1286 }
1287}
1288
1289/*
1290 * mxser_stop() and mxser_start()
1291 *
1292 * This routines are called before setting or resetting tty->flow.stopped.
1293 * They enable or disable transmitter interrupts, as necessary.
1294 */
1295static void mxser_stop(struct tty_struct *tty)
1296{
1297 struct mxser_port *info = tty->driver_data;
1298
1299 guard(spinlock_irqsave)(&info->slock);
1300 if (info->IER & UART_IER_THRI)
1301 __mxser_stop_tx(info);
1302}
1303
1304static void mxser_start(struct tty_struct *tty)
1305{
1306 struct mxser_port *info = tty->driver_data;
1307
1308 guard(spinlock_irqsave)(&info->slock);
1309 if (!kfifo_is_empty(&info->port.xmit_fifo))
1310 __mxser_start_tx(info);
1311}
1312
1313static void mxser_set_termios(struct tty_struct *tty,
1314 const struct ktermios *old_termios)
1315{
1316 struct mxser_port *info = tty->driver_data;
1317
1318 scoped_guard(spinlock_irqsave, &info->slock)
1319 mxser_change_speed(tty, old_termios);
1320
1321 if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty)) {
1322 tty->hw_stopped = false;
1323 mxser_start(tty);
1324 }
1325
1326 /* Handle sw stopped */
1327 if ((old_termios->c_iflag & IXON) && !I_IXON(tty)) {
1328 tty->flow.stopped = 0;
1329
1330 if (info->board->must_hwid) {
1331 guard(spinlock_irqsave)(&info->slock);
1332 mxser_must_set_rx_sw_flow_control(info->ioaddr, false);
1333 }
1334
1335 mxser_start(tty);
1336 }
1337}
1338
1339static bool mxser_tx_empty(struct mxser_port *info)
1340{
1341 guard(spinlock_irqsave)(&info->slock);
1342 return !(inb(info->ioaddr + UART_LSR) & UART_LSR_TEMT);
1343}
1344
1345/*
1346 * mxser_wait_until_sent() --- wait until the transmitter is empty
1347 */
1348static void mxser_wait_until_sent(struct tty_struct *tty, int timeout)
1349{
1350 struct mxser_port *info = tty->driver_data;
1351 unsigned long expire, char_time;
1352
1353 if (info->type == PORT_UNKNOWN)
1354 return;
1355
1356 if (info->xmit_fifo_size == 0)
1357 return; /* Just in case.... */
1358
1359 /*
1360 * Set the check interval to be 1/5 of the estimated time to
1361 * send a single character, and make it at least 1. The check
1362 * interval should also be less than the timeout.
1363 *
1364 * Note: we have to use pretty tight timings here to satisfy
1365 * the NIST-PCTS.
1366 */
1367 char_time = (info->timeout - HZ / 50) / info->xmit_fifo_size;
1368 char_time = char_time / 5;
1369 if (char_time == 0)
1370 char_time = 1;
1371 if (timeout && timeout < char_time)
1372 char_time = timeout;
1373
1374 char_time = jiffies_to_msecs(char_time);
1375
1376 /*
1377 * If the transmitter hasn't cleared in twice the approximate
1378 * amount of time to send the entire FIFO, it probably won't
1379 * ever clear. This assumes the UART isn't doing flow
1380 * control, which is currently the case. Hence, if it ever
1381 * takes longer than info->timeout, this is probably due to a
1382 * UART bug of some kind. So, we clamp the timeout parameter at
1383 * 2*info->timeout.
1384 */
1385 if (!timeout || timeout > 2 * info->timeout)
1386 timeout = 2 * info->timeout;
1387
1388 expire = jiffies + timeout;
1389
1390 while (mxser_tx_empty(info)) {
1391 msleep_interruptible(char_time);
1392 if (signal_pending(current))
1393 break;
1394 if (time_after(jiffies, expire))
1395 break;
1396 }
1397}
1398
1399/*
1400 * This routine is called by tty_hangup() when a hangup is signaled.
1401 */
1402static void mxser_hangup(struct tty_struct *tty)
1403{
1404 struct mxser_port *info = tty->driver_data;
1405
1406 mxser_flush_buffer(tty);
1407 tty_port_hangup(&info->port);
1408}
1409
1410/*
1411 * mxser_rs_break() --- routine which turns the break handling on or off
1412 */
1413static int mxser_rs_break(struct tty_struct *tty, int break_state)
1414{
1415 struct mxser_port *info = tty->driver_data;
1416 u8 lcr;
1417
1418 guard(spinlock_irqsave)(&info->slock);
1419 lcr = inb(info->ioaddr + UART_LCR);
1420 if (break_state == -1)
1421 lcr |= UART_LCR_SBC;
1422 else
1423 lcr &= ~UART_LCR_SBC;
1424 outb(lcr, info->ioaddr + UART_LCR);
1425
1426 return 0;
1427}
1428
1429static bool mxser_receive_chars_new(struct mxser_port *port, u8 status)
1430{
1431 enum mxser_must_hwid hwid = port->board->must_hwid;
1432 u8 gdl;
1433
1434 if (hwid == MOXA_OTHER_UART)
1435 return false;
1436 if (status & (UART_LSR_BRK_ERROR_BITS | MOXA_MUST_LSR_RERR))
1437 return false;
1438
1439 gdl = inb(port->ioaddr + MOXA_MUST_GDL_REGISTER);
1440 if (hwid == MOXA_MUST_MU150_HWID)
1441 gdl &= MOXA_MUST_GDL_MASK;
1442
1443 while (gdl--) {
1444 u8 ch = inb(port->ioaddr + UART_RX);
1445 if (!tty_insert_flip_char(&port->port, ch, 0))
1446 port->icount.buf_overrun++;
1447 }
1448
1449 return true;
1450}
1451
1452static u8 mxser_receive_chars_old(struct tty_struct *tty,
1453 struct mxser_port *port, u8 status)
1454{
1455 enum mxser_must_hwid hwid = port->board->must_hwid;
1456 int ignored = 0;
1457 int max = 256;
1458 u8 ch;
1459
1460 do {
1461 if (max-- < 0)
1462 break;
1463
1464 ch = inb(port->ioaddr + UART_RX);
1465 if (hwid && (status & UART_LSR_OE))
1466 outb(port->FCR | UART_FCR_CLEAR_RCVR,
1467 port->ioaddr + UART_FCR);
1468 status &= port->read_status_mask;
1469 if (status & port->ignore_status_mask) {
1470 if (++ignored > 100)
1471 break;
1472 } else {
1473 u8 flag = 0;
1474 if (status & UART_LSR_BRK_ERROR_BITS) {
1475 if (status & UART_LSR_BI) {
1476 flag = TTY_BREAK;
1477 port->icount.brk++;
1478
1479 if (port->port.flags & ASYNC_SAK)
1480 do_SAK(tty);
1481 } else if (status & UART_LSR_PE) {
1482 flag = TTY_PARITY;
1483 port->icount.parity++;
1484 } else if (status & UART_LSR_FE) {
1485 flag = TTY_FRAME;
1486 port->icount.frame++;
1487 } else if (status & UART_LSR_OE) {
1488 flag = TTY_OVERRUN;
1489 port->icount.overrun++;
1490 }
1491 }
1492 if (!tty_insert_flip_char(&port->port, ch, flag)) {
1493 port->icount.buf_overrun++;
1494 break;
1495 }
1496 }
1497
1498 if (hwid)
1499 break;
1500
1501 status = inb(port->ioaddr + UART_LSR);
1502 } while (status & UART_LSR_DR);
1503
1504 return status;
1505}
1506
1507static u8 mxser_receive_chars(struct tty_struct *tty,
1508 struct mxser_port *port, u8 status)
1509{
1510 if (!mxser_receive_chars_new(port, status))
1511 status = mxser_receive_chars_old(tty, port, status);
1512
1513 tty_flip_buffer_push(&port->port);
1514
1515 return status;
1516}
1517
1518static void mxser_transmit_chars(struct tty_struct *tty, struct mxser_port *port)
1519{
1520 int count;
1521
1522 if (port->x_char) {
1523 outb(port->x_char, port->ioaddr + UART_TX);
1524 port->x_char = 0;
1525 port->icount.tx++;
1526 return;
1527 }
1528
1529 if (kfifo_is_empty(&port->port.xmit_fifo) || tty->flow.stopped ||
1530 (tty->hw_stopped && !mxser_16550A_or_MUST(port))) {
1531 __mxser_stop_tx(port);
1532 return;
1533 }
1534
1535 count = port->xmit_fifo_size;
1536 do {
1537 u8 c;
1538
1539 if (!kfifo_get(&port->port.xmit_fifo, &c))
1540 break;
1541
1542 outb(c, port->ioaddr + UART_TX);
1543 port->icount.tx++;
1544 } while (--count > 0);
1545
1546 if (kfifo_len(&port->port.xmit_fifo) < WAKEUP_CHARS)
1547 tty_wakeup(tty);
1548
1549 if (kfifo_is_empty(&port->port.xmit_fifo))
1550 __mxser_stop_tx(port);
1551}
1552
1553static bool mxser_port_isr(struct mxser_port *port)
1554{
1555 u8 iir, status;
1556
1557 iir = inb(port->ioaddr + UART_IIR);
1558 if (iir & UART_IIR_NO_INT)
1559 return true;
1560
1561 iir &= MOXA_MUST_IIR_MASK;
1562
1563 scoped_guard(tty_port_tty, &port->port) {
1564 struct tty_struct *tty = scoped_tty();
1565
1566 status = inb(port->ioaddr + UART_LSR);
1567
1568 if (port->board->must_hwid) {
1569 if (iir == MOXA_MUST_IIR_GDA ||
1570 iir == MOXA_MUST_IIR_RDA ||
1571 iir == MOXA_MUST_IIR_RTO ||
1572 iir == MOXA_MUST_IIR_LSR)
1573 status = mxser_receive_chars(tty, port, status);
1574 } else {
1575 status &= port->read_status_mask;
1576 if (status & UART_LSR_DR)
1577 status = mxser_receive_chars(tty, port, status);
1578 }
1579
1580 mxser_check_modem_status(tty, port);
1581
1582 if (port->board->must_hwid) {
1583 if (iir == 0x02 && (status & UART_LSR_THRE))
1584 mxser_transmit_chars(tty, port);
1585 } else {
1586 if (status & UART_LSR_THRE)
1587 mxser_transmit_chars(tty, port);
1588 }
1589
1590 return false;
1591 }
1592
1593 status = inb(port->ioaddr + UART_LSR);
1594 outb(port->FCR | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
1595 port->ioaddr + UART_FCR);
1596 inb(port->ioaddr + UART_MSR);
1597
1598 return true;
1599}
1600
1601/*
1602 * This is the serial driver's generic interrupt routine
1603 */
1604static irqreturn_t mxser_interrupt(int irq, void *dev_id)
1605{
1606 struct mxser_board *brd = dev_id;
1607 struct mxser_port *port;
1608 unsigned int int_cnt, pass_counter = 0;
1609 unsigned int i, max = brd->nports;
1610 int handled = IRQ_NONE;
1611 u8 irqbits, bits, mask = BIT(max) - 1;
1612
1613 while (pass_counter++ < MXSER_ISR_PASS_LIMIT) {
1614 irqbits = inb(brd->vector) & mask;
1615 if (irqbits == mask)
1616 break;
1617
1618 handled = IRQ_HANDLED;
1619 for (i = 0, bits = 1; i < max; i++, irqbits |= bits, bits <<= 1) {
1620 if (irqbits == mask)
1621 break;
1622 if (bits & irqbits)
1623 continue;
1624 port = &brd->ports[i];
1625
1626 int_cnt = 0;
1627 guard(spinlock)(&port->slock);
1628 do {
1629 if (mxser_port_isr(port))
1630 break;
1631 } while (int_cnt++ < MXSER_ISR_PASS_LIMIT);
1632 }
1633 }
1634
1635 return handled;
1636}
1637
1638static const struct tty_operations mxser_ops = {
1639 .open = mxser_open,
1640 .close = mxser_close,
1641 .write = mxser_write,
1642 .put_char = mxser_put_char,
1643 .flush_chars = mxser_flush_chars,
1644 .write_room = mxser_write_room,
1645 .chars_in_buffer = mxser_chars_in_buffer,
1646 .flush_buffer = mxser_flush_buffer,
1647 .ioctl = mxser_ioctl,
1648 .throttle = mxser_throttle,
1649 .unthrottle = mxser_unthrottle,
1650 .set_termios = mxser_set_termios,
1651 .stop = mxser_stop,
1652 .start = mxser_start,
1653 .hangup = mxser_hangup,
1654 .break_ctl = mxser_rs_break,
1655 .wait_until_sent = mxser_wait_until_sent,
1656 .tiocmget = mxser_tiocmget,
1657 .tiocmset = mxser_tiocmset,
1658 .set_serial = mxser_set_serial_info,
1659 .get_serial = mxser_get_serial_info,
1660 .get_icount = mxser_get_icount,
1661};
1662
1663static const struct tty_port_operations mxser_port_ops = {
1664 .carrier_raised = mxser_carrier_raised,
1665 .dtr_rts = mxser_dtr_rts,
1666 .activate = mxser_activate,
1667 .shutdown = mxser_shutdown_port,
1668};
1669
1670/*
1671 * The MOXA Smartio/Industio serial driver boot-time initialization code!
1672 */
1673
1674static void mxser_initbrd(struct mxser_board *brd, bool high_baud)
1675{
1676 struct mxser_port *info;
1677 unsigned int i;
1678 bool is_mu860;
1679
1680 brd->must_hwid = mxser_must_get_hwid(brd->ports[0].ioaddr);
1681 is_mu860 = brd->must_hwid == MOXA_MUST_MU860_HWID;
1682
1683 for (i = 0; i < UART_INFO_NUM; i++) {
1684 if (Gpci_uart_info[i].type == brd->must_hwid) {
1685 brd->max_baud = Gpci_uart_info[i].max_baud;
1686
1687 /* exception....CP-102 */
1688 if (high_baud)
1689 brd->max_baud = 921600;
1690 break;
1691 }
1692 }
1693
1694 if (is_mu860) {
1695 /* set to RS232 mode by default */
1696 outb(0, brd->vector + 4);
1697 outb(0, brd->vector + 0x0c);
1698 }
1699
1700 for (i = 0; i < brd->nports; i++) {
1701 info = &brd->ports[i];
1702 if (is_mu860) {
1703 if (i < 4)
1704 info->opmode_ioaddr = brd->vector + 4;
1705 else
1706 info->opmode_ioaddr = brd->vector + 0x0c;
1707 }
1708 tty_port_init(&info->port);
1709 info->port.ops = &mxser_port_ops;
1710 info->board = brd;
1711
1712 /* Enhance mode enabled here */
1713 if (brd->must_hwid != MOXA_OTHER_UART)
1714 mxser_must_set_enhance_mode(info->ioaddr, true);
1715
1716 info->type = PORT_16550A;
1717
1718 mxser_process_txrx_fifo(info);
1719
1720 spin_lock_init(&info->slock);
1721
1722 /* before set INT ISR, disable all int */
1723 outb(inb(info->ioaddr + UART_IER) & 0xf0,
1724 info->ioaddr + UART_IER);
1725 }
1726}
1727
1728static int mxser_probe(struct pci_dev *pdev,
1729 const struct pci_device_id *ent)
1730{
1731 struct mxser_board *brd;
1732 unsigned int i, base;
1733 unsigned long ioaddress;
1734 unsigned short nports = MXSER_NPORTS(ent->driver_data);
1735 struct device *tty_dev;
1736 int retval = -EINVAL;
1737
1738 i = find_first_zero_bit(mxser_boards, MXSER_BOARDS);
1739 if (i >= MXSER_BOARDS) {
1740 dev_err(&pdev->dev, "too many boards found (maximum %d), board "
1741 "not configured\n", MXSER_BOARDS);
1742 goto err;
1743 }
1744
1745 brd = devm_kzalloc(&pdev->dev, struct_size(brd, ports, nports),
1746 GFP_KERNEL);
1747 if (!brd)
1748 goto err;
1749
1750 brd->idx = i;
1751 __set_bit(brd->idx, mxser_boards);
1752 base = i * MXSER_PORTS_PER_BOARD;
1753
1754 retval = pcim_enable_device(pdev);
1755 if (retval) {
1756 dev_err(&pdev->dev, "PCI enable failed\n");
1757 goto err_zero;
1758 }
1759
1760 /* io address */
1761 ioaddress = pci_resource_start(pdev, 2);
1762 retval = pcim_request_region(pdev, 2, "mxser(IO)");
1763 if (retval)
1764 goto err_zero;
1765
1766 brd->nports = nports;
1767 for (i = 0; i < nports; i++)
1768 brd->ports[i].ioaddr = ioaddress + 8 * i;
1769
1770 /* vector */
1771 ioaddress = pci_resource_start(pdev, 3);
1772 retval = pcim_request_region(pdev, 3, "mxser(vector)");
1773 if (retval)
1774 goto err_zero;
1775 brd->vector = ioaddress;
1776
1777 /* irq */
1778 brd->irq = pdev->irq;
1779
1780 mxser_initbrd(brd, ent->driver_data & MXSER_HIGHBAUD);
1781
1782 retval = devm_request_irq(&pdev->dev, brd->irq, mxser_interrupt,
1783 IRQF_SHARED, "mxser", brd);
1784 if (retval) {
1785 dev_err(&pdev->dev, "request irq failed");
1786 goto err_relbrd;
1787 }
1788
1789 for (i = 0; i < nports; i++) {
1790 tty_dev = tty_port_register_device(&brd->ports[i].port,
1791 mxvar_sdriver, base + i, &pdev->dev);
1792 if (IS_ERR(tty_dev)) {
1793 retval = PTR_ERR(tty_dev);
1794 for (; i > 0; i--)
1795 tty_unregister_device(mxvar_sdriver,
1796 base + i - 1);
1797 goto err_relbrd;
1798 }
1799 }
1800
1801 pci_set_drvdata(pdev, brd);
1802
1803 return 0;
1804err_relbrd:
1805 for (i = 0; i < nports; i++)
1806 tty_port_destroy(&brd->ports[i].port);
1807err_zero:
1808 __clear_bit(brd->idx, mxser_boards);
1809err:
1810 return retval;
1811}
1812
1813static void mxser_remove(struct pci_dev *pdev)
1814{
1815 struct mxser_board *brd = pci_get_drvdata(pdev);
1816 unsigned int i, base = brd->idx * MXSER_PORTS_PER_BOARD;
1817
1818 for (i = 0; i < brd->nports; i++) {
1819 tty_unregister_device(mxvar_sdriver, base + i);
1820 tty_port_destroy(&brd->ports[i].port);
1821 }
1822
1823 __clear_bit(brd->idx, mxser_boards);
1824}
1825
1826static struct pci_driver mxser_driver = {
1827 .name = "mxser",
1828 .id_table = mxser_pcibrds,
1829 .probe = mxser_probe,
1830 .remove = mxser_remove
1831};
1832
1833static int __init mxser_module_init(void)
1834{
1835 int retval;
1836
1837 mxvar_sdriver = tty_alloc_driver(MXSER_PORTS, TTY_DRIVER_REAL_RAW |
1838 TTY_DRIVER_DYNAMIC_DEV);
1839 if (IS_ERR(mxvar_sdriver))
1840 return PTR_ERR(mxvar_sdriver);
1841
1842 /* Initialize the tty_driver structure */
1843 mxvar_sdriver->name = "ttyMI";
1844 mxvar_sdriver->major = ttymajor;
1845 mxvar_sdriver->minor_start = 0;
1846 mxvar_sdriver->type = TTY_DRIVER_TYPE_SERIAL;
1847 mxvar_sdriver->subtype = SERIAL_TYPE_NORMAL;
1848 mxvar_sdriver->init_termios = tty_std_termios;
1849 mxvar_sdriver->init_termios.c_cflag = B9600|CS8|CREAD|HUPCL|CLOCAL;
1850 tty_set_operations(mxvar_sdriver, &mxser_ops);
1851
1852 retval = tty_register_driver(mxvar_sdriver);
1853 if (retval) {
1854 printk(KERN_ERR "Couldn't install MOXA Smartio/Industio family "
1855 "tty driver !\n");
1856 goto err_put;
1857 }
1858
1859 retval = pci_register_driver(&mxser_driver);
1860 if (retval) {
1861 printk(KERN_ERR "mxser: can't register pci driver\n");
1862 goto err_unr;
1863 }
1864
1865 return 0;
1866err_unr:
1867 tty_unregister_driver(mxvar_sdriver);
1868err_put:
1869 tty_driver_kref_put(mxvar_sdriver);
1870 return retval;
1871}
1872
1873static void __exit mxser_module_exit(void)
1874{
1875 pci_unregister_driver(&mxser_driver);
1876 tty_unregister_driver(mxvar_sdriver);
1877 tty_driver_kref_put(mxvar_sdriver);
1878}
1879
1880module_init(mxser_module_init);
1881module_exit(mxser_module_exit);