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2883 lines · 78.4 KiB

1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Driver for Motorola/Freescale IMX serial ports
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Author: Sascha Hauer <[email protected]>
8 * Copyright (C) 2004 Pengutronix
9 */
10
11#include <linux/circ_buf.h>
12#include <linux/module.h>
13#include <linux/ioport.h>
14#include <linux/init.h>
15#include <linux/console.h>
16#include <linux/sysrq.h>
17#include <linux/platform_device.h>
18#include <linux/tty.h>
19#include <linux/tty_flip.h>
20#include <linux/serial_core.h>
21#include <linux/serial.h>
22#include <linux/clk.h>
23#include <linux/delay.h>
24#include <linux/ktime.h>
25#include <linux/mutex.h>
26#include <linux/pinctrl/consumer.h>
27#include <linux/rational.h>
28#include <linux/slab.h>
29#include <linux/of.h>
30#include <linux/io.h>
31#include <linux/iopoll.h>
32#include <linux/dma-mapping.h>
33
34#include <linux/irq.h>
35#include <linux/dma/imx-dma.h>
36
37#include "serial_mctrl_gpio.h"
38
39/* Register definitions */
40#define URXD0 0x0 /* Receiver Register */
41#define URTX0 0x40 /* Transmitter Register */
42#define UCR1 0x80 /* Control Register 1 */
43#define UCR2 0x84 /* Control Register 2 */
44#define UCR3 0x88 /* Control Register 3 */
45#define UCR4 0x8c /* Control Register 4 */
46#define UFCR 0x90 /* FIFO Control Register */
47#define USR1 0x94 /* Status Register 1 */
48#define USR2 0x98 /* Status Register 2 */
49#define UESC 0x9c /* Escape Character Register */
50#define UTIM 0xa0 /* Escape Timer Register */
51#define UBIR 0xa4 /* BRM Incremental Register */
52#define UBMR 0xa8 /* BRM Modulator Register */
53#define UBRC 0xac /* Baud Rate Count Register */
54#define IMX21_ONEMS 0xb0 /* One Millisecond register */
55#define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
56#define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
57
58/* UART Control Register Bit Fields.*/
59#define URXD_DUMMY_READ (1<<16)
60#define URXD_CHARRDY (1<<15)
61#define URXD_ERR (1<<14)
62#define URXD_OVRRUN (1<<13)
63#define URXD_FRMERR (1<<12)
64#define URXD_BRK (1<<11)
65#define URXD_PRERR (1<<10)
66#define URXD_RX_DATA (0xFF<<0)
67#define UCR1_ADEN (1<<15) /* Auto detect interrupt */
68#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
69#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
70#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
71#define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
72#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
73#define UCR1_RXDMAEN (1<<8) /* Recv ready DMA enable */
74#define UCR1_IREN (1<<7) /* Infrared interface enable */
75#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
76#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
77#define UCR1_SNDBRK (1<<4) /* Send break */
78#define UCR1_TXDMAEN (1<<3) /* Transmitter ready DMA enable */
79#define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
80#define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */
81#define UCR1_DOZE (1<<1) /* Doze */
82#define UCR1_UARTEN (1<<0) /* UART enabled */
83#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
84#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
85#define UCR2_CTSC (1<<13) /* CTS pin control */
86#define UCR2_CTS (1<<12) /* Clear to send */
87#define UCR2_ESCEN (1<<11) /* Escape enable */
88#define UCR2_PREN (1<<8) /* Parity enable */
89#define UCR2_PROE (1<<7) /* Parity odd/even */
90#define UCR2_STPB (1<<6) /* Stop */
91#define UCR2_WS (1<<5) /* Word size */
92#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
93#define UCR2_ATEN (1<<3) /* Aging Timer Enable */
94#define UCR2_TXEN (1<<2) /* Transmitter enabled */
95#define UCR2_RXEN (1<<1) /* Receiver enabled */
96#define UCR2_SRST (1<<0) /* SW reset */
97#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
98#define UCR3_PARERREN (1<<12) /* Parity enable */
99#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
100#define UCR3_DSR (1<<10) /* Data set ready */
101#define UCR3_DCD (1<<9) /* Data carrier detect */
102#define UCR3_RI (1<<8) /* Ring indicator */
103#define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
104#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
105#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
106#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
107#define UCR3_DTRDEN (1<<3) /* Data Terminal Ready Delta Enable. */
108#define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
109#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
110#define UCR3_BPEN (1<<0) /* Preset registers enable */
111#define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
112#define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
113#define UCR4_INVR (1<<9) /* Inverted infrared reception */
114#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
115#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
116#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
117#define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */
118#define UCR4_IRSC (1<<5) /* IR special case */
119#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
120#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
121#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
122#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
123#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
124#define UFCR_RXTL_MASK 0x3F /* Receiver trigger 6 bits wide */
125#define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
126#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
127#define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
128#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
129#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
130#define USR1_RTSS (1<<14) /* RTS pin status */
131#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
132#define USR1_RTSD (1<<12) /* RTS delta */
133#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
134#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
135#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
136#define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */
137#define USR1_DTRD (1<<7) /* DTR Delta */
138#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
139#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
140#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
141#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
142#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
143#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
144#define USR2_IDLE (1<<12) /* Idle condition */
145#define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */
146#define USR2_RIIN (1<<9) /* Ring Indicator Input */
147#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
148#define USR2_WAKE (1<<7) /* Wake */
149#define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */
150#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
151#define USR2_TXDC (1<<3) /* Transmitter complete */
152#define USR2_BRCD (1<<2) /* Break condition */
153#define USR2_ORE (1<<1) /* Overrun error */
154#define USR2_RDR (1<<0) /* Recv data ready */
155#define UTS_FRCPERR (1<<13) /* Force parity error */
156#define UTS_LOOP (1<<12) /* Loop tx and rx */
157#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
158#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
159#define UTS_TXFULL (1<<4) /* TxFIFO full */
160#define UTS_RXFULL (1<<3) /* RxFIFO full */
161#define UTS_SOFTRST (1<<0) /* Software reset */
162
163/* We've been assigned a range on the "Low-density serial ports" major */
164#define SERIAL_IMX_MAJOR 207
165#define MINOR_START 16
166#define DEV_NAME "ttymxc"
167
168/*
169 * This determines how often we check the modem status signals
170 * for any change. They generally aren't connected to an IRQ
171 * so we have to poll them. We also check immediately before
172 * filling the TX fifo incase CTS has been dropped.
173 */
174#define MCTRL_TIMEOUT (250*HZ/1000)
175
176#define DRIVER_NAME "IMX-uart"
177
178#define UART_NR 8
179
180/* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */
181enum imx_uart_type {
182 IMX1_UART,
183 IMX21_UART,
184};
185
186/* device type dependent stuff */
187struct imx_uart_data {
188 unsigned uts_reg;
189 enum imx_uart_type devtype;
190};
191
192enum imx_tx_state {
193 OFF,
194 WAIT_AFTER_RTS,
195 SEND,
196 WAIT_AFTER_SEND,
197};
198
199struct imx_port {
200 struct uart_port port;
201 struct timer_list timer;
202 unsigned int old_status;
203 unsigned int have_rtscts:1;
204 unsigned int have_rtsgpio:1;
205 unsigned int dte_mode:1;
206 unsigned int inverted_tx:1;
207 unsigned int inverted_rx:1;
208 struct clk *clk_ipg;
209 struct clk *clk_per;
210 const struct imx_uart_data *devdata;
211
212 struct mctrl_gpios *gpios;
213
214 /* counter to stop 0xff flood */
215 int idle_counter;
216
217 /* DMA fields */
218 unsigned int dma_is_enabled:1;
219 unsigned int dma_is_rxing:1;
220 unsigned int dma_is_txing:1;
221 struct dma_chan *dma_chan_rx, *dma_chan_tx;
222 struct scatterlist rx_sgl, tx_sgl[2];
223 void *rx_buf;
224 struct circ_buf rx_ring;
225 unsigned int rx_buf_size;
226 unsigned int rx_period_length;
227 unsigned int rx_periods;
228 dma_cookie_t rx_cookie;
229 unsigned int tx_bytes;
230 unsigned int dma_tx_nents;
231 unsigned int saved_reg[10];
232 bool context_saved;
233
234 bool last_putchar_was_newline;
235
236 enum imx_tx_state tx_state;
237 struct hrtimer trigger_start_tx;
238 struct hrtimer trigger_stop_tx;
239 unsigned int rxtl;
240};
241
242struct imx_port_ucrs {
243 unsigned int ucr1;
244 unsigned int ucr2;
245 unsigned int ucr3;
246};
247
248static const struct imx_uart_data imx_uart_imx1_devdata = {
249 .uts_reg = IMX1_UTS,
250 .devtype = IMX1_UART,
251};
252
253static const struct imx_uart_data imx_uart_imx21_devdata = {
254 .uts_reg = IMX21_UTS,
255 .devtype = IMX21_UART,
256};
257
258static const struct of_device_id imx_uart_dt_ids[] = {
259 /*
260 * For reasons unknown to me, some UART devices (e.g. imx6ul's) are
261 * compatible to fsl,imx6q-uart, but not fsl,imx21-uart, while the
262 * original imx6q's UART is compatible to fsl,imx21-uart. This driver
263 * doesn't make any distinction between these two variants.
264 */
265 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_imx21_devdata, },
266 { .compatible = "fsl,imx1-uart", .data = &imx_uart_imx1_devdata, },
267 { .compatible = "fsl,imx21-uart", .data = &imx_uart_imx21_devdata, },
268 { /* sentinel */ }
269};
270MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
271
272static inline struct imx_port *to_imx_port(struct uart_port *port)
273{
274 return container_of(port, struct imx_port, port);
275}
276
277static inline void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset)
278{
279 writel(val, sport->port.membase + offset);
280}
281
282static inline u32 imx_uart_readl(struct imx_port *sport, u32 offset)
283{
284 return readl(sport->port.membase + offset);
285}
286
287static inline unsigned imx_uart_uts_reg(struct imx_port *sport)
288{
289 return sport->devdata->uts_reg;
290}
291
292static inline int imx_uart_is_imx1(struct imx_port *sport)
293{
294 return sport->devdata->devtype == IMX1_UART;
295}
296
297/*
298 * Save and restore functions for UCR1, UCR2 and UCR3 registers
299 */
300#if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE)
301static void imx_uart_ucrs_save(struct imx_port *sport,
302 struct imx_port_ucrs *ucr)
303{
304 /* save control registers */
305 ucr->ucr1 = imx_uart_readl(sport, UCR1);
306 ucr->ucr2 = imx_uart_readl(sport, UCR2);
307 ucr->ucr3 = imx_uart_readl(sport, UCR3);
308}
309
310static void imx_uart_ucrs_restore(struct imx_port *sport,
311 struct imx_port_ucrs *ucr)
312{
313 /* restore control registers */
314 imx_uart_writel(sport, ucr->ucr1, UCR1);
315 imx_uart_writel(sport, ucr->ucr2, UCR2);
316 imx_uart_writel(sport, ucr->ucr3, UCR3);
317}
318#endif
319
320/* called with port.lock taken and irqs caller dependent */
321static void imx_uart_rts_active(struct imx_port *sport, u32 *ucr2)
322{
323 *ucr2 &= ~(UCR2_CTSC | UCR2_CTS);
324
325 mctrl_gpio_set(sport->gpios, sport->port.mctrl | TIOCM_RTS);
326}
327
328/* called with port.lock taken and irqs caller dependent */
329static void imx_uart_rts_inactive(struct imx_port *sport, u32 *ucr2)
330{
331 *ucr2 &= ~UCR2_CTSC;
332 *ucr2 |= UCR2_CTS;
333
334 mctrl_gpio_set(sport->gpios, sport->port.mctrl & ~TIOCM_RTS);
335}
336
337static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec)
338{
339 hrtimer_start(hrt, ms_to_ktime(msec), HRTIMER_MODE_REL);
340}
341
342/* called with port.lock taken and irqs off */
343static void imx_uart_soft_reset(struct imx_port *sport)
344{
345 int i = 10;
346 u32 ucr2, ubir, ubmr, uts;
347
348 /*
349 * According to the Reference Manual description of the UART SRST bit:
350 *
351 * "Reset the transmit and receive state machines,
352 * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD
353 * and UTS[6-3]".
354 *
355 * We don't need to restore the old values from USR1, USR2, URXD and
356 * UTXD. UBRC is read only, so only save/restore the other three
357 * registers.
358 */
359 ubir = imx_uart_readl(sport, UBIR);
360 ubmr = imx_uart_readl(sport, UBMR);
361 uts = imx_uart_readl(sport, IMX21_UTS);
362
363 ucr2 = imx_uart_readl(sport, UCR2);
364 imx_uart_writel(sport, ucr2 & ~UCR2_SRST, UCR2);
365
366 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0))
367 udelay(1);
368
369 /* Restore the registers */
370 imx_uart_writel(sport, ubir, UBIR);
371 imx_uart_writel(sport, ubmr, UBMR);
372 imx_uart_writel(sport, uts, IMX21_UTS);
373
374 sport->idle_counter = 0;
375}
376
377/* called with port.lock taken and irqs off */
378static void imx_uart_disable_loopback_rs485(struct imx_port *sport)
379{
380 unsigned int uts;
381
382 /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */
383 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
384 uts &= ~UTS_LOOP;
385 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
386}
387
388/* called with port.lock taken and irqs off */
389static void imx_uart_start_rx(struct uart_port *port)
390{
391 struct imx_port *sport = to_imx_port(port);
392 unsigned int ucr1, ucr2;
393
394 ucr1 = imx_uart_readl(sport, UCR1);
395 ucr2 = imx_uart_readl(sport, UCR2);
396
397 ucr2 |= UCR2_RXEN;
398
399 if (sport->dma_is_enabled) {
400 ucr1 |= UCR1_RXDMAEN | UCR1_ATDMAEN;
401 } else {
402 ucr1 |= UCR1_RRDYEN;
403 ucr2 |= UCR2_ATEN;
404 }
405
406 /* Write UCR2 first as it includes RXEN */
407 imx_uart_writel(sport, ucr2, UCR2);
408 imx_uart_writel(sport, ucr1, UCR1);
409 imx_uart_disable_loopback_rs485(sport);
410}
411
412/* called with port.lock taken and irqs off */
413static void imx_uart_stop_tx(struct uart_port *port)
414{
415 struct imx_port *sport = to_imx_port(port);
416 u32 ucr1, ucr4, usr2;
417
418 if (sport->tx_state == OFF)
419 return;
420
421 /*
422 * We are maybe in the SMP context, so if the DMA TX thread is running
423 * on other cpu, we have to wait for it to finish.
424 */
425 if (sport->dma_is_txing)
426 return;
427
428 ucr1 = imx_uart_readl(sport, UCR1);
429 imx_uart_writel(sport, ucr1 & ~UCR1_TRDYEN, UCR1);
430
431 ucr4 = imx_uart_readl(sport, UCR4);
432 usr2 = imx_uart_readl(sport, USR2);
433 if ((!(usr2 & USR2_TXDC)) && (ucr4 & UCR4_TCEN)) {
434 /* The shifter is still busy, so retry once TC triggers */
435 return;
436 }
437
438 ucr4 &= ~UCR4_TCEN;
439 imx_uart_writel(sport, ucr4, UCR4);
440
441 /* in rs485 mode disable transmitter */
442 if (port->rs485.flags & SER_RS485_ENABLED) {
443 if (sport->tx_state == SEND) {
444 sport->tx_state = WAIT_AFTER_SEND;
445
446 if (port->rs485.delay_rts_after_send > 0) {
447 start_hrtimer_ms(&sport->trigger_stop_tx,
448 port->rs485.delay_rts_after_send);
449 return;
450 }
451
452 /* continue without any delay */
453 }
454
455 if (sport->tx_state == WAIT_AFTER_RTS ||
456 sport->tx_state == WAIT_AFTER_SEND) {
457 u32 ucr2;
458
459 hrtimer_try_to_cancel(&sport->trigger_start_tx);
460
461 ucr2 = imx_uart_readl(sport, UCR2);
462 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
463 imx_uart_rts_active(sport, &ucr2);
464 else
465 imx_uart_rts_inactive(sport, &ucr2);
466 imx_uart_writel(sport, ucr2, UCR2);
467
468 if (!port->rs485_rx_during_tx_gpio)
469 imx_uart_start_rx(port);
470
471 sport->tx_state = OFF;
472 }
473 } else {
474 sport->tx_state = OFF;
475 }
476}
477
478/* called with port.lock taken and irqs off */
479static void imx_uart_stop_rx_with_loopback_ctrl(struct uart_port *port, bool loopback)
480{
481 struct imx_port *sport = to_imx_port(port);
482 u32 ucr1, ucr2, ucr4, uts;
483
484 ucr1 = imx_uart_readl(sport, UCR1);
485 ucr2 = imx_uart_readl(sport, UCR2);
486 ucr4 = imx_uart_readl(sport, UCR4);
487
488 if (sport->dma_is_enabled) {
489 ucr1 &= ~(UCR1_RXDMAEN | UCR1_ATDMAEN);
490 } else {
491 ucr1 &= ~UCR1_RRDYEN;
492 ucr2 &= ~UCR2_ATEN;
493 ucr4 &= ~UCR4_OREN;
494 }
495 imx_uart_writel(sport, ucr1, UCR1);
496 imx_uart_writel(sport, ucr4, UCR4);
497
498 /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */
499 if (port->rs485.flags & SER_RS485_ENABLED &&
500 port->rs485.flags & SER_RS485_RTS_ON_SEND &&
501 sport->have_rtscts && !sport->have_rtsgpio && loopback) {
502 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
503 uts |= UTS_LOOP;
504 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
505 ucr2 |= UCR2_RXEN;
506 } else {
507 ucr2 &= ~UCR2_RXEN;
508 }
509
510 imx_uart_writel(sport, ucr2, UCR2);
511}
512
513/* called with port.lock taken and irqs off */
514static void imx_uart_stop_rx(struct uart_port *port)
515{
516 /*
517 * Stop RX and enable loopback in order to make sure RS485 bus
518 * is not blocked. Se comment in imx_uart_probe().
519 */
520 imx_uart_stop_rx_with_loopback_ctrl(port, true);
521}
522
523/* called with port.lock taken and irqs off */
524static void imx_uart_enable_ms(struct uart_port *port)
525{
526 struct imx_port *sport = to_imx_port(port);
527
528 mod_timer(&sport->timer, jiffies);
529
530 mctrl_gpio_enable_ms(sport->gpios);
531}
532
533static void imx_uart_dma_tx(struct imx_port *sport);
534
535/* called with port.lock taken and irqs off */
536static inline void imx_uart_transmit_buffer(struct imx_port *sport)
537{
538 struct tty_port *tport = &sport->port.state->port;
539 unsigned char c;
540
541 if (sport->port.x_char) {
542 /* Send next char */
543 imx_uart_writel(sport, sport->port.x_char, URTX0);
544 sport->port.icount.tx++;
545 sport->port.x_char = 0;
546 return;
547 }
548
549 if (kfifo_is_empty(&tport->xmit_fifo) ||
550 uart_tx_stopped(&sport->port)) {
551 imx_uart_stop_tx(&sport->port);
552 return;
553 }
554
555 if (sport->dma_is_enabled) {
556 u32 ucr1;
557 /*
558 * We've just sent a X-char Ensure the TX DMA is enabled
559 * and the TX IRQ is disabled.
560 **/
561 ucr1 = imx_uart_readl(sport, UCR1);
562 ucr1 &= ~UCR1_TRDYEN;
563 if (sport->dma_is_txing) {
564 ucr1 |= UCR1_TXDMAEN;
565 imx_uart_writel(sport, ucr1, UCR1);
566 } else {
567 imx_uart_writel(sport, ucr1, UCR1);
568 imx_uart_dma_tx(sport);
569 }
570
571 return;
572 }
573
574 while (!(imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL) &&
575 uart_fifo_get(&sport->port, &c))
576 imx_uart_writel(sport, c, URTX0);
577
578 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
579 uart_write_wakeup(&sport->port);
580
581 if (kfifo_is_empty(&tport->xmit_fifo))
582 imx_uart_stop_tx(&sport->port);
583}
584
585static void imx_uart_dma_tx_callback(void *data)
586{
587 struct imx_port *sport = data;
588 struct tty_port *tport = &sport->port.state->port;
589 struct scatterlist *sgl = &sport->tx_sgl[0];
590 unsigned long flags;
591 u32 ucr1;
592
593 uart_port_lock_irqsave(&sport->port, &flags);
594
595 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
596
597 ucr1 = imx_uart_readl(sport, UCR1);
598 ucr1 &= ~UCR1_TXDMAEN;
599 imx_uart_writel(sport, ucr1, UCR1);
600
601 uart_xmit_advance(&sport->port, sport->tx_bytes);
602
603 dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
604
605 sport->dma_is_txing = 0;
606
607 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
608 uart_write_wakeup(&sport->port);
609
610 if (!kfifo_is_empty(&tport->xmit_fifo) &&
611 !uart_tx_stopped(&sport->port))
612 imx_uart_dma_tx(sport);
613 else if (sport->port.rs485.flags & SER_RS485_ENABLED) {
614 u32 ucr4 = imx_uart_readl(sport, UCR4);
615 ucr4 |= UCR4_TCEN;
616 imx_uart_writel(sport, ucr4, UCR4);
617 }
618
619 uart_port_unlock_irqrestore(&sport->port, flags);
620}
621
622/* called with port.lock taken and irqs off */
623static void imx_uart_dma_tx(struct imx_port *sport)
624{
625 struct tty_port *tport = &sport->port.state->port;
626 struct scatterlist *sgl = sport->tx_sgl;
627 struct dma_async_tx_descriptor *desc;
628 struct dma_chan *chan = sport->dma_chan_tx;
629 struct device *dev = sport->port.dev;
630 u32 ucr1, ucr4;
631 int ret;
632
633 if (sport->dma_is_txing)
634 return;
635
636 ucr4 = imx_uart_readl(sport, UCR4);
637 ucr4 &= ~UCR4_TCEN;
638 imx_uart_writel(sport, ucr4, UCR4);
639
640 sg_init_table(sgl, ARRAY_SIZE(sport->tx_sgl));
641 sport->tx_bytes = kfifo_len(&tport->xmit_fifo);
642 sport->dma_tx_nents = kfifo_dma_out_prepare(&tport->xmit_fifo, sgl,
643 ARRAY_SIZE(sport->tx_sgl), sport->tx_bytes);
644
645 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
646 if (ret == 0) {
647 dev_err(dev, "DMA mapping error for TX.\n");
648 return;
649 }
650 desc = dmaengine_prep_slave_sg(chan, sgl, ret,
651 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
652 if (!desc) {
653 dma_unmap_sg(dev, sgl, sport->dma_tx_nents,
654 DMA_TO_DEVICE);
655 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
656 return;
657 }
658 desc->callback = imx_uart_dma_tx_callback;
659 desc->callback_param = sport;
660
661 dev_dbg(dev, "TX: prepare to send %u bytes by DMA.\n", sport->tx_bytes);
662
663 ucr1 = imx_uart_readl(sport, UCR1);
664 ucr1 |= UCR1_TXDMAEN;
665 imx_uart_writel(sport, ucr1, UCR1);
666
667 /* fire it */
668 sport->dma_is_txing = 1;
669 dmaengine_submit(desc);
670 dma_async_issue_pending(chan);
671 return;
672}
673
674/* called with port.lock taken and irqs off */
675static void imx_uart_start_tx(struct uart_port *port)
676{
677 struct imx_port *sport = to_imx_port(port);
678 struct tty_port *tport = &sport->port.state->port;
679 u32 ucr1;
680
681 if (!sport->port.x_char && kfifo_is_empty(&tport->xmit_fifo))
682 return;
683
684 /*
685 * We cannot simply do nothing here if sport->tx_state == SEND already
686 * because UCR1_TXMPTYEN might already have been cleared in
687 * imx_uart_stop_tx(), but tx_state is still SEND.
688 */
689
690 if (port->rs485.flags & SER_RS485_ENABLED) {
691 if (sport->tx_state == OFF) {
692 u32 ucr2 = imx_uart_readl(sport, UCR2);
693 if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
694 imx_uart_rts_active(sport, &ucr2);
695 else
696 imx_uart_rts_inactive(sport, &ucr2);
697 imx_uart_writel(sport, ucr2, UCR2);
698
699 /*
700 * Since we are about to transmit we can not stop RX
701 * with loopback enabled because that will make our
702 * transmitted data being just looped to RX.
703 */
704 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX) &&
705 !port->rs485_rx_during_tx_gpio)
706 imx_uart_stop_rx_with_loopback_ctrl(port, false);
707
708 sport->tx_state = WAIT_AFTER_RTS;
709
710 if (port->rs485.delay_rts_before_send > 0) {
711 start_hrtimer_ms(&sport->trigger_start_tx,
712 port->rs485.delay_rts_before_send);
713 return;
714 }
715
716 /* continue without any delay */
717 }
718
719 if (sport->tx_state == WAIT_AFTER_SEND
720 || sport->tx_state == WAIT_AFTER_RTS) {
721
722 hrtimer_try_to_cancel(&sport->trigger_stop_tx);
723
724 /*
725 * Enable transmitter and shifter empty irq only if DMA
726 * is off. In the DMA case this is done in the
727 * tx-callback.
728 */
729 if (!sport->dma_is_enabled) {
730 u32 ucr4 = imx_uart_readl(sport, UCR4);
731 ucr4 |= UCR4_TCEN;
732 imx_uart_writel(sport, ucr4, UCR4);
733 }
734
735 sport->tx_state = SEND;
736 }
737 } else {
738 sport->tx_state = SEND;
739 }
740
741 if (!sport->dma_is_enabled) {
742 ucr1 = imx_uart_readl(sport, UCR1);
743 imx_uart_writel(sport, ucr1 | UCR1_TRDYEN, UCR1);
744 }
745
746 if (sport->dma_is_enabled) {
747 if (sport->port.x_char) {
748 /* We have X-char to send, so enable TX IRQ and
749 * disable TX DMA to let TX interrupt to send X-char */
750 ucr1 = imx_uart_readl(sport, UCR1);
751 ucr1 &= ~UCR1_TXDMAEN;
752 ucr1 |= UCR1_TRDYEN;
753 imx_uart_writel(sport, ucr1, UCR1);
754 return;
755 }
756
757 if (!kfifo_is_empty(&tport->xmit_fifo) &&
758 !uart_tx_stopped(port))
759 imx_uart_dma_tx(sport);
760 return;
761 }
762}
763
764static irqreturn_t __imx_uart_rtsint(int irq, void *dev_id)
765{
766 struct imx_port *sport = dev_id;
767 u32 usr1;
768
769 imx_uart_writel(sport, USR1_RTSD, USR1);
770 usr1 = imx_uart_readl(sport, USR1) & USR1_RTSS;
771 /*
772 * Update sport->old_status here, so any follow-up calls to
773 * imx_uart_mctrl_check() will be able to recognize that RTS
774 * state changed since last imx_uart_mctrl_check() call.
775 *
776 * In case RTS has been detected as asserted here and later on
777 * deasserted by the time imx_uart_mctrl_check() was called,
778 * imx_uart_mctrl_check() can detect the RTS state change and
779 * trigger uart_handle_cts_change() to unblock the port for
780 * further TX transfers.
781 */
782 if (usr1 & USR1_RTSS)
783 sport->old_status |= TIOCM_CTS;
784 else
785 sport->old_status &= ~TIOCM_CTS;
786 uart_handle_cts_change(&sport->port, usr1);
787 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
788
789 return IRQ_HANDLED;
790}
791
792static irqreturn_t imx_uart_rtsint(int irq, void *dev_id)
793{
794 struct imx_port *sport = dev_id;
795 irqreturn_t ret;
796
797 uart_port_lock(&sport->port);
798
799 ret = __imx_uart_rtsint(irq, dev_id);
800
801 uart_port_unlock(&sport->port);
802
803 return ret;
804}
805
806static irqreturn_t imx_uart_txint(int irq, void *dev_id)
807{
808 struct imx_port *sport = dev_id;
809
810 uart_port_lock(&sport->port);
811 imx_uart_transmit_buffer(sport);
812 uart_port_unlock(&sport->port);
813 return IRQ_HANDLED;
814}
815
816/* Check if hardware Rx flood is in progress, and issue soft reset to stop it.
817 * This is to be called from Rx ISRs only when some bytes were actually
818 * received.
819 *
820 * A way to reproduce the flood (checked on iMX6SX) is: open iMX UART at 9600
821 * 8N1, and from external source send 0xf0 char at 115200 8N1. In about 90% of
822 * cases this starts a flood of "receiving" of 0xff characters by the iMX6 UART
823 * that is terminated by any activity on RxD line, or could be stopped by
824 * issuing soft reset to the UART (just stop/start of RX does not help). Note
825 * that what we do here is sending isolated start bit about 2.4 times shorter
826 * than it is to be on UART configured baud rate.
827 *
828 * Called with port.lock taken and irqs off.
829 */
830static void imx_uart_check_flood(struct imx_port *sport, u32 usr2)
831{
832 /* To detect hardware 0xff flood we monitor RxD line between RX
833 * interrupts to isolate "receiving" of char(s) with no activity
834 * on RxD line, that'd never happen on actual data transfers.
835 *
836 * We use USR2_WAKE bit to check for activity on RxD line, but we have a
837 * race here if we clear USR2_WAKE when receiving of a char is in
838 * progress, so we might get RX interrupt later with USR2_WAKE bit
839 * cleared. Note though that as we don't try to clear USR2_WAKE when we
840 * detected no activity, this race may hide actual activity only once.
841 *
842 * Yet another case where receive interrupt may occur without RxD
843 * activity is expiration of aging timer, so we consider this as well.
844 *
845 * We use 'idle_counter' to ensure that we got at least so many RX
846 * interrupts without any detected activity on RxD line. 2 cases
847 * described plus 1 to be on the safe side gives us a margin of 3,
848 * below. In practice I was not able to produce a false positive to
849 * induce soft reset at regular data transfers even using 1 as the
850 * margin, so 3 is actually very strong.
851 *
852 * We count interrupts, not chars in 'idle-counter' for simplicity.
853 */
854
855 if (usr2 & USR2_WAKE) {
856 imx_uart_writel(sport, USR2_WAKE, USR2);
857 sport->idle_counter = 0;
858 } else if (++sport->idle_counter > 3) {
859 dev_warn(sport->port.dev, "RX flood detected: soft reset.");
860 imx_uart_soft_reset(sport); /* also clears 'sport->idle_counter' */
861 }
862}
863
864/* called with port.lock taken and irqs off */
865static irqreturn_t __imx_uart_rxint(int irq, void *dev_id)
866{
867 struct imx_port *sport = dev_id;
868 struct tty_port *port = &sport->port.state->port;
869 u32 usr2, rx;
870
871 /* If we received something, check for 0xff flood */
872 usr2 = imx_uart_readl(sport, USR2);
873 if (usr2 & USR2_RDR)
874 imx_uart_check_flood(sport, usr2);
875
876 while ((rx = imx_uart_readl(sport, URXD0)) & URXD_CHARRDY) {
877 unsigned int flg = TTY_NORMAL;
878 sport->port.icount.rx++;
879
880 if (unlikely(rx & URXD_ERR)) {
881 if (rx & URXD_BRK) {
882 sport->port.icount.brk++;
883 if (uart_handle_break(&sport->port))
884 continue;
885 }
886 else if (rx & URXD_PRERR)
887 sport->port.icount.parity++;
888 else if (rx & URXD_FRMERR)
889 sport->port.icount.frame++;
890 if (rx & URXD_OVRRUN)
891 sport->port.icount.overrun++;
892
893 if (rx & sport->port.ignore_status_mask)
894 continue;
895
896 rx &= (sport->port.read_status_mask | 0xFF);
897
898 if (rx & URXD_BRK)
899 flg = TTY_BREAK;
900 else if (rx & URXD_PRERR)
901 flg = TTY_PARITY;
902 else if (rx & URXD_FRMERR)
903 flg = TTY_FRAME;
904 if (rx & URXD_OVRRUN)
905 flg = TTY_OVERRUN;
906
907 sport->port.sysrq = 0;
908 } else if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) {
909 continue;
910 }
911
912 if (sport->port.ignore_status_mask & URXD_DUMMY_READ)
913 continue;
914
915 if (tty_insert_flip_char(port, rx, flg) == 0)
916 sport->port.icount.buf_overrun++;
917 }
918
919 tty_flip_buffer_push(port);
920
921 return IRQ_HANDLED;
922}
923
924static irqreturn_t imx_uart_rxint(int irq, void *dev_id)
925{
926 struct imx_port *sport = dev_id;
927 irqreturn_t ret;
928
929 uart_port_lock(&sport->port);
930
931 ret = __imx_uart_rxint(irq, dev_id);
932
933 uart_port_unlock(&sport->port);
934
935 return ret;
936}
937
938static void imx_uart_clear_rx_errors(struct imx_port *sport);
939
940/*
941 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
942 */
943/* called with port.lock taken and irqs off */
944static unsigned int imx_uart_get_hwmctrl(struct imx_port *sport)
945{
946 unsigned int tmp = TIOCM_DSR;
947 unsigned usr1 = imx_uart_readl(sport, USR1);
948 unsigned usr2 = imx_uart_readl(sport, USR2);
949
950 if (usr1 & USR1_RTSS)
951 tmp |= TIOCM_CTS;
952
953 /* in DCE mode DCDIN is always 0 */
954 if (!(usr2 & USR2_DCDIN))
955 tmp |= TIOCM_CAR;
956
957 if (sport->dte_mode)
958 if (!(imx_uart_readl(sport, USR2) & USR2_RIIN))
959 tmp |= TIOCM_RI;
960
961 return tmp;
962}
963
964/*
965 * Handle any change of modem status signal since we were last called.
966 *
967 * Called with port.lock taken and irqs off.
968 */
969static void imx_uart_mctrl_check(struct imx_port *sport)
970{
971 unsigned int status, changed;
972
973 status = imx_uart_get_hwmctrl(sport);
974 changed = status ^ sport->old_status;
975
976 if (changed == 0)
977 return;
978
979 sport->old_status = status;
980
981 if (changed & TIOCM_RI && status & TIOCM_RI)
982 sport->port.icount.rng++;
983 if (changed & TIOCM_DSR)
984 sport->port.icount.dsr++;
985 if (changed & TIOCM_CAR)
986 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
987 if (changed & TIOCM_CTS)
988 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
989
990 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
991}
992
993static irqreturn_t imx_uart_int(int irq, void *dev_id)
994{
995 struct imx_port *sport = dev_id;
996 unsigned int usr1, usr2, ucr1, ucr2, ucr3, ucr4;
997 irqreturn_t ret = IRQ_NONE;
998
999 uart_port_lock(&sport->port);
1000
1001 usr1 = imx_uart_readl(sport, USR1);
1002 usr2 = imx_uart_readl(sport, USR2);
1003 ucr1 = imx_uart_readl(sport, UCR1);
1004 ucr2 = imx_uart_readl(sport, UCR2);
1005 ucr3 = imx_uart_readl(sport, UCR3);
1006 ucr4 = imx_uart_readl(sport, UCR4);
1007
1008 /*
1009 * Even if a condition is true that can trigger an irq only handle it if
1010 * the respective irq source is enabled. This prevents some undesired
1011 * actions, for example if a character that sits in the RX FIFO and that
1012 * should be fetched via DMA is tried to be fetched using PIO. Or the
1013 * receiver is currently off and so reading from URXD0 results in an
1014 * exception. So just mask the (raw) status bits for disabled irqs.
1015 */
1016 if ((ucr1 & UCR1_RRDYEN) == 0)
1017 usr1 &= ~USR1_RRDY;
1018 if ((ucr2 & UCR2_ATEN) == 0)
1019 usr1 &= ~USR1_AGTIM;
1020 if ((ucr1 & UCR1_TRDYEN) == 0)
1021 usr1 &= ~USR1_TRDY;
1022 if ((ucr4 & UCR4_TCEN) == 0)
1023 usr2 &= ~USR2_TXDC;
1024 if ((ucr3 & UCR3_DTRDEN) == 0)
1025 usr1 &= ~USR1_DTRD;
1026 if ((ucr1 & UCR1_RTSDEN) == 0)
1027 usr1 &= ~USR1_RTSD;
1028 if ((ucr3 & UCR3_AWAKEN) == 0)
1029 usr1 &= ~USR1_AWAKE;
1030 if ((ucr4 & UCR4_OREN) == 0)
1031 usr2 &= ~USR2_ORE;
1032
1033 if (usr1 & (USR1_RRDY | USR1_AGTIM)) {
1034 imx_uart_writel(sport, USR1_AGTIM, USR1);
1035
1036 __imx_uart_rxint(irq, dev_id);
1037 ret = IRQ_HANDLED;
1038 }
1039
1040 if ((usr1 & USR1_TRDY) || (usr2 & USR2_TXDC)) {
1041 imx_uart_transmit_buffer(sport);
1042 ret = IRQ_HANDLED;
1043 }
1044
1045 if (usr1 & USR1_DTRD) {
1046 imx_uart_writel(sport, USR1_DTRD, USR1);
1047
1048 imx_uart_mctrl_check(sport);
1049
1050 ret = IRQ_HANDLED;
1051 }
1052
1053 if (usr1 & USR1_RTSD) {
1054 __imx_uart_rtsint(irq, dev_id);
1055 ret = IRQ_HANDLED;
1056 }
1057
1058 if (usr1 & USR1_AWAKE) {
1059 imx_uart_writel(sport, USR1_AWAKE, USR1);
1060 ret = IRQ_HANDLED;
1061 }
1062
1063 if (usr2 & USR2_ORE) {
1064 sport->port.icount.overrun++;
1065 imx_uart_writel(sport, USR2_ORE, USR2);
1066 ret = IRQ_HANDLED;
1067 }
1068
1069 uart_port_unlock(&sport->port);
1070
1071 return ret;
1072}
1073
1074/*
1075 * Return TIOCSER_TEMT when transmitter is not busy.
1076 */
1077static unsigned int imx_uart_tx_empty(struct uart_port *port)
1078{
1079 struct imx_port *sport = to_imx_port(port);
1080 unsigned int ret;
1081
1082 ret = (imx_uart_readl(sport, USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
1083
1084 /* If the TX DMA is working, return 0. */
1085 if (sport->dma_is_txing)
1086 ret = 0;
1087
1088 return ret;
1089}
1090
1091/* called with port.lock taken and irqs off */
1092static unsigned int imx_uart_get_mctrl(struct uart_port *port)
1093{
1094 struct imx_port *sport = to_imx_port(port);
1095 unsigned int ret = imx_uart_get_hwmctrl(sport);
1096
1097 mctrl_gpio_get(sport->gpios, &ret);
1098
1099 return ret;
1100}
1101
1102/* called with port.lock taken and irqs off */
1103static void imx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1104{
1105 struct imx_port *sport = to_imx_port(port);
1106 u32 ucr3, uts;
1107
1108 if (!(port->rs485.flags & SER_RS485_ENABLED)) {
1109 u32 ucr2;
1110
1111 /*
1112 * Turn off autoRTS if RTS is lowered and restore autoRTS
1113 * setting if RTS is raised.
1114 */
1115 ucr2 = imx_uart_readl(sport, UCR2);
1116 ucr2 &= ~(UCR2_CTS | UCR2_CTSC);
1117 if (mctrl & TIOCM_RTS) {
1118 ucr2 |= UCR2_CTS;
1119 /*
1120 * UCR2_IRTS is unset if and only if the port is
1121 * configured for CRTSCTS, so we use inverted UCR2_IRTS
1122 * to get the state to restore to.
1123 */
1124 if (!(ucr2 & UCR2_IRTS))
1125 ucr2 |= UCR2_CTSC;
1126 }
1127 imx_uart_writel(sport, ucr2, UCR2);
1128 }
1129
1130 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_DSR;
1131 if (!(mctrl & TIOCM_DTR))
1132 ucr3 |= UCR3_DSR;
1133 imx_uart_writel(sport, ucr3, UCR3);
1134
1135 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)) & ~UTS_LOOP;
1136 if (mctrl & TIOCM_LOOP)
1137 uts |= UTS_LOOP;
1138 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
1139
1140 mctrl_gpio_set(sport->gpios, mctrl);
1141}
1142
1143/*
1144 * Interrupts always disabled.
1145 */
1146static void imx_uart_break_ctl(struct uart_port *port, int break_state)
1147{
1148 struct imx_port *sport = to_imx_port(port);
1149 unsigned long flags;
1150 u32 ucr1;
1151
1152 uart_port_lock_irqsave(&sport->port, &flags);
1153
1154 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_SNDBRK;
1155
1156 if (break_state != 0)
1157 ucr1 |= UCR1_SNDBRK;
1158
1159 imx_uart_writel(sport, ucr1, UCR1);
1160
1161 uart_port_unlock_irqrestore(&sport->port, flags);
1162}
1163
1164/*
1165 * This is our per-port timeout handler, for checking the
1166 * modem status signals.
1167 */
1168static void imx_uart_timeout(struct timer_list *t)
1169{
1170 struct imx_port *sport = timer_container_of(sport, t, timer);
1171 unsigned long flags;
1172
1173 if (sport->port.state) {
1174 uart_port_lock_irqsave(&sport->port, &flags);
1175 imx_uart_mctrl_check(sport);
1176 uart_port_unlock_irqrestore(&sport->port, flags);
1177
1178 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
1179 }
1180}
1181
1182/*
1183 * There are two kinds of RX DMA interrupts(such as in the MX6Q):
1184 * [1] the RX DMA buffer is full.
1185 * [2] the aging timer expires
1186 *
1187 * Condition [2] is triggered when a character has been sitting in the FIFO
1188 * for at least 8 byte durations.
1189 */
1190static void imx_uart_dma_rx_callback(void *data)
1191{
1192 struct imx_port *sport = data;
1193 struct dma_chan *chan = sport->dma_chan_rx;
1194 struct scatterlist *sgl = &sport->rx_sgl;
1195 struct tty_port *port = &sport->port.state->port;
1196 struct dma_tx_state state;
1197 struct circ_buf *rx_ring = &sport->rx_ring;
1198 enum dma_status status;
1199 unsigned int w_bytes = 0;
1200 unsigned int r_bytes;
1201 unsigned int bd_size;
1202
1203 status = dmaengine_tx_status(chan, sport->rx_cookie, &state);
1204
1205 if (status == DMA_ERROR) {
1206 uart_port_lock(&sport->port);
1207 imx_uart_clear_rx_errors(sport);
1208 uart_port_unlock(&sport->port);
1209 return;
1210 }
1211
1212 /*
1213 * The state-residue variable represents the empty space
1214 * relative to the entire buffer. Taking this in consideration
1215 * the head is always calculated base on the buffer total
1216 * length - DMA transaction residue. The UART script from the
1217 * SDMA firmware will jump to the next buffer descriptor,
1218 * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4).
1219 * Taking this in consideration the tail is always at the
1220 * beginning of the buffer descriptor that contains the head.
1221 */
1222
1223 /* Calculate the head */
1224 rx_ring->head = sg_dma_len(sgl) - state.residue;
1225
1226 /* Calculate the tail. */
1227 bd_size = sg_dma_len(sgl) / sport->rx_periods;
1228 rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size;
1229
1230 if (rx_ring->head <= sg_dma_len(sgl) &&
1231 rx_ring->head > rx_ring->tail) {
1232
1233 /* Move data from tail to head */
1234 r_bytes = rx_ring->head - rx_ring->tail;
1235
1236 /* If we received something, check for 0xff flood */
1237 uart_port_lock(&sport->port);
1238 imx_uart_check_flood(sport, imx_uart_readl(sport, USR2));
1239 uart_port_unlock(&sport->port);
1240
1241 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) {
1242
1243 /* CPU claims ownership of RX DMA buffer */
1244 dma_sync_sg_for_cpu(sport->port.dev, sgl, 1,
1245 DMA_FROM_DEVICE);
1246
1247 w_bytes = tty_insert_flip_string(port,
1248 sport->rx_buf + rx_ring->tail, r_bytes);
1249
1250 /* UART retrieves ownership of RX DMA buffer */
1251 dma_sync_sg_for_device(sport->port.dev, sgl, 1,
1252 DMA_FROM_DEVICE);
1253
1254 if (w_bytes != r_bytes)
1255 sport->port.icount.buf_overrun++;
1256
1257 sport->port.icount.rx += w_bytes;
1258 }
1259 } else {
1260 WARN_ON(rx_ring->head > sg_dma_len(sgl));
1261 WARN_ON(rx_ring->head <= rx_ring->tail);
1262 }
1263
1264 if (w_bytes) {
1265 tty_flip_buffer_push(port);
1266 dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes);
1267 }
1268}
1269
1270static int imx_uart_start_rx_dma(struct imx_port *sport)
1271{
1272 struct scatterlist *sgl = &sport->rx_sgl;
1273 struct dma_chan *chan = sport->dma_chan_rx;
1274 struct device *dev = sport->port.dev;
1275 struct dma_async_tx_descriptor *desc;
1276 int ret;
1277
1278 sport->rx_ring.head = 0;
1279 sport->rx_ring.tail = 0;
1280
1281 sg_init_one(sgl, sport->rx_buf, sport->rx_buf_size);
1282 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1283 if (ret == 0) {
1284 dev_err(dev, "DMA mapping error for RX.\n");
1285 return -EINVAL;
1286 }
1287
1288 desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl),
1289 sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods,
1290 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
1291
1292 if (!desc) {
1293 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1294 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
1295 return -EINVAL;
1296 }
1297 desc->callback = imx_uart_dma_rx_callback;
1298 desc->callback_param = sport;
1299
1300 dev_dbg(dev, "RX: prepare for the DMA.\n");
1301 sport->dma_is_rxing = 1;
1302 sport->rx_cookie = dmaengine_submit(desc);
1303 dma_async_issue_pending(chan);
1304 return 0;
1305}
1306
1307/* called with port.lock taken and irqs off */
1308static void imx_uart_clear_rx_errors(struct imx_port *sport)
1309{
1310 struct tty_port *port = &sport->port.state->port;
1311 u32 usr1, usr2;
1312
1313 usr1 = imx_uart_readl(sport, USR1);
1314 usr2 = imx_uart_readl(sport, USR2);
1315
1316 if (usr2 & USR2_BRCD) {
1317 sport->port.icount.brk++;
1318 imx_uart_writel(sport, USR2_BRCD, USR2);
1319 uart_handle_break(&sport->port);
1320 if (tty_insert_flip_char(port, 0, TTY_BREAK) == 0)
1321 sport->port.icount.buf_overrun++;
1322 tty_flip_buffer_push(port);
1323 } else {
1324 if (usr1 & USR1_FRAMERR) {
1325 sport->port.icount.frame++;
1326 imx_uart_writel(sport, USR1_FRAMERR, USR1);
1327 } else if (usr1 & USR1_PARITYERR) {
1328 sport->port.icount.parity++;
1329 imx_uart_writel(sport, USR1_PARITYERR, USR1);
1330 }
1331 }
1332
1333 if (usr2 & USR2_ORE) {
1334 sport->port.icount.overrun++;
1335 imx_uart_writel(sport, USR2_ORE, USR2);
1336 }
1337
1338 sport->idle_counter = 0;
1339
1340}
1341
1342#define TXTL_DEFAULT 8
1343#define RXTL_DEFAULT 8 /* 8 characters or aging timer */
1344#define RXTL_CONSOLE_DEFAULT 1
1345#define TXTL_DMA 8 /* DMA burst setting */
1346#define RXTL_DMA 9 /* DMA burst setting */
1347
1348static void imx_uart_setup_ufcr(struct imx_port *sport,
1349 unsigned char txwl, unsigned char rxwl)
1350{
1351 unsigned int val;
1352
1353 /* set receiver / transmitter trigger level */
1354 val = imx_uart_readl(sport, UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
1355 val |= txwl << UFCR_TXTL_SHF | rxwl;
1356 imx_uart_writel(sport, val, UFCR);
1357}
1358
1359static void imx_uart_dma_exit(struct imx_port *sport)
1360{
1361 if (sport->dma_chan_rx) {
1362 dmaengine_terminate_sync(sport->dma_chan_rx);
1363 dma_release_channel(sport->dma_chan_rx);
1364 sport->dma_chan_rx = NULL;
1365 sport->rx_cookie = -EINVAL;
1366 kfree(sport->rx_buf);
1367 sport->rx_buf = NULL;
1368 }
1369
1370 if (sport->dma_chan_tx) {
1371 dmaengine_terminate_sync(sport->dma_chan_tx);
1372 dma_release_channel(sport->dma_chan_tx);
1373 sport->dma_chan_tx = NULL;
1374 }
1375}
1376
1377static int imx_uart_dma_init(struct imx_port *sport)
1378{
1379 struct dma_slave_config slave_config = {};
1380 struct device *dev = sport->port.dev;
1381 struct dma_chan *chan;
1382 int ret;
1383
1384 /* Prepare for RX : */
1385 chan = dma_request_chan(dev, "rx");
1386 if (IS_ERR(chan)) {
1387 dev_dbg(dev, "cannot get the DMA channel.\n");
1388 sport->dma_chan_rx = NULL;
1389 ret = PTR_ERR(chan);
1390 goto err;
1391 }
1392 sport->dma_chan_rx = chan;
1393
1394 slave_config.direction = DMA_DEV_TO_MEM;
1395 slave_config.src_addr = sport->port.mapbase + URXD0;
1396 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1397 /* one byte less than the watermark level to enable the aging timer */
1398 slave_config.src_maxburst = RXTL_DMA - 1;
1399 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
1400 if (ret) {
1401 dev_err(dev, "error in RX dma configuration.\n");
1402 goto err;
1403 }
1404
1405 sport->rx_buf_size = sport->rx_period_length * sport->rx_periods;
1406 sport->rx_buf = kzalloc(sport->rx_buf_size, GFP_KERNEL);
1407 if (!sport->rx_buf) {
1408 ret = -ENOMEM;
1409 goto err;
1410 }
1411 sport->rx_ring.buf = sport->rx_buf;
1412
1413 /* Prepare for TX : */
1414 chan = dma_request_chan(dev, "tx");
1415 if (IS_ERR(chan)) {
1416 dev_err(dev, "cannot get the TX DMA channel!\n");
1417 sport->dma_chan_tx = NULL;
1418 ret = PTR_ERR(chan);
1419 goto err;
1420 }
1421 sport->dma_chan_tx = chan;
1422
1423 slave_config.direction = DMA_MEM_TO_DEV;
1424 slave_config.dst_addr = sport->port.mapbase + URTX0;
1425 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1426 slave_config.dst_maxburst = TXTL_DMA;
1427 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1428 if (ret) {
1429 dev_err(dev, "error in TX dma configuration.");
1430 goto err;
1431 }
1432
1433 return 0;
1434err:
1435 imx_uart_dma_exit(sport);
1436 return ret;
1437}
1438
1439/* called with port.lock taken and irqs off */
1440static void imx_uart_enable_dma(struct imx_port *sport)
1441{
1442 u32 ucr1;
1443
1444 imx_uart_setup_ufcr(sport, TXTL_DMA, RXTL_DMA);
1445
1446 /* set UCR1 except TXDMAEN which would be enabled in imx_uart_dma_tx */
1447 ucr1 = imx_uart_readl(sport, UCR1);
1448 ucr1 |= UCR1_RXDMAEN | UCR1_ATDMAEN;
1449 imx_uart_writel(sport, ucr1, UCR1);
1450
1451 sport->dma_is_enabled = 1;
1452}
1453
1454static void imx_uart_disable_dma(struct imx_port *sport)
1455{
1456 u32 ucr1;
1457
1458 /* clear UCR1 */
1459 ucr1 = imx_uart_readl(sport, UCR1);
1460 ucr1 &= ~(UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN);
1461 imx_uart_writel(sport, ucr1, UCR1);
1462
1463 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, sport->rxtl);
1464
1465 sport->dma_is_enabled = 0;
1466}
1467
1468/* half the RX buffer size */
1469#define CTSTL 16
1470
1471static int imx_uart_startup(struct uart_port *port)
1472{
1473 struct imx_port *sport = to_imx_port(port);
1474 int retval;
1475 unsigned long flags;
1476 int dma_is_inited = 0;
1477 u32 ucr1, ucr2, ucr3, ucr4;
1478
1479 retval = clk_prepare_enable(sport->clk_per);
1480 if (retval)
1481 return retval;
1482 retval = clk_prepare_enable(sport->clk_ipg);
1483 if (retval) {
1484 clk_disable_unprepare(sport->clk_per);
1485 return retval;
1486 }
1487
1488 if (uart_console(&sport->port))
1489 sport->rxtl = RXTL_CONSOLE_DEFAULT;
1490 else
1491 sport->rxtl = RXTL_DEFAULT;
1492
1493 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, sport->rxtl);
1494
1495 /* disable the DREN bit (Data Ready interrupt enable) before
1496 * requesting IRQs
1497 */
1498 ucr4 = imx_uart_readl(sport, UCR4);
1499
1500 /* set the trigger level for CTS */
1501 ucr4 &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1502 ucr4 |= CTSTL << UCR4_CTSTL_SHF;
1503
1504 imx_uart_writel(sport, ucr4 & ~UCR4_DREN, UCR4);
1505
1506 /* Can we enable the DMA support? */
1507 if (!uart_console(port) && imx_uart_dma_init(sport) == 0) {
1508 lockdep_set_subclass(&port->lock, 1);
1509 dma_is_inited = 1;
1510 }
1511
1512 uart_port_lock_irqsave(&sport->port, &flags);
1513
1514 /* Reset fifo's and state machines */
1515 imx_uart_soft_reset(sport);
1516
1517 /*
1518 * Finally, clear and enable interrupts
1519 */
1520 imx_uart_writel(sport, USR1_RTSD | USR1_DTRD, USR1);
1521 imx_uart_writel(sport, USR2_ORE, USR2);
1522
1523 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN;
1524 ucr1 |= UCR1_UARTEN;
1525 if (sport->have_rtscts)
1526 ucr1 |= UCR1_RTSDEN;
1527
1528 imx_uart_writel(sport, ucr1, UCR1);
1529
1530 ucr4 = imx_uart_readl(sport, UCR4) & ~(UCR4_OREN | UCR4_INVR);
1531 if (!dma_is_inited)
1532 ucr4 |= UCR4_OREN;
1533 if (sport->inverted_rx)
1534 ucr4 |= UCR4_INVR;
1535 imx_uart_writel(sport, ucr4, UCR4);
1536
1537 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_INVT;
1538 /*
1539 * configure tx polarity before enabling tx
1540 */
1541 if (sport->inverted_tx)
1542 ucr3 |= UCR3_INVT;
1543
1544 if (!imx_uart_is_imx1(sport)) {
1545 ucr3 |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD;
1546
1547 if (sport->dte_mode)
1548 /* disable broken interrupts */
1549 ucr3 &= ~(UCR3_RI | UCR3_DCD);
1550 }
1551 imx_uart_writel(sport, ucr3, UCR3);
1552
1553 ucr2 = imx_uart_readl(sport, UCR2) & ~UCR2_ATEN;
1554 ucr2 |= (UCR2_RXEN | UCR2_TXEN);
1555 if (!sport->have_rtscts)
1556 ucr2 |= UCR2_IRTS;
1557 /*
1558 * make sure the edge sensitive RTS-irq is disabled,
1559 * we're using RTSD instead.
1560 */
1561 if (!imx_uart_is_imx1(sport))
1562 ucr2 &= ~UCR2_RTSEN;
1563 imx_uart_writel(sport, ucr2, UCR2);
1564
1565 /*
1566 * Enable modem status interrupts
1567 */
1568 imx_uart_enable_ms(&sport->port);
1569
1570 if (dma_is_inited) {
1571 /* Note: enable dma request after transfer start! */
1572 imx_uart_start_rx_dma(sport);
1573 imx_uart_enable_dma(sport);
1574 } else {
1575 ucr1 = imx_uart_readl(sport, UCR1);
1576 ucr1 |= UCR1_RRDYEN;
1577 imx_uart_writel(sport, ucr1, UCR1);
1578
1579 ucr2 = imx_uart_readl(sport, UCR2);
1580 ucr2 |= UCR2_ATEN;
1581 imx_uart_writel(sport, ucr2, UCR2);
1582 }
1583
1584 imx_uart_disable_loopback_rs485(sport);
1585
1586 uart_port_unlock_irqrestore(&sport->port, flags);
1587
1588 return 0;
1589}
1590
1591static void imx_uart_shutdown(struct uart_port *port)
1592{
1593 struct imx_port *sport = to_imx_port(port);
1594 unsigned long flags;
1595 u32 ucr1, ucr2, ucr4, uts;
1596 int loops;
1597
1598 if (sport->dma_is_enabled) {
1599 dmaengine_terminate_sync(sport->dma_chan_tx);
1600 if (sport->dma_is_txing) {
1601 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0],
1602 sport->dma_tx_nents, DMA_TO_DEVICE);
1603 sport->dma_is_txing = 0;
1604 }
1605 dmaengine_terminate_sync(sport->dma_chan_rx);
1606 if (sport->dma_is_rxing) {
1607 dma_unmap_sg(sport->port.dev, &sport->rx_sgl,
1608 1, DMA_FROM_DEVICE);
1609 sport->dma_is_rxing = 0;
1610 }
1611
1612 uart_port_lock_irqsave(&sport->port, &flags);
1613 imx_uart_stop_tx(port);
1614 imx_uart_stop_rx(port);
1615 imx_uart_disable_dma(sport);
1616 uart_port_unlock_irqrestore(&sport->port, flags);
1617 imx_uart_dma_exit(sport);
1618 }
1619
1620 mctrl_gpio_disable_ms_sync(sport->gpios);
1621
1622 uart_port_lock_irqsave(&sport->port, &flags);
1623 ucr2 = imx_uart_readl(sport, UCR2);
1624 ucr2 &= ~(UCR2_TXEN | UCR2_ATEN);
1625 imx_uart_writel(sport, ucr2, UCR2);
1626 uart_port_unlock_irqrestore(&sport->port, flags);
1627
1628 /*
1629 * Stop our timer.
1630 */
1631 timer_delete_sync(&sport->timer);
1632
1633 /*
1634 * Disable all interrupts, port and break condition.
1635 */
1636
1637 uart_port_lock_irqsave(&sport->port, &flags);
1638
1639 ucr1 = imx_uart_readl(sport, UCR1);
1640 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_RXDMAEN |
1641 UCR1_ATDMAEN | UCR1_SNDBRK);
1642 /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */
1643 if (port->rs485.flags & SER_RS485_ENABLED &&
1644 port->rs485.flags & SER_RS485_RTS_ON_SEND &&
1645 sport->have_rtscts && !sport->have_rtsgpio) {
1646 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
1647 uts |= UTS_LOOP;
1648 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
1649 ucr1 |= UCR1_UARTEN;
1650 } else {
1651 ucr1 &= ~UCR1_UARTEN;
1652 }
1653 imx_uart_writel(sport, ucr1, UCR1);
1654
1655 ucr4 = imx_uart_readl(sport, UCR4);
1656 ucr4 &= ~UCR4_TCEN;
1657 imx_uart_writel(sport, ucr4, UCR4);
1658
1659 /*
1660 * We have to ensure the tx state machine ends up in OFF. This
1661 * is especially important for rs485 where we must not leave
1662 * the RTS signal high, blocking the bus indefinitely.
1663 *
1664 * All interrupts are now disabled, so imx_uart_stop_tx() will
1665 * no longer be called from imx_uart_transmit_buffer(). It may
1666 * still be called via the hrtimers, and if those are in play,
1667 * we have to honour the delays.
1668 */
1669 if (sport->tx_state == WAIT_AFTER_RTS || sport->tx_state == SEND)
1670 imx_uart_stop_tx(port);
1671
1672 /*
1673 * In many cases (rs232 mode, or if tx_state was
1674 * WAIT_AFTER_RTS, or if tx_state was SEND and there is no
1675 * delay_rts_after_send), this will have moved directly to
1676 * OFF. In rs485 mode, tx_state might already have been
1677 * WAIT_AFTER_SEND and the hrtimer thus already started, or
1678 * the above imx_uart_stop_tx() call could have started it. In
1679 * those cases, we have to wait for the hrtimer to fire and
1680 * complete the transition to OFF.
1681 */
1682 loops = port->rs485.flags & SER_RS485_ENABLED ?
1683 port->rs485.delay_rts_after_send : 0;
1684 while (sport->tx_state != OFF && loops--) {
1685 uart_port_unlock_irqrestore(&sport->port, flags);
1686 msleep(1);
1687 uart_port_lock_irqsave(&sport->port, &flags);
1688 }
1689
1690 if (sport->tx_state != OFF) {
1691 dev_warn(sport->port.dev, "unexpected tx_state %d\n",
1692 sport->tx_state);
1693 /*
1694 * This machine may be busted, but ensure the RTS
1695 * signal is inactive in order not to block other
1696 * devices.
1697 */
1698 if (port->rs485.flags & SER_RS485_ENABLED) {
1699 ucr2 = imx_uart_readl(sport, UCR2);
1700 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
1701 imx_uart_rts_active(sport, &ucr2);
1702 else
1703 imx_uart_rts_inactive(sport, &ucr2);
1704 imx_uart_writel(sport, ucr2, UCR2);
1705 }
1706 sport->tx_state = OFF;
1707 }
1708
1709 uart_port_unlock_irqrestore(&sport->port, flags);
1710
1711 clk_disable_unprepare(sport->clk_per);
1712 clk_disable_unprepare(sport->clk_ipg);
1713}
1714
1715/* called with port.lock taken and irqs off */
1716static void imx_uart_flush_buffer(struct uart_port *port)
1717{
1718 struct imx_port *sport = to_imx_port(port);
1719 struct scatterlist *sgl = &sport->tx_sgl[0];
1720
1721 if (!sport->dma_chan_tx)
1722 return;
1723
1724 sport->tx_bytes = 0;
1725 dmaengine_terminate_all(sport->dma_chan_tx);
1726 if (sport->dma_is_txing) {
1727 u32 ucr1;
1728
1729 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents,
1730 DMA_TO_DEVICE);
1731 ucr1 = imx_uart_readl(sport, UCR1);
1732 ucr1 &= ~UCR1_TXDMAEN;
1733 imx_uart_writel(sport, ucr1, UCR1);
1734 sport->dma_is_txing = 0;
1735 }
1736
1737 imx_uart_soft_reset(sport);
1738
1739}
1740
1741static void
1742imx_uart_set_termios(struct uart_port *port, struct ktermios *termios,
1743 const struct ktermios *old)
1744{
1745 struct imx_port *sport = to_imx_port(port);
1746 unsigned long flags;
1747 u32 ucr2, old_ucr2, ufcr;
1748 unsigned int baud, quot;
1749 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1750 unsigned long div;
1751 unsigned long num, denom, old_ubir, old_ubmr;
1752 uint64_t tdiv64;
1753
1754 /*
1755 * We only support CS7 and CS8.
1756 */
1757 while ((termios->c_cflag & CSIZE) != CS7 &&
1758 (termios->c_cflag & CSIZE) != CS8) {
1759 termios->c_cflag &= ~CSIZE;
1760 termios->c_cflag |= old_csize;
1761 old_csize = CS8;
1762 }
1763
1764 timer_delete_sync(&sport->timer);
1765
1766 /*
1767 * Ask the core to calculate the divisor for us.
1768 */
1769 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1770 quot = uart_get_divisor(port, baud);
1771
1772 uart_port_lock_irqsave(&sport->port, &flags);
1773
1774 /*
1775 * Read current UCR2 and save it for future use, then clear all the bits
1776 * except those we will or may need to preserve.
1777 */
1778 old_ucr2 = imx_uart_readl(sport, UCR2);
1779 ucr2 = old_ucr2 & (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN | UCR2_CTS);
1780
1781 ucr2 |= UCR2_SRST | UCR2_IRTS;
1782 if ((termios->c_cflag & CSIZE) == CS8)
1783 ucr2 |= UCR2_WS;
1784
1785 if (!sport->have_rtscts)
1786 termios->c_cflag &= ~CRTSCTS;
1787
1788 if (port->rs485.flags & SER_RS485_ENABLED) {
1789 /*
1790 * RTS is mandatory for rs485 operation, so keep
1791 * it under manual control and keep transmitter
1792 * disabled.
1793 */
1794 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
1795 imx_uart_rts_active(sport, &ucr2);
1796 else
1797 imx_uart_rts_inactive(sport, &ucr2);
1798
1799 } else if (termios->c_cflag & CRTSCTS) {
1800 /*
1801 * Only let receiver control RTS output if we were not requested
1802 * to have RTS inactive (which then should take precedence).
1803 */
1804 if (ucr2 & UCR2_CTS)
1805 ucr2 |= UCR2_CTSC;
1806 }
1807
1808 if (termios->c_cflag & CRTSCTS)
1809 ucr2 &= ~UCR2_IRTS;
1810 if (termios->c_cflag & CSTOPB)
1811 ucr2 |= UCR2_STPB;
1812 if (termios->c_cflag & PARENB) {
1813 ucr2 |= UCR2_PREN;
1814 if (termios->c_cflag & PARODD)
1815 ucr2 |= UCR2_PROE;
1816 }
1817
1818 sport->port.read_status_mask = 0;
1819 if (termios->c_iflag & INPCK)
1820 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1821 if (termios->c_iflag & (BRKINT | PARMRK))
1822 sport->port.read_status_mask |= URXD_BRK;
1823
1824 /*
1825 * Characters to ignore
1826 */
1827 sport->port.ignore_status_mask = 0;
1828 if (termios->c_iflag & IGNPAR)
1829 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR;
1830 if (termios->c_iflag & IGNBRK) {
1831 sport->port.ignore_status_mask |= URXD_BRK;
1832 /*
1833 * If we're ignoring parity and break indicators,
1834 * ignore overruns too (for real raw support).
1835 */
1836 if (termios->c_iflag & IGNPAR)
1837 sport->port.ignore_status_mask |= URXD_OVRRUN;
1838 }
1839
1840 if ((termios->c_cflag & CREAD) == 0)
1841 sport->port.ignore_status_mask |= URXD_DUMMY_READ;
1842
1843 /*
1844 * Update the per-port timeout.
1845 */
1846 uart_update_timeout(port, termios->c_cflag, baud);
1847
1848 /* custom-baudrate handling */
1849 div = sport->port.uartclk / (baud * 16);
1850 if (baud == 38400 && quot != div)
1851 baud = sport->port.uartclk / (quot * 16);
1852
1853 div = sport->port.uartclk / (baud * 16);
1854 if (div > 7)
1855 div = 7;
1856 if (!div)
1857 div = 1;
1858
1859 rational_best_approximation(16 * div * baud, sport->port.uartclk,
1860 1 << 16, 1 << 16, &num, &denom);
1861
1862 tdiv64 = sport->port.uartclk;
1863 tdiv64 *= num;
1864 do_div(tdiv64, denom * 16 * div);
1865 tty_termios_encode_baud_rate(termios,
1866 (speed_t)tdiv64, (speed_t)tdiv64);
1867
1868 num -= 1;
1869 denom -= 1;
1870
1871 ufcr = imx_uart_readl(sport, UFCR);
1872 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1873 imx_uart_writel(sport, ufcr, UFCR);
1874
1875 /*
1876 * Two registers below should always be written both and in this
1877 * particular order. One consequence is that we need to check if any of
1878 * them changes and then update both. We do need the check for change
1879 * as even writing the same values seem to "restart"
1880 * transmission/receiving logic in the hardware, that leads to data
1881 * breakage even when rate doesn't in fact change. E.g., user switches
1882 * RTS/CTS handshake and suddenly gets broken bytes.
1883 */
1884 old_ubir = imx_uart_readl(sport, UBIR);
1885 old_ubmr = imx_uart_readl(sport, UBMR);
1886 if (old_ubir != num || old_ubmr != denom) {
1887 imx_uart_writel(sport, num, UBIR);
1888 imx_uart_writel(sport, denom, UBMR);
1889 }
1890
1891 if (!imx_uart_is_imx1(sport))
1892 imx_uart_writel(sport, sport->port.uartclk / div / 1000,
1893 IMX21_ONEMS);
1894
1895 imx_uart_writel(sport, ucr2, UCR2);
1896
1897 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1898 imx_uart_enable_ms(&sport->port);
1899
1900 uart_port_unlock_irqrestore(&sport->port, flags);
1901}
1902
1903static const char *imx_uart_type(struct uart_port *port)
1904{
1905 return port->type == PORT_IMX ? "IMX" : NULL;
1906}
1907
1908/*
1909 * Configure/autoconfigure the port.
1910 */
1911static void imx_uart_config_port(struct uart_port *port, int flags)
1912{
1913 if (flags & UART_CONFIG_TYPE)
1914 port->type = PORT_IMX;
1915}
1916
1917/*
1918 * Verify the new serial_struct (for TIOCSSERIAL).
1919 * The only change we allow are to the flags and type, and
1920 * even then only between PORT_IMX and PORT_UNKNOWN
1921 */
1922static int
1923imx_uart_verify_port(struct uart_port *port, struct serial_struct *ser)
1924{
1925 int ret = 0;
1926
1927 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1928 ret = -EINVAL;
1929 if (port->irq != ser->irq)
1930 ret = -EINVAL;
1931 if (ser->io_type != UPIO_MEM)
1932 ret = -EINVAL;
1933 if (port->uartclk / 16 != ser->baud_base)
1934 ret = -EINVAL;
1935 if (port->mapbase != (unsigned long)ser->iomem_base)
1936 ret = -EINVAL;
1937 if (port->iobase != ser->port)
1938 ret = -EINVAL;
1939 if (ser->hub6 != 0)
1940 ret = -EINVAL;
1941 return ret;
1942}
1943
1944#if defined(CONFIG_CONSOLE_POLL)
1945
1946static int imx_uart_poll_init(struct uart_port *port)
1947{
1948 struct imx_port *sport = to_imx_port(port);
1949 unsigned long flags;
1950 u32 ucr1, ucr2;
1951 int retval;
1952
1953 retval = clk_prepare_enable(sport->clk_ipg);
1954 if (retval)
1955 return retval;
1956 retval = clk_prepare_enable(sport->clk_per);
1957 if (retval)
1958 clk_disable_unprepare(sport->clk_ipg);
1959
1960 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, sport->rxtl);
1961
1962 uart_port_lock_irqsave(&sport->port, &flags);
1963
1964 /*
1965 * Be careful about the order of enabling bits here. First enable the
1966 * receiver (UARTEN + RXEN) and only then the corresponding irqs.
1967 * This prevents that a character that already sits in the RX fifo is
1968 * triggering an irq but the try to fetch it from there results in an
1969 * exception because UARTEN or RXEN is still off.
1970 */
1971 ucr1 = imx_uart_readl(sport, UCR1);
1972 ucr2 = imx_uart_readl(sport, UCR2);
1973
1974 if (imx_uart_is_imx1(sport))
1975 ucr1 |= IMX1_UCR1_UARTCLKEN;
1976
1977 ucr1 |= UCR1_UARTEN;
1978 ucr1 &= ~(UCR1_TRDYEN | UCR1_RTSDEN | UCR1_RRDYEN);
1979
1980 ucr2 |= UCR2_RXEN | UCR2_TXEN;
1981 ucr2 &= ~UCR2_ATEN;
1982
1983 imx_uart_writel(sport, ucr1, UCR1);
1984 imx_uart_writel(sport, ucr2, UCR2);
1985
1986 /* now enable irqs */
1987 imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1);
1988 imx_uart_writel(sport, ucr2 | UCR2_ATEN, UCR2);
1989
1990 uart_port_unlock_irqrestore(&sport->port, flags);
1991
1992 return 0;
1993}
1994
1995static int imx_uart_poll_get_char(struct uart_port *port)
1996{
1997 struct imx_port *sport = to_imx_port(port);
1998 if (!(imx_uart_readl(sport, USR2) & USR2_RDR))
1999 return NO_POLL_CHAR;
2000
2001 return imx_uart_readl(sport, URXD0) & URXD_RX_DATA;
2002}
2003
2004static void imx_uart_poll_put_char(struct uart_port *port, unsigned char c)
2005{
2006 struct imx_port *sport = to_imx_port(port);
2007 unsigned int status;
2008
2009 /* drain */
2010 do {
2011 status = imx_uart_readl(sport, USR1);
2012 } while (~status & USR1_TRDY);
2013
2014 /* write */
2015 imx_uart_writel(sport, c, URTX0);
2016
2017 /* flush */
2018 do {
2019 status = imx_uart_readl(sport, USR2);
2020 } while (~status & USR2_TXDC);
2021}
2022#endif
2023
2024/* called with port.lock taken and irqs off or from .probe without locking */
2025static int imx_uart_rs485_config(struct uart_port *port, struct ktermios *termios,
2026 struct serial_rs485 *rs485conf)
2027{
2028 struct imx_port *sport = to_imx_port(port);
2029 u32 ucr2, ufcr;
2030
2031 if (rs485conf->flags & SER_RS485_ENABLED) {
2032 /* Enable receiver if low-active RTS signal is requested */
2033 if (sport->have_rtscts && !sport->have_rtsgpio &&
2034 !(rs485conf->flags & SER_RS485_RTS_ON_SEND))
2035 rs485conf->flags |= SER_RS485_RX_DURING_TX;
2036
2037 /* disable transmitter */
2038 ucr2 = imx_uart_readl(sport, UCR2);
2039 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND)
2040 imx_uart_rts_active(sport, &ucr2);
2041 else
2042 imx_uart_rts_inactive(sport, &ucr2);
2043 imx_uart_writel(sport, ucr2, UCR2);
2044 }
2045
2046 /* Make sure Rx is enabled in case Tx is active with Rx disabled */
2047 if (!(rs485conf->flags & SER_RS485_ENABLED) ||
2048 rs485conf->flags & SER_RS485_RX_DURING_TX) {
2049 /* If the receiver trigger is 0, set it to a default value */
2050 ufcr = imx_uart_readl(sport, UFCR);
2051 if ((ufcr & UFCR_RXTL_MASK) == 0)
2052 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, sport->rxtl);
2053 imx_uart_start_rx(port);
2054 }
2055
2056 return 0;
2057}
2058
2059static const struct uart_ops imx_uart_pops = {
2060 .tx_empty = imx_uart_tx_empty,
2061 .set_mctrl = imx_uart_set_mctrl,
2062 .get_mctrl = imx_uart_get_mctrl,
2063 .stop_tx = imx_uart_stop_tx,
2064 .start_tx = imx_uart_start_tx,
2065 .stop_rx = imx_uart_stop_rx,
2066 .enable_ms = imx_uart_enable_ms,
2067 .break_ctl = imx_uart_break_ctl,
2068 .startup = imx_uart_startup,
2069 .shutdown = imx_uart_shutdown,
2070 .flush_buffer = imx_uart_flush_buffer,
2071 .set_termios = imx_uart_set_termios,
2072 .type = imx_uart_type,
2073 .config_port = imx_uart_config_port,
2074 .verify_port = imx_uart_verify_port,
2075#if defined(CONFIG_CONSOLE_POLL)
2076 .poll_init = imx_uart_poll_init,
2077 .poll_get_char = imx_uart_poll_get_char,
2078 .poll_put_char = imx_uart_poll_put_char,
2079#endif
2080};
2081
2082static struct imx_port *imx_uart_ports[UART_NR];
2083
2084/* Held across uart_add/remove_one_port(); console callbacks must not take it. */
2085static DEFINE_MUTEX(imx_uart_ports_lock);
2086
2087#if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE)
2088static void imx_uart_console_putchar(struct uart_port *port, unsigned char ch)
2089{
2090 struct imx_port *sport = to_imx_port(port);
2091
2092 while (imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)
2093 barrier();
2094
2095 imx_uart_writel(sport, ch, URTX0);
2096
2097 sport->last_putchar_was_newline = (ch == '\n');
2098}
2099
2100static void imx_uart_console_device_lock(struct console *co, unsigned long *flags)
2101{
2102 struct uart_port *up = &imx_uart_ports[co->index]->port;
2103
2104 return __uart_port_lock_irqsave(up, flags);
2105}
2106
2107static void imx_uart_console_device_unlock(struct console *co, unsigned long flags)
2108{
2109 struct uart_port *up = &imx_uart_ports[co->index]->port;
2110
2111 return __uart_port_unlock_irqrestore(up, flags);
2112}
2113
2114static void imx_uart_console_write_atomic(struct console *co,
2115 struct nbcon_write_context *wctxt)
2116{
2117 struct imx_port *sport = imx_uart_ports[co->index];
2118 struct uart_port *port = &sport->port;
2119 struct imx_port_ucrs old_ucr;
2120 unsigned int ucr1, usr2;
2121
2122 if (!nbcon_enter_unsafe(wctxt))
2123 return;
2124
2125 /*
2126 * First, save UCR1/2/3 and then disable interrupts
2127 */
2128 imx_uart_ucrs_save(sport, &old_ucr);
2129 ucr1 = old_ucr.ucr1;
2130
2131 if (imx_uart_is_imx1(sport))
2132 ucr1 |= IMX1_UCR1_UARTCLKEN;
2133 ucr1 |= UCR1_UARTEN;
2134 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN);
2135
2136 imx_uart_writel(sport, ucr1, UCR1);
2137 imx_uart_writel(sport, old_ucr.ucr2 | UCR2_TXEN, UCR2);
2138
2139 if (unlikely(!sport->last_putchar_was_newline && !nbcon_is_braille(co)))
2140 uart_console_write(port, "\n", 1, imx_uart_console_putchar);
2141 uart_console_write(port, wctxt->outbuf, wctxt->len,
2142 imx_uart_console_putchar);
2143
2144 /*
2145 * Finally, wait for transmitter to become empty
2146 * and restore UCR1/2/3
2147 */
2148 read_poll_timeout_atomic(imx_uart_readl, usr2, usr2 & USR2_TXDC,
2149 0, USEC_PER_SEC, false, sport, USR2);
2150 imx_uart_ucrs_restore(sport, &old_ucr);
2151
2152 nbcon_exit_unsafe(wctxt);
2153}
2154
2155static void imx_uart_console_write_thread(struct console *co,
2156 struct nbcon_write_context *wctxt)
2157{
2158 struct imx_port *sport = imx_uart_ports[co->index];
2159 struct uart_port *port = &sport->port;
2160 struct imx_port_ucrs old_ucr;
2161 unsigned int ucr1, usr2;
2162
2163 if (!nbcon_enter_unsafe(wctxt))
2164 return;
2165
2166 /*
2167 * First, save UCR1/2/3 and then disable interrupts
2168 */
2169 imx_uart_ucrs_save(sport, &old_ucr);
2170 ucr1 = old_ucr.ucr1;
2171
2172 if (imx_uart_is_imx1(sport))
2173 ucr1 |= IMX1_UCR1_UARTCLKEN;
2174 ucr1 |= UCR1_UARTEN;
2175 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN);
2176
2177 imx_uart_writel(sport, ucr1, UCR1);
2178 imx_uart_writel(sport, old_ucr.ucr2 | UCR2_TXEN, UCR2);
2179
2180 if (nbcon_exit_unsafe(wctxt)) {
2181 int len = READ_ONCE(wctxt->len);
2182 int i;
2183
2184 /*
2185 * Write out the message. Toggle unsafe for each byte in order
2186 * to give another (higher priority) context the opportunity
2187 * for a friendly takeover. If such a takeover occurs, this
2188 * context must reacquire ownership in order to perform final
2189 * actions (such as re-enabling the interrupts).
2190 *
2191 * IMPORTANT: wctxt->outbuf and wctxt->len are no longer valid
2192 * after a reacquire so writing the message must be
2193 * aborted.
2194 */
2195 for (i = 0; i < len; i++) {
2196 if (!nbcon_enter_unsafe(wctxt))
2197 break;
2198
2199 uart_console_write(port, wctxt->outbuf + i, 1,
2200 imx_uart_console_putchar);
2201
2202 if (!nbcon_exit_unsafe(wctxt))
2203 break;
2204 }
2205 }
2206
2207 while (!nbcon_enter_unsafe(wctxt))
2208 nbcon_reacquire_nobuf(wctxt);
2209
2210 /*
2211 * Finally, wait for transmitter to become empty
2212 * and restore UCR1/2/3
2213 */
2214 read_poll_timeout(imx_uart_readl, usr2, usr2 & USR2_TXDC,
2215 0, USEC_PER_SEC, false, sport, USR2);
2216 imx_uart_ucrs_restore(sport, &old_ucr);
2217
2218 nbcon_exit_unsafe(wctxt);
2219}
2220
2221/*
2222 * If the port was already initialised (eg, by a boot loader),
2223 * try to determine the current setup.
2224 */
2225static void
2226imx_uart_console_get_options(struct imx_port *sport, int *baud,
2227 int *parity, int *bits)
2228{
2229
2230 if (imx_uart_readl(sport, UCR1) & UCR1_UARTEN) {
2231 /* ok, the port was enabled */
2232 unsigned int ucr2, ubir, ubmr, uartclk;
2233 unsigned int baud_raw;
2234 unsigned int ucfr_rfdiv;
2235
2236 ucr2 = imx_uart_readl(sport, UCR2);
2237
2238 *parity = 'n';
2239 if (ucr2 & UCR2_PREN) {
2240 if (ucr2 & UCR2_PROE)
2241 *parity = 'o';
2242 else
2243 *parity = 'e';
2244 }
2245
2246 if (ucr2 & UCR2_WS)
2247 *bits = 8;
2248 else
2249 *bits = 7;
2250
2251 ubir = imx_uart_readl(sport, UBIR) & 0xffff;
2252 ubmr = imx_uart_readl(sport, UBMR) & 0xffff;
2253
2254 ucfr_rfdiv = (imx_uart_readl(sport, UFCR) & UFCR_RFDIV) >> 7;
2255 if (ucfr_rfdiv == 6)
2256 ucfr_rfdiv = 7;
2257 else
2258 ucfr_rfdiv = 6 - ucfr_rfdiv;
2259
2260 uartclk = clk_get_rate(sport->clk_per);
2261 uartclk /= ucfr_rfdiv;
2262
2263 { /*
2264 * The next code provides exact computation of
2265 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
2266 * without need of float support or long long division,
2267 * which would be required to prevent 32bit arithmetic overflow
2268 */
2269 unsigned int mul = ubir + 1;
2270 unsigned int div = 16 * (ubmr + 1);
2271 unsigned int rem = uartclk % div;
2272
2273 baud_raw = (uartclk / div) * mul;
2274 baud_raw += (rem * mul + div / 2) / div;
2275 *baud = (baud_raw + 50) / 100 * 100;
2276 }
2277
2278 if (*baud != baud_raw)
2279 dev_info(sport->port.dev, "Console IMX rounded baud rate from %d to %d\n",
2280 baud_raw, *baud);
2281 }
2282}
2283
2284static int
2285imx_uart_console_setup(struct console *co, char *options)
2286{
2287 struct imx_port *sport;
2288 int baud = 9600;
2289 int bits = 8;
2290 int parity = 'n';
2291 int flow = 'n';
2292 int retval;
2293
2294 /*
2295 * Check whether an invalid uart number has been specified, and
2296 * if so, search for the first available port that does have
2297 * console support.
2298 */
2299 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports))
2300 co->index = 0;
2301 sport = imx_uart_ports[co->index];
2302 if (sport == NULL)
2303 return -ENODEV;
2304
2305 /* For setting the registers, we only need to enable the ipg clock. */
2306 retval = clk_prepare_enable(sport->clk_ipg);
2307 if (retval)
2308 goto error_console;
2309
2310 sport->last_putchar_was_newline = true;
2311
2312 if (options)
2313 uart_parse_options(options, &baud, &parity, &bits, &flow);
2314 else
2315 imx_uart_console_get_options(sport, &baud, &parity, &bits);
2316
2317 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, sport->rxtl);
2318
2319 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
2320
2321 if (retval) {
2322 clk_disable_unprepare(sport->clk_ipg);
2323 goto error_console;
2324 }
2325
2326 retval = clk_prepare_enable(sport->clk_per);
2327 if (retval)
2328 clk_disable_unprepare(sport->clk_ipg);
2329
2330error_console:
2331 return retval;
2332}
2333
2334static int
2335imx_uart_console_exit(struct console *co)
2336{
2337 struct imx_port *sport = imx_uart_ports[co->index];
2338
2339 clk_disable_unprepare(sport->clk_per);
2340 clk_disable_unprepare(sport->clk_ipg);
2341
2342 return 0;
2343}
2344
2345static struct uart_driver imx_uart_uart_driver;
2346static struct console imx_uart_console = {
2347 .name = DEV_NAME,
2348 .write_atomic = imx_uart_console_write_atomic,
2349 .write_thread = imx_uart_console_write_thread,
2350 .device_lock = imx_uart_console_device_lock,
2351 .device_unlock = imx_uart_console_device_unlock,
2352 .flags = CON_PRINTBUFFER | CON_NBCON,
2353 .device = uart_console_device,
2354 .setup = imx_uart_console_setup,
2355 .exit = imx_uart_console_exit,
2356 .index = -1,
2357 .data = &imx_uart_uart_driver,
2358};
2359
2360#define IMX_CONSOLE &imx_uart_console
2361
2362#else
2363#define IMX_CONSOLE NULL
2364#endif
2365
2366static struct uart_driver imx_uart_uart_driver = {
2367 .owner = THIS_MODULE,
2368 .driver_name = DRIVER_NAME,
2369 .dev_name = DEV_NAME,
2370 .major = SERIAL_IMX_MAJOR,
2371 .minor = MINOR_START,
2372 .nr = ARRAY_SIZE(imx_uart_ports),
2373 .cons = IMX_CONSOLE,
2374};
2375
2376static enum hrtimer_restart imx_trigger_start_tx(struct hrtimer *t)
2377{
2378 struct imx_port *sport = container_of(t, struct imx_port, trigger_start_tx);
2379 unsigned long flags;
2380
2381 uart_port_lock_irqsave(&sport->port, &flags);
2382 if (sport->tx_state == WAIT_AFTER_RTS)
2383 imx_uart_start_tx(&sport->port);
2384 uart_port_unlock_irqrestore(&sport->port, flags);
2385
2386 return HRTIMER_NORESTART;
2387}
2388
2389static enum hrtimer_restart imx_trigger_stop_tx(struct hrtimer *t)
2390{
2391 struct imx_port *sport = container_of(t, struct imx_port, trigger_stop_tx);
2392 unsigned long flags;
2393
2394 uart_port_lock_irqsave(&sport->port, &flags);
2395 if (sport->tx_state == WAIT_AFTER_SEND)
2396 imx_uart_stop_tx(&sport->port);
2397 uart_port_unlock_irqrestore(&sport->port, flags);
2398
2399 return HRTIMER_NORESTART;
2400}
2401
2402static const struct serial_rs485 imx_rs485_supported = {
2403 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND |
2404 SER_RS485_RX_DURING_TX,
2405 .delay_rts_before_send = 1,
2406 .delay_rts_after_send = 1,
2407};
2408
2409/* Default RX DMA buffer configuration */
2410#define RX_DMA_PERIODS 16
2411#define RX_DMA_PERIOD_LEN (PAGE_SIZE / 4)
2412
2413static int imx_uart_probe(struct platform_device *pdev)
2414{
2415 struct device_node *np = pdev->dev.of_node;
2416 struct imx_port *sport;
2417 void __iomem *base;
2418 u32 dma_buf_conf[2];
2419 int ret = 0;
2420 u32 ucr1, ucr2, uts;
2421 struct resource *res;
2422 int txirq, rxirq, rtsirq;
2423
2424 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2425 if (!sport)
2426 return -ENOMEM;
2427
2428 sport->devdata = of_device_get_match_data(&pdev->dev);
2429
2430 ret = of_alias_get_id(np, "serial");
2431 if (ret < 0) {
2432 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
2433 return ret;
2434 }
2435 sport->port.line = ret;
2436
2437 sport->have_rtscts = of_property_read_bool(np, "uart-has-rtscts") ||
2438 of_property_read_bool(np, "fsl,uart-has-rtscts"); /* deprecated */
2439
2440 sport->dte_mode = of_property_read_bool(np, "fsl,dte-mode");
2441
2442 sport->have_rtsgpio = of_property_present(np, "rts-gpios");
2443
2444 sport->inverted_tx = of_property_read_bool(np, "fsl,inverted-tx");
2445
2446 sport->inverted_rx = of_property_read_bool(np, "fsl,inverted-rx");
2447
2448 if (!of_property_read_u32_array(np, "fsl,dma-info", dma_buf_conf, 2)) {
2449 sport->rx_period_length = dma_buf_conf[0];
2450 sport->rx_periods = dma_buf_conf[1];
2451 } else {
2452 sport->rx_period_length = RX_DMA_PERIOD_LEN;
2453 sport->rx_periods = RX_DMA_PERIODS;
2454 }
2455
2456 if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) {
2457 dev_err(&pdev->dev, "serial%d out of range\n",
2458 sport->port.line);
2459 return -EINVAL;
2460 }
2461
2462 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
2463 if (IS_ERR(base))
2464 return PTR_ERR(base);
2465
2466 rxirq = platform_get_irq(pdev, 0);
2467 if (rxirq < 0)
2468 return rxirq;
2469 txirq = platform_get_irq_optional(pdev, 1);
2470 rtsirq = platform_get_irq_optional(pdev, 2);
2471
2472 sport->port.dev = &pdev->dev;
2473 sport->port.mapbase = res->start;
2474 sport->port.membase = base;
2475 sport->port.type = PORT_IMX;
2476 sport->port.iotype = UPIO_MEM;
2477 sport->port.irq = rxirq;
2478 sport->port.fifosize = 32;
2479 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE);
2480 sport->port.ops = &imx_uart_pops;
2481 sport->port.rs485_config = imx_uart_rs485_config;
2482 /* RTS is required to control the RS485 transmitter */
2483 if (sport->have_rtscts || sport->have_rtsgpio)
2484 sport->port.rs485_supported = imx_rs485_supported;
2485 sport->port.flags = UPF_BOOT_AUTOCONF;
2486 timer_setup(&sport->timer, imx_uart_timeout, 0);
2487
2488 sport->gpios = mctrl_gpio_init(&sport->port, 0);
2489 if (IS_ERR(sport->gpios))
2490 return PTR_ERR(sport->gpios);
2491
2492 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2493 if (IS_ERR(sport->clk_ipg)) {
2494 ret = PTR_ERR(sport->clk_ipg);
2495 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
2496 return ret;
2497 }
2498
2499 sport->clk_per = devm_clk_get(&pdev->dev, "per");
2500 if (IS_ERR(sport->clk_per)) {
2501 ret = PTR_ERR(sport->clk_per);
2502 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
2503 return ret;
2504 }
2505
2506 sport->port.uartclk = clk_get_rate(sport->clk_per);
2507
2508 /* For register access, we only need to enable the ipg clock. */
2509 ret = clk_prepare_enable(sport->clk_ipg);
2510 if (ret) {
2511 dev_err(&pdev->dev, "failed to enable ipg clk: %d\n", ret);
2512 return ret;
2513 }
2514
2515 ret = uart_get_rs485_mode(&sport->port);
2516 if (ret)
2517 goto err_clk;
2518
2519 /*
2520 * If using the i.MX UART RTS/CTS control then the RTS (CTS_B)
2521 * signal cannot be set low during transmission in case the
2522 * receiver is off (limitation of the i.MX UART IP).
2523 */
2524 if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2525 sport->have_rtscts && !sport->have_rtsgpio &&
2526 (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) &&
2527 !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX)))
2528 dev_err(&pdev->dev,
2529 "low-active RTS not possible when receiver is off, enabling receiver\n");
2530
2531 /* Disable interrupts before requesting them */
2532 ucr1 = imx_uart_readl(sport, UCR1);
2533 ucr1 &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN | UCR1_RTSDEN);
2534 imx_uart_writel(sport, ucr1, UCR1);
2535
2536 /* Disable Ageing Timer interrupt */
2537 ucr2 = imx_uart_readl(sport, UCR2);
2538 ucr2 &= ~UCR2_ATEN;
2539 imx_uart_writel(sport, ucr2, UCR2);
2540
2541 /*
2542 * In case RS485 is enabled without GPIO RTS control, the UART IP
2543 * is used to control CTS signal. Keep both the UART and Receiver
2544 * enabled, otherwise the UART IP pulls CTS signal always HIGH no
2545 * matter how the UCR2 CTSC and CTS bits are set. To prevent any
2546 * data from being fed into the RX FIFO, enable loopback mode in
2547 * UTS register, which disconnects the RX path from external RXD
2548 * pin and connects it to the Transceiver, which is disabled, so
2549 * no data can be fed to the RX FIFO that way.
2550 */
2551 if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2552 sport->have_rtscts && !sport->have_rtsgpio) {
2553 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
2554 uts |= UTS_LOOP;
2555 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
2556
2557 ucr1 = imx_uart_readl(sport, UCR1);
2558 ucr1 |= UCR1_UARTEN;
2559 imx_uart_writel(sport, ucr1, UCR1);
2560
2561 ucr2 = imx_uart_readl(sport, UCR2);
2562 ucr2 |= UCR2_RXEN;
2563 imx_uart_writel(sport, ucr2, UCR2);
2564 }
2565
2566 if (!imx_uart_is_imx1(sport) && sport->dte_mode) {
2567 /*
2568 * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI
2569 * and influences if UCR3_RI and UCR3_DCD changes the level of RI
2570 * and DCD (when they are outputs) or enables the respective
2571 * irqs. So set this bit early, i.e. before requesting irqs.
2572 */
2573 u32 ufcr = imx_uart_readl(sport, UFCR);
2574 if (!(ufcr & UFCR_DCEDTE))
2575 imx_uart_writel(sport, ufcr | UFCR_DCEDTE, UFCR);
2576
2577 /*
2578 * Disable UCR3_RI and UCR3_DCD irqs. They are also not
2579 * enabled later because they cannot be cleared
2580 * (confirmed on i.MX25) which makes them unusable.
2581 */
2582 imx_uart_writel(sport,
2583 IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR,
2584 UCR3);
2585
2586 } else {
2587 u32 ucr3 = UCR3_DSR;
2588 u32 ufcr = imx_uart_readl(sport, UFCR);
2589 if (ufcr & UFCR_DCEDTE)
2590 imx_uart_writel(sport, ufcr & ~UFCR_DCEDTE, UFCR);
2591
2592 if (!imx_uart_is_imx1(sport))
2593 ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
2594 imx_uart_writel(sport, ucr3, UCR3);
2595 }
2596
2597 hrtimer_setup(&sport->trigger_start_tx, imx_trigger_start_tx, CLOCK_MONOTONIC,
2598 HRTIMER_MODE_REL);
2599 hrtimer_setup(&sport->trigger_stop_tx, imx_trigger_stop_tx, CLOCK_MONOTONIC,
2600 HRTIMER_MODE_REL);
2601
2602 /*
2603 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
2604 * chips only have one interrupt.
2605 */
2606 if (txirq > 0) {
2607 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_rxint, 0,
2608 dev_name(&pdev->dev), sport);
2609 if (ret)
2610 goto err_clk;
2611
2612 ret = devm_request_irq(&pdev->dev, txirq, imx_uart_txint, 0,
2613 dev_name(&pdev->dev), sport);
2614 if (ret)
2615 goto err_clk;
2616
2617 ret = devm_request_irq(&pdev->dev, rtsirq, imx_uart_rtsint, 0,
2618 dev_name(&pdev->dev), sport);
2619 if (ret)
2620 goto err_clk;
2621 } else {
2622 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_int, 0,
2623 dev_name(&pdev->dev), sport);
2624 if (ret)
2625 goto err_clk;
2626 }
2627
2628 platform_set_drvdata(pdev, sport);
2629
2630 scoped_guard(mutex, &imx_uart_ports_lock) {
2631 if (imx_uart_ports[sport->port.line]) {
2632 ret = -EBUSY;
2633 } else {
2634 imx_uart_ports[sport->port.line] = sport;
2635 ret = uart_add_one_port(&imx_uart_uart_driver,
2636 &sport->port);
2637 if (ret)
2638 imx_uart_ports[sport->port.line] = NULL;
2639 }
2640 }
2641
2642err_clk:
2643 clk_disable_unprepare(sport->clk_ipg);
2644
2645 return ret;
2646}
2647
2648static void imx_uart_remove(struct platform_device *pdev)
2649{
2650 struct imx_port *sport = platform_get_drvdata(pdev);
2651
2652 guard(mutex)(&imx_uart_ports_lock);
2653 uart_remove_one_port(&imx_uart_uart_driver, &sport->port);
2654 imx_uart_ports[sport->port.line] = NULL;
2655}
2656
2657static void imx_uart_restore_context(struct imx_port *sport)
2658{
2659 unsigned long flags;
2660
2661 uart_port_lock_irqsave(&sport->port, &flags);
2662 if (!sport->context_saved) {
2663 uart_port_unlock_irqrestore(&sport->port, flags);
2664 return;
2665 }
2666
2667 imx_uart_writel(sport, sport->saved_reg[4], UFCR);
2668 imx_uart_writel(sport, sport->saved_reg[5], UESC);
2669 imx_uart_writel(sport, sport->saved_reg[6], UTIM);
2670 imx_uart_writel(sport, sport->saved_reg[7], UBIR);
2671 imx_uart_writel(sport, sport->saved_reg[8], UBMR);
2672 imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS);
2673 imx_uart_writel(sport, sport->saved_reg[0], UCR1);
2674 imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2);
2675 imx_uart_writel(sport, sport->saved_reg[2], UCR3);
2676 imx_uart_writel(sport, sport->saved_reg[3], UCR4);
2677 sport->context_saved = false;
2678 uart_port_unlock_irqrestore(&sport->port, flags);
2679}
2680
2681static void imx_uart_save_context(struct imx_port *sport)
2682{
2683 unsigned long flags;
2684
2685 /* Save necessary regs */
2686 uart_port_lock_irqsave(&sport->port, &flags);
2687 sport->saved_reg[0] = imx_uart_readl(sport, UCR1);
2688 sport->saved_reg[1] = imx_uart_readl(sport, UCR2);
2689 sport->saved_reg[2] = imx_uart_readl(sport, UCR3);
2690 sport->saved_reg[3] = imx_uart_readl(sport, UCR4);
2691 sport->saved_reg[4] = imx_uart_readl(sport, UFCR);
2692 sport->saved_reg[5] = imx_uart_readl(sport, UESC);
2693 sport->saved_reg[6] = imx_uart_readl(sport, UTIM);
2694 sport->saved_reg[7] = imx_uart_readl(sport, UBIR);
2695 sport->saved_reg[8] = imx_uart_readl(sport, UBMR);
2696 sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS);
2697 sport->context_saved = true;
2698 uart_port_unlock_irqrestore(&sport->port, flags);
2699}
2700
2701/* called with irq off */
2702static void imx_uart_enable_wakeup(struct imx_port *sport, bool on)
2703{
2704 struct tty_port *port = &sport->port.state->port;
2705 struct device *tty_dev;
2706 bool may_wake = false, wake_active = false;
2707 u32 ucr3, usr1;
2708
2709 scoped_guard(tty_port_tty, port) {
2710 struct tty_struct *tty = scoped_tty();
2711
2712 tty_dev = tty->dev;
2713 may_wake = tty_dev && device_may_wakeup(tty_dev);
2714 }
2715
2716 /* only configure the wake register when device set as wakeup source */
2717 if (!may_wake)
2718 return;
2719
2720 uart_port_lock_irq(&sport->port);
2721
2722 usr1 = imx_uart_readl(sport, USR1);
2723 ucr3 = imx_uart_readl(sport, UCR3);
2724 if (on) {
2725 imx_uart_writel(sport, USR1_AWAKE, USR1);
2726 ucr3 |= UCR3_AWAKEN;
2727 } else {
2728 ucr3 &= ~UCR3_AWAKEN;
2729 wake_active = usr1 & USR1_AWAKE;
2730 }
2731 imx_uart_writel(sport, ucr3, UCR3);
2732
2733 if (sport->have_rtscts) {
2734 u32 ucr1 = imx_uart_readl(sport, UCR1);
2735 if (on) {
2736 imx_uart_writel(sport, USR1_RTSD, USR1);
2737 ucr1 |= UCR1_RTSDEN;
2738 } else {
2739 ucr1 &= ~UCR1_RTSDEN;
2740 wake_active = wake_active || (usr1 & USR1_RTSD);
2741 }
2742 imx_uart_writel(sport, ucr1, UCR1);
2743 }
2744
2745 if (wake_active && irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq)))
2746 pm_wakeup_event(tty_port_tty_get(port)->dev, 0);
2747
2748 uart_port_unlock_irq(&sport->port);
2749}
2750
2751static int imx_uart_suspend_noirq(struct device *dev)
2752{
2753 struct imx_port *sport = dev_get_drvdata(dev);
2754
2755 imx_uart_save_context(sport);
2756
2757 clk_disable(sport->clk_ipg);
2758
2759 pinctrl_pm_select_sleep_state(dev);
2760
2761 return 0;
2762}
2763
2764static int imx_uart_resume_noirq(struct device *dev)
2765{
2766 struct imx_port *sport = dev_get_drvdata(dev);
2767 int ret;
2768
2769 pinctrl_pm_select_default_state(dev);
2770
2771 ret = clk_enable(sport->clk_ipg);
2772 if (ret)
2773 return ret;
2774
2775 imx_uart_restore_context(sport);
2776
2777 return 0;
2778}
2779
2780static int imx_uart_suspend(struct device *dev)
2781{
2782 struct imx_port *sport = dev_get_drvdata(dev);
2783 int ret;
2784
2785 uart_suspend_port(&imx_uart_uart_driver, &sport->port);
2786 disable_irq(sport->port.irq);
2787
2788 ret = clk_prepare_enable(sport->clk_ipg);
2789 if (ret)
2790 return ret;
2791
2792 /* enable wakeup from i.MX UART */
2793 imx_uart_enable_wakeup(sport, true);
2794
2795 return 0;
2796}
2797
2798static int imx_uart_resume(struct device *dev)
2799{
2800 struct imx_port *sport = dev_get_drvdata(dev);
2801
2802 /* disable wakeup from i.MX UART */
2803 imx_uart_enable_wakeup(sport, false);
2804
2805 uart_resume_port(&imx_uart_uart_driver, &sport->port);
2806 enable_irq(sport->port.irq);
2807
2808 clk_disable_unprepare(sport->clk_ipg);
2809
2810 return 0;
2811}
2812
2813static int imx_uart_freeze(struct device *dev)
2814{
2815 struct imx_port *sport = dev_get_drvdata(dev);
2816
2817 uart_suspend_port(&imx_uart_uart_driver, &sport->port);
2818
2819 return clk_prepare_enable(sport->clk_ipg);
2820}
2821
2822static int imx_uart_thaw(struct device *dev)
2823{
2824 struct imx_port *sport = dev_get_drvdata(dev);
2825
2826 uart_resume_port(&imx_uart_uart_driver, &sport->port);
2827
2828 clk_disable_unprepare(sport->clk_ipg);
2829
2830 return 0;
2831}
2832
2833static const struct dev_pm_ops imx_uart_pm_ops = {
2834 .suspend_noirq = imx_uart_suspend_noirq,
2835 .resume_noirq = imx_uart_resume_noirq,
2836 .freeze_noirq = imx_uart_suspend_noirq,
2837 .thaw_noirq = imx_uart_resume_noirq,
2838 .restore_noirq = imx_uart_resume_noirq,
2839 .suspend = imx_uart_suspend,
2840 .resume = imx_uart_resume,
2841 .freeze = imx_uart_freeze,
2842 .thaw = imx_uart_thaw,
2843 .restore = imx_uart_thaw,
2844};
2845
2846static struct platform_driver imx_uart_platform_driver = {
2847 .probe = imx_uart_probe,
2848 .remove = imx_uart_remove,
2849
2850 .driver = {
2851 .name = "imx-uart",
2852 .of_match_table = imx_uart_dt_ids,
2853 .pm = &imx_uart_pm_ops,
2854 },
2855};
2856
2857static int __init imx_uart_init(void)
2858{
2859 int ret = uart_register_driver(&imx_uart_uart_driver);
2860
2861 if (ret)
2862 return ret;
2863
2864 ret = platform_driver_register(&imx_uart_platform_driver);
2865 if (ret != 0)
2866 uart_unregister_driver(&imx_uart_uart_driver);
2867
2868 return ret;
2869}
2870
2871static void __exit imx_uart_exit(void)
2872{
2873 platform_driver_unregister(&imx_uart_platform_driver);
2874 uart_unregister_driver(&imx_uart_uart_driver);
2875}
2876
2877module_init(imx_uart_init);
2878module_exit(imx_uart_exit);
2879
2880MODULE_AUTHOR("Sascha Hauer");
2881MODULE_DESCRIPTION("IMX generic serial port driver");
2882MODULE_LICENSE("GPL");
2883MODULE_ALIAS("platform:imx-uart");