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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * serial_tegra.c
4 *
5 * High-speed serial driver for NVIDIA Tegra SoCs
6 *
7 * Copyright (c) 2012-2019, NVIDIA CORPORATION. All rights reserved.
8 *
9 * Author: Laxman Dewangan <[email protected]>
10 */
11
12#include <linux/clk.h>
13#include <linux/debugfs.h>
14#include <linux/delay.h>
15#include <linux/dmaengine.h>
16#include <linux/dma-mapping.h>
17#include <linux/dmapool.h>
18#include <linux/err.h>
19#include <linux/io.h>
20#include <linux/irq.h>
21#include <linux/module.h>
22#include <linux/of.h>
23#include <linux/pagemap.h>
24#include <linux/platform_device.h>
25#include <linux/reset.h>
26#include <linux/serial.h>
27#include <linux/serial_8250.h>
28#include <linux/serial_core.h>
29#include <linux/serial_reg.h>
30#include <linux/slab.h>
31#include <linux/string.h>
32#include <linux/termios.h>
33#include <linux/tty.h>
34#include <linux/tty_flip.h>
35
36#define TEGRA_UART_TYPE "TEGRA_UART"
37#define TX_EMPTY_STATUS (UART_LSR_TEMT | UART_LSR_THRE)
38#define BYTES_TO_ALIGN(x) ((unsigned long)(x) & 0x3)
39
40#define TEGRA_UART_RX_DMA_BUFFER_SIZE 4096
41#define TEGRA_UART_LSR_TXFIFO_FULL 0x100
42#define TEGRA_UART_IER_EORD 0x20
43#define TEGRA_UART_MCR_RTS_EN 0x40
44#define TEGRA_UART_MCR_CTS_EN 0x20
45#define TEGRA_UART_LSR_ANY (UART_LSR_OE | UART_LSR_BI | \
46 UART_LSR_PE | UART_LSR_FE)
47#define TEGRA_UART_IRDA_CSR 0x08
48#define TEGRA_UART_SIR_ENABLED 0x80
49
50#define TEGRA_UART_TX_PIO 1
51#define TEGRA_UART_TX_DMA 2
52#define TEGRA_UART_MIN_DMA 16
53#define TEGRA_UART_FIFO_SIZE 32
54
55/*
56 * Tx fifo trigger level setting in tegra uart is in
57 * reverse way then conventional uart.
58 */
59#define TEGRA_UART_TX_TRIG_16B 0x00
60#define TEGRA_UART_TX_TRIG_8B 0x10
61#define TEGRA_UART_TX_TRIG_4B 0x20
62#define TEGRA_UART_TX_TRIG_1B 0x30
63
64#define TEGRA_UART_MAXIMUM 8
65
66/* Default UART setting when started: 115200 no parity, stop, 8 data bits */
67#define TEGRA_UART_DEFAULT_BAUD 115200
68#define TEGRA_UART_DEFAULT_LSR UART_LCR_WLEN8
69
70/* Tx transfer mode */
71#define TEGRA_TX_PIO 1
72#define TEGRA_TX_DMA 2
73
74#define TEGRA_UART_FCR_IIR_FIFO_EN 0x40
75
76/**
77 * struct tegra_uart_chip_data: SOC specific data.
78 *
79 * @tx_fifo_full_status: Status flag available for checking tx fifo full.
80 * @allow_txfifo_reset_fifo_mode: allow_tx fifo reset with fifo mode or not.
81 * Tegra30 does not allow this.
82 * @support_clk_src_div: Clock source support the clock divider.
83 * @fifo_mode_enable_status: Is FIFO mode enabled?
84 * @uart_max_port: Maximum number of UART ports
85 * @max_dma_burst_bytes: Maximum size of DMA bursts
86 * @error_tolerance_low_range: Lowest number in the error tolerance range
87 * @error_tolerance_high_range: Highest number in the error tolerance range
88 */
89struct tegra_uart_chip_data {
90 bool tx_fifo_full_status;
91 bool allow_txfifo_reset_fifo_mode;
92 bool support_clk_src_div;
93 bool fifo_mode_enable_status;
94 int uart_max_port;
95 int max_dma_burst_bytes;
96 int error_tolerance_low_range;
97 int error_tolerance_high_range;
98};
99
100struct tegra_baud_tolerance {
101 u32 lower_range_baud;
102 u32 upper_range_baud;
103 s32 tolerance;
104};
105
106struct tegra_uart_port {
107 struct uart_port uport;
108 const struct tegra_uart_chip_data *cdata;
109
110 struct clk *uart_clk;
111 struct reset_control *rst;
112 unsigned int current_baud;
113
114 /* Register shadow */
115 unsigned long fcr_shadow;
116 unsigned long mcr_shadow;
117 unsigned long lcr_shadow;
118 unsigned long ier_shadow;
119 bool rts_active;
120
121 int tx_in_progress;
122 unsigned int tx_bytes;
123
124 bool enable_modem_interrupt;
125
126 bool rx_timeout;
127 int rx_in_progress;
128 int symb_bit;
129
130 struct dma_chan *rx_dma_chan;
131 struct dma_chan *tx_dma_chan;
132 dma_addr_t rx_dma_buf_phys;
133 dma_addr_t tx_dma_buf_phys;
134 unsigned char *rx_dma_buf_virt;
135 unsigned char *tx_dma_buf_virt;
136 struct dma_async_tx_descriptor *tx_dma_desc;
137 struct dma_async_tx_descriptor *rx_dma_desc;
138 dma_cookie_t tx_cookie;
139 dma_cookie_t rx_cookie;
140 unsigned int tx_bytes_requested;
141 unsigned int rx_bytes_requested;
142 struct tegra_baud_tolerance *baud_tolerance;
143 int n_adjustable_baud_rates;
144 int required_rate;
145 int configured_rate;
146 bool use_rx_pio;
147 bool use_tx_pio;
148 bool rx_dma_active;
149};
150
151static void tegra_uart_start_next_tx(struct tegra_uart_port *tup);
152static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup);
153static void tegra_uart_dma_channel_free(struct tegra_uart_port *tup,
154 bool dma_to_memory);
155
156static inline unsigned long tegra_uart_read(struct tegra_uart_port *tup,
157 unsigned long reg)
158{
159 return readl(tup->uport.membase + (reg << tup->uport.regshift));
160}
161
162static inline void tegra_uart_write(struct tegra_uart_port *tup, unsigned val,
163 unsigned long reg)
164{
165 writel(val, tup->uport.membase + (reg << tup->uport.regshift));
166}
167
168static inline struct tegra_uart_port *to_tegra_uport(struct uart_port *u)
169{
170 return container_of(u, struct tegra_uart_port, uport);
171}
172
173static unsigned int tegra_uart_get_mctrl(struct uart_port *u)
174{
175 struct tegra_uart_port *tup = to_tegra_uport(u);
176
177 /*
178 * RI - Ring detector is active
179 * CD/DCD/CAR - Carrier detect is always active. For some reason
180 * linux has different names for carrier detect.
181 * DSR - Data Set ready is active as the hardware doesn't support it.
182 * Don't know if the linux support this yet?
183 * CTS - Clear to send. Always set to active, as the hardware handles
184 * CTS automatically.
185 */
186 if (tup->enable_modem_interrupt)
187 return TIOCM_RI | TIOCM_CD | TIOCM_DSR | TIOCM_CTS;
188 return TIOCM_CTS;
189}
190
191static void set_rts(struct tegra_uart_port *tup, bool active)
192{
193 unsigned long mcr;
194
195 mcr = tup->mcr_shadow;
196 if (active)
197 mcr |= TEGRA_UART_MCR_RTS_EN;
198 else
199 mcr &= ~TEGRA_UART_MCR_RTS_EN;
200 if (mcr != tup->mcr_shadow) {
201 tegra_uart_write(tup, mcr, UART_MCR);
202 tup->mcr_shadow = mcr;
203 }
204}
205
206static void set_dtr(struct tegra_uart_port *tup, bool active)
207{
208 unsigned long mcr;
209
210 mcr = tup->mcr_shadow;
211 if (active)
212 mcr |= UART_MCR_DTR;
213 else
214 mcr &= ~UART_MCR_DTR;
215 if (mcr != tup->mcr_shadow) {
216 tegra_uart_write(tup, mcr, UART_MCR);
217 tup->mcr_shadow = mcr;
218 }
219}
220
221static void set_loopbk(struct tegra_uart_port *tup, bool active)
222{
223 unsigned long mcr = tup->mcr_shadow;
224
225 if (active)
226 mcr |= UART_MCR_LOOP;
227 else
228 mcr &= ~UART_MCR_LOOP;
229
230 if (mcr != tup->mcr_shadow) {
231 tegra_uart_write(tup, mcr, UART_MCR);
232 tup->mcr_shadow = mcr;
233 }
234}
235
236static void tegra_uart_set_mctrl(struct uart_port *u, unsigned int mctrl)
237{
238 struct tegra_uart_port *tup = to_tegra_uport(u);
239 int enable;
240
241 tup->rts_active = !!(mctrl & TIOCM_RTS);
242 set_rts(tup, tup->rts_active);
243
244 enable = !!(mctrl & TIOCM_DTR);
245 set_dtr(tup, enable);
246
247 enable = !!(mctrl & TIOCM_LOOP);
248 set_loopbk(tup, enable);
249}
250
251static void tegra_uart_break_ctl(struct uart_port *u, int break_ctl)
252{
253 struct tegra_uart_port *tup = to_tegra_uport(u);
254 unsigned long lcr;
255
256 lcr = tup->lcr_shadow;
257 if (break_ctl)
258 lcr |= UART_LCR_SBC;
259 else
260 lcr &= ~UART_LCR_SBC;
261 tegra_uart_write(tup, lcr, UART_LCR);
262 tup->lcr_shadow = lcr;
263}
264
265/**
266 * tegra_uart_wait_cycle_time: Wait for N UART clock periods
267 *
268 * @tup: Tegra serial port data structure.
269 * @cycles: Number of clock periods to wait.
270 *
271 * Tegra UARTs are clocked at 16X the baud/bit rate and hence the UART
272 * clock speed is 16X the current baud rate.
273 */
274static void tegra_uart_wait_cycle_time(struct tegra_uart_port *tup,
275 unsigned int cycles)
276{
277 if (tup->current_baud)
278 udelay(DIV_ROUND_UP(cycles * 1000000, tup->current_baud * 16));
279}
280
281/* Wait for a symbol-time. */
282static void tegra_uart_wait_sym_time(struct tegra_uart_port *tup,
283 unsigned int syms)
284{
285 if (tup->current_baud)
286 udelay(DIV_ROUND_UP(syms * tup->symb_bit * 1000000,
287 tup->current_baud));
288}
289
290static int tegra_uart_wait_fifo_mode_enabled(struct tegra_uart_port *tup)
291{
292 unsigned long iir;
293 unsigned int tmout = 100;
294
295 do {
296 iir = tegra_uart_read(tup, UART_IIR);
297 if (iir & TEGRA_UART_FCR_IIR_FIFO_EN)
298 return 0;
299 udelay(1);
300 } while (--tmout);
301
302 return -ETIMEDOUT;
303}
304
305static void tegra_uart_fifo_reset(struct tegra_uart_port *tup, u8 fcr_bits)
306{
307 unsigned long fcr = tup->fcr_shadow;
308 unsigned int lsr, tmout = 10000;
309 bool clear_tx = !!(fcr_bits & UART_FCR_CLEAR_XMIT);
310
311 if (tup->rts_active)
312 set_rts(tup, false);
313
314 /*
315 * Leaving FIFO mode below is a workaround for a Tegra30
316 * restriction on clearing the Tx FIFO while FIFO mode is
317 * enabled. It empties both FIFOs, so applying it to an
318 * Rx-only reset would destroy an in-flight transmission.
319 * Only take that path when the caller asked for CLEAR_XMIT.
320 */
321 if (tup->cdata->allow_txfifo_reset_fifo_mode || !clear_tx) {
322 fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
323 tegra_uart_write(tup, fcr, UART_FCR);
324 } else {
325 fcr &= ~UART_FCR_ENABLE_FIFO;
326 tegra_uart_write(tup, fcr, UART_FCR);
327 udelay(60);
328 fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
329 tegra_uart_write(tup, fcr, UART_FCR);
330 fcr |= UART_FCR_ENABLE_FIFO;
331 tegra_uart_write(tup, fcr, UART_FCR);
332 if (tup->cdata->fifo_mode_enable_status)
333 tegra_uart_wait_fifo_mode_enabled(tup);
334 }
335
336 /* Dummy read to ensure the write is posted */
337 tegra_uart_read(tup, UART_SCR);
338
339 /*
340 * For all tegra devices (up to t210), there is a hardware issue that
341 * requires software to wait for 32 UART clock periods for the flush
342 * to propagate, otherwise data could be lost.
343 */
344 tegra_uart_wait_cycle_time(tup, 32);
345
346 /*
347 * Only wait for the transmitter to drain when the Tx FIFO was
348 * part of the reset. For an Rx-only reset it is left intact,
349 * and waiting for TEMT here would spin for a full frame time.
350 */
351 do {
352 lsr = tegra_uart_read(tup, UART_LSR);
353 if ((!clear_tx || (lsr & UART_LSR_TEMT)) &&
354 !(lsr & UART_LSR_DR))
355 break;
356 udelay(1);
357 } while (--tmout);
358
359 if (tup->rts_active)
360 set_rts(tup, true);
361}
362
363static long tegra_get_tolerance_rate(struct tegra_uart_port *tup,
364 unsigned int baud, long rate)
365{
366 int i;
367
368 for (i = 0; i < tup->n_adjustable_baud_rates; ++i) {
369 if (baud >= tup->baud_tolerance[i].lower_range_baud &&
370 baud <= tup->baud_tolerance[i].upper_range_baud)
371 return (rate + (rate *
372 tup->baud_tolerance[i].tolerance) / 10000);
373 }
374
375 return rate;
376}
377
378static int tegra_check_rate_in_range(struct tegra_uart_port *tup)
379{
380 long diff;
381
382 diff = ((long)(tup->configured_rate - tup->required_rate) * 10000)
383 / tup->required_rate;
384 if (diff < (tup->cdata->error_tolerance_low_range * 100) ||
385 diff > (tup->cdata->error_tolerance_high_range * 100)) {
386 dev_err(tup->uport.dev,
387 "configured baud rate is out of range by %ld", diff);
388 return -EIO;
389 }
390
391 return 0;
392}
393
394static int tegra_set_baudrate(struct tegra_uart_port *tup, unsigned int baud)
395{
396 unsigned long rate;
397 unsigned int divisor;
398 unsigned long lcr;
399 unsigned long flags;
400 int ret;
401
402 if (tup->current_baud == baud)
403 return 0;
404
405 if (tup->cdata->support_clk_src_div) {
406 rate = baud * 16;
407 tup->required_rate = rate;
408
409 if (tup->n_adjustable_baud_rates)
410 rate = tegra_get_tolerance_rate(tup, baud, rate);
411
412 ret = clk_set_rate(tup->uart_clk, rate);
413 if (ret < 0) {
414 dev_err(tup->uport.dev,
415 "clk_set_rate() failed for rate %lu\n", rate);
416 return ret;
417 }
418 tup->configured_rate = clk_get_rate(tup->uart_clk);
419 divisor = 1;
420 ret = tegra_check_rate_in_range(tup);
421 if (ret < 0)
422 return ret;
423 } else {
424 rate = clk_get_rate(tup->uart_clk);
425 divisor = DIV_ROUND_CLOSEST(rate, baud * 16);
426 }
427
428 uart_port_lock_irqsave(&tup->uport, &flags);
429 lcr = tup->lcr_shadow;
430 lcr |= UART_LCR_DLAB;
431 tegra_uart_write(tup, lcr, UART_LCR);
432
433 tegra_uart_write(tup, divisor & 0xFF, UART_TX);
434 tegra_uart_write(tup, ((divisor >> 8) & 0xFF), UART_IER);
435
436 lcr &= ~UART_LCR_DLAB;
437 tegra_uart_write(tup, lcr, UART_LCR);
438
439 /* Dummy read to ensure the write is posted */
440 tegra_uart_read(tup, UART_SCR);
441 uart_port_unlock_irqrestore(&tup->uport, flags);
442
443 tup->current_baud = baud;
444
445 /* wait two character intervals at new rate */
446 tegra_uart_wait_sym_time(tup, 2);
447 return 0;
448}
449
450static u8 tegra_uart_decode_rx_error(struct tegra_uart_port *tup,
451 unsigned long lsr)
452{
453 u8 flag = TTY_NORMAL;
454
455 if (unlikely(lsr & TEGRA_UART_LSR_ANY)) {
456 if (lsr & UART_LSR_OE) {
457 /* Overrun error */
458 flag = TTY_OVERRUN;
459 tup->uport.icount.overrun++;
460 dev_dbg(tup->uport.dev, "Got overrun errors\n");
461 } else if (lsr & UART_LSR_PE) {
462 /* Parity error */
463 flag = TTY_PARITY;
464 tup->uport.icount.parity++;
465 dev_dbg(tup->uport.dev, "Got Parity errors\n");
466 } else if (lsr & UART_LSR_FE) {
467 flag = TTY_FRAME;
468 tup->uport.icount.frame++;
469 dev_dbg(tup->uport.dev, "Got frame errors\n");
470 } else if (lsr & UART_LSR_BI) {
471 /*
472 * Break error
473 * If FIFO read error without any data, reset Rx FIFO
474 */
475 if (!(lsr & UART_LSR_DR) && (lsr & UART_LSR_FIFOE))
476 tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_RCVR);
477 if (tup->uport.ignore_status_mask & UART_LSR_BI)
478 return TTY_BREAK;
479 flag = TTY_BREAK;
480 tup->uport.icount.brk++;
481 dev_dbg(tup->uport.dev, "Got Break\n");
482 }
483 uart_insert_char(&tup->uport, lsr, UART_LSR_OE, 0, flag);
484 }
485
486 return flag;
487}
488
489static int tegra_uart_request_port(struct uart_port *u)
490{
491 return 0;
492}
493
494static void tegra_uart_release_port(struct uart_port *u)
495{
496 /* Nothing to do here */
497}
498
499static void tegra_uart_fill_tx_fifo(struct tegra_uart_port *tup, int max_bytes)
500{
501 unsigned char ch;
502 int i;
503
504 for (i = 0; i < max_bytes; i++) {
505 if (tup->cdata->tx_fifo_full_status) {
506 unsigned long lsr = tegra_uart_read(tup, UART_LSR);
507 if ((lsr & TEGRA_UART_LSR_TXFIFO_FULL))
508 break;
509 }
510 if (WARN_ON_ONCE(!uart_fifo_get(&tup->uport, &ch)))
511 break;
512 tegra_uart_write(tup, ch, UART_TX);
513 }
514}
515
516static void tegra_uart_start_pio_tx(struct tegra_uart_port *tup,
517 unsigned int bytes)
518{
519 if (bytes > TEGRA_UART_MIN_DMA)
520 bytes = TEGRA_UART_MIN_DMA;
521
522 tup->tx_in_progress = TEGRA_UART_TX_PIO;
523 tup->tx_bytes = bytes;
524 tup->ier_shadow |= UART_IER_THRI;
525 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
526}
527
528static void tegra_uart_tx_dma_complete(void *args)
529{
530 struct tegra_uart_port *tup = args;
531 struct tty_port *tport = &tup->uport.state->port;
532 struct dma_tx_state state;
533 unsigned long flags;
534 unsigned int count;
535
536 dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state);
537 count = tup->tx_bytes_requested - state.residue;
538 async_tx_ack(tup->tx_dma_desc);
539 uart_port_lock_irqsave(&tup->uport, &flags);
540 uart_xmit_advance(&tup->uport, count);
541 tup->tx_in_progress = 0;
542 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
543 uart_write_wakeup(&tup->uport);
544 tegra_uart_start_next_tx(tup);
545 uart_port_unlock_irqrestore(&tup->uport, flags);
546}
547
548static int tegra_uart_start_tx_dma(struct tegra_uart_port *tup,
549 unsigned long count)
550{
551 struct tty_port *tport = &tup->uport.state->port;
552 dma_addr_t tx_phys_addr;
553 unsigned int tail;
554
555 tup->tx_bytes = count & ~(0xF);
556 WARN_ON_ONCE(kfifo_out_linear(&tport->xmit_fifo, &tail,
557 UART_XMIT_SIZE) < count);
558 tx_phys_addr = tup->tx_dma_buf_phys + tail;
559
560 dma_sync_single_for_device(tup->uport.dev, tx_phys_addr,
561 tup->tx_bytes, DMA_TO_DEVICE);
562
563 tup->tx_dma_desc = dmaengine_prep_slave_single(tup->tx_dma_chan,
564 tx_phys_addr, tup->tx_bytes, DMA_MEM_TO_DEV,
565 DMA_PREP_INTERRUPT);
566 if (!tup->tx_dma_desc) {
567 dev_err(tup->uport.dev, "Not able to get desc for Tx\n");
568 return -EIO;
569 }
570
571 tup->tx_dma_desc->callback = tegra_uart_tx_dma_complete;
572 tup->tx_dma_desc->callback_param = tup;
573 tup->tx_in_progress = TEGRA_UART_TX_DMA;
574 tup->tx_bytes_requested = tup->tx_bytes;
575 tup->tx_cookie = dmaengine_submit(tup->tx_dma_desc);
576 dma_async_issue_pending(tup->tx_dma_chan);
577 return 0;
578}
579
580static void tegra_uart_start_next_tx(struct tegra_uart_port *tup)
581{
582 struct tty_port *tport = &tup->uport.state->port;
583 unsigned char *tail_ptr;
584 unsigned long tail;
585 unsigned int count;
586
587 if (!tup->current_baud)
588 return;
589
590 count = kfifo_out_linear_ptr(&tport->xmit_fifo, &tail_ptr,
591 UART_XMIT_SIZE);
592 if (!count)
593 return;
594
595 tail = (unsigned long)tail_ptr;
596
597 if (tup->use_tx_pio || count < TEGRA_UART_MIN_DMA)
598 tegra_uart_start_pio_tx(tup, count);
599 else if (BYTES_TO_ALIGN(tail) > 0)
600 tegra_uart_start_pio_tx(tup, BYTES_TO_ALIGN(tail));
601 else
602 tegra_uart_start_tx_dma(tup, count);
603}
604
605/* Called by serial core driver with u->lock taken. */
606static void tegra_uart_start_tx(struct uart_port *u)
607{
608 struct tegra_uart_port *tup = to_tegra_uport(u);
609 struct tty_port *tport = &u->state->port;
610
611 if (!kfifo_is_empty(&tport->xmit_fifo) && !tup->tx_in_progress)
612 tegra_uart_start_next_tx(tup);
613}
614
615static unsigned int tegra_uart_tx_empty(struct uart_port *u)
616{
617 struct tegra_uart_port *tup = to_tegra_uport(u);
618 unsigned int ret = 0;
619 unsigned long flags;
620
621 uart_port_lock_irqsave(u, &flags);
622 if (!tup->tx_in_progress) {
623 unsigned long lsr = tegra_uart_read(tup, UART_LSR);
624 if ((lsr & TX_EMPTY_STATUS) == TX_EMPTY_STATUS)
625 ret = TIOCSER_TEMT;
626 }
627 uart_port_unlock_irqrestore(u, flags);
628 return ret;
629}
630
631static void tegra_uart_stop_tx(struct uart_port *u)
632{
633 struct tegra_uart_port *tup = to_tegra_uport(u);
634 struct dma_tx_state state;
635 unsigned int count;
636
637 if (tup->tx_in_progress != TEGRA_UART_TX_DMA)
638 return;
639
640 dmaengine_pause(tup->tx_dma_chan);
641 dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state);
642 dmaengine_terminate_all(tup->tx_dma_chan);
643 count = tup->tx_bytes_requested - state.residue;
644 async_tx_ack(tup->tx_dma_desc);
645 uart_xmit_advance(&tup->uport, count);
646 tup->tx_in_progress = 0;
647}
648
649static void tegra_uart_handle_tx_pio(struct tegra_uart_port *tup)
650{
651 struct tty_port *tport = &tup->uport.state->port;
652
653 tegra_uart_fill_tx_fifo(tup, tup->tx_bytes);
654 tup->tx_in_progress = 0;
655 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
656 uart_write_wakeup(&tup->uport);
657 tegra_uart_start_next_tx(tup);
658}
659
660static void tegra_uart_handle_rx_pio(struct tegra_uart_port *tup,
661 struct tty_port *port)
662{
663 do {
664 unsigned long lsr = 0;
665 u8 ch, flag = TTY_NORMAL;
666
667 lsr = tegra_uart_read(tup, UART_LSR);
668 if (!(lsr & UART_LSR_DR))
669 break;
670
671 flag = tegra_uart_decode_rx_error(tup, lsr);
672 if (flag != TTY_NORMAL)
673 continue;
674
675 ch = (unsigned char) tegra_uart_read(tup, UART_RX);
676 tup->uport.icount.rx++;
677
678 if (uart_handle_sysrq_char(&tup->uport, ch))
679 continue;
680
681 if (tup->uport.ignore_status_mask & UART_LSR_DR)
682 continue;
683
684 tty_insert_flip_char(port, ch, flag);
685 } while (1);
686}
687
688static void tegra_uart_copy_rx_to_tty(struct tegra_uart_port *tup,
689 struct tty_port *port,
690 unsigned int count)
691{
692 int copied;
693
694 /* If count is zero, then there is no data to be copied */
695 if (!count)
696 return;
697
698 tup->uport.icount.rx += count;
699
700 if (tup->uport.ignore_status_mask & UART_LSR_DR)
701 return;
702
703 dma_sync_single_for_cpu(tup->uport.dev, tup->rx_dma_buf_phys,
704 count, DMA_FROM_DEVICE);
705 copied = tty_insert_flip_string(port,
706 ((unsigned char *)(tup->rx_dma_buf_virt)), count);
707 if (copied != count) {
708 WARN_ON(1);
709 dev_err(tup->uport.dev, "RxData copy to tty layer failed\n");
710 }
711 dma_sync_single_for_device(tup->uport.dev, tup->rx_dma_buf_phys,
712 count, DMA_TO_DEVICE);
713}
714
715static void do_handle_rx_pio(struct tegra_uart_port *tup)
716{
717 struct tty_struct *tty = tty_port_tty_get(&tup->uport.state->port);
718 struct tty_port *port = &tup->uport.state->port;
719
720 tegra_uart_handle_rx_pio(tup, port);
721 if (tty) {
722 tty_flip_buffer_push(port);
723 tty_kref_put(tty);
724 }
725}
726
727static void tegra_uart_rx_buffer_push(struct tegra_uart_port *tup,
728 unsigned int residue)
729{
730 struct tty_port *port = &tup->uport.state->port;
731 unsigned int count;
732
733 async_tx_ack(tup->rx_dma_desc);
734 count = tup->rx_bytes_requested - residue;
735
736 /* If we are here, DMA is stopped */
737 tegra_uart_copy_rx_to_tty(tup, port, count);
738
739 do_handle_rx_pio(tup);
740}
741
742static void tegra_uart_rx_dma_complete(void *args)
743{
744 struct tegra_uart_port *tup = args;
745 struct uart_port *u = &tup->uport;
746 unsigned long flags;
747 struct dma_tx_state state;
748 enum dma_status status;
749
750 uart_port_lock_irqsave(u, &flags);
751
752 status = dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state);
753
754 if (status == DMA_IN_PROGRESS) {
755 dev_dbg(tup->uport.dev, "RX DMA is in progress\n");
756 goto done;
757 }
758
759 /* Deactivate flow control to stop sender */
760 if (tup->rts_active)
761 set_rts(tup, false);
762
763 tup->rx_dma_active = false;
764 tegra_uart_rx_buffer_push(tup, 0);
765 tegra_uart_start_rx_dma(tup);
766
767 /* Activate flow control to start transfer */
768 if (tup->rts_active)
769 set_rts(tup, true);
770
771done:
772 uart_port_unlock_irqrestore(u, flags);
773}
774
775static void tegra_uart_terminate_rx_dma(struct tegra_uart_port *tup)
776{
777 struct dma_tx_state state;
778
779 if (!tup->rx_dma_active) {
780 do_handle_rx_pio(tup);
781 return;
782 }
783
784 dmaengine_pause(tup->rx_dma_chan);
785 dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state);
786 dmaengine_terminate_all(tup->rx_dma_chan);
787
788 tegra_uart_rx_buffer_push(tup, state.residue);
789 tup->rx_dma_active = false;
790}
791
792static void tegra_uart_handle_rx_dma(struct tegra_uart_port *tup)
793{
794 /* Deactivate flow control to stop sender */
795 if (tup->rts_active)
796 set_rts(tup, false);
797
798 tegra_uart_terminate_rx_dma(tup);
799
800 if (tup->rts_active)
801 set_rts(tup, true);
802}
803
804static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup)
805{
806 unsigned int count = TEGRA_UART_RX_DMA_BUFFER_SIZE;
807
808 if (tup->rx_dma_active)
809 return 0;
810
811 tup->rx_dma_desc = dmaengine_prep_slave_single(tup->rx_dma_chan,
812 tup->rx_dma_buf_phys, count, DMA_DEV_TO_MEM,
813 DMA_PREP_INTERRUPT);
814 if (!tup->rx_dma_desc) {
815 dev_err(tup->uport.dev, "Not able to get desc for Rx\n");
816 return -EIO;
817 }
818
819 tup->rx_dma_active = true;
820 tup->rx_dma_desc->callback = tegra_uart_rx_dma_complete;
821 tup->rx_dma_desc->callback_param = tup;
822 tup->rx_bytes_requested = count;
823 tup->rx_cookie = dmaengine_submit(tup->rx_dma_desc);
824 dma_async_issue_pending(tup->rx_dma_chan);
825 return 0;
826}
827
828static void tegra_uart_handle_modem_signal_change(struct uart_port *u)
829{
830 struct tegra_uart_port *tup = to_tegra_uport(u);
831 unsigned long msr;
832
833 msr = tegra_uart_read(tup, UART_MSR);
834 if (!(msr & UART_MSR_ANY_DELTA))
835 return;
836
837 if (msr & UART_MSR_TERI)
838 tup->uport.icount.rng++;
839 if (msr & UART_MSR_DDSR)
840 tup->uport.icount.dsr++;
841 /* We may only get DDCD when HW init and reset */
842 if (msr & UART_MSR_DDCD)
843 uart_handle_dcd_change(&tup->uport, msr & UART_MSR_DCD);
844 /* Will start/stop_tx accordingly */
845 if (msr & UART_MSR_DCTS)
846 uart_handle_cts_change(&tup->uport, msr & UART_MSR_CTS);
847}
848
849static irqreturn_t tegra_uart_isr(int irq, void *data)
850{
851 struct tegra_uart_port *tup = data;
852 struct uart_port *u = &tup->uport;
853 unsigned long iir;
854 unsigned long ier;
855 bool is_rx_start = false;
856 bool is_rx_int = false;
857 unsigned long flags;
858
859 uart_port_lock_irqsave(u, &flags);
860 while (1) {
861 iir = tegra_uart_read(tup, UART_IIR);
862 if (iir & UART_IIR_NO_INT) {
863 if (!tup->use_rx_pio && is_rx_int) {
864 tegra_uart_handle_rx_dma(tup);
865 if (tup->rx_in_progress) {
866 ier = tup->ier_shadow;
867 ier |= (UART_IER_RLSI | UART_IER_RTOIE |
868 TEGRA_UART_IER_EORD | UART_IER_RDI);
869 tup->ier_shadow = ier;
870 tegra_uart_write(tup, ier, UART_IER);
871 }
872 } else if (is_rx_start) {
873 tegra_uart_start_rx_dma(tup);
874 }
875 uart_port_unlock_irqrestore(u, flags);
876 return IRQ_HANDLED;
877 }
878
879 switch ((iir >> 1) & 0x7) {
880 case 0: /* Modem signal change interrupt */
881 tegra_uart_handle_modem_signal_change(u);
882 break;
883
884 case 1: /* Transmit interrupt only triggered when using PIO */
885 tup->ier_shadow &= ~UART_IER_THRI;
886 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
887 tegra_uart_handle_tx_pio(tup);
888 break;
889
890 case 4: /* End of data */
891 case 6: /* Rx timeout */
892 if (!tup->use_rx_pio) {
893 is_rx_int = tup->rx_in_progress;
894 /* Disable Rx interrupts */
895 ier = tup->ier_shadow;
896 ier &= ~(UART_IER_RDI | UART_IER_RLSI |
897 UART_IER_RTOIE | TEGRA_UART_IER_EORD);
898 tup->ier_shadow = ier;
899 tegra_uart_write(tup, ier, UART_IER);
900 break;
901 }
902 fallthrough;
903 case 2: /* Receive */
904 if (!tup->use_rx_pio) {
905 is_rx_start = tup->rx_in_progress;
906 tup->ier_shadow &= ~UART_IER_RDI;
907 tegra_uart_write(tup, tup->ier_shadow,
908 UART_IER);
909 } else {
910 do_handle_rx_pio(tup);
911 }
912 break;
913
914 case 3: /* Receive error */
915 tegra_uart_decode_rx_error(tup,
916 tegra_uart_read(tup, UART_LSR));
917 break;
918
919 case 5: /* break nothing to handle */
920 case 7: /* break nothing to handle */
921 break;
922 }
923 }
924}
925
926static void tegra_uart_stop_rx(struct uart_port *u)
927{
928 struct tegra_uart_port *tup = to_tegra_uport(u);
929 struct tty_port *port = &tup->uport.state->port;
930 unsigned long ier;
931
932 if (tup->rts_active)
933 set_rts(tup, false);
934
935 if (!tup->rx_in_progress)
936 return;
937
938 tegra_uart_wait_sym_time(tup, 1); /* wait one character interval */
939
940 ier = tup->ier_shadow;
941 ier &= ~(UART_IER_RDI | UART_IER_RLSI | UART_IER_RTOIE |
942 TEGRA_UART_IER_EORD);
943 tup->ier_shadow = ier;
944 tegra_uart_write(tup, ier, UART_IER);
945 tup->rx_in_progress = 0;
946
947 if (!tup->use_rx_pio)
948 tegra_uart_terminate_rx_dma(tup);
949 else
950 tegra_uart_handle_rx_pio(tup, port);
951}
952
953static void tegra_uart_hw_deinit(struct tegra_uart_port *tup)
954{
955 unsigned long flags;
956 unsigned long char_time = DIV_ROUND_UP(10000000, tup->current_baud);
957 unsigned long fifo_empty_time = tup->uport.fifosize * char_time;
958 unsigned long wait_time;
959 unsigned long lsr;
960 unsigned long msr;
961 unsigned long mcr;
962
963 /* Disable interrupts */
964 tegra_uart_write(tup, 0, UART_IER);
965
966 lsr = tegra_uart_read(tup, UART_LSR);
967 if ((lsr & UART_LSR_TEMT) != UART_LSR_TEMT) {
968 msr = tegra_uart_read(tup, UART_MSR);
969 mcr = tegra_uart_read(tup, UART_MCR);
970 if ((mcr & TEGRA_UART_MCR_CTS_EN) && (msr & UART_MSR_CTS))
971 dev_err(tup->uport.dev,
972 "Tx Fifo not empty, CTS disabled, waiting\n");
973
974 /* Wait for Tx fifo to be empty */
975 while ((lsr & UART_LSR_TEMT) != UART_LSR_TEMT) {
976 wait_time = min(fifo_empty_time, 100lu);
977 udelay(wait_time);
978 fifo_empty_time -= wait_time;
979 if (!fifo_empty_time) {
980 msr = tegra_uart_read(tup, UART_MSR);
981 mcr = tegra_uart_read(tup, UART_MCR);
982 if ((mcr & TEGRA_UART_MCR_CTS_EN) &&
983 (msr & UART_MSR_CTS))
984 dev_err(tup->uport.dev,
985 "Slave not ready\n");
986 break;
987 }
988 lsr = tegra_uart_read(tup, UART_LSR);
989 }
990 }
991
992 uart_port_lock_irqsave(&tup->uport, &flags);
993 /* Reset the Rx and Tx FIFOs */
994 tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR);
995 tup->current_baud = 0;
996 uart_port_unlock_irqrestore(&tup->uport, flags);
997
998 tup->rx_in_progress = 0;
999 tup->tx_in_progress = 0;
1000
1001 if (!tup->use_rx_pio)
1002 tegra_uart_dma_channel_free(tup, true);
1003 if (!tup->use_tx_pio)
1004 tegra_uart_dma_channel_free(tup, false);
1005
1006 clk_disable_unprepare(tup->uart_clk);
1007}
1008
1009static int tegra_uart_hw_init(struct tegra_uart_port *tup)
1010{
1011 int ret;
1012
1013 tup->fcr_shadow = 0;
1014 tup->mcr_shadow = 0;
1015 tup->lcr_shadow = 0;
1016 tup->ier_shadow = 0;
1017 tup->current_baud = 0;
1018
1019 ret = clk_prepare_enable(tup->uart_clk);
1020 if (ret) {
1021 dev_err(tup->uport.dev, "could not enable clk\n");
1022 return ret;
1023 }
1024
1025 /* Reset the UART controller to clear all previous status.*/
1026 reset_control_assert(tup->rst);
1027 udelay(10);
1028 reset_control_deassert(tup->rst);
1029
1030 tup->rx_in_progress = 0;
1031 tup->tx_in_progress = 0;
1032
1033 /*
1034 * Set the trigger level
1035 *
1036 * For PIO mode:
1037 *
1038 * For receive, this will interrupt the CPU after that many number of
1039 * bytes are received, for the remaining bytes the receive timeout
1040 * interrupt is received. Rx high watermark is set to 4.
1041 *
1042 * For transmit, if the trasnmit interrupt is enabled, this will
1043 * interrupt the CPU when the number of entries in the FIFO reaches the
1044 * low watermark. Tx low watermark is set to 16 bytes.
1045 *
1046 * For DMA mode:
1047 *
1048 * Set the Tx trigger to 16. This should match the DMA burst size that
1049 * programmed in the DMA registers.
1050 */
1051 tup->fcr_shadow = UART_FCR_ENABLE_FIFO;
1052
1053 if (tup->use_rx_pio) {
1054 tup->fcr_shadow |= UART_FCR_R_TRIG_11;
1055 } else {
1056 if (tup->cdata->max_dma_burst_bytes == 8)
1057 tup->fcr_shadow |= UART_FCR_R_TRIG_10;
1058 else
1059 tup->fcr_shadow |= UART_FCR_R_TRIG_01;
1060 }
1061
1062 tup->fcr_shadow |= TEGRA_UART_TX_TRIG_16B;
1063 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
1064
1065 /* Dummy read to ensure the write is posted */
1066 tegra_uart_read(tup, UART_SCR);
1067
1068 if (tup->cdata->fifo_mode_enable_status) {
1069 ret = tegra_uart_wait_fifo_mode_enabled(tup);
1070 if (ret < 0) {
1071 clk_disable_unprepare(tup->uart_clk);
1072 dev_err(tup->uport.dev,
1073 "Failed to enable FIFO mode: %d\n", ret);
1074 return ret;
1075 }
1076 } else {
1077 /*
1078 * For all tegra devices (up to t210), there is a hardware
1079 * issue that requires software to wait for 3 UART clock
1080 * periods after enabling the TX fifo, otherwise data could
1081 * be lost.
1082 */
1083 tegra_uart_wait_cycle_time(tup, 3);
1084 }
1085
1086 /*
1087 * Initialize the UART with default configuration
1088 * (115200, N, 8, 1) so that the receive DMA buffer may be
1089 * enqueued
1090 */
1091 ret = tegra_set_baudrate(tup, TEGRA_UART_DEFAULT_BAUD);
1092 if (ret < 0) {
1093 clk_disable_unprepare(tup->uart_clk);
1094 dev_err(tup->uport.dev, "Failed to set baud rate\n");
1095 return ret;
1096 }
1097 if (!tup->use_rx_pio) {
1098 tup->lcr_shadow = TEGRA_UART_DEFAULT_LSR;
1099 tup->fcr_shadow |= UART_FCR_DMA_SELECT;
1100 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
1101 } else {
1102 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
1103 }
1104 tup->rx_in_progress = 1;
1105
1106 /*
1107 * Enable IE_RXS for the receive status interrupts like line errors.
1108 * Enable IE_RX_TIMEOUT to get the bytes which cannot be DMA'd.
1109 *
1110 * EORD is different interrupt than RX_TIMEOUT - RX_TIMEOUT occurs when
1111 * the DATA is sitting in the FIFO and couldn't be transferred to the
1112 * DMA as the DMA size alignment (4 bytes) is not met. EORD will be
1113 * triggered when there is a pause of the incomming data stream for 4
1114 * characters long.
1115 *
1116 * For pauses in the data which is not aligned to 4 bytes, we get
1117 * both the EORD as well as RX_TIMEOUT - SW sees RX_TIMEOUT first
1118 * then the EORD.
1119 */
1120 tup->ier_shadow = UART_IER_RLSI | UART_IER_RTOIE | UART_IER_RDI;
1121
1122 /*
1123 * If using DMA mode, enable EORD interrupt to notify about RX
1124 * completion.
1125 */
1126 if (!tup->use_rx_pio)
1127 tup->ier_shadow |= TEGRA_UART_IER_EORD;
1128
1129 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
1130 return 0;
1131}
1132
1133static void tegra_uart_dma_channel_free(struct tegra_uart_port *tup,
1134 bool dma_to_memory)
1135{
1136 if (dma_to_memory) {
1137 dmaengine_terminate_all(tup->rx_dma_chan);
1138 dma_release_channel(tup->rx_dma_chan);
1139 dma_free_coherent(tup->uport.dev, TEGRA_UART_RX_DMA_BUFFER_SIZE,
1140 tup->rx_dma_buf_virt, tup->rx_dma_buf_phys);
1141 tup->rx_dma_chan = NULL;
1142 tup->rx_dma_buf_phys = 0;
1143 tup->rx_dma_buf_virt = NULL;
1144 } else {
1145 dmaengine_terminate_all(tup->tx_dma_chan);
1146 dma_release_channel(tup->tx_dma_chan);
1147 dma_unmap_single(tup->uport.dev, tup->tx_dma_buf_phys,
1148 UART_XMIT_SIZE, DMA_TO_DEVICE);
1149 tup->tx_dma_chan = NULL;
1150 tup->tx_dma_buf_phys = 0;
1151 tup->tx_dma_buf_virt = NULL;
1152 }
1153}
1154
1155static int tegra_uart_dma_channel_allocate(struct tegra_uart_port *tup,
1156 bool dma_to_memory)
1157{
1158 struct dma_chan *dma_chan;
1159 unsigned char *dma_buf;
1160 dma_addr_t dma_phys;
1161 int ret;
1162 struct dma_slave_config dma_sconfig;
1163
1164 dma_chan = dma_request_chan(tup->uport.dev, dma_to_memory ? "rx" : "tx");
1165 if (IS_ERR(dma_chan)) {
1166 ret = PTR_ERR(dma_chan);
1167 dev_err(tup->uport.dev,
1168 "DMA channel alloc failed: %d\n", ret);
1169 return ret;
1170 }
1171
1172 if (dma_to_memory) {
1173 dma_buf = dma_alloc_coherent(tup->uport.dev,
1174 TEGRA_UART_RX_DMA_BUFFER_SIZE,
1175 &dma_phys, GFP_KERNEL);
1176 if (!dma_buf) {
1177 dev_err(tup->uport.dev,
1178 "Not able to allocate the dma buffer\n");
1179 dma_release_channel(dma_chan);
1180 return -ENOMEM;
1181 }
1182 dma_sync_single_for_device(tup->uport.dev, dma_phys,
1183 TEGRA_UART_RX_DMA_BUFFER_SIZE,
1184 DMA_TO_DEVICE);
1185 dma_sconfig.src_addr = tup->uport.mapbase;
1186 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1187 dma_sconfig.src_maxburst = tup->cdata->max_dma_burst_bytes;
1188 tup->rx_dma_chan = dma_chan;
1189 tup->rx_dma_buf_virt = dma_buf;
1190 tup->rx_dma_buf_phys = dma_phys;
1191 } else {
1192 dma_buf = tup->uport.state->port.xmit_buf;
1193 dma_phys = dma_map_single(tup->uport.dev,
1194 dma_buf, UART_XMIT_SIZE, DMA_TO_DEVICE);
1195 if (dma_mapping_error(tup->uport.dev, dma_phys)) {
1196 dev_err(tup->uport.dev, "dma_map_single tx failed\n");
1197 dma_release_channel(dma_chan);
1198 return -ENOMEM;
1199 }
1200 dma_sconfig.dst_addr = tup->uport.mapbase;
1201 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1202 dma_sconfig.dst_maxburst = 16;
1203 tup->tx_dma_chan = dma_chan;
1204 tup->tx_dma_buf_virt = dma_buf;
1205 tup->tx_dma_buf_phys = dma_phys;
1206 }
1207
1208 ret = dmaengine_slave_config(dma_chan, &dma_sconfig);
1209 if (ret < 0) {
1210 dev_err(tup->uport.dev,
1211 "Dma slave config failed, err = %d\n", ret);
1212 tegra_uart_dma_channel_free(tup, dma_to_memory);
1213 return ret;
1214 }
1215
1216 return 0;
1217}
1218
1219static int tegra_uart_startup(struct uart_port *u)
1220{
1221 struct tegra_uart_port *tup = to_tegra_uport(u);
1222 int ret;
1223
1224 if (!tup->use_tx_pio) {
1225 ret = tegra_uart_dma_channel_allocate(tup, false);
1226 if (ret < 0) {
1227 dev_err(u->dev, "Tx Dma allocation failed, err = %d\n",
1228 ret);
1229 return ret;
1230 }
1231 }
1232
1233 if (!tup->use_rx_pio) {
1234 ret = tegra_uart_dma_channel_allocate(tup, true);
1235 if (ret < 0) {
1236 dev_err(u->dev, "Rx Dma allocation failed, err = %d\n",
1237 ret);
1238 goto fail_rx_dma;
1239 }
1240 }
1241
1242 ret = tegra_uart_hw_init(tup);
1243 if (ret < 0) {
1244 dev_err(u->dev, "Uart HW init failed, err = %d\n", ret);
1245 goto fail_hw_init;
1246 }
1247
1248 ret = request_irq(u->irq, tegra_uart_isr, 0,
1249 dev_name(u->dev), tup);
1250 if (ret < 0) {
1251 dev_err(u->dev, "Failed to register ISR for IRQ %d\n", u->irq);
1252 goto fail_request_irq;
1253 }
1254 return 0;
1255
1256fail_request_irq:
1257 /* tup->uart_clk is already enabled in tegra_uart_hw_init */
1258 clk_disable_unprepare(tup->uart_clk);
1259fail_hw_init:
1260 if (!tup->use_rx_pio)
1261 tegra_uart_dma_channel_free(tup, true);
1262fail_rx_dma:
1263 if (!tup->use_tx_pio)
1264 tegra_uart_dma_channel_free(tup, false);
1265 return ret;
1266}
1267
1268/*
1269 * Flush any TX data submitted for DMA and PIO. Called when the
1270 * TX circular buffer is reset.
1271 */
1272static void tegra_uart_flush_buffer(struct uart_port *u)
1273{
1274 struct tegra_uart_port *tup = to_tegra_uport(u);
1275
1276 tup->tx_bytes = 0;
1277 if (tup->tx_dma_chan)
1278 dmaengine_terminate_all(tup->tx_dma_chan);
1279}
1280
1281static void tegra_uart_shutdown(struct uart_port *u)
1282{
1283 struct tegra_uart_port *tup = to_tegra_uport(u);
1284
1285 tegra_uart_hw_deinit(tup);
1286 free_irq(u->irq, tup);
1287}
1288
1289static void tegra_uart_enable_ms(struct uart_port *u)
1290{
1291 struct tegra_uart_port *tup = to_tegra_uport(u);
1292
1293 if (tup->enable_modem_interrupt) {
1294 tup->ier_shadow |= UART_IER_MSI;
1295 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
1296 }
1297}
1298
1299static void tegra_uart_set_termios(struct uart_port *u,
1300 struct ktermios *termios,
1301 const struct ktermios *oldtermios)
1302{
1303 struct tegra_uart_port *tup = to_tegra_uport(u);
1304 unsigned int baud;
1305 unsigned long flags;
1306 unsigned int lcr;
1307 unsigned char char_bits;
1308 struct clk *parent_clk = clk_get_parent(tup->uart_clk);
1309 unsigned long parent_clk_rate = clk_get_rate(parent_clk);
1310 int max_divider = (tup->cdata->support_clk_src_div) ? 0x7FFF : 0xFFFF;
1311 int ret;
1312
1313 max_divider *= 16;
1314 uart_port_lock_irqsave(u, &flags);
1315
1316 /* Changing configuration, it is safe to stop any rx now */
1317 if (tup->rts_active)
1318 set_rts(tup, false);
1319
1320 /* Clear all interrupts as configuration is going to be changed */
1321 tegra_uart_write(tup, tup->ier_shadow | UART_IER_RDI, UART_IER);
1322 tegra_uart_read(tup, UART_IER);
1323 tegra_uart_write(tup, 0, UART_IER);
1324 tegra_uart_read(tup, UART_IER);
1325
1326 /* Parity */
1327 lcr = tup->lcr_shadow;
1328 lcr &= ~UART_LCR_PARITY;
1329
1330 /* CMSPAR isn't supported by this driver */
1331 termios->c_cflag &= ~CMSPAR;
1332
1333 if ((termios->c_cflag & PARENB) == PARENB) {
1334 if (termios->c_cflag & PARODD) {
1335 lcr |= UART_LCR_PARITY;
1336 lcr &= ~UART_LCR_EPAR;
1337 lcr &= ~UART_LCR_SPAR;
1338 } else {
1339 lcr |= UART_LCR_PARITY;
1340 lcr |= UART_LCR_EPAR;
1341 lcr &= ~UART_LCR_SPAR;
1342 }
1343 }
1344
1345 char_bits = tty_get_char_size(termios->c_cflag);
1346 lcr &= ~UART_LCR_WLEN8;
1347 lcr |= UART_LCR_WLEN(char_bits);
1348
1349 /* Stop bits */
1350 if (termios->c_cflag & CSTOPB)
1351 lcr |= UART_LCR_STOP;
1352 else
1353 lcr &= ~UART_LCR_STOP;
1354
1355 tegra_uart_write(tup, lcr, UART_LCR);
1356 tup->lcr_shadow = lcr;
1357 tup->symb_bit = tty_get_frame_size(termios->c_cflag);
1358
1359 /* Baud rate. */
1360 baud = uart_get_baud_rate(u, termios, oldtermios,
1361 parent_clk_rate/max_divider,
1362 parent_clk_rate/16);
1363 uart_port_unlock_irqrestore(u, flags);
1364 ret = tegra_set_baudrate(tup, baud);
1365 if (ret < 0) {
1366 dev_err(tup->uport.dev, "Failed to set baud rate\n");
1367 return;
1368 }
1369 if (tty_termios_baud_rate(termios))
1370 tty_termios_encode_baud_rate(termios, baud, baud);
1371 uart_port_lock_irqsave(u, &flags);
1372
1373 /* Flow control */
1374 if (termios->c_cflag & CRTSCTS) {
1375 tup->mcr_shadow |= TEGRA_UART_MCR_CTS_EN;
1376 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN;
1377 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR);
1378 /* if top layer has asked to set rts active then do so here */
1379 if (tup->rts_active)
1380 set_rts(tup, true);
1381 } else {
1382 tup->mcr_shadow &= ~TEGRA_UART_MCR_CTS_EN;
1383 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN;
1384 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR);
1385 }
1386
1387 /* update the port timeout based on new settings */
1388 uart_update_timeout(u, termios->c_cflag, baud);
1389
1390 /* Make sure all writes have completed */
1391 tegra_uart_read(tup, UART_IER);
1392
1393 /* Re-enable interrupt */
1394 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
1395 tegra_uart_read(tup, UART_IER);
1396
1397 tup->uport.ignore_status_mask = 0;
1398 /* Ignore all characters if CREAD is not set */
1399 if ((termios->c_cflag & CREAD) == 0)
1400 tup->uport.ignore_status_mask |= UART_LSR_DR;
1401 if (termios->c_iflag & IGNBRK)
1402 tup->uport.ignore_status_mask |= UART_LSR_BI;
1403
1404 uart_port_unlock_irqrestore(u, flags);
1405}
1406
1407static const char *tegra_uart_type(struct uart_port *u)
1408{
1409 return TEGRA_UART_TYPE;
1410}
1411
1412static const struct uart_ops tegra_uart_ops = {
1413 .tx_empty = tegra_uart_tx_empty,
1414 .set_mctrl = tegra_uart_set_mctrl,
1415 .get_mctrl = tegra_uart_get_mctrl,
1416 .stop_tx = tegra_uart_stop_tx,
1417 .start_tx = tegra_uart_start_tx,
1418 .stop_rx = tegra_uart_stop_rx,
1419 .flush_buffer = tegra_uart_flush_buffer,
1420 .enable_ms = tegra_uart_enable_ms,
1421 .break_ctl = tegra_uart_break_ctl,
1422 .startup = tegra_uart_startup,
1423 .shutdown = tegra_uart_shutdown,
1424 .set_termios = tegra_uart_set_termios,
1425 .type = tegra_uart_type,
1426 .request_port = tegra_uart_request_port,
1427 .release_port = tegra_uart_release_port,
1428};
1429
1430static struct uart_driver tegra_uart_driver = {
1431 .owner = THIS_MODULE,
1432 .driver_name = "tegra_hsuart",
1433 .dev_name = "ttyTHS",
1434 .cons = NULL,
1435 .nr = TEGRA_UART_MAXIMUM,
1436};
1437
1438static int tegra_uart_parse_dt(struct platform_device *pdev,
1439 struct tegra_uart_port *tup)
1440{
1441 struct device_node *np = pdev->dev.of_node;
1442 int port;
1443 int ret;
1444 int index;
1445 u32 pval;
1446 int count;
1447 int n_entries;
1448
1449 port = of_alias_get_id(np, "serial");
1450 if (port < 0) {
1451 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", port);
1452 return port;
1453 }
1454 tup->uport.line = port;
1455
1456 tup->enable_modem_interrupt = of_property_read_bool(np,
1457 "nvidia,enable-modem-interrupt");
1458
1459 index = of_property_match_string(np, "dma-names", "rx");
1460 if (index < 0) {
1461 tup->use_rx_pio = true;
1462 dev_info(&pdev->dev, "RX in PIO mode\n");
1463 }
1464 index = of_property_match_string(np, "dma-names", "tx");
1465 if (index < 0) {
1466 tup->use_tx_pio = true;
1467 dev_info(&pdev->dev, "TX in PIO mode\n");
1468 }
1469
1470 n_entries = of_property_count_u32_elems(np, "nvidia,adjust-baud-rates");
1471 if (n_entries > 0) {
1472 tup->n_adjustable_baud_rates = n_entries / 3;
1473 tup->baud_tolerance =
1474 devm_kzalloc(&pdev->dev, (tup->n_adjustable_baud_rates) *
1475 sizeof(*tup->baud_tolerance), GFP_KERNEL);
1476 if (!tup->baud_tolerance)
1477 return -ENOMEM;
1478 for (count = 0, index = 0; count < n_entries; count += 3,
1479 index++) {
1480 ret =
1481 of_property_read_u32_index(np,
1482 "nvidia,adjust-baud-rates",
1483 count, &pval);
1484 if (!ret)
1485 tup->baud_tolerance[index].lower_range_baud =
1486 pval;
1487 ret =
1488 of_property_read_u32_index(np,
1489 "nvidia,adjust-baud-rates",
1490 count + 1, &pval);
1491 if (!ret)
1492 tup->baud_tolerance[index].upper_range_baud =
1493 pval;
1494 ret =
1495 of_property_read_u32_index(np,
1496 "nvidia,adjust-baud-rates",
1497 count + 2, &pval);
1498 if (!ret)
1499 tup->baud_tolerance[index].tolerance =
1500 (s32)pval;
1501 }
1502 } else {
1503 tup->n_adjustable_baud_rates = 0;
1504 }
1505
1506 return 0;
1507}
1508
1509static struct tegra_uart_chip_data tegra20_uart_chip_data = {
1510 .tx_fifo_full_status = false,
1511 .allow_txfifo_reset_fifo_mode = true,
1512 .support_clk_src_div = false,
1513 .fifo_mode_enable_status = false,
1514 .uart_max_port = 5,
1515 .max_dma_burst_bytes = 4,
1516 .error_tolerance_low_range = -4,
1517 .error_tolerance_high_range = 4,
1518};
1519
1520static struct tegra_uart_chip_data tegra30_uart_chip_data = {
1521 .tx_fifo_full_status = true,
1522 .allow_txfifo_reset_fifo_mode = false,
1523 .support_clk_src_div = true,
1524 .fifo_mode_enable_status = false,
1525 .uart_max_port = 5,
1526 .max_dma_burst_bytes = 4,
1527 .error_tolerance_low_range = -4,
1528 .error_tolerance_high_range = 4,
1529};
1530
1531static struct tegra_uart_chip_data tegra186_uart_chip_data = {
1532 .tx_fifo_full_status = true,
1533 .allow_txfifo_reset_fifo_mode = false,
1534 .support_clk_src_div = true,
1535 .fifo_mode_enable_status = true,
1536 .uart_max_port = 8,
1537 .max_dma_burst_bytes = 8,
1538 .error_tolerance_low_range = 0,
1539 .error_tolerance_high_range = 4,
1540};
1541
1542static struct tegra_uart_chip_data tegra194_uart_chip_data = {
1543 .tx_fifo_full_status = true,
1544 .allow_txfifo_reset_fifo_mode = false,
1545 .support_clk_src_div = true,
1546 .fifo_mode_enable_status = true,
1547 .uart_max_port = 8,
1548 .max_dma_burst_bytes = 8,
1549 .error_tolerance_low_range = -2,
1550 .error_tolerance_high_range = 2,
1551};
1552
1553static const struct of_device_id tegra_uart_of_match[] = {
1554 {
1555 .compatible = "nvidia,tegra30-hsuart",
1556 .data = &tegra30_uart_chip_data,
1557 }, {
1558 .compatible = "nvidia,tegra20-hsuart",
1559 .data = &tegra20_uart_chip_data,
1560 }, {
1561 .compatible = "nvidia,tegra186-hsuart",
1562 .data = &tegra186_uart_chip_data,
1563 }, {
1564 .compatible = "nvidia,tegra194-hsuart",
1565 .data = &tegra194_uart_chip_data,
1566 }, {
1567 },
1568};
1569MODULE_DEVICE_TABLE(of, tegra_uart_of_match);
1570
1571static int tegra_uart_probe(struct platform_device *pdev)
1572{
1573 struct tegra_uart_port *tup;
1574 struct uart_port *u;
1575 struct resource *resource;
1576 int ret;
1577 const struct tegra_uart_chip_data *cdata;
1578
1579 cdata = of_device_get_match_data(&pdev->dev);
1580 if (!cdata) {
1581 dev_err(&pdev->dev, "Error: No device match found\n");
1582 return -ENODEV;
1583 }
1584
1585 tup = devm_kzalloc(&pdev->dev, sizeof(*tup), GFP_KERNEL);
1586 if (!tup) {
1587 dev_err(&pdev->dev, "Failed to allocate memory for tup\n");
1588 return -ENOMEM;
1589 }
1590
1591 ret = tegra_uart_parse_dt(pdev, tup);
1592 if (ret < 0)
1593 return ret;
1594
1595 u = &tup->uport;
1596 u->dev = &pdev->dev;
1597 u->ops = &tegra_uart_ops;
1598 u->type = PORT_TEGRA;
1599 u->fifosize = 32;
1600 tup->cdata = cdata;
1601
1602 platform_set_drvdata(pdev, tup);
1603
1604 u->membase = devm_platform_get_and_ioremap_resource(pdev, 0, &resource);
1605 if (IS_ERR(u->membase))
1606 return PTR_ERR(u->membase);
1607 u->mapbase = resource->start;
1608
1609 tup->uart_clk = devm_clk_get(&pdev->dev, NULL);
1610 if (IS_ERR(tup->uart_clk))
1611 return dev_err_probe(&pdev->dev, PTR_ERR(tup->uart_clk), "Couldn't get the clock");
1612
1613 tup->rst = devm_reset_control_get_exclusive(&pdev->dev, "serial");
1614 if (IS_ERR(tup->rst)) {
1615 dev_err(&pdev->dev, "Couldn't get the reset\n");
1616 return PTR_ERR(tup->rst);
1617 }
1618
1619 u->iotype = UPIO_MEM32;
1620 ret = platform_get_irq(pdev, 0);
1621 if (ret < 0)
1622 return ret;
1623 u->irq = ret;
1624 u->regshift = 2;
1625 ret = uart_add_one_port(&tegra_uart_driver, u);
1626 if (ret < 0) {
1627 dev_err(&pdev->dev, "Failed to add uart port, err %d\n", ret);
1628 return ret;
1629 }
1630 return ret;
1631}
1632
1633static void tegra_uart_remove(struct platform_device *pdev)
1634{
1635 struct tegra_uart_port *tup = platform_get_drvdata(pdev);
1636 struct uart_port *u = &tup->uport;
1637
1638 uart_remove_one_port(&tegra_uart_driver, u);
1639}
1640
1641#ifdef CONFIG_PM_SLEEP
1642static int tegra_uart_suspend(struct device *dev)
1643{
1644 struct tegra_uart_port *tup = dev_get_drvdata(dev);
1645 struct uart_port *u = &tup->uport;
1646
1647 return uart_suspend_port(&tegra_uart_driver, u);
1648}
1649
1650static int tegra_uart_resume(struct device *dev)
1651{
1652 struct tegra_uart_port *tup = dev_get_drvdata(dev);
1653 struct uart_port *u = &tup->uport;
1654
1655 return uart_resume_port(&tegra_uart_driver, u);
1656}
1657#endif
1658
1659static const struct dev_pm_ops tegra_uart_pm_ops = {
1660 SET_SYSTEM_SLEEP_PM_OPS(tegra_uart_suspend, tegra_uart_resume)
1661};
1662
1663static struct platform_driver tegra_uart_platform_driver = {
1664 .probe = tegra_uart_probe,
1665 .remove = tegra_uart_remove,
1666 .driver = {
1667 .name = "serial-tegra",
1668 .of_match_table = tegra_uart_of_match,
1669 .pm = &tegra_uart_pm_ops,
1670 },
1671};
1672
1673static int __init tegra_uart_init(void)
1674{
1675 int ret;
1676 struct device_node *node;
1677 const struct of_device_id *match = NULL;
1678 const struct tegra_uart_chip_data *cdata = NULL;
1679
1680 node = of_find_matching_node(NULL, tegra_uart_of_match);
1681 if (node)
1682 match = of_match_node(tegra_uart_of_match, node);
1683 of_node_put(node);
1684 if (match)
1685 cdata = match->data;
1686 if (cdata)
1687 tegra_uart_driver.nr = cdata->uart_max_port;
1688
1689 ret = uart_register_driver(&tegra_uart_driver);
1690 if (ret < 0) {
1691 pr_err("Could not register %s driver\n",
1692 tegra_uart_driver.driver_name);
1693 return ret;
1694 }
1695
1696 ret = platform_driver_register(&tegra_uart_platform_driver);
1697 if (ret < 0) {
1698 pr_err("Uart platform driver register failed, e = %d\n", ret);
1699 uart_unregister_driver(&tegra_uart_driver);
1700 return ret;
1701 }
1702 return 0;
1703}
1704
1705static void __exit tegra_uart_exit(void)
1706{
1707 pr_info("Unloading tegra uart driver\n");
1708 platform_driver_unregister(&tegra_uart_platform_driver);
1709 uart_unregister_driver(&tegra_uart_driver);
1710}
1711
1712module_init(tegra_uart_init);
1713module_exit(tegra_uart_exit);
1714
1715MODULE_ALIAS("platform:serial-tegra");
1716MODULE_DESCRIPTION("High speed UART driver for tegra chipset");
1717MODULE_AUTHOR("Laxman Dewangan <[email protected]>");
1718MODULE_LICENSE("GPL v2");