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4134 lines · 105.6 KiB

1// SPDX-License-Identifier: GPL-2.0
2/*
3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
4 *
5 * Copyright (C) 2002 - 2011 Paul Mundt
6 * Copyright (C) 2015 Glider bvba
7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
8 *
9 * based off of the old drivers/char/sh-sci.c by:
10 *
11 * Copyright (C) 1999, 2000 Niibe Yutaka
12 * Copyright (C) 2000 Sugioka Toshinobu
13 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
14 * Modified to support SecureEdge. David McCullough (2002)
15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
16 * Removed SH7300 support (Jul 2007).
17 */
18#undef DEBUG
19
20#include <linux/bitops.h>
21#include <linux/clk.h>
22#include <linux/console.h>
23#include <linux/cpufreq.h>
24#include <linux/ctype.h>
25#include <linux/delay.h>
26#include <linux/dma-mapping.h>
27#include <linux/dmaengine.h>
28#include <linux/err.h>
29#include <linux/errno.h>
30#include <linux/init.h>
31#include <linux/interrupt.h>
32#include <linux/io.h>
33#include <linux/ioport.h>
34#include <linux/ktime.h>
35#include <linux/major.h>
36#include <linux/minmax.h>
37#include <linux/mm.h>
38#include <linux/module.h>
39#include <linux/of.h>
40#include <linux/platform_device.h>
41#include <linux/pm_runtime.h>
42#include <linux/reset.h>
43#include <linux/scatterlist.h>
44#include <linux/serial.h>
45#include <linux/serial_core.h>
46#include <linux/serial_sci.h>
47#include <linux/sh_dma.h>
48#include <linux/slab.h>
49#include <linux/string.h>
50#include <linux/sysrq.h>
51#include <linux/timer.h>
52#include <linux/tty.h>
53#include <linux/tty_flip.h>
54
55#ifdef CONFIG_SUPERH
56#include <asm/platform_early.h>
57#include <asm/sh_bios.h>
58#endif
59
60#include "rsci.h"
61#include "serial_mctrl_gpio.h"
62#include "sh-sci-common.h"
63
64#define SCI_MAJOR 204
65#define SCI_MINOR_START 8
66
67/*
68 * SCI register subset common for all port types.
69 * Not all registers will exist on all parts.
70 */
71enum {
72 SCSMR, /* Serial Mode Register */
73 SCBRR, /* Bit Rate Register */
74 SCSCR, /* Serial Control Register */
75 SCxSR, /* Serial Status Register */
76 SCFCR, /* FIFO Control Register */
77 SCFDR, /* FIFO Data Count Register */
78 SCxTDR, /* Transmit (FIFO) Data Register */
79 SCxRDR, /* Receive (FIFO) Data Register */
80 SCLSR, /* Line Status Register */
81 SCTFDR, /* Transmit FIFO Data Count Register */
82 SCRFDR, /* Receive FIFO Data Count Register */
83 SCSPTR, /* Serial Port Register */
84 HSSRR, /* Sampling Rate Register */
85 SCPCR, /* Serial Port Control Register */
86 SCPDR, /* Serial Port Data Register */
87 SCDL, /* BRG Frequency Division Register */
88 SCCKS, /* BRG Clock Select Register */
89 HSRTRGR, /* Rx FIFO Data Count Trigger Register */
90 HSTTRGR, /* Tx FIFO Data Count Trigger Register */
91 SEMR, /* Serial extended mode register */
92};
93
94/* SCSMR (Serial Mode Register) */
95#define SCSMR_C_A BIT(7) /* Communication Mode */
96#define SCSMR_CSYNC BIT(7) /* - Clocked synchronous mode */
97#define SCSMR_ASYNC 0 /* - Asynchronous mode */
98#define SCSMR_CHR BIT(6) /* 7-bit Character Length */
99#define SCSMR_PE BIT(5) /* Parity Enable */
100#define SCSMR_ODD BIT(4) /* Odd Parity */
101#define SCSMR_STOP BIT(3) /* Stop Bit Length */
102#define SCSMR_CKS 0x0003 /* Clock Select */
103
104/* Serial Mode Register, SCIFA/SCIFB only bits */
105#define SCSMR_CKEDG BIT(12) /* Transmit/Receive Clock Edge Select */
106#define SCSMR_SRC_MASK 0x0700 /* Sampling Control */
107#define SCSMR_SRC_16 0x0000 /* Sampling rate 1/16 */
108#define SCSMR_SRC_5 0x0100 /* Sampling rate 1/5 */
109#define SCSMR_SRC_7 0x0200 /* Sampling rate 1/7 */
110#define SCSMR_SRC_11 0x0300 /* Sampling rate 1/11 */
111#define SCSMR_SRC_13 0x0400 /* Sampling rate 1/13 */
112#define SCSMR_SRC_17 0x0500 /* Sampling rate 1/17 */
113#define SCSMR_SRC_19 0x0600 /* Sampling rate 1/19 */
114#define SCSMR_SRC_27 0x0700 /* Sampling rate 1/27 */
115
116/* Serial Control Register, SCI only bits */
117#define SCSCR_TEIE BIT(2) /* Transmit End Interrupt Enable */
118
119/* Serial Control Register, SCIFA/SCIFB only bits */
120#define SCSCR_TDRQE BIT(15) /* Tx Data Transfer Request Enable */
121#define SCSCR_RDRQE BIT(14) /* Rx Data Transfer Request Enable */
122
123/* Serial Control Register, HSCIF-only bits */
124#define HSSCR_TOT_SHIFT 14
125
126/* SCxSR (Serial Status Register) on SCI */
127#define SCI_TDRE BIT(7) /* Transmit Data Register Empty */
128#define SCI_RDRF BIT(6) /* Receive Data Register Full */
129#define SCI_ORER BIT(5) /* Overrun Error */
130#define SCI_FER BIT(4) /* Framing Error */
131#define SCI_PER BIT(3) /* Parity Error */
132#define SCI_TEND BIT(2) /* Transmit End */
133#define SCI_RESERVED 0x03 /* All reserved bits */
134
135#define SCI_DEFAULT_ERROR_MASK (SCI_PER | SCI_FER)
136
137#define SCI_RDxF_CLEAR (u32)(~(SCI_RESERVED | SCI_RDRF))
138#define SCI_ERROR_CLEAR (u32)(~(SCI_RESERVED | SCI_PER | SCI_FER | SCI_ORER))
139#define SCI_TDxE_CLEAR (u32)(~(SCI_RESERVED | SCI_TEND | SCI_TDRE))
140#define SCI_BREAK_CLEAR (u32)(~(SCI_RESERVED | SCI_PER | SCI_FER | SCI_ORER))
141
142/* SCxSR (Serial Status Register) on SCIF, SCIFA, SCIFB, HSCIF */
143#define SCIF_ER BIT(7) /* Receive Error */
144#define SCIF_TEND BIT(6) /* Transmission End */
145#define SCIF_TDFE BIT(5) /* Transmit FIFO Data Empty */
146#define SCIF_BRK BIT(4) /* Break Detect */
147#define SCIF_FER BIT(3) /* Framing Error */
148#define SCIF_PER BIT(2) /* Parity Error */
149#define SCIF_RDF BIT(1) /* Receive FIFO Data Full */
150#define SCIF_DR BIT(0) /* Receive Data Ready */
151/* SCIF only (optional) */
152#define SCIF_PERC 0xf000 /* Number of Parity Errors */
153#define SCIF_FERC 0x0f00 /* Number of Framing Errors */
154/*SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 only */
155#define SCIFA_ORER BIT(9) /* Overrun Error */
156
157#define SCIF_DEFAULT_ERROR_MASK (SCIF_PER | SCIF_FER | SCIF_BRK | SCIF_ER)
158
159#define SCIF_RDxF_CLEAR (u32)(~(SCIF_DR | SCIF_RDF))
160#define SCIF_ERROR_CLEAR (u32)(~(SCIF_PER | SCIF_FER | SCIF_ER))
161#define SCIF_TDxE_CLEAR (u32)(~(SCIF_TDFE))
162#define SCIF_BREAK_CLEAR (u32)(~(SCIF_PER | SCIF_FER | SCIF_BRK))
163
164/* SCFCR (FIFO Control Register) */
165#define SCFCR_RTRG1 BIT(7) /* Receive FIFO Data Count Trigger */
166#define SCFCR_RTRG0 BIT(6)
167#define SCFCR_TTRG1 BIT(5) /* Transmit FIFO Data Count Trigger */
168#define SCFCR_TTRG0 BIT(4)
169#define SCFCR_MCE BIT(3) /* Modem Control Enable */
170#define SCFCR_TFRST BIT(2) /* Transmit FIFO Data Register Reset */
171#define SCFCR_RFRST BIT(1) /* Receive FIFO Data Register Reset */
172#define SCFCR_LOOP BIT(0) /* Loopback Test */
173
174/* SCLSR (Line Status Register) on (H)SCIF */
175#define SCLSR_TO BIT(2) /* Timeout */
176#define SCLSR_ORER BIT(0) /* Overrun Error */
177
178/* SCSPTR (Serial Port Register), optional */
179#define SCSPTR_RTSIO BIT(7) /* Serial Port RTS# Pin Input/Output */
180#define SCSPTR_RTSDT BIT(6) /* Serial Port RTS# Pin Data */
181#define SCSPTR_CTSIO BIT(5) /* Serial Port CTS# Pin Input/Output */
182#define SCSPTR_CTSDT BIT(4) /* Serial Port CTS# Pin Data */
183#define SCSPTR_SCKIO BIT(3) /* Serial Port Clock Pin Input/Output */
184#define SCSPTR_SCKDT BIT(2) /* Serial Port Clock Pin Data */
185#define SCSPTR_SPB2IO BIT(1) /* Serial Port Break Input/Output */
186#define SCSPTR_SPB2DT BIT(0) /* Serial Port Break Data */
187
188/* HSSRR HSCIF */
189#define HSCIF_SRE BIT(15) /* Sampling Rate Register Enable */
190#define HSCIF_SRDE BIT(14) /* Sampling Point Register Enable */
191
192#define HSCIF_SRHP_SHIFT 8
193#define HSCIF_SRHP_MASK 0x0f00
194
195/* SCPCR (Serial Port Control Register), SCIFA/SCIFB only */
196#define SCPCR_RTSC BIT(4) /* Serial Port RTS# Pin / Output Pin */
197#define SCPCR_CTSC BIT(3) /* Serial Port CTS# Pin / Input Pin */
198#define SCPCR_SCKC BIT(2) /* Serial Port SCK Pin / Output Pin */
199#define SCPCR_RXDC BIT(1) /* Serial Port RXD Pin / Input Pin */
200#define SCPCR_TXDC BIT(0) /* Serial Port TXD Pin / Output Pin */
201
202/* SCPDR (Serial Port Data Register), SCIFA/SCIFB only */
203#define SCPDR_RTSD BIT(4) /* Serial Port RTS# Output Pin Data */
204#define SCPDR_CTSD BIT(3) /* Serial Port CTS# Input Pin Data */
205#define SCPDR_SCKD BIT(2) /* Serial Port SCK Output Pin Data */
206#define SCPDR_RXDD BIT(1) /* Serial Port RXD Input Pin Data */
207#define SCPDR_TXDD BIT(0) /* Serial Port TXD Output Pin Data */
208
209/*
210 * BRG Clock Select Register (Some SCIF and HSCIF)
211 * The Baud Rate Generator for external clock can provide a clock source for
212 * the sampling clock. It outputs either its frequency divided clock, or the
213 * (undivided) (H)SCK external clock.
214 */
215#define SCCKS_CKS BIT(15) /* Select (H)SCK (1) or divided SC_CLK (0) */
216#define SCCKS_XIN BIT(14) /* SC_CLK uses bus clock (1) or SCIF_CLK (0) */
217
218#define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
219#define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_DR | SCIF_RDF)
220#define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
221#define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
222#define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
223#define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
224
225#define SCxSR_ERRORS(port) (to_sci_port(port)->params->error_mask)
226
227#define SCxSR_RDxF_CLEAR(port) \
228 (((port)->type == PORT_SCI) ? SCI_RDxF_CLEAR : SCIF_RDxF_CLEAR)
229#define SCxSR_ERROR_CLEAR(port) \
230 (to_sci_port(port)->params->error_clear)
231#define SCxSR_TDxE_CLEAR(port) \
232 (((port)->type == PORT_SCI) ? SCI_TDxE_CLEAR : SCIF_TDxE_CLEAR)
233#define SCxSR_BREAK_CLEAR(port) \
234 (((port)->type == PORT_SCI) ? SCI_BREAK_CLEAR : SCIF_BREAK_CLEAR)
235
236#define SCIx_IRQ_IS_MUXED(port) \
237 ((port)->irqs[SCIx_ERI_IRQ] == \
238 (port)->irqs[SCIx_RXI_IRQ]) || \
239 ((port)->irqs[SCIx_ERI_IRQ] && \
240 ((port)->irqs[SCIx_RXI_IRQ] < 0))
241
242#define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \
243 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \
244 SCI_SR(19) | SCI_SR(27)
245
246/* Iterate over all supported sampling rates, from high to low */
247#define for_each_sr(_sr, _port) \
248 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \
249 if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
250
251#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
252
253#define SCI_PUBLIC_PORT_ID(port) (((port) & BIT(7)) ? PORT_GENERIC : (port))
254
255static struct sci_port sci_ports[SCI_NPORTS];
256static unsigned long sci_ports_in_use;
257static struct uart_driver sci_uart_driver;
258static bool sci_uart_earlycon;
259static bool sci_uart_earlycon_dev_probing;
260
261static const struct sci_port_params_bits sci_sci_port_params_bits = {
262 .rxtx_enable = SCSCR_RE | SCSCR_TE,
263 .te_clear = SCSCR_TE | SCSCR_TEIE,
264 .poll_sent_bits = SCI_TDRE | SCI_TEND
265};
266
267static const struct sci_port_params_bits sci_scif_port_params_bits = {
268 .rxtx_enable = SCSCR_RE | SCSCR_TE,
269 .te_clear = SCSCR_TE | SCSCR_TEIE,
270 .poll_sent_bits = SCIF_TDFE | SCIF_TEND
271};
272
273static const struct sci_common_regs sci_common_regs = {
274 .status = SCxSR,
275 .control = SCSCR,
276};
277
278struct sci_suspend_regs {
279 u16 scdl;
280 u16 sccks;
281 u16 scsmr;
282 u16 scscr;
283 u16 scfcr;
284 u16 scsptr;
285 u16 hssrr;
286 u16 scpcr;
287 u16 scpdr;
288 u8 scbrr;
289 u8 semr;
290};
291
292static size_t sci_suspend_regs_size(void)
293{
294 return sizeof(struct sci_suspend_regs);
295}
296
297static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
298 /*
299 * Common SCI definitions, dependent on the port's regshift
300 * value.
301 */
302 [SCIx_SCI_REGTYPE] = {
303 .regs = {
304 [SCSMR] = { 0x00, 8 },
305 [SCBRR] = { 0x01, 8 },
306 [SCSCR] = { 0x02, 8 },
307 [SCxTDR] = { 0x03, 8 },
308 [SCxSR] = { 0x04, 8 },
309 [SCxRDR] = { 0x05, 8 },
310 },
311 .fifosize = 1,
312 .overrun_reg = SCxSR,
313 .overrun_mask = SCI_ORER,
314 .sampling_rate_mask = SCI_SR(32),
315 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
316 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
317 .param_bits = &sci_sci_port_params_bits,
318 .common_regs = &sci_common_regs,
319 },
320
321 /*
322 * Common definitions for legacy IrDA ports.
323 */
324 [SCIx_IRDA_REGTYPE] = {
325 .regs = {
326 [SCSMR] = { 0x00, 8 },
327 [SCBRR] = { 0x02, 8 },
328 [SCSCR] = { 0x04, 8 },
329 [SCxTDR] = { 0x06, 8 },
330 [SCxSR] = { 0x08, 16 },
331 [SCxRDR] = { 0x0a, 8 },
332 [SCFCR] = { 0x0c, 8 },
333 [SCFDR] = { 0x0e, 16 },
334 },
335 .fifosize = 1,
336 .overrun_reg = SCxSR,
337 .overrun_mask = SCI_ORER,
338 .sampling_rate_mask = SCI_SR(32),
339 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
340 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
341 .param_bits = &sci_scif_port_params_bits,
342 .common_regs = &sci_common_regs,
343 },
344
345 /*
346 * Common SCIFA definitions.
347 */
348 [SCIx_SCIFA_REGTYPE] = {
349 .regs = {
350 [SCSMR] = { 0x00, 16 },
351 [SCBRR] = { 0x04, 8 },
352 [SCSCR] = { 0x08, 16 },
353 [SCxTDR] = { 0x20, 8 },
354 [SCxSR] = { 0x14, 16 },
355 [SCxRDR] = { 0x24, 8 },
356 [SCFCR] = { 0x18, 16 },
357 [SCFDR] = { 0x1c, 16 },
358 [SCPCR] = { 0x30, 16 },
359 [SCPDR] = { 0x34, 16 },
360 },
361 .fifosize = 64,
362 .overrun_reg = SCxSR,
363 .overrun_mask = SCIFA_ORER,
364 .sampling_rate_mask = SCI_SR_SCIFAB,
365 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
366 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
367 .param_bits = &sci_scif_port_params_bits,
368 .common_regs = &sci_common_regs,
369 },
370
371 /*
372 * Common SCIFB definitions.
373 */
374 [SCIx_SCIFB_REGTYPE] = {
375 .regs = {
376 [SCSMR] = { 0x00, 16 },
377 [SCBRR] = { 0x04, 8 },
378 [SCSCR] = { 0x08, 16 },
379 [SCxTDR] = { 0x40, 8 },
380 [SCxSR] = { 0x14, 16 },
381 [SCxRDR] = { 0x60, 8 },
382 [SCFCR] = { 0x18, 16 },
383 [SCTFDR] = { 0x38, 16 },
384 [SCRFDR] = { 0x3c, 16 },
385 [SCPCR] = { 0x30, 16 },
386 [SCPDR] = { 0x34, 16 },
387 },
388 .fifosize = 256,
389 .overrun_reg = SCxSR,
390 .overrun_mask = SCIFA_ORER,
391 .sampling_rate_mask = SCI_SR_SCIFAB,
392 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
393 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
394 .param_bits = &sci_scif_port_params_bits,
395 .common_regs = &sci_common_regs,
396 },
397
398 /*
399 * Common SH-2(A) SCIF definitions for ports with FIFO data
400 * count registers.
401 */
402 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
403 .regs = {
404 [SCSMR] = { 0x00, 16 },
405 [SCBRR] = { 0x04, 8 },
406 [SCSCR] = { 0x08, 16 },
407 [SCxTDR] = { 0x0c, 8 },
408 [SCxSR] = { 0x10, 16 },
409 [SCxRDR] = { 0x14, 8 },
410 [SCFCR] = { 0x18, 16 },
411 [SCFDR] = { 0x1c, 16 },
412 [SCSPTR] = { 0x20, 16 },
413 [SCLSR] = { 0x24, 16 },
414 },
415 .fifosize = 16,
416 .overrun_reg = SCLSR,
417 .overrun_mask = SCLSR_ORER,
418 .sampling_rate_mask = SCI_SR(32),
419 .error_mask = SCIF_DEFAULT_ERROR_MASK,
420 .error_clear = SCIF_ERROR_CLEAR,
421 .param_bits = &sci_scif_port_params_bits,
422 .common_regs = &sci_common_regs,
423 },
424
425 /*
426 * The "SCIFA" that is in RZ/A2, RZ/G2L and RZ/T1.
427 * It looks like a normal SCIF with FIFO data, but with a
428 * compressed address space. Also, the break out of interrupts
429 * are different: ERI/BRI, RXI, TXI, TEI, DRI.
430 */
431 [SCIx_RZ_SCIFA_REGTYPE] = {
432 .regs = {
433 [SCSMR] = { 0x00, 16 },
434 [SCBRR] = { 0x02, 8 },
435 [SCSCR] = { 0x04, 16 },
436 [SCxTDR] = { 0x06, 8 },
437 [SCxSR] = { 0x08, 16 },
438 [SCxRDR] = { 0x0A, 8 },
439 [SCFCR] = { 0x0C, 16 },
440 [SCFDR] = { 0x0E, 16 },
441 [SCSPTR] = { 0x10, 16 },
442 [SCLSR] = { 0x12, 16 },
443 [SEMR] = { 0x14, 8 },
444 },
445 .fifosize = 16,
446 .overrun_reg = SCLSR,
447 .overrun_mask = SCLSR_ORER,
448 .sampling_rate_mask = SCI_SR(32),
449 .error_mask = SCIF_DEFAULT_ERROR_MASK,
450 .error_clear = SCIF_ERROR_CLEAR,
451 .param_bits = &sci_scif_port_params_bits,
452 .common_regs = &sci_common_regs,
453 },
454
455 /*
456 * The "SCIF" that is in RZ/V2H(P) SoC is similar to one found on RZ/G2L SoC
457 * with below differences,
458 * - Break out of interrupts are different: ERI, BRI, RXI, TXI, TEI, DRI,
459 * TEI-DRI, RXI-EDGE and TXI-EDGE.
460 * - SCSMR register does not have CM bit (BIT(7)) ie it does not support synchronous mode.
461 * - SCFCR register does not have SCFCR_MCE bit.
462 * - SCSPTR register has only bits SCSPTR_SPB2DT and SCSPTR_SPB2IO.
463 */
464 [SCIx_RZV2H_SCIF_REGTYPE] = {
465 .regs = {
466 [SCSMR] = { 0x00, 16 },
467 [SCBRR] = { 0x02, 8 },
468 [SCSCR] = { 0x04, 16 },
469 [SCxTDR] = { 0x06, 8 },
470 [SCxSR] = { 0x08, 16 },
471 [SCxRDR] = { 0x0a, 8 },
472 [SCFCR] = { 0x0c, 16 },
473 [SCFDR] = { 0x0e, 16 },
474 [SCSPTR] = { 0x10, 16 },
475 [SCLSR] = { 0x12, 16 },
476 [SEMR] = { 0x14, 8 },
477 },
478 .fifosize = 16,
479 .overrun_reg = SCLSR,
480 .overrun_mask = SCLSR_ORER,
481 .sampling_rate_mask = SCI_SR(32),
482 .error_mask = SCIF_DEFAULT_ERROR_MASK,
483 .error_clear = SCIF_ERROR_CLEAR,
484 .param_bits = &sci_scif_port_params_bits,
485 .common_regs = &sci_common_regs,
486 },
487
488 /*
489 * Common SH-3 SCIF definitions.
490 */
491 [SCIx_SH3_SCIF_REGTYPE] = {
492 .regs = {
493 [SCSMR] = { 0x00, 8 },
494 [SCBRR] = { 0x02, 8 },
495 [SCSCR] = { 0x04, 8 },
496 [SCxTDR] = { 0x06, 8 },
497 [SCxSR] = { 0x08, 16 },
498 [SCxRDR] = { 0x0a, 8 },
499 [SCFCR] = { 0x0c, 8 },
500 [SCFDR] = { 0x0e, 16 },
501 },
502 .fifosize = 16,
503 .overrun_reg = SCLSR,
504 .overrun_mask = SCLSR_ORER,
505 .sampling_rate_mask = SCI_SR(32),
506 .error_mask = SCIF_DEFAULT_ERROR_MASK,
507 .error_clear = SCIF_ERROR_CLEAR,
508 .param_bits = &sci_scif_port_params_bits,
509 .common_regs = &sci_common_regs,
510 },
511
512 /*
513 * Common SH-4(A) SCIF(B) definitions.
514 */
515 [SCIx_SH4_SCIF_REGTYPE] = {
516 .regs = {
517 [SCSMR] = { 0x00, 16 },
518 [SCBRR] = { 0x04, 8 },
519 [SCSCR] = { 0x08, 16 },
520 [SCxTDR] = { 0x0c, 8 },
521 [SCxSR] = { 0x10, 16 },
522 [SCxRDR] = { 0x14, 8 },
523 [SCFCR] = { 0x18, 16 },
524 [SCFDR] = { 0x1c, 16 },
525 [SCSPTR] = { 0x20, 16 },
526 [SCLSR] = { 0x24, 16 },
527 },
528 .fifosize = 16,
529 .overrun_reg = SCLSR,
530 .overrun_mask = SCLSR_ORER,
531 .sampling_rate_mask = SCI_SR(32),
532 .error_mask = SCIF_DEFAULT_ERROR_MASK,
533 .error_clear = SCIF_ERROR_CLEAR,
534 .param_bits = &sci_scif_port_params_bits,
535 .common_regs = &sci_common_regs,
536 },
537
538 /*
539 * Common SCIF definitions for ports with a Baud Rate Generator for
540 * External Clock (BRG).
541 */
542 [SCIx_SH4_SCIF_BRG_REGTYPE] = {
543 .regs = {
544 [SCSMR] = { 0x00, 16 },
545 [SCBRR] = { 0x04, 8 },
546 [SCSCR] = { 0x08, 16 },
547 [SCxTDR] = { 0x0c, 8 },
548 [SCxSR] = { 0x10, 16 },
549 [SCxRDR] = { 0x14, 8 },
550 [SCFCR] = { 0x18, 16 },
551 [SCFDR] = { 0x1c, 16 },
552 [SCSPTR] = { 0x20, 16 },
553 [SCLSR] = { 0x24, 16 },
554 [SCDL] = { 0x30, 16 },
555 [SCCKS] = { 0x34, 16 },
556 },
557 .fifosize = 16,
558 .overrun_reg = SCLSR,
559 .overrun_mask = SCLSR_ORER,
560 .sampling_rate_mask = SCI_SR(32),
561 .error_mask = SCIF_DEFAULT_ERROR_MASK,
562 .error_clear = SCIF_ERROR_CLEAR,
563 .param_bits = &sci_scif_port_params_bits,
564 .common_regs = &sci_common_regs,
565 },
566
567 /*
568 * Common HSCIF definitions.
569 */
570 [SCIx_HSCIF_REGTYPE] = {
571 .regs = {
572 [SCSMR] = { 0x00, 16 },
573 [SCBRR] = { 0x04, 8 },
574 [SCSCR] = { 0x08, 16 },
575 [SCxTDR] = { 0x0c, 8 },
576 [SCxSR] = { 0x10, 16 },
577 [SCxRDR] = { 0x14, 8 },
578 [SCFCR] = { 0x18, 16 },
579 [SCFDR] = { 0x1c, 16 },
580 [SCSPTR] = { 0x20, 16 },
581 [SCLSR] = { 0x24, 16 },
582 [HSSRR] = { 0x40, 16 },
583 [SCDL] = { 0x30, 16 },
584 [SCCKS] = { 0x34, 16 },
585 [HSRTRGR] = { 0x54, 16 },
586 [HSTTRGR] = { 0x58, 16 },
587 },
588 .fifosize = 128,
589 .overrun_reg = SCLSR,
590 .overrun_mask = SCLSR_ORER,
591 .sampling_rate_mask = SCI_SR_RANGE(8, 32),
592 .error_mask = SCIF_DEFAULT_ERROR_MASK,
593 .error_clear = SCIF_ERROR_CLEAR,
594 .param_bits = &sci_scif_port_params_bits,
595 .common_regs = &sci_common_regs,
596 },
597
598 /*
599 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
600 * register.
601 */
602 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
603 .regs = {
604 [SCSMR] = { 0x00, 16 },
605 [SCBRR] = { 0x04, 8 },
606 [SCSCR] = { 0x08, 16 },
607 [SCxTDR] = { 0x0c, 8 },
608 [SCxSR] = { 0x10, 16 },
609 [SCxRDR] = { 0x14, 8 },
610 [SCFCR] = { 0x18, 16 },
611 [SCFDR] = { 0x1c, 16 },
612 [SCLSR] = { 0x24, 16 },
613 },
614 .fifosize = 16,
615 .overrun_reg = SCLSR,
616 .overrun_mask = SCLSR_ORER,
617 .sampling_rate_mask = SCI_SR(32),
618 .error_mask = SCIF_DEFAULT_ERROR_MASK,
619 .error_clear = SCIF_ERROR_CLEAR,
620 .param_bits = &sci_scif_port_params_bits,
621 .common_regs = &sci_common_regs,
622 },
623
624 /*
625 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
626 * count registers.
627 */
628 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
629 .regs = {
630 [SCSMR] = { 0x00, 16 },
631 [SCBRR] = { 0x04, 8 },
632 [SCSCR] = { 0x08, 16 },
633 [SCxTDR] = { 0x0c, 8 },
634 [SCxSR] = { 0x10, 16 },
635 [SCxRDR] = { 0x14, 8 },
636 [SCFCR] = { 0x18, 16 },
637 [SCFDR] = { 0x1c, 16 },
638 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
639 [SCRFDR] = { 0x20, 16 },
640 [SCSPTR] = { 0x24, 16 },
641 [SCLSR] = { 0x28, 16 },
642 },
643 .fifosize = 16,
644 .overrun_reg = SCLSR,
645 .overrun_mask = SCLSR_ORER,
646 .sampling_rate_mask = SCI_SR(32),
647 .error_mask = SCIF_DEFAULT_ERROR_MASK,
648 .error_clear = SCIF_ERROR_CLEAR,
649 .param_bits = &sci_scif_port_params_bits,
650 .common_regs = &sci_common_regs,
651 },
652
653 /*
654 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
655 * registers.
656 */
657 [SCIx_SH7705_SCIF_REGTYPE] = {
658 .regs = {
659 [SCSMR] = { 0x00, 16 },
660 [SCBRR] = { 0x04, 8 },
661 [SCSCR] = { 0x08, 16 },
662 [SCxTDR] = { 0x20, 8 },
663 [SCxSR] = { 0x14, 16 },
664 [SCxRDR] = { 0x24, 8 },
665 [SCFCR] = { 0x18, 16 },
666 [SCFDR] = { 0x1c, 16 },
667 },
668 .fifosize = 64,
669 .overrun_reg = SCxSR,
670 .overrun_mask = SCIFA_ORER,
671 .sampling_rate_mask = SCI_SR(16),
672 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
673 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
674 .param_bits = &sci_scif_port_params_bits,
675 .common_regs = &sci_common_regs,
676 },
677};
678
679#define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset])
680
681/*
682 * The "offset" here is rather misleading, in that it refers to an enum
683 * value relative to the port mapping rather than the fixed offset
684 * itself, which needs to be manually retrieved from the platform's
685 * register map for the given port.
686 */
687static unsigned int sci_serial_in(struct uart_port *p, int offset)
688{
689 const struct plat_sci_reg *reg = sci_getreg(p, offset);
690
691 if (reg->size == 8)
692 return ioread8(p->membase + (reg->offset << p->regshift));
693 else if (reg->size == 16)
694 return ioread16(p->membase + (reg->offset << p->regshift));
695 else
696 WARN(1, "Invalid register access\n");
697
698 return 0;
699}
700
701static void sci_serial_out(struct uart_port *p, int offset, int value)
702{
703 const struct plat_sci_reg *reg = sci_getreg(p, offset);
704
705 if (reg->size == 8)
706 iowrite8(value, p->membase + (reg->offset << p->regshift));
707 else if (reg->size == 16)
708 iowrite16(value, p->membase + (reg->offset << p->regshift));
709 else
710 WARN(1, "Invalid register access\n");
711}
712
713void sci_port_enable(struct sci_port *sci_port)
714{
715 unsigned int i;
716
717 if (!sci_port->port.dev)
718 return;
719
720 pm_runtime_get_sync(sci_port->port.dev);
721
722 for (i = 0; i < SCI_NUM_CLKS; i++) {
723 clk_prepare_enable(sci_port->clks[i]);
724 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
725 }
726 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
727}
728EXPORT_SYMBOL_NS_GPL(sci_port_enable, "SH_SCI");
729
730void sci_port_disable(struct sci_port *sci_port)
731{
732 unsigned int i;
733
734 if (!sci_port->port.dev)
735 return;
736
737 for (i = SCI_NUM_CLKS; i-- > 0; )
738 clk_disable_unprepare(sci_port->clks[i]);
739
740 pm_runtime_put_sync(sci_port->port.dev);
741}
742EXPORT_SYMBOL_NS_GPL(sci_port_disable, "SH_SCI");
743
744static inline unsigned long port_rx_irq_mask(struct uart_port *port)
745{
746 /*
747 * Not all ports (such as SCIFA) will support REIE. Rather than
748 * special-casing the port type, we check the port initialization
749 * IRQ enable mask to see whether the IRQ is desired at all. If
750 * it's unset, it's logically inferred that there's no point in
751 * testing for it.
752 */
753 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
754}
755
756static void sci_start_tx(struct uart_port *port)
757{
758 struct sci_port *s = to_sci_port(port);
759 unsigned short ctrl;
760
761#ifdef CONFIG_SERIAL_SH_SCI_DMA
762 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) {
763 u16 new, scr = sci_serial_in(port, SCSCR);
764 if (s->chan_tx)
765 new = scr | SCSCR_TDRQE;
766 else
767 new = scr & ~SCSCR_TDRQE;
768 if (new != scr)
769 sci_serial_out(port, SCSCR, new);
770 }
771
772 if (s->chan_tx && !kfifo_is_empty(&port->state->port.xmit_fifo) &&
773 dma_submit_error(s->cookie_tx)) {
774 if (s->regtype == SCIx_RZ_SCIFA_REGTYPE)
775 /* Switch irq from SCIF to DMA */
776 disable_irq_nosync(s->irqs[SCIx_TXI_IRQ]);
777
778 s->cookie_tx = 0;
779 schedule_work(&s->work_tx);
780 }
781#endif
782
783 if (!s->chan_tx || s->regtype == SCIx_RZ_SCIFA_REGTYPE ||
784 s->type == PORT_SCIFA || s->type == PORT_SCIFB) {
785 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
786 ctrl = sci_serial_in(port, SCSCR);
787
788 /*
789 * For SCI, TE (transmit enable) must be set after setting TIE
790 * (transmit interrupt enable) or in the same instruction to start
791 * the transmit process.
792 */
793 if (s->type == PORT_SCI)
794 ctrl |= SCSCR_TE;
795
796 sci_serial_out(port, SCSCR, ctrl | SCSCR_TIE);
797 }
798}
799
800static void sci_stop_tx(struct uart_port *port)
801{
802 struct sci_port *s = to_sci_port(port);
803 unsigned short ctrl;
804
805 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
806 ctrl = sci_serial_in(port, SCSCR);
807
808 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB)
809 ctrl &= ~SCSCR_TDRQE;
810
811 ctrl &= ~SCSCR_TIE;
812
813 sci_serial_out(port, SCSCR, ctrl);
814
815#ifdef CONFIG_SERIAL_SH_SCI_DMA
816 if (s->chan_tx &&
817 !dma_submit_error(s->cookie_tx)) {
818 dmaengine_terminate_async(s->chan_tx);
819 s->cookie_tx = -EINVAL;
820 }
821#endif
822}
823
824static void sci_start_rx(struct uart_port *port)
825{
826 struct sci_port *s = to_sci_port(port);
827 unsigned short ctrl;
828
829 ctrl = sci_serial_in(port, SCSCR) | port_rx_irq_mask(port);
830
831 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB)
832 ctrl &= ~SCSCR_RDRQE;
833
834 sci_serial_out(port, SCSCR, ctrl);
835}
836
837static void sci_stop_rx(struct uart_port *port)
838{
839 struct sci_port *s = to_sci_port(port);
840 unsigned short ctrl;
841
842 ctrl = sci_serial_in(port, SCSCR);
843
844 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB)
845 ctrl &= ~SCSCR_RDRQE;
846
847 ctrl &= ~port_rx_irq_mask(port);
848
849 sci_serial_out(port, SCSCR, ctrl);
850}
851
852static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
853{
854 struct sci_port *s = to_sci_port(port);
855
856 if (s->type == PORT_SCI) {
857 /* Just store the mask */
858 sci_serial_out(port, SCxSR, mask);
859 } else if (s->params->overrun_mask == SCIFA_ORER) {
860 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
861 /* Only clear the status bits we want to clear */
862 sci_serial_out(port, SCxSR, sci_serial_in(port, SCxSR) & mask);
863 } else {
864 /* Store the mask, clear parity/framing errors */
865 sci_serial_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
866 }
867}
868
869#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
870 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
871
872#ifdef CONFIG_CONSOLE_POLL
873static int sci_poll_get_char(struct uart_port *port)
874{
875 unsigned short status;
876 struct sci_port *s = to_sci_port(port);
877 int c;
878
879 do {
880 status = sci_serial_in(port, SCxSR);
881 if (status & SCxSR_ERRORS(port)) {
882 s->ops->clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
883 continue;
884 }
885 break;
886 } while (1);
887
888 if (!(status & SCxSR_RDxF(port)))
889 return NO_POLL_CHAR;
890
891 c = sci_serial_in(port, SCxRDR);
892
893 /* Dummy read */
894 sci_serial_in(port, SCxSR);
895 s->ops->clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
896
897 return c;
898}
899#endif
900
901static void sci_poll_put_char(struct uart_port *port, unsigned char c)
902{
903 struct sci_port *s = to_sci_port(port);
904 const struct sci_common_regs *regs = s->params->common_regs;
905 unsigned int status;
906
907 do {
908 status = s->ops->read_reg(port, regs->status);
909 } while (!(status & SCxSR_TDxE(port)));
910
911 sci_serial_out(port, SCxTDR, c);
912 s->ops->clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
913}
914#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE ||
915 CONFIG_SERIAL_SH_SCI_EARLYCON */
916
917static void sci_init_pins(struct uart_port *port, unsigned int cflag)
918{
919 struct sci_port *s = to_sci_port(port);
920
921 /*
922 * Use port-specific handler if provided.
923 */
924 if (s->cfg->ops && s->cfg->ops->init_pins) {
925 s->cfg->ops->init_pins(port, cflag);
926 return;
927 }
928
929 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) {
930 u16 data = sci_serial_in(port, SCPDR);
931 u16 ctrl = sci_serial_in(port, SCPCR);
932
933 /* Enable RXD and TXD pin functions */
934 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC);
935 if (s->has_rtscts) {
936 /* RTS# is output, active low, unless autorts */
937 if (!(port->mctrl & TIOCM_RTS)) {
938 ctrl |= SCPCR_RTSC;
939 data |= SCPDR_RTSD;
940 } else if (!s->autorts) {
941 ctrl |= SCPCR_RTSC;
942 data &= ~SCPDR_RTSD;
943 } else {
944 /* Enable RTS# pin function */
945 ctrl &= ~SCPCR_RTSC;
946 }
947 /* Enable CTS# pin function */
948 ctrl &= ~SCPCR_CTSC;
949 }
950 sci_serial_out(port, SCPDR, data);
951 sci_serial_out(port, SCPCR, ctrl);
952 } else if (sci_getreg(port, SCSPTR)->size && s->regtype != SCIx_RZV2H_SCIF_REGTYPE) {
953 u16 status = sci_serial_in(port, SCSPTR);
954
955 /* RTS# is always output; and active low, unless autorts */
956 status |= SCSPTR_RTSIO;
957 if (!(port->mctrl & TIOCM_RTS))
958 status |= SCSPTR_RTSDT;
959 else if (!s->autorts)
960 status &= ~SCSPTR_RTSDT;
961 /* CTS# and SCK are inputs */
962 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO);
963 sci_serial_out(port, SCSPTR, status);
964 }
965}
966
967static int sci_txfill(struct uart_port *port)
968{
969 struct sci_port *s = to_sci_port(port);
970 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
971 const struct plat_sci_reg *reg;
972
973 reg = sci_getreg(port, SCTFDR);
974 if (reg->size)
975 return sci_serial_in(port, SCTFDR) & fifo_mask;
976
977 reg = sci_getreg(port, SCFDR);
978 if (reg->size)
979 return sci_serial_in(port, SCFDR) >> 8;
980
981 return !(sci_serial_in(port, SCxSR) & SCI_TDRE);
982}
983
984static int sci_txroom(struct uart_port *port)
985{
986 return port->fifosize - sci_txfill(port);
987}
988
989static int sci_rxfill(struct uart_port *port)
990{
991 struct sci_port *s = to_sci_port(port);
992 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
993 const struct plat_sci_reg *reg;
994
995 reg = sci_getreg(port, SCRFDR);
996 if (reg->size)
997 return sci_serial_in(port, SCRFDR) & fifo_mask;
998
999 reg = sci_getreg(port, SCFDR);
1000 if (reg->size)
1001 return sci_serial_in(port, SCFDR) & fifo_mask;
1002
1003 return (sci_serial_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
1004}
1005
1006/* ********************************************************************** *
1007 * the interrupt related routines *
1008 * ********************************************************************** */
1009
1010static void sci_transmit_chars(struct uart_port *port)
1011{
1012 struct tty_port *tport = &port->state->port;
1013 unsigned int stopped = uart_tx_stopped(port);
1014 struct sci_port *s = to_sci_port(port);
1015 unsigned short status;
1016 unsigned short ctrl;
1017 int count;
1018
1019 status = sci_serial_in(port, SCxSR);
1020 if (!(status & SCxSR_TDxE(port))) {
1021 ctrl = sci_serial_in(port, SCSCR);
1022 if (kfifo_is_empty(&tport->xmit_fifo))
1023 ctrl &= ~SCSCR_TIE;
1024 else
1025 ctrl |= SCSCR_TIE;
1026 sci_serial_out(port, SCSCR, ctrl);
1027 return;
1028 }
1029
1030 count = sci_txroom(port);
1031
1032 do {
1033 unsigned char c;
1034
1035 if (port->x_char) {
1036 c = port->x_char;
1037 port->x_char = 0;
1038 } else if (stopped || !kfifo_get(&tport->xmit_fifo, &c)) {
1039 if (s->type == PORT_SCI &&
1040 kfifo_is_empty(&tport->xmit_fifo)) {
1041 ctrl = sci_serial_in(port, SCSCR);
1042 ctrl &= ~SCSCR_TE;
1043 sci_serial_out(port, SCSCR, ctrl);
1044 return;
1045 }
1046 break;
1047 }
1048
1049 sci_serial_out(port, SCxTDR, c);
1050 s->tx_occurred = true;
1051
1052 port->icount.tx++;
1053 } while (--count > 0);
1054
1055 s->ops->clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
1056
1057 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
1058 uart_write_wakeup(port);
1059 if (kfifo_is_empty(&tport->xmit_fifo)) {
1060 if (s->type == PORT_SCI) {
1061 ctrl = sci_serial_in(port, SCSCR);
1062 ctrl &= ~SCSCR_TIE;
1063 ctrl |= SCSCR_TEIE;
1064 sci_serial_out(port, SCSCR, ctrl);
1065 }
1066
1067 sci_stop_tx(port);
1068 }
1069}
1070
1071static void sci_receive_chars(struct uart_port *port)
1072{
1073 struct tty_port *tport = &port->state->port;
1074 struct sci_port *s = to_sci_port(port);
1075 int i, count, copied = 0;
1076 unsigned short status;
1077 unsigned char flag;
1078
1079 status = sci_serial_in(port, SCxSR);
1080 if (!(status & SCxSR_RDxF(port)))
1081 return;
1082
1083 while (1) {
1084 /* Don't copy more bytes than there is room for in the buffer */
1085 count = tty_buffer_request_room(tport, sci_rxfill(port));
1086
1087 /* If for any reason we can't copy more data, we're done! */
1088 if (count == 0)
1089 break;
1090
1091 if (s->type == PORT_SCI) {
1092 char c = sci_serial_in(port, SCxRDR);
1093 if (uart_handle_sysrq_char(port, c))
1094 count = 0;
1095 else
1096 tty_insert_flip_char(tport, c, TTY_NORMAL);
1097 } else {
1098 for (i = 0; i < count; i++) {
1099 char c;
1100
1101 if (s->type == PORT_SCIF ||
1102 s->type == PORT_HSCIF) {
1103 status = sci_serial_in(port, SCxSR);
1104 c = sci_serial_in(port, SCxRDR);
1105 } else {
1106 c = sci_serial_in(port, SCxRDR);
1107 status = sci_serial_in(port, SCxSR);
1108 }
1109 if (uart_handle_sysrq_char(port, c)) {
1110 count--; i--;
1111 continue;
1112 }
1113
1114 /* Store data and status */
1115 if (status & SCxSR_FER(port)) {
1116 flag = TTY_FRAME;
1117 port->icount.frame++;
1118 } else if (status & SCxSR_PER(port)) {
1119 flag = TTY_PARITY;
1120 port->icount.parity++;
1121 } else
1122 flag = TTY_NORMAL;
1123
1124 tty_insert_flip_char(tport, c, flag);
1125 }
1126 }
1127
1128 sci_serial_in(port, SCxSR); /* dummy read */
1129 s->ops->clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1130
1131 copied += count;
1132 port->icount.rx += count;
1133 }
1134
1135 if (copied) {
1136 /* Tell the rest of the system the news. New characters! */
1137 tty_flip_buffer_push(tport);
1138 } else {
1139 /* TTY buffers full; read from RX reg to prevent lockup */
1140 sci_serial_in(port, SCxRDR);
1141 sci_serial_in(port, SCxSR); /* dummy read */
1142 s->ops->clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1143 }
1144}
1145
1146static int sci_handle_errors(struct uart_port *port)
1147{
1148 int copied = 0;
1149 struct sci_port *s = to_sci_port(port);
1150 const struct sci_common_regs *regs = s->params->common_regs;
1151 unsigned int status = s->ops->read_reg(port, regs->status);
1152 struct tty_port *tport = &port->state->port;
1153
1154 /* Handle overruns */
1155 if (status & s->params->overrun_mask) {
1156 port->icount.overrun++;
1157
1158 /* overrun error */
1159 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
1160 copied++;
1161 }
1162
1163 if (status & SCxSR_FER(port)) {
1164 /* frame error */
1165 port->icount.frame++;
1166
1167 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
1168 copied++;
1169 }
1170
1171 if (status & SCxSR_PER(port)) {
1172 /* parity error */
1173 port->icount.parity++;
1174
1175 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
1176 copied++;
1177 }
1178
1179 if (copied)
1180 tty_flip_buffer_push(tport);
1181
1182 return copied;
1183}
1184
1185static bool sci_is_rsci_type(u8 type)
1186{
1187 return (type == RSCI_PORT_SCIF16 || type == RSCI_PORT_SCIF32 ||
1188 type == RSCI_PORT_SCIF32_SINGLE_TCLK);
1189}
1190
1191static int sci_handle_fifo_overrun(struct uart_port *port)
1192{
1193 struct tty_port *tport = &port->state->port;
1194 struct sci_port *s = to_sci_port(port);
1195 const struct plat_sci_reg *reg;
1196 int copied = 0;
1197 u32 status;
1198
1199 if (!sci_is_rsci_type(s->type)) {
1200 reg = sci_getreg(port, s->params->overrun_reg);
1201 if (!reg->size)
1202 return 0;
1203 }
1204
1205 status = s->ops->read_reg(port, s->params->overrun_reg);
1206 if (status & s->params->overrun_mask) {
1207 if (sci_is_rsci_type(s->type)) {
1208 /*
1209 * All of the CFCLR_*C clearing bits match the corresponding
1210 * CSR_*status bits. So, reuse the overrun mask for clearing.
1211 */
1212 s->ops->clear_SCxSR(port, s->params->overrun_mask);
1213 } else {
1214 status &= ~s->params->overrun_mask;
1215 s->ops->write_reg(port, s->params->overrun_reg, status);
1216 }
1217
1218 port->icount.overrun++;
1219
1220 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
1221 tty_flip_buffer_push(tport);
1222 copied++;
1223 }
1224
1225 return copied;
1226}
1227
1228static int sci_handle_breaks(struct uart_port *port)
1229{
1230 int copied = 0;
1231 unsigned short status = sci_serial_in(port, SCxSR);
1232 struct tty_port *tport = &port->state->port;
1233
1234 if (uart_handle_break(port))
1235 return 0;
1236
1237 if (status & SCxSR_BRK(port)) {
1238 port->icount.brk++;
1239
1240 /* Notify of BREAK */
1241 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
1242 copied++;
1243 }
1244
1245 if (copied)
1246 tty_flip_buffer_push(tport);
1247
1248 copied += sci_handle_fifo_overrun(port);
1249
1250 return copied;
1251}
1252
1253static int scif_set_rtrg(struct uart_port *port, int rx_trig)
1254{
1255 struct sci_port *s = to_sci_port(port);
1256 unsigned int bits;
1257
1258 if (rx_trig >= port->fifosize)
1259 rx_trig = port->fifosize - 1;
1260 if (rx_trig < 1)
1261 rx_trig = 1;
1262
1263 /* HSCIF can be set to an arbitrary level. */
1264 if (sci_getreg(port, HSRTRGR)->size) {
1265 sci_serial_out(port, HSRTRGR, rx_trig);
1266 return rx_trig;
1267 }
1268
1269 switch (s->type) {
1270 case PORT_SCIF:
1271 if (rx_trig < 4) {
1272 bits = 0;
1273 rx_trig = 1;
1274 } else if (rx_trig < 8) {
1275 bits = SCFCR_RTRG0;
1276 rx_trig = 4;
1277 } else if (rx_trig < 14) {
1278 bits = SCFCR_RTRG1;
1279 rx_trig = 8;
1280 } else {
1281 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1282 rx_trig = 14;
1283 }
1284 break;
1285 case PORT_SCIFA:
1286 case PORT_SCIFB:
1287 if (rx_trig < 16) {
1288 bits = 0;
1289 rx_trig = 1;
1290 } else if (rx_trig < 32) {
1291 bits = SCFCR_RTRG0;
1292 rx_trig = 16;
1293 } else if (rx_trig < 48) {
1294 bits = SCFCR_RTRG1;
1295 rx_trig = 32;
1296 } else {
1297 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1298 rx_trig = 48;
1299 }
1300 break;
1301 default:
1302 WARN(1, "unknown FIFO configuration");
1303 return 1;
1304 }
1305
1306 sci_serial_out(port, SCFCR,
1307 (sci_serial_in(port, SCFCR) &
1308 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits);
1309
1310 return rx_trig;
1311}
1312
1313static int scif_rtrg_enabled(struct uart_port *port)
1314{
1315 if (sci_getreg(port, HSRTRGR)->size)
1316 return sci_serial_in(port, HSRTRGR) != 0;
1317 else
1318 return (sci_serial_in(port, SCFCR) &
1319 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0;
1320}
1321
1322static void rx_fifo_timer_fn(struct timer_list *t)
1323{
1324 struct sci_port *s = timer_container_of(s, t, rx_fifo_timer);
1325 struct uart_port *port = &s->port;
1326
1327 dev_dbg(port->dev, "Rx timed out\n");
1328 s->ops->set_rtrg(port, 1);
1329}
1330
1331static ssize_t rx_fifo_trigger_show(struct device *dev,
1332 struct device_attribute *attr, char *buf)
1333{
1334 struct uart_port *port = dev_get_drvdata(dev);
1335 struct sci_port *sci = to_sci_port(port);
1336
1337 return sprintf(buf, "%d\n", sci->rx_trigger);
1338}
1339
1340static ssize_t rx_fifo_trigger_store(struct device *dev,
1341 struct device_attribute *attr,
1342 const char *buf, size_t count)
1343{
1344 struct uart_port *port = dev_get_drvdata(dev);
1345 struct sci_port *sci = to_sci_port(port);
1346 int ret;
1347 long r;
1348
1349 ret = kstrtol(buf, 0, &r);
1350 if (ret)
1351 return ret;
1352
1353 sci->rx_trigger = sci->ops->set_rtrg(port, r);
1354 if (sci->type == PORT_SCIFA || sci->type == PORT_SCIFB)
1355 sci->ops->set_rtrg(port, 1);
1356
1357 return count;
1358}
1359
1360static DEVICE_ATTR_RW(rx_fifo_trigger);
1361
1362static ssize_t rx_fifo_timeout_show(struct device *dev,
1363 struct device_attribute *attr,
1364 char *buf)
1365{
1366 struct uart_port *port = dev_get_drvdata(dev);
1367 struct sci_port *sci = to_sci_port(port);
1368 int v;
1369
1370 if (sci->type == PORT_HSCIF)
1371 v = sci->hscif_tot >> HSSCR_TOT_SHIFT;
1372 else
1373 v = sci->rx_fifo_timeout;
1374
1375 return sprintf(buf, "%d\n", v);
1376}
1377
1378static ssize_t rx_fifo_timeout_store(struct device *dev,
1379 struct device_attribute *attr,
1380 const char *buf,
1381 size_t count)
1382{
1383 struct uart_port *port = dev_get_drvdata(dev);
1384 struct sci_port *sci = to_sci_port(port);
1385 int ret;
1386 long r;
1387
1388 ret = kstrtol(buf, 0, &r);
1389 if (ret)
1390 return ret;
1391
1392 if (sci->type == PORT_HSCIF) {
1393 if (r < 0 || r > 3)
1394 return -EINVAL;
1395 sci->hscif_tot = r << HSSCR_TOT_SHIFT;
1396 } else {
1397 sci->rx_fifo_timeout = r;
1398 sci->ops->set_rtrg(port, 1);
1399 if (r > 0)
1400 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0);
1401 }
1402
1403 return count;
1404}
1405
1406static DEVICE_ATTR_RW(rx_fifo_timeout);
1407
1408
1409#ifdef CONFIG_SERIAL_SH_SCI_DMA
1410static void sci_dma_tx_complete(void *arg)
1411{
1412 struct sci_port *s = arg;
1413 struct uart_port *port = &s->port;
1414 struct tty_port *tport = &port->state->port;
1415 unsigned long flags;
1416
1417 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1418
1419 uart_port_lock_irqsave(port, &flags);
1420
1421 uart_xmit_advance(port, s->tx_dma_len);
1422
1423 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
1424 uart_write_wakeup(port);
1425
1426 s->tx_occurred = true;
1427
1428 if (!kfifo_is_empty(&tport->xmit_fifo)) {
1429 s->cookie_tx = 0;
1430 schedule_work(&s->work_tx);
1431 } else {
1432 s->cookie_tx = -EINVAL;
1433 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB ||
1434 s->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1435 u16 ctrl = sci_serial_in(port, SCSCR);
1436 sci_serial_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1437 if (s->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1438 /* Switch irq from DMA to SCIF */
1439 dmaengine_pause(s->chan_tx_saved);
1440 enable_irq(s->irqs[SCIx_TXI_IRQ]);
1441 }
1442 }
1443 }
1444
1445 uart_port_unlock_irqrestore(port, flags);
1446}
1447
1448/* Locking: called with port lock held */
1449static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1450{
1451 struct uart_port *port = &s->port;
1452 struct tty_port *tport = &port->state->port;
1453 int copied;
1454
1455 copied = tty_insert_flip_string(tport, buf, count);
1456 if (copied < count)
1457 port->icount.buf_overrun++;
1458
1459 port->icount.rx += copied;
1460
1461 return copied;
1462}
1463
1464static int sci_dma_rx_find_active(struct sci_port *s)
1465{
1466 unsigned int i;
1467
1468 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1469 if (s->active_rx == s->cookie_rx[i])
1470 return i;
1471
1472 return -1;
1473}
1474
1475/* Must only be called with uart_port_lock taken */
1476static void sci_dma_rx_chan_invalidate(struct sci_port *s)
1477{
1478 unsigned int i;
1479
1480 s->chan_rx = NULL;
1481 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1482 s->cookie_rx[i] = -EINVAL;
1483 s->active_rx = 0;
1484}
1485
1486static void sci_dma_rx_release(struct sci_port *s)
1487{
1488 struct dma_chan *chan = s->chan_rx_saved;
1489 struct uart_port *port = &s->port;
1490 unsigned long flags;
1491
1492 uart_port_lock_irqsave(port, &flags);
1493 s->chan_rx_saved = NULL;
1494 sci_dma_rx_chan_invalidate(s);
1495 uart_port_unlock_irqrestore(port, flags);
1496
1497 dmaengine_terminate_sync(chan);
1498 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1499 sg_dma_address(&s->sg_rx[0]));
1500 dma_release_channel(chan);
1501}
1502
1503static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec)
1504{
1505 long sec = usec / 1000000;
1506 long nsec = (usec % 1000000) * 1000;
1507 ktime_t t = ktime_set(sec, nsec);
1508
1509 hrtimer_start(hrt, t, HRTIMER_MODE_REL);
1510}
1511
1512static void sci_dma_rx_reenable_irq(struct sci_port *s)
1513{
1514 struct uart_port *port = &s->port;
1515 u16 scr;
1516
1517 /* Direct new serial port interrupts back to CPU */
1518 scr = sci_serial_in(port, SCSCR);
1519 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB ||
1520 s->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1521 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1522 if (s->regtype == SCIx_RZ_SCIFA_REGTYPE)
1523 s->ops->set_rtrg(port, s->rx_trigger);
1524 else
1525 scr &= ~SCSCR_RDRQE;
1526 }
1527 sci_serial_out(port, SCSCR, scr | SCSCR_RIE);
1528}
1529
1530static void sci_dma_rx_complete(void *arg)
1531{
1532 struct sci_port *s = arg;
1533 struct dma_chan *chan = s->chan_rx;
1534 struct uart_port *port = &s->port;
1535 struct dma_async_tx_descriptor *desc;
1536 unsigned long flags;
1537 int active, count = 0;
1538
1539 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1540 s->active_rx);
1541
1542 hrtimer_cancel(&s->rx_timer);
1543
1544 uart_port_lock_irqsave(port, &flags);
1545
1546 active = sci_dma_rx_find_active(s);
1547 if (active >= 0)
1548 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
1549
1550 if (count)
1551 tty_flip_buffer_push(&port->state->port);
1552
1553 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1554 DMA_DEV_TO_MEM,
1555 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1556 if (!desc)
1557 goto fail;
1558
1559 desc->callback = sci_dma_rx_complete;
1560 desc->callback_param = s;
1561 s->cookie_rx[active] = dmaengine_submit(desc);
1562 if (dma_submit_error(s->cookie_rx[active]))
1563 goto fail;
1564
1565 s->active_rx = s->cookie_rx[!active];
1566
1567 dma_async_issue_pending(chan);
1568
1569 uart_port_unlock_irqrestore(port, flags);
1570 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1571 __func__, s->cookie_rx[active], active, s->active_rx);
1572
1573 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
1574
1575 return;
1576
1577fail:
1578 /* Switch to PIO */
1579 dmaengine_terminate_async(chan);
1580 sci_dma_rx_chan_invalidate(s);
1581 sci_dma_rx_reenable_irq(s);
1582 uart_port_unlock_irqrestore(port, flags);
1583 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1584}
1585
1586static void sci_dma_tx_release(struct sci_port *s)
1587{
1588 struct dma_chan *chan = s->chan_tx_saved;
1589
1590 cancel_work_sync(&s->work_tx);
1591 s->chan_tx_saved = s->chan_tx = NULL;
1592 s->cookie_tx = -EINVAL;
1593 dmaengine_terminate_sync(chan);
1594 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1595 DMA_TO_DEVICE);
1596 dma_release_channel(chan);
1597}
1598
1599static int sci_dma_rx_submit(struct sci_port *s, bool port_lock_held)
1600{
1601 struct dma_chan *chan = s->chan_rx;
1602 struct uart_port *port = &s->port;
1603 unsigned long flags;
1604 int i;
1605
1606 for (i = 0; i < 2; i++) {
1607 struct scatterlist *sg = &s->sg_rx[i];
1608 struct dma_async_tx_descriptor *desc;
1609
1610 desc = dmaengine_prep_slave_sg(chan,
1611 sg, 1, DMA_DEV_TO_MEM,
1612 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1613 if (!desc)
1614 goto fail;
1615
1616 desc->callback = sci_dma_rx_complete;
1617 desc->callback_param = s;
1618 s->cookie_rx[i] = dmaengine_submit(desc);
1619 if (dma_submit_error(s->cookie_rx[i]))
1620 goto fail;
1621
1622 }
1623
1624 s->active_rx = s->cookie_rx[0];
1625
1626 dma_async_issue_pending(chan);
1627 return 0;
1628
1629fail:
1630 /* Switch to PIO */
1631 if (!port_lock_held)
1632 uart_port_lock_irqsave(port, &flags);
1633 if (i)
1634 dmaengine_terminate_async(chan);
1635 sci_dma_rx_chan_invalidate(s);
1636 sci_start_rx(port);
1637 if (!port_lock_held)
1638 uart_port_unlock_irqrestore(port, flags);
1639 return -EAGAIN;
1640}
1641
1642static void sci_dma_tx_work_fn(struct work_struct *work)
1643{
1644 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1645 struct dma_async_tx_descriptor *desc;
1646 struct dma_chan *chan = s->chan_tx;
1647 struct uart_port *port = &s->port;
1648 struct tty_port *tport = &port->state->port;
1649 unsigned long flags;
1650 unsigned int tail;
1651 dma_addr_t buf;
1652
1653 /*
1654 * DMA is idle now.
1655 * Port xmit buffer is already mapped, and it is one page... Just adjust
1656 * offsets and lengths. Since it is a circular buffer, we have to
1657 * transmit till the end, and then the rest. Take the port lock to get a
1658 * consistent xmit buffer state.
1659 */
1660 uart_port_lock_irq(port);
1661 s->tx_dma_len = kfifo_out_linear(&tport->xmit_fifo, &tail,
1662 UART_XMIT_SIZE);
1663 buf = s->tx_dma_addr + tail;
1664 if (!s->tx_dma_len) {
1665 /* Transmit buffer has been flushed */
1666 uart_port_unlock_irq(port);
1667 return;
1668 }
1669
1670 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1671 DMA_MEM_TO_DEV,
1672 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1673 if (!desc) {
1674 uart_port_unlock_irq(port);
1675 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1676 goto switch_to_pio;
1677 }
1678
1679 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1680 DMA_TO_DEVICE);
1681
1682 desc->callback = sci_dma_tx_complete;
1683 desc->callback_param = s;
1684 s->cookie_tx = dmaengine_submit(desc);
1685 if (dma_submit_error(s->cookie_tx)) {
1686 uart_port_unlock_irq(port);
1687 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1688 goto switch_to_pio;
1689 }
1690
1691 uart_port_unlock_irq(port);
1692 dev_dbg(port->dev, "%s: %p: %u, cookie %d\n",
1693 __func__, tport->xmit_buf, tail, s->cookie_tx);
1694
1695 dma_async_issue_pending(chan);
1696 return;
1697
1698switch_to_pio:
1699 uart_port_lock_irqsave(port, &flags);
1700 s->chan_tx = NULL;
1701 sci_start_tx(port);
1702 uart_port_unlock_irqrestore(port, flags);
1703 return;
1704}
1705
1706static enum hrtimer_restart sci_dma_rx_timer_fn(struct hrtimer *t)
1707{
1708 struct sci_port *s = container_of(t, struct sci_port, rx_timer);
1709 struct dma_chan *chan = s->chan_rx;
1710 struct uart_port *port = &s->port;
1711 struct dma_tx_state state;
1712 enum dma_status status;
1713 unsigned long flags;
1714 unsigned int read;
1715 int active, count;
1716
1717 dev_dbg(port->dev, "DMA Rx timed out\n");
1718
1719 uart_port_lock_irqsave(port, &flags);
1720
1721 active = sci_dma_rx_find_active(s);
1722 if (active < 0) {
1723 uart_port_unlock_irqrestore(port, flags);
1724 return HRTIMER_NORESTART;
1725 }
1726
1727 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1728 if (status == DMA_COMPLETE) {
1729 uart_port_unlock_irqrestore(port, flags);
1730 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1731 s->active_rx, active);
1732
1733 /* Let packet complete handler take care of the packet */
1734 return HRTIMER_NORESTART;
1735 }
1736
1737 dmaengine_pause(chan);
1738
1739 /*
1740 * sometimes DMA transfer doesn't stop even if it is stopped and
1741 * data keeps on coming until transaction is complete so check
1742 * for DMA_COMPLETE again
1743 * Let packet complete handler take care of the packet
1744 */
1745 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1746 if (status == DMA_COMPLETE) {
1747 uart_port_unlock_irqrestore(port, flags);
1748 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1749 return HRTIMER_NORESTART;
1750 }
1751
1752 /* Handle incomplete DMA receive */
1753 dmaengine_terminate_async(s->chan_rx);
1754 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
1755
1756 if (read) {
1757 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1758 if (count)
1759 tty_flip_buffer_push(&port->state->port);
1760 }
1761
1762 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB ||
1763 s->regtype == SCIx_RZ_SCIFA_REGTYPE)
1764 sci_dma_rx_submit(s, true);
1765
1766 sci_dma_rx_reenable_irq(s);
1767
1768 uart_port_unlock_irqrestore(port, flags);
1769
1770 return HRTIMER_NORESTART;
1771}
1772
1773static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
1774 enum dma_transfer_direction dir)
1775{
1776 struct dma_chan *chan;
1777 struct dma_slave_config cfg;
1778 int ret;
1779
1780 chan = dma_request_chan(port->dev, dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1781 if (IS_ERR(chan)) {
1782 dev_dbg(port->dev, "dma_request_chan failed\n");
1783 return NULL;
1784 }
1785
1786 memset(&cfg, 0, sizeof(cfg));
1787 cfg.direction = dir;
1788 cfg.dst_addr = port->mapbase +
1789 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1790 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1791 cfg.src_addr = port->mapbase +
1792 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1793 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1794
1795 ret = dmaengine_slave_config(chan, &cfg);
1796 if (ret) {
1797 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1798 dma_release_channel(chan);
1799 return NULL;
1800 }
1801
1802 return chan;
1803}
1804
1805static void sci_request_dma(struct uart_port *port)
1806{
1807 struct sci_port *s = to_sci_port(port);
1808 struct tty_port *tport = &port->state->port;
1809 struct dma_chan *chan;
1810
1811 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1812
1813 /*
1814 * DMA on console may interfere with Kernel log messages which use
1815 * plain putchar(). So, simply don't use it with a console.
1816 */
1817 if (uart_console(port))
1818 return;
1819
1820 if (!port->dev->of_node)
1821 return;
1822
1823 s->cookie_tx = -EINVAL;
1824
1825 /*
1826 * Don't request a dma channel if no channel was specified
1827 * in the device tree.
1828 */
1829 if (!of_property_present(port->dev->of_node, "dmas"))
1830 return;
1831
1832 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV);
1833 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1834 if (chan) {
1835 /* UART circular tx buffer is an aligned page. */
1836 s->tx_dma_addr = dma_map_single(chan->device->dev,
1837 tport->xmit_buf,
1838 UART_XMIT_SIZE,
1839 DMA_TO_DEVICE);
1840 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1841 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1842 dma_release_channel(chan);
1843 } else {
1844 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1845 __func__, UART_XMIT_SIZE,
1846 tport->xmit_buf, &s->tx_dma_addr);
1847
1848 INIT_WORK(&s->work_tx, sci_dma_tx_work_fn);
1849 s->chan_tx_saved = s->chan_tx = chan;
1850 }
1851 }
1852
1853 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM);
1854 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1855 if (chan) {
1856 unsigned int i;
1857 dma_addr_t dma;
1858 void *buf;
1859
1860 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1861 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1862 &dma, GFP_KERNEL);
1863 if (!buf) {
1864 dev_warn(port->dev,
1865 "Failed to allocate Rx dma buffer, using PIO\n");
1866 dma_release_channel(chan);
1867 return;
1868 }
1869
1870 for (i = 0; i < 2; i++) {
1871 struct scatterlist *sg = &s->sg_rx[i];
1872
1873 sg_init_table(sg, 1);
1874 s->rx_buf[i] = buf;
1875 sg_dma_address(sg) = dma;
1876 sg_dma_len(sg) = s->buf_len_rx;
1877
1878 buf += s->buf_len_rx;
1879 dma += s->buf_len_rx;
1880 }
1881
1882 hrtimer_setup(&s->rx_timer, sci_dma_rx_timer_fn, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1883
1884 s->chan_rx_saved = s->chan_rx = chan;
1885
1886 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB ||
1887 s->regtype == SCIx_RZ_SCIFA_REGTYPE)
1888 sci_dma_rx_submit(s, false);
1889 }
1890}
1891
1892static void sci_free_dma(struct uart_port *port)
1893{
1894 struct sci_port *s = to_sci_port(port);
1895
1896 if (s->chan_tx_saved)
1897 sci_dma_tx_release(s);
1898 if (s->chan_rx_saved)
1899 sci_dma_rx_release(s);
1900}
1901
1902static void sci_flush_buffer(struct uart_port *port)
1903{
1904 struct sci_port *s = to_sci_port(port);
1905
1906 /*
1907 * In uart_flush_buffer(), the xmit circular buffer has just been
1908 * cleared, so we have to reset tx_dma_len accordingly, and stop any
1909 * pending transfers
1910 */
1911 s->tx_dma_len = 0;
1912 if (s->chan_tx) {
1913 dmaengine_terminate_async(s->chan_tx);
1914 s->cookie_tx = -EINVAL;
1915 }
1916}
1917
1918static void sci_dma_check_tx_occurred(struct sci_port *s)
1919{
1920 struct dma_tx_state state;
1921 enum dma_status status;
1922
1923 if (!s->chan_tx || s->cookie_tx <= 0)
1924 return;
1925
1926 status = dmaengine_tx_status(s->chan_tx, s->cookie_tx, &state);
1927 if (status == DMA_COMPLETE || status == DMA_IN_PROGRESS)
1928 s->tx_occurred = true;
1929}
1930#else /* !CONFIG_SERIAL_SH_SCI_DMA */
1931static inline void sci_request_dma(struct uart_port *port)
1932{
1933}
1934
1935static inline void sci_free_dma(struct uart_port *port)
1936{
1937}
1938
1939static void sci_dma_check_tx_occurred(struct sci_port *s)
1940{
1941}
1942
1943#define sci_flush_buffer NULL
1944#endif /* !CONFIG_SERIAL_SH_SCI_DMA */
1945
1946static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1947{
1948 struct uart_port *port = ptr;
1949 struct sci_port *s = to_sci_port(port);
1950
1951#ifdef CONFIG_SERIAL_SH_SCI_DMA
1952 if (s->chan_rx) {
1953 u16 scr = sci_serial_in(port, SCSCR);
1954 u16 ssr = sci_serial_in(port, SCxSR);
1955
1956 /* Disable future Rx interrupts */
1957 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB ||
1958 s->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1959 disable_irq_nosync(s->irqs[SCIx_RXI_IRQ]);
1960 if (s->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1961 s->ops->set_rtrg(port, 1);
1962 scr |= SCSCR_RIE;
1963 } else {
1964 scr |= SCSCR_RDRQE;
1965 }
1966 } else {
1967 if (sci_dma_rx_submit(s, false) < 0)
1968 goto handle_pio;
1969
1970 scr &= ~SCSCR_RIE;
1971 }
1972 sci_serial_out(port, SCSCR, scr);
1973 /* Clear current interrupt */
1974 sci_serial_out(port, SCxSR,
1975 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1976 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n",
1977 jiffies, s->rx_timeout);
1978 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
1979
1980 return IRQ_HANDLED;
1981 }
1982
1983handle_pio:
1984#endif
1985
1986 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) {
1987 if (!s->ops->rtrg_enabled(port))
1988 s->ops->set_rtrg(port, s->rx_trigger);
1989
1990 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP(
1991 s->rx_frame * HZ * s->rx_fifo_timeout, 1000000));
1992 }
1993
1994 /* I think sci_receive_chars has to be called irrespective
1995 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1996 * to be disabled?
1997 */
1998 s->ops->receive_chars(port);
1999
2000 return IRQ_HANDLED;
2001}
2002
2003static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
2004{
2005 struct uart_port *port = ptr;
2006 unsigned long flags;
2007 struct sci_port *s = to_sci_port(port);
2008
2009 uart_port_lock_irqsave(port, &flags);
2010 s->ops->transmit_chars(port);
2011 uart_port_unlock_irqrestore(port, flags);
2012
2013 return IRQ_HANDLED;
2014}
2015
2016static irqreturn_t sci_tx_end_interrupt(int irq, void *ptr)
2017{
2018 struct uart_port *port = ptr;
2019 struct sci_port *s = to_sci_port(port);
2020 const struct sci_common_regs *regs = s->params->common_regs;
2021 unsigned long flags;
2022 u32 ctrl;
2023
2024 if (s->type != PORT_SCI && !sci_is_rsci_type(s->type))
2025 return sci_tx_interrupt(irq, ptr);
2026
2027 uart_port_lock_irqsave(port, &flags);
2028 ctrl = s->ops->read_reg(port, regs->control) &
2029 ~(s->params->param_bits->te_clear);
2030 s->ops->write_reg(port, regs->control, ctrl);
2031 uart_port_unlock_irqrestore(port, flags);
2032
2033 return IRQ_HANDLED;
2034}
2035
2036static irqreturn_t sci_br_interrupt(int irq, void *ptr)
2037{
2038 struct uart_port *port = ptr;
2039 struct sci_port *s = to_sci_port(port);
2040
2041 /* Handle BREAKs */
2042 sci_handle_breaks(port);
2043
2044 /* drop invalid character received before break was detected */
2045 sci_serial_in(port, SCxRDR);
2046
2047 s->ops->clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
2048
2049 return IRQ_HANDLED;
2050}
2051
2052static irqreturn_t sci_er_interrupt(int irq, void *ptr)
2053{
2054 struct uart_port *port = ptr;
2055 struct sci_port *s = to_sci_port(port);
2056
2057 if (s->irqs[SCIx_ERI_IRQ] == s->irqs[SCIx_BRI_IRQ]) {
2058 /* Break and Error interrupts are muxed */
2059 unsigned short ssr_status = sci_serial_in(port, SCxSR);
2060
2061 /* Break Interrupt */
2062 if (ssr_status & SCxSR_BRK(port))
2063 sci_br_interrupt(irq, ptr);
2064
2065 /* Break only? */
2066 if (!(ssr_status & SCxSR_ERRORS(port)))
2067 return IRQ_HANDLED;
2068 }
2069
2070 /* Handle errors */
2071 if (s->type == PORT_SCI) {
2072 if (sci_handle_errors(port)) {
2073 /* discard character in rx buffer */
2074 sci_serial_in(port, SCxSR);
2075 s->ops->clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
2076 }
2077 } else {
2078 sci_handle_fifo_overrun(port);
2079 if (!s->chan_rx)
2080 s->ops->receive_chars(port);
2081 }
2082
2083 s->ops->clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
2084
2085 /* Kick the transmission */
2086 if (!s->chan_tx)
2087 sci_tx_interrupt(irq, ptr);
2088
2089 return IRQ_HANDLED;
2090}
2091
2092static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
2093{
2094 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
2095 struct uart_port *port = ptr;
2096 struct sci_port *s = to_sci_port(port);
2097 irqreturn_t ret = IRQ_NONE;
2098
2099 ssr_status = sci_serial_in(port, SCxSR);
2100 scr_status = sci_serial_in(port, SCSCR);
2101 if (s->params->overrun_reg == SCxSR)
2102 orer_status = ssr_status;
2103 else if (sci_getreg(port, s->params->overrun_reg)->size)
2104 orer_status = sci_serial_in(port, s->params->overrun_reg);
2105
2106 err_enabled = scr_status & port_rx_irq_mask(port);
2107
2108 /* Tx Interrupt */
2109 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
2110 !s->chan_tx)
2111 ret = sci_tx_interrupt(irq, ptr);
2112
2113 /*
2114 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
2115 * DR flags
2116 */
2117 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
2118 (scr_status & SCSCR_RIE))
2119 ret = sci_rx_interrupt(irq, ptr);
2120
2121 /* Error Interrupt */
2122 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
2123 ret = sci_er_interrupt(irq, ptr);
2124
2125 /* Break Interrupt */
2126 if (s->irqs[SCIx_ERI_IRQ] != s->irqs[SCIx_BRI_IRQ] &&
2127 (ssr_status & SCxSR_BRK(port)) && err_enabled)
2128 ret = sci_br_interrupt(irq, ptr);
2129
2130 /* Overrun Interrupt */
2131 if (orer_status & s->params->overrun_mask) {
2132 sci_handle_fifo_overrun(port);
2133 ret = IRQ_HANDLED;
2134 }
2135
2136 return ret;
2137}
2138
2139static const struct sci_irq_desc {
2140 const char *desc;
2141 irq_handler_t handler;
2142} sci_irq_desc[] = {
2143 /*
2144 * Split out handlers, the default case.
2145 */
2146 [SCIx_ERI_IRQ] = {
2147 .desc = "rx err",
2148 .handler = sci_er_interrupt,
2149 },
2150
2151 [SCIx_RXI_IRQ] = {
2152 .desc = "rx full",
2153 .handler = sci_rx_interrupt,
2154 },
2155
2156 [SCIx_TXI_IRQ] = {
2157 .desc = "tx empty",
2158 .handler = sci_tx_interrupt,
2159 },
2160
2161 [SCIx_BRI_IRQ] = {
2162 .desc = "break",
2163 .handler = sci_br_interrupt,
2164 },
2165
2166 [SCIx_DRI_IRQ] = {
2167 .desc = "rx ready",
2168 .handler = sci_rx_interrupt,
2169 },
2170
2171 [SCIx_TEI_IRQ] = {
2172 .desc = "tx end",
2173 .handler = sci_tx_end_interrupt,
2174 },
2175
2176 /*
2177 * Special muxed handler.
2178 */
2179 [SCIx_MUX_IRQ] = {
2180 .desc = "mux",
2181 .handler = sci_mpxed_interrupt,
2182 },
2183};
2184
2185static int sci_request_irq(struct sci_port *port)
2186{
2187 struct uart_port *up = &port->port;
2188 int i, j, w, ret = 0;
2189
2190 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
2191 const struct sci_irq_desc *desc;
2192 int irq;
2193
2194 /* Check if already registered (muxed) */
2195 for (w = 0; w < i; w++)
2196 if (port->irqs[w] == port->irqs[i])
2197 w = i + 1;
2198 if (w > i)
2199 continue;
2200
2201 if (SCIx_IRQ_IS_MUXED(port)) {
2202 i = SCIx_MUX_IRQ;
2203 irq = up->irq;
2204 } else {
2205 irq = port->irqs[i];
2206
2207 /*
2208 * Certain port types won't support all of the
2209 * available interrupt sources.
2210 */
2211 if (unlikely(irq < 0))
2212 continue;
2213 }
2214
2215 desc = sci_irq_desc + i;
2216 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
2217 dev_name(up->dev), desc->desc);
2218 if (!port->irqstr[j]) {
2219 ret = -ENOMEM;
2220 goto out_nomem;
2221 }
2222
2223 ret = request_irq(irq, desc->handler, up->irqflags,
2224 port->irqstr[j], port);
2225 if (unlikely(ret)) {
2226 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
2227 goto out_noirq;
2228 }
2229 }
2230
2231 return 0;
2232
2233out_noirq:
2234 while (--i >= 0)
2235 free_irq(port->irqs[i], port);
2236
2237out_nomem:
2238 while (--j >= 0)
2239 kfree(port->irqstr[j]);
2240
2241 return ret;
2242}
2243
2244static void sci_free_irq(struct sci_port *port)
2245{
2246 int i, j;
2247
2248 /*
2249 * Intentionally in reverse order so we iterate over the muxed
2250 * IRQ first.
2251 */
2252 for (i = 0; i < SCIx_NR_IRQS; i++) {
2253 int irq = port->irqs[i];
2254
2255 /*
2256 * Certain port types won't support all of the available
2257 * interrupt sources.
2258 */
2259 if (unlikely(irq < 0))
2260 continue;
2261
2262 /* Check if already freed (irq was muxed) */
2263 for (j = 0; j < i; j++)
2264 if (port->irqs[j] == irq)
2265 j = i + 1;
2266 if (j > i)
2267 continue;
2268
2269 free_irq(port->irqs[i], port);
2270 kfree(port->irqstr[i]);
2271
2272 if (SCIx_IRQ_IS_MUXED(port)) {
2273 /* If there's only one IRQ, we're done. */
2274 return;
2275 }
2276 }
2277}
2278
2279static unsigned int sci_tx_empty(struct uart_port *port)
2280{
2281 unsigned short status = sci_serial_in(port, SCxSR);
2282 unsigned short in_tx_fifo = sci_txfill(port);
2283 struct sci_port *s = to_sci_port(port);
2284
2285 sci_dma_check_tx_occurred(s);
2286
2287 if (!s->tx_occurred)
2288 return TIOCSER_TEMT;
2289
2290 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
2291}
2292
2293static void sci_set_rts(struct uart_port *port, bool state)
2294{
2295 struct sci_port *s = to_sci_port(port);
2296
2297 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) {
2298 u16 data = sci_serial_in(port, SCPDR);
2299
2300 /* Active low */
2301 if (state)
2302 data &= ~SCPDR_RTSD;
2303 else
2304 data |= SCPDR_RTSD;
2305 sci_serial_out(port, SCPDR, data);
2306
2307 /* RTS# is output */
2308 sci_serial_out(port, SCPCR,
2309 sci_serial_in(port, SCPCR) | SCPCR_RTSC);
2310 } else if (sci_getreg(port, SCSPTR)->size) {
2311 u16 ctrl = sci_serial_in(port, SCSPTR);
2312
2313 /* Active low */
2314 if (state)
2315 ctrl &= ~SCSPTR_RTSDT;
2316 else
2317 ctrl |= SCSPTR_RTSDT;
2318 sci_serial_out(port, SCSPTR, ctrl);
2319 }
2320}
2321
2322static bool sci_get_cts(struct uart_port *port)
2323{
2324 struct sci_port *s = to_sci_port(port);
2325
2326 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) {
2327 /* Active low */
2328 return !(sci_serial_in(port, SCPDR) & SCPDR_CTSD);
2329 } else if (sci_getreg(port, SCSPTR)->size) {
2330 /* Active low */
2331 return !(sci_serial_in(port, SCSPTR) & SCSPTR_CTSDT);
2332 }
2333
2334 return true;
2335}
2336
2337/*
2338 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
2339 * CTS/RTS is supported in hardware by at least one port and controlled
2340 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
2341 * handled via the ->init_pins() op, which is a bit of a one-way street,
2342 * lacking any ability to defer pin control -- this will later be
2343 * converted over to the GPIO framework).
2344 *
2345 * Other modes (such as loopback) are supported generically on certain
2346 * port types, but not others. For these it's sufficient to test for the
2347 * existence of the support register and simply ignore the port type.
2348 */
2349static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
2350{
2351 struct sci_port *s = to_sci_port(port);
2352
2353 if (mctrl & TIOCM_LOOP) {
2354 const struct plat_sci_reg *reg;
2355
2356 /*
2357 * Standard loopback mode for SCFCR ports.
2358 */
2359 reg = sci_getreg(port, SCFCR);
2360 if (reg->size)
2361 sci_serial_out(port, SCFCR,
2362 sci_serial_in(port, SCFCR) | SCFCR_LOOP);
2363 }
2364
2365 mctrl_gpio_set(s->gpios, mctrl);
2366
2367 if (!s->has_rtscts)
2368 return;
2369
2370 if (!(mctrl & TIOCM_RTS)) {
2371 /* Disable Auto RTS */
2372 if (s->regtype != SCIx_RZV2H_SCIF_REGTYPE)
2373 sci_serial_out(port, SCFCR,
2374 sci_serial_in(port, SCFCR) & ~SCFCR_MCE);
2375
2376 /* Clear RTS */
2377 sci_set_rts(port, 0);
2378 } else if (s->autorts) {
2379 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) {
2380 /* Enable RTS# pin function */
2381 sci_serial_out(port, SCPCR,
2382 sci_serial_in(port, SCPCR) & ~SCPCR_RTSC);
2383 }
2384
2385 /* Enable Auto RTS */
2386 if (s->regtype != SCIx_RZV2H_SCIF_REGTYPE)
2387 sci_serial_out(port, SCFCR,
2388 sci_serial_in(port, SCFCR) | SCFCR_MCE);
2389 } else {
2390 /* Set RTS */
2391 sci_set_rts(port, 1);
2392 }
2393}
2394
2395static unsigned int sci_get_mctrl(struct uart_port *port)
2396{
2397 struct sci_port *s = to_sci_port(port);
2398 struct mctrl_gpios *gpios = s->gpios;
2399 unsigned int mctrl = 0;
2400
2401 mctrl_gpio_get(gpios, &mctrl);
2402
2403 /*
2404 * CTS/RTS is handled in hardware when supported, while nothing
2405 * else is wired up.
2406 */
2407 if (s->autorts) {
2408 if (sci_get_cts(port))
2409 mctrl |= TIOCM_CTS;
2410 } else if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS)) {
2411 mctrl |= TIOCM_CTS;
2412 }
2413 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR))
2414 mctrl |= TIOCM_DSR;
2415 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD))
2416 mctrl |= TIOCM_CAR;
2417
2418 return mctrl;
2419}
2420
2421static void sci_enable_ms(struct uart_port *port)
2422{
2423 mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
2424}
2425
2426static void sci_break_ctl(struct uart_port *port, int break_state)
2427{
2428 unsigned short scscr, scsptr;
2429 unsigned long flags;
2430
2431 /* check whether the port has SCSPTR */
2432 if (!sci_getreg(port, SCSPTR)->size) {
2433 /*
2434 * Not supported by hardware. Most parts couple break and rx
2435 * interrupts together, with break detection always enabled.
2436 */
2437 return;
2438 }
2439
2440 uart_port_lock_irqsave(port, &flags);
2441 scsptr = sci_serial_in(port, SCSPTR);
2442 scscr = sci_serial_in(port, SCSCR);
2443
2444 if (break_state == -1) {
2445 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
2446 scscr &= ~SCSCR_TE;
2447 } else {
2448 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
2449 scscr |= SCSCR_TE;
2450 }
2451
2452 sci_serial_out(port, SCSPTR, scsptr);
2453 sci_serial_out(port, SCSCR, scscr);
2454 uart_port_unlock_irqrestore(port, flags);
2455}
2456
2457static void sci_shutdown_complete(struct uart_port *port)
2458{
2459 struct sci_port *s = to_sci_port(port);
2460 u16 scr;
2461
2462 scr = sci_serial_in(port, SCSCR);
2463 sci_serial_out(port, SCSCR,
2464 scr & (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot));
2465}
2466
2467int sci_startup(struct uart_port *port)
2468{
2469 struct sci_port *s = to_sci_port(port);
2470 int ret;
2471
2472 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2473
2474 s->tx_occurred = false;
2475 sci_request_dma(port);
2476
2477 ret = sci_request_irq(s);
2478 if (unlikely(ret < 0)) {
2479 sci_free_dma(port);
2480 return ret;
2481 }
2482
2483 return 0;
2484}
2485EXPORT_SYMBOL_NS_GPL(sci_startup, "SH_SCI");
2486
2487void sci_shutdown(struct uart_port *port)
2488{
2489 struct sci_port *s = to_sci_port(port);
2490 unsigned long flags;
2491
2492 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2493
2494 s->autorts = false;
2495 mctrl_gpio_disable_ms_sync(to_sci_port(port)->gpios);
2496
2497 uart_port_lock_irqsave(port, &flags);
2498 s->port.ops->stop_rx(port);
2499 s->port.ops->stop_tx(port);
2500 s->ops->shutdown_complete(port);
2501 uart_port_unlock_irqrestore(port, flags);
2502
2503#ifdef CONFIG_SERIAL_SH_SCI_DMA
2504 if (s->chan_rx_saved) {
2505 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
2506 port->line);
2507 hrtimer_cancel(&s->rx_timer);
2508 }
2509#endif
2510
2511 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0)
2512 timer_delete_sync(&s->rx_fifo_timer);
2513 sci_free_irq(s);
2514 sci_free_dma(port);
2515}
2516EXPORT_SYMBOL_NS_GPL(sci_shutdown, "SH_SCI");
2517
2518static int sci_sck_calc(struct sci_port *s, unsigned int bps,
2519 unsigned int *srr)
2520{
2521 unsigned long freq = s->clk_rates[SCI_SCK];
2522 int err, min_err = INT_MAX;
2523 unsigned int sr;
2524
2525 if (s->type != PORT_HSCIF)
2526 freq *= 2;
2527
2528 for_each_sr(sr, s) {
2529 err = DIV_ROUND_CLOSEST(freq, sr) - bps;
2530 if (abs(err) >= abs(min_err))
2531 continue;
2532
2533 min_err = err;
2534 *srr = sr - 1;
2535
2536 if (!err)
2537 break;
2538 }
2539
2540 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err,
2541 *srr + 1);
2542 return min_err;
2543}
2544
2545static int sci_brg_calc(struct sci_port *s, unsigned int bps,
2546 unsigned long freq, unsigned int *dlr,
2547 unsigned int *srr)
2548{
2549 int err, min_err = INT_MAX;
2550 unsigned int sr, dl;
2551
2552 if (s->type != PORT_HSCIF)
2553 freq *= 2;
2554
2555 for_each_sr(sr, s) {
2556 dl = DIV_ROUND_CLOSEST(freq, sr * bps);
2557 dl = clamp(dl, 1U, 65535U);
2558
2559 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps;
2560 if (abs(err) >= abs(min_err))
2561 continue;
2562
2563 min_err = err;
2564 *dlr = dl;
2565 *srr = sr - 1;
2566
2567 if (!err)
2568 break;
2569 }
2570
2571 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps,
2572 min_err, *dlr, *srr + 1);
2573 return min_err;
2574}
2575
2576/* calculate sample rate, BRR, and clock select */
2577int sci_scbrr_calc(struct sci_port *s, unsigned int bps, unsigned int *brr,
2578 unsigned int *srr, unsigned int *cks)
2579{
2580 unsigned long freq = s->clk_rates[SCI_FCK];
2581 unsigned int sr, br, prediv, scrate, c;
2582 int err, min_err = INT_MAX;
2583
2584 if (s->type != PORT_HSCIF)
2585 freq *= 2;
2586
2587 /*
2588 * Find the combination of sample rate and clock select with the
2589 * smallest deviation from the desired baud rate.
2590 * Prefer high sample rates to maximise the receive margin.
2591 *
2592 * M: Receive margin (%)
2593 * N: Ratio of bit rate to clock (N = sampling rate)
2594 * D: Clock duty (D = 0 to 1.0)
2595 * L: Frame length (L = 9 to 12)
2596 * F: Absolute value of clock frequency deviation
2597 *
2598 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
2599 * (|D - 0.5| / N * (1 + F))|
2600 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation.
2601 */
2602 for_each_sr(sr, s) {
2603 for (c = 0; c <= 3; c++) {
2604 /* integerized formulas from HSCIF documentation */
2605 prediv = sr << (2 * c + 1);
2606
2607 /*
2608 * We need to calculate:
2609 *
2610 * br = freq / (prediv * bps) clamped to [1..256]
2611 * err = freq / (br * prediv) - bps
2612 *
2613 * Watch out for overflow when calculating the desired
2614 * sampling clock rate!
2615 */
2616 if (bps > UINT_MAX / prediv)
2617 break;
2618
2619 scrate = prediv * bps;
2620 br = DIV_ROUND_CLOSEST(freq, scrate);
2621 br = clamp(br, 1U, 256U);
2622
2623 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
2624 if (abs(err) >= abs(min_err))
2625 continue;
2626
2627 min_err = err;
2628 *brr = br - 1;
2629 *srr = sr - 1;
2630 *cks = c;
2631
2632 if (!err)
2633 goto found;
2634 }
2635 }
2636
2637found:
2638 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
2639 min_err, *brr, *srr + 1, *cks);
2640 return min_err;
2641}
2642EXPORT_SYMBOL_NS_GPL(sci_scbrr_calc, "SH_SCI");
2643
2644static void sci_reset(struct uart_port *port)
2645{
2646 const struct plat_sci_reg *reg;
2647 unsigned int status;
2648 struct sci_port *s = to_sci_port(port);
2649
2650 sci_serial_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */
2651
2652 reg = sci_getreg(port, SCFCR);
2653 if (reg->size)
2654 sci_serial_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
2655
2656 s->ops->clear_SCxSR(port,
2657 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) &
2658 SCxSR_BREAK_CLEAR(port));
2659 if (sci_getreg(port, SCLSR)->size) {
2660 status = sci_serial_in(port, SCLSR);
2661 status &= ~(SCLSR_TO | SCLSR_ORER);
2662 sci_serial_out(port, SCLSR, status);
2663 }
2664
2665 if (s->rx_trigger > 1) {
2666 if (s->rx_fifo_timeout) {
2667 s->ops->set_rtrg(port, 1);
2668 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0);
2669 } else {
2670 if (s->type == PORT_SCIFA ||
2671 s->type == PORT_SCIFB)
2672 s->ops->set_rtrg(port, 1);
2673 else
2674 s->ops->set_rtrg(port, s->rx_trigger);
2675 }
2676 }
2677}
2678
2679static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
2680 const struct ktermios *old)
2681{
2682 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits;
2683 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0;
2684 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0;
2685 struct sci_port *s = to_sci_port(port);
2686 const struct plat_sci_reg *reg;
2687 int min_err = INT_MAX, err;
2688 unsigned long max_freq = 0;
2689 int best_clk = -1;
2690 unsigned long flags;
2691
2692 if ((termios->c_cflag & CSIZE) == CS7) {
2693 smr_val |= SCSMR_CHR;
2694 } else {
2695 termios->c_cflag &= ~CSIZE;
2696 termios->c_cflag |= CS8;
2697 }
2698 if (termios->c_cflag & PARENB)
2699 smr_val |= SCSMR_PE;
2700 if (termios->c_cflag & PARODD)
2701 smr_val |= SCSMR_PE | SCSMR_ODD;
2702 if (termios->c_cflag & CSTOPB)
2703 smr_val |= SCSMR_STOP;
2704
2705 /*
2706 * earlyprintk comes here early on with port->uartclk set to zero.
2707 * the clock framework is not up and running at this point so here
2708 * we assume that 115200 is the maximum baud rate. please note that
2709 * the baud rate is not programmed during earlyprintk - it is assumed
2710 * that the previous boot loader has enabled required clocks and
2711 * setup the baud rate generator hardware for us already.
2712 */
2713 if (!port->uartclk) {
2714 baud = uart_get_baud_rate(port, termios, old, 0, 115200);
2715 goto done;
2716 }
2717
2718 for (i = 0; i < SCI_NUM_CLKS; i++)
2719 max_freq = max(max_freq, s->clk_rates[i]);
2720
2721 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s));
2722
2723 /*
2724 * There can be multiple sources for the sampling clock. Find the one
2725 * that gives us the smallest deviation from the desired baud rate.
2726 */
2727
2728 /* Optional Undivided External Clock */
2729 if (s->clk_rates[SCI_SCK] && s->type != PORT_SCIFA &&
2730 s->type != PORT_SCIFB) {
2731 err = sci_sck_calc(s, baud, &srr1);
2732 if (abs(err) < abs(min_err)) {
2733 best_clk = SCI_SCK;
2734 scr_val = SCSCR_CKE1;
2735 sccks = SCCKS_CKS;
2736 min_err = err;
2737 srr = srr1;
2738 if (!err)
2739 goto done;
2740 }
2741 }
2742
2743 /* Optional BRG Frequency Divided External Clock */
2744 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
2745 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1,
2746 &srr1);
2747 if (abs(err) < abs(min_err)) {
2748 best_clk = SCI_SCIF_CLK;
2749 scr_val = SCSCR_CKE1;
2750 sccks = 0;
2751 min_err = err;
2752 dl = dl1;
2753 srr = srr1;
2754 if (!err)
2755 goto done;
2756 }
2757 }
2758
2759 /* Optional BRG Frequency Divided Internal Clock */
2760 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {
2761 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1,
2762 &srr1);
2763 if (abs(err) < abs(min_err)) {
2764 best_clk = SCI_BRG_INT;
2765 scr_val = SCSCR_CKE1;
2766 sccks = SCCKS_XIN;
2767 min_err = err;
2768 dl = dl1;
2769 srr = srr1;
2770 if (!min_err)
2771 goto done;
2772 }
2773 }
2774
2775 /* Divided Functional Clock using standard Bit Rate Register */
2776 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
2777 if (abs(err) < abs(min_err)) {
2778 best_clk = SCI_FCK;
2779 scr_val = 0;
2780 min_err = err;
2781 brr = brr1;
2782 srr = srr1;
2783 cks = cks1;
2784 }
2785
2786done:
2787 if (best_clk >= 0)
2788 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
2789 s->clks[best_clk], baud, min_err);
2790
2791 sci_port_enable(s);
2792
2793 /*
2794 * Program the optional External Baud Rate Generator (BRG) first.
2795 * It controls the mux to select (H)SCK or frequency divided clock.
2796 */
2797 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
2798 sci_serial_out(port, SCDL, dl);
2799 sci_serial_out(port, SCCKS, sccks);
2800 }
2801
2802 uart_port_lock_irqsave(port, &flags);
2803
2804 sci_reset(port);
2805
2806 uart_update_timeout(port, termios->c_cflag, baud);
2807
2808 /* byte size and parity */
2809 bits = tty_get_frame_size(termios->c_cflag);
2810
2811 if (sci_getreg(port, SEMR)->size)
2812 sci_serial_out(port, SEMR, 0);
2813
2814 if (best_clk >= 0) {
2815 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB)
2816 switch (srr + 1) {
2817 case 5: smr_val |= SCSMR_SRC_5; break;
2818 case 7: smr_val |= SCSMR_SRC_7; break;
2819 case 11: smr_val |= SCSMR_SRC_11; break;
2820 case 13: smr_val |= SCSMR_SRC_13; break;
2821 case 16: smr_val |= SCSMR_SRC_16; break;
2822 case 17: smr_val |= SCSMR_SRC_17; break;
2823 case 19: smr_val |= SCSMR_SRC_19; break;
2824 case 27: smr_val |= SCSMR_SRC_27; break;
2825 }
2826 smr_val |= cks;
2827 sci_serial_out(port, SCSCR, scr_val | s->hscif_tot);
2828 sci_serial_out(port, SCSMR, smr_val);
2829 sci_serial_out(port, SCBRR, brr);
2830 if (sci_getreg(port, HSSRR)->size) {
2831 unsigned int hssrr = srr | HSCIF_SRE;
2832 /* Calculate deviation from intended rate at the
2833 * center of the last stop bit in sampling clocks.
2834 */
2835 int last_stop = bits * 2 - 1;
2836 int deviation = DIV_ROUND_CLOSEST(min_err * last_stop *
2837 (int)(srr + 1),
2838 2 * (int)baud);
2839
2840 if (abs(deviation) >= 2) {
2841 /* At least two sampling clocks off at the
2842 * last stop bit; we can increase the error
2843 * margin by shifting the sampling point.
2844 */
2845 int shift = clamp(deviation / 2, -8, 7);
2846
2847 hssrr |= (shift << HSCIF_SRHP_SHIFT) &
2848 HSCIF_SRHP_MASK;
2849 hssrr |= HSCIF_SRDE;
2850 }
2851 sci_serial_out(port, HSSRR, hssrr);
2852 }
2853
2854 /* Wait one bit interval */
2855 udelay((1000000 + (baud - 1)) / baud);
2856 } else {
2857 /* Don't touch the bit rate configuration */
2858 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
2859 smr_val |= sci_serial_in(port, SCSMR) &
2860 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS);
2861 sci_serial_out(port, SCSCR, scr_val | s->hscif_tot);
2862 sci_serial_out(port, SCSMR, smr_val);
2863 }
2864
2865 sci_init_pins(port, termios->c_cflag);
2866
2867 port->status &= ~UPSTAT_AUTOCTS;
2868 s->autorts = false;
2869 reg = sci_getreg(port, SCFCR);
2870 if (reg->size) {
2871 unsigned short ctrl = sci_serial_in(port, SCFCR);
2872
2873 if ((port->flags & UPF_HARD_FLOW) &&
2874 (termios->c_cflag & CRTSCTS)) {
2875 /* There is no CTS interrupt to restart the hardware */
2876 port->status |= UPSTAT_AUTOCTS;
2877 /* MCE is enabled when RTS is raised */
2878 s->autorts = true;
2879 }
2880
2881 /*
2882 * As we've done a sci_reset() above, ensure we don't
2883 * interfere with the FIFOs while toggling MCE. As the
2884 * reset values could still be set, simply mask them out.
2885 */
2886 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2887
2888 sci_serial_out(port, SCFCR, ctrl);
2889 }
2890 if (port->flags & UPF_HARD_FLOW) {
2891 /* Refresh (Auto) RTS */
2892 sci_set_mctrl(port, port->mctrl);
2893 }
2894
2895 /*
2896 * For SCI, TE (transmit enable) must be set after setting TIE
2897 * (transmit interrupt enable) or in the same instruction to
2898 * start the transmitting process. So skip setting TE here for SCI.
2899 */
2900 if (s->type != PORT_SCI)
2901 scr_val |= SCSCR_TE;
2902 scr_val |= SCSCR_RE | (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0));
2903 sci_serial_out(port, SCSCR, scr_val | s->hscif_tot);
2904 if ((srr + 1 == 5) &&
2905 (s->type == PORT_SCIFA || s->type == PORT_SCIFB)) {
2906 /*
2907 * In asynchronous mode, when the sampling rate is 1/5, first
2908 * received data may become invalid on some SCIFA and SCIFB.
2909 * To avoid this problem wait more than 1 serial data time (1
2910 * bit time x serial data number) after setting SCSCR.RE = 1.
2911 */
2912 udelay(DIV_ROUND_UP(10 * 1000000, baud));
2913 }
2914
2915 /* Calculate delay for 2 DMA buffers (4 FIFO). */
2916 s->rx_frame = (10000 * bits) / (baud / 100);
2917#ifdef CONFIG_SERIAL_SH_SCI_DMA
2918 s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame;
2919#endif
2920
2921 if ((termios->c_cflag & CREAD) != 0)
2922 sci_start_rx(port);
2923
2924 uart_port_unlock_irqrestore(port, flags);
2925
2926 sci_port_disable(s);
2927
2928 if (UART_ENABLE_MS(port, termios->c_cflag))
2929 sci_enable_ms(port);
2930}
2931
2932void sci_pm(struct uart_port *port, unsigned int state,
2933 unsigned int oldstate)
2934{
2935 struct sci_port *sci_port = to_sci_port(port);
2936
2937 switch (state) {
2938 case UART_PM_STATE_OFF:
2939 sci_port_disable(sci_port);
2940 break;
2941 default:
2942 sci_port_enable(sci_port);
2943 break;
2944 }
2945}
2946EXPORT_SYMBOL_NS_GPL(sci_pm, "SH_SCI");
2947
2948static const char *sci_type(struct uart_port *port)
2949{
2950 struct sci_port *s = to_sci_port(port);
2951
2952 switch (s->type) {
2953 case PORT_IRDA:
2954 return "irda";
2955 case PORT_SCI:
2956 return "sci";
2957 case PORT_SCIF:
2958 return "scif";
2959 case PORT_SCIFA:
2960 return "scifa";
2961 case PORT_SCIFB:
2962 return "scifb";
2963 case PORT_HSCIF:
2964 return "hscif";
2965 }
2966
2967 return NULL;
2968}
2969
2970static int sci_remap_port(struct uart_port *port)
2971{
2972 struct sci_port *sport = to_sci_port(port);
2973
2974 /*
2975 * Nothing to do if there's already an established membase.
2976 */
2977 if (port->membase)
2978 return 0;
2979
2980 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2981 port->membase = ioremap(port->mapbase, sport->reg_size);
2982 if (unlikely(!port->membase)) {
2983 dev_err(port->dev, "can't remap port#%d\n", port->line);
2984 return -ENXIO;
2985 }
2986 } else {
2987 /*
2988 * For the simple (and majority of) cases where we don't
2989 * need to do any remapping, just cast the cookie
2990 * directly.
2991 */
2992 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2993 }
2994
2995 return 0;
2996}
2997
2998void sci_release_port(struct uart_port *port)
2999{
3000 struct sci_port *sport = to_sci_port(port);
3001
3002 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
3003 iounmap(port->membase);
3004 port->membase = NULL;
3005 }
3006
3007 release_mem_region(port->mapbase, sport->reg_size);
3008}
3009EXPORT_SYMBOL_NS_GPL(sci_release_port, "SH_SCI");
3010
3011int sci_request_port(struct uart_port *port)
3012{
3013 struct resource *res;
3014 struct sci_port *sport = to_sci_port(port);
3015 int ret;
3016
3017 res = request_mem_region(port->mapbase, sport->reg_size,
3018 dev_name(port->dev));
3019 if (unlikely(res == NULL)) {
3020 dev_err(port->dev, "request_mem_region failed.");
3021 return -EBUSY;
3022 }
3023
3024 ret = sci_remap_port(port);
3025 if (unlikely(ret != 0)) {
3026 release_mem_region(port->mapbase, sport->reg_size);
3027 return ret;
3028 }
3029
3030 return 0;
3031}
3032EXPORT_SYMBOL_NS_GPL(sci_request_port, "SH_SCI");
3033
3034void sci_config_port(struct uart_port *port, int flags)
3035{
3036 if (flags & UART_CONFIG_TYPE) {
3037 struct sci_port *sport = to_sci_port(port);
3038 port->type = SCI_PUBLIC_PORT_ID(sport->type);
3039 sci_request_port(port);
3040 }
3041}
3042EXPORT_SYMBOL_NS_GPL(sci_config_port, "SH_SCI");
3043
3044int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
3045{
3046 if (ser->baud_base < 2400)
3047 /* No paper tape reader for Mitch.. */
3048 return -EINVAL;
3049
3050 return 0;
3051}
3052EXPORT_SYMBOL_NS_GPL(sci_verify_port, "SH_SCI");
3053
3054static void sci_prepare_console_write(struct uart_port *port, u32 ctrl)
3055{
3056 struct sci_port *s = to_sci_port(port);
3057 u32 ctrl_temp =
3058 s->params->param_bits->rxtx_enable |
3059 (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
3060 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0)) |
3061 s->hscif_tot;
3062 sci_serial_out(port, SCSCR, ctrl_temp);
3063}
3064
3065static void sci_console_save(struct uart_port *port)
3066{
3067 struct sci_port *s = to_sci_port(port);
3068 struct sci_suspend_regs *regs = s->suspend_regs;
3069
3070 if (sci_getreg(port, SCDL)->size)
3071 regs->scdl = sci_serial_in(port, SCDL);
3072 if (sci_getreg(port, SCCKS)->size)
3073 regs->sccks = sci_serial_in(port, SCCKS);
3074 if (sci_getreg(port, SCSMR)->size)
3075 regs->scsmr = sci_serial_in(port, SCSMR);
3076 if (sci_getreg(port, SCSCR)->size)
3077 regs->scscr = sci_serial_in(port, SCSCR);
3078 if (sci_getreg(port, SCFCR)->size)
3079 regs->scfcr = sci_serial_in(port, SCFCR);
3080 if (sci_getreg(port, SCSPTR)->size)
3081 regs->scsptr = sci_serial_in(port, SCSPTR);
3082 if (sci_getreg(port, SCBRR)->size)
3083 regs->scbrr = sci_serial_in(port, SCBRR);
3084 if (sci_getreg(port, HSSRR)->size)
3085 regs->hssrr = sci_serial_in(port, HSSRR);
3086 if (sci_getreg(port, SCPCR)->size)
3087 regs->scpcr = sci_serial_in(port, SCPCR);
3088 if (sci_getreg(port, SCPDR)->size)
3089 regs->scpdr = sci_serial_in(port, SCPDR);
3090 if (sci_getreg(port, SEMR)->size)
3091 regs->semr = sci_serial_in(port, SEMR);
3092}
3093
3094static void sci_console_restore(struct uart_port *port)
3095{
3096 struct sci_port *s = to_sci_port(port);
3097 struct sci_suspend_regs *regs = s->suspend_regs;
3098
3099 if (sci_getreg(port, SCDL)->size)
3100 sci_serial_out(port, SCDL, regs->scdl);
3101 if (sci_getreg(port, SCCKS)->size)
3102 sci_serial_out(port, SCCKS, regs->sccks);
3103 if (sci_getreg(port, SCSMR)->size)
3104 sci_serial_out(port, SCSMR, regs->scsmr);
3105 if (sci_getreg(port, SCSCR)->size)
3106 sci_serial_out(port, SCSCR, regs->scscr);
3107 if (sci_getreg(port, SCFCR)->size)
3108 sci_serial_out(port, SCFCR, regs->scfcr);
3109 if (sci_getreg(port, SCSPTR)->size)
3110 sci_serial_out(port, SCSPTR, regs->scsptr);
3111 if (sci_getreg(port, SCBRR)->size)
3112 sci_serial_out(port, SCBRR, regs->scbrr);
3113 if (sci_getreg(port, HSSRR)->size)
3114 sci_serial_out(port, HSSRR, regs->hssrr);
3115 if (sci_getreg(port, SCPCR)->size)
3116 sci_serial_out(port, SCPCR, regs->scpcr);
3117 if (sci_getreg(port, SCPDR)->size)
3118 sci_serial_out(port, SCPDR, regs->scpdr);
3119 if (sci_getreg(port, SEMR)->size)
3120 sci_serial_out(port, SEMR, regs->semr);
3121}
3122
3123static const struct uart_ops sci_uart_ops = {
3124 .tx_empty = sci_tx_empty,
3125 .set_mctrl = sci_set_mctrl,
3126 .get_mctrl = sci_get_mctrl,
3127 .start_tx = sci_start_tx,
3128 .stop_tx = sci_stop_tx,
3129 .stop_rx = sci_stop_rx,
3130 .enable_ms = sci_enable_ms,
3131 .break_ctl = sci_break_ctl,
3132 .startup = sci_startup,
3133 .shutdown = sci_shutdown,
3134 .flush_buffer = sci_flush_buffer,
3135 .set_termios = sci_set_termios,
3136 .pm = sci_pm,
3137 .type = sci_type,
3138 .release_port = sci_release_port,
3139 .request_port = sci_request_port,
3140 .config_port = sci_config_port,
3141 .verify_port = sci_verify_port,
3142#ifdef CONFIG_CONSOLE_POLL
3143 .poll_get_char = sci_poll_get_char,
3144 .poll_put_char = sci_poll_put_char,
3145#endif
3146};
3147
3148static const struct sci_port_ops sci_port_ops = {
3149 .read_reg = sci_serial_in,
3150 .write_reg = sci_serial_out,
3151 .clear_SCxSR = sci_clear_SCxSR,
3152 .transmit_chars = sci_transmit_chars,
3153 .receive_chars = sci_receive_chars,
3154#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
3155 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
3156 .poll_put_char = sci_poll_put_char,
3157#endif
3158 .set_rtrg = scif_set_rtrg,
3159 .rtrg_enabled = scif_rtrg_enabled,
3160 .shutdown_complete = sci_shutdown_complete,
3161 .prepare_console_write = sci_prepare_console_write,
3162 .console_save = sci_console_save,
3163 .console_restore = sci_console_restore,
3164 .suspend_regs_size = sci_suspend_regs_size,
3165};
3166
3167static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
3168{
3169 const char *clk_names[] = {
3170 [SCI_FCK] = "fck",
3171 [SCI_SCK] = "sck",
3172 [SCI_BRG_INT] = "brg_int",
3173 [SCI_SCIF_CLK] = "scif_clk",
3174 [SCI_FCK_DIV4] = "tclk_div4",
3175 [SCI_FCK_DIV16] = "tclk_div16",
3176 [SCI_FCK_DIV64] = "tclk_div64",
3177 };
3178 struct clk *clk;
3179 unsigned int i;
3180
3181 if (sci_port->type == PORT_HSCIF) {
3182 clk_names[SCI_SCK] = "hsck";
3183 } else if (sci_port->type == RSCI_PORT_SCIF16 ||
3184 sci_port->type == RSCI_PORT_SCIF32_SINGLE_TCLK) {
3185 clk_names[SCI_FCK] = "operation";
3186 clk_names[SCI_BRG_INT] = "bus";
3187 } else if (sci_port->type == RSCI_PORT_SCIF32) {
3188 clk_names[SCI_FCK] = "tclk";
3189 clk_names[SCI_BRG_INT] = "pclk";
3190 }
3191
3192 for (i = 0; i < SCI_NUM_CLKS; i++) {
3193 const char *name = clk_names[i];
3194
3195 clk = devm_clk_get_optional(dev, name);
3196 if (IS_ERR(clk))
3197 return PTR_ERR(clk);
3198
3199 if (!clk && (sci_port->type == RSCI_PORT_SCIF16 ||
3200 sci_port->type == RSCI_PORT_SCIF32_SINGLE_TCLK) &&
3201 (i == SCI_FCK || i == SCI_BRG_INT))
3202 return dev_err_probe(dev, -ENODEV, "failed to get %s\n", name);
3203
3204 if (!clk && sci_port->type == RSCI_PORT_SCIF32 &&
3205 (i != SCI_SCK && i != SCI_SCIF_CLK))
3206 return dev_err_probe(dev, -ENODEV, "failed to get %s\n", name);
3207
3208 if (!clk && i == SCI_FCK) {
3209 /*
3210 * Not all SH platforms declare a clock lookup entry
3211 * for SCI devices, in which case we need to get the
3212 * global "peripheral_clk" clock.
3213 */
3214 clk = devm_clk_get(dev, "peripheral_clk");
3215 if (IS_ERR(clk))
3216 return dev_err_probe(dev, PTR_ERR(clk), "failed to get %s\n", name);
3217 }
3218
3219 if (!clk)
3220 dev_dbg(dev, "failed to get %s\n", name);
3221 else
3222 dev_dbg(dev, "clk %s is %pC rate %lu\n", name, clk, clk_get_rate(clk));
3223 sci_port->clks[i] = clk;
3224 }
3225 return 0;
3226}
3227
3228static const struct sci_port_params *
3229sci_probe_regmap(const struct plat_sci_port *cfg, struct sci_port *sci_port)
3230{
3231 unsigned int regtype;
3232
3233 sci_port->ops = &sci_port_ops;
3234 sci_port->port.ops = &sci_uart_ops;
3235
3236 if (cfg->regtype != SCIx_PROBE_REGTYPE)
3237 return &sci_port_params[cfg->regtype];
3238
3239 switch (cfg->type) {
3240 case PORT_SCI:
3241 regtype = SCIx_SCI_REGTYPE;
3242 break;
3243 case PORT_IRDA:
3244 regtype = SCIx_IRDA_REGTYPE;
3245 break;
3246 case PORT_SCIFA:
3247 regtype = SCIx_SCIFA_REGTYPE;
3248 break;
3249 case PORT_SCIFB:
3250 regtype = SCIx_SCIFB_REGTYPE;
3251 break;
3252 case PORT_SCIF:
3253 /*
3254 * The SH-4 is a bit of a misnomer here, although that's
3255 * where this particular port layout originated. This
3256 * configuration (or some slight variation thereof)
3257 * remains the dominant model for all SCIFs.
3258 */
3259 regtype = SCIx_SH4_SCIF_REGTYPE;
3260 break;
3261 case PORT_HSCIF:
3262 regtype = SCIx_HSCIF_REGTYPE;
3263 break;
3264 default:
3265 pr_err("Can't probe register map for given port\n");
3266 return NULL;
3267 }
3268
3269 return &sci_port_params[regtype];
3270}
3271
3272static int sci_init_single(struct platform_device *dev,
3273 struct sci_port *sci_port, unsigned int index,
3274 const struct plat_sci_port *p, bool early)
3275{
3276 struct uart_port *port = &sci_port->port;
3277 const struct resource *res;
3278 unsigned int i;
3279 int ret;
3280
3281 sci_port->cfg = p;
3282
3283 sci_port->type = p->type;
3284 sci_port->regtype = p->regtype;
3285
3286 port->iotype = UPIO_MEM;
3287 port->line = index;
3288 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_SH_SCI_CONSOLE);
3289
3290 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
3291 if (res == NULL)
3292 return -ENOMEM;
3293
3294 port->mapbase = res->start;
3295 sci_port->reg_size = resource_size(res);
3296
3297 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) {
3298 if (i)
3299 sci_port->irqs[i] = platform_get_irq_optional(dev, i);
3300 else
3301 sci_port->irqs[i] = platform_get_irq(dev, i);
3302 }
3303
3304 /*
3305 * The fourth interrupt on SCI and RSCI port is transmit end interrupt, so
3306 * shuffle the interrupts.
3307 */
3308 if (p->type == PORT_SCI || sci_is_rsci_type(p->type))
3309 swap(sci_port->irqs[SCIx_BRI_IRQ], sci_port->irqs[SCIx_TEI_IRQ]);
3310
3311 /* The SCI generates several interrupts. They can be muxed together or
3312 * connected to different interrupt lines. In the muxed case only one
3313 * interrupt resource is specified as there is only one interrupt ID.
3314 * In the non-muxed case, up to 6 interrupt signals might be generated
3315 * from the SCI, however those signals might have their own individual
3316 * interrupt ID numbers, or muxed together with another interrupt.
3317 */
3318 if (sci_port->irqs[0] < 0)
3319 return -ENXIO;
3320
3321 if (sci_port->irqs[1] < 0)
3322 for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++)
3323 sci_port->irqs[i] = sci_port->irqs[0];
3324
3325 switch (p->type) {
3326 case PORT_SCIFB:
3327 sci_port->rx_trigger = 48;
3328 break;
3329 case PORT_HSCIF:
3330 sci_port->rx_trigger = 64;
3331 break;
3332 case PORT_SCIFA:
3333 case RSCI_PORT_SCIF32:
3334 case RSCI_PORT_SCIF32_SINGLE_TCLK:
3335 sci_port->rx_trigger = 32;
3336 break;
3337 case PORT_SCIF:
3338 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE)
3339 /* RX triggering not implemented for this IP */
3340 sci_port->rx_trigger = 1;
3341 else
3342 sci_port->rx_trigger = 8;
3343 break;
3344 case RSCI_PORT_SCIF16:
3345 sci_port->rx_trigger = 16;
3346 break;
3347 default:
3348 sci_port->rx_trigger = 1;
3349 break;
3350 }
3351
3352 sci_port->rx_fifo_timeout = 0;
3353 sci_port->hscif_tot = 0;
3354
3355 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
3356 * match the SoC datasheet, this should be investigated. Let platform
3357 * data override the sampling rate for now.
3358 */
3359 sci_port->sampling_rate_mask = p->sampling_rate
3360 ? SCI_SR(p->sampling_rate)
3361 : sci_port->params->sampling_rate_mask;
3362
3363 if (!early) {
3364 ret = sci_init_clocks(sci_port, &dev->dev);
3365 if (ret < 0)
3366 return ret;
3367 }
3368
3369 port->type = SCI_PUBLIC_PORT_ID(p->type);
3370 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF;
3371 port->fifosize = sci_port->params->fifosize;
3372
3373 if (p->type == PORT_SCI && !dev->dev.of_node) {
3374 if (sci_port->reg_size >= 0x20)
3375 port->regshift = 2;
3376 else
3377 port->regshift = 1;
3378 }
3379
3380 /*
3381 * The UART port needs an IRQ value, so we peg this to the RX IRQ
3382 * for the multi-IRQ ports, which is where we are primarily
3383 * concerned with the shutdown path synchronization.
3384 *
3385 * For the muxed case there's nothing more to do.
3386 */
3387 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
3388 port->irqflags = 0;
3389
3390 return 0;
3391}
3392
3393#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
3394 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
3395static void serial_console_putchar(struct uart_port *port, unsigned char ch)
3396{
3397 to_sci_port(port)->ops->poll_put_char(port, ch);
3398}
3399
3400/*
3401 * Print a string to the serial port trying not to disturb
3402 * any possible real use of the port...
3403 */
3404static void serial_console_write(struct console *co, const char *s,
3405 unsigned count)
3406{
3407 struct sci_port *sci_port = &sci_ports[co->index];
3408 struct uart_port *port = &sci_port->port;
3409 const struct sci_common_regs *regs = sci_port->params->common_regs;
3410 unsigned int bits;
3411 u32 ctrl;
3412 unsigned long flags;
3413 int locked = 1;
3414
3415 if (port->sysrq)
3416 locked = 0;
3417 else if (oops_in_progress)
3418 locked = uart_port_trylock_irqsave(port, &flags);
3419 else
3420 uart_port_lock_irqsave(port, &flags);
3421
3422 /* first save SCSCR then disable interrupts, keep clock source */
3423
3424 ctrl = sci_port->ops->read_reg(port, regs->control);
3425 sci_port->ops->prepare_console_write(port, ctrl);
3426
3427 uart_console_write(port, s, count, serial_console_putchar);
3428
3429 /* wait until fifo is empty and last bit has been transmitted */
3430
3431 bits = sci_port->params->param_bits->poll_sent_bits;
3432
3433 while ((sci_port->ops->read_reg(port, regs->status) & bits) != bits)
3434 cpu_relax();
3435
3436 /* restore the SCSCR */
3437 if (sci_port->ops->finish_console_write)
3438 sci_port->ops->finish_console_write(port, ctrl);
3439 else
3440 sci_port->ops->write_reg(port, regs->control, ctrl);
3441
3442 if (locked)
3443 uart_port_unlock_irqrestore(port, flags);
3444}
3445
3446static int serial_console_setup(struct console *co, char *options)
3447{
3448 struct sci_port *sci_port;
3449 struct uart_port *port;
3450 int baud = 115200;
3451 int bits = 8;
3452 int parity = 'n';
3453 int flow = 'n';
3454 int ret;
3455
3456 /*
3457 * Refuse to handle any bogus ports.
3458 */
3459 if (co->index < 0 || co->index >= SCI_NPORTS)
3460 return -ENODEV;
3461
3462 sci_port = &sci_ports[co->index];
3463 port = &sci_port->port;
3464
3465 /*
3466 * Refuse to handle uninitialized ports.
3467 */
3468 if (!port->ops)
3469 return -ENODEV;
3470
3471 ret = sci_remap_port(port);
3472 if (unlikely(ret != 0))
3473 return ret;
3474
3475 if (options)
3476 uart_parse_options(options, &baud, &parity, &bits, &flow);
3477
3478 return uart_set_options(port, co, baud, parity, bits, flow);
3479}
3480
3481static struct console serial_console = {
3482 .name = "ttySC",
3483 .device = uart_console_device,
3484 .write = serial_console_write,
3485 .setup = serial_console_setup,
3486 .flags = CON_PRINTBUFFER,
3487 .index = -1,
3488 .data = &sci_uart_driver,
3489};
3490
3491#ifdef CONFIG_SUPERH
3492static char early_serial_buf[32];
3493
3494static int early_serial_console_setup(struct console *co, char *options)
3495{
3496 /*
3497 * This early console is always registered using the earlyprintk=
3498 * parameter, which does not call add_preferred_console(). Thus
3499 * @options is always NULL and the options for this early console
3500 * are passed using a custom buffer.
3501 */
3502 WARN_ON(options);
3503
3504 return serial_console_setup(co, early_serial_buf);
3505}
3506
3507static struct console early_serial_console = {
3508 .name = "early_ttySC",
3509 .write = serial_console_write,
3510 .setup = early_serial_console_setup,
3511 .flags = CON_PRINTBUFFER,
3512 .index = -1,
3513};
3514
3515static int sci_probe_earlyprintk(struct platform_device *pdev)
3516{
3517 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
3518 struct sci_port *sp = &sci_ports[pdev->id];
3519
3520 if (early_serial_console.data)
3521 return -EEXIST;
3522
3523 early_serial_console.index = pdev->id;
3524
3525 sp->params = sci_probe_regmap(cfg, sp);
3526 if (!sp->params)
3527 return -ENODEV;
3528
3529 sci_init_single(pdev, sp, pdev->id, cfg, true);
3530
3531 if (!strstr(early_serial_buf, "keep"))
3532 early_serial_console.flags |= CON_BOOT;
3533
3534 register_console(&early_serial_console);
3535 return 0;
3536}
3537#endif
3538
3539#define SCI_CONSOLE (&serial_console)
3540
3541#else
3542static inline int sci_probe_earlyprintk(struct platform_device *pdev)
3543{
3544 return -EINVAL;
3545}
3546
3547#define SCI_CONSOLE NULL
3548
3549#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */
3550
3551static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
3552
3553static DEFINE_MUTEX(sci_uart_registration_lock);
3554static struct uart_driver sci_uart_driver = {
3555 .owner = THIS_MODULE,
3556 .driver_name = "sci",
3557 .dev_name = "ttySC",
3558 .major = SCI_MAJOR,
3559 .minor = SCI_MINOR_START,
3560 .nr = SCI_NPORTS,
3561 .cons = SCI_CONSOLE,
3562};
3563
3564static void sci_remove(struct platform_device *dev)
3565{
3566 struct sci_port *s = platform_get_drvdata(dev);
3567
3568 sci_ports_in_use &= ~BIT(s->port.line);
3569 uart_remove_one_port(&sci_uart_driver, &s->port);
3570
3571 if (s->port.fifosize > 1) {
3572 device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger);
3573 device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout);
3574 }
3575}
3576
3577static const struct sci_of_data of_sci_scif_sh2 = {
3578 .type = PORT_SCIF,
3579 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
3580 .ops = &sci_port_ops,
3581 .uart_ops = &sci_uart_ops,
3582 .params = &sci_port_params[SCIx_SH2_SCIF_FIFODATA_REGTYPE],
3583};
3584
3585static const struct sci_of_data of_sci_scif_rz_scifa = {
3586 .type = PORT_SCIF,
3587 .regtype = SCIx_RZ_SCIFA_REGTYPE,
3588 .ops = &sci_port_ops,
3589 .uart_ops = &sci_uart_ops,
3590 .params = &sci_port_params[SCIx_RZ_SCIFA_REGTYPE],
3591};
3592
3593static const struct sci_of_data of_sci_scif_rzv2h = {
3594 .type = PORT_SCIF,
3595 .regtype = SCIx_RZV2H_SCIF_REGTYPE,
3596 .ops = &sci_port_ops,
3597 .uart_ops = &sci_uart_ops,
3598 .params = &sci_port_params[SCIx_RZV2H_SCIF_REGTYPE],
3599};
3600
3601static const struct sci_of_data of_sci_rcar_scif = {
3602 .type = PORT_SCIF,
3603 .regtype = SCIx_SH4_SCIF_BRG_REGTYPE,
3604 .ops = &sci_port_ops,
3605 .uart_ops = &sci_uart_ops,
3606 .params = &sci_port_params[SCIx_SH4_SCIF_BRG_REGTYPE],
3607};
3608
3609static const struct sci_of_data of_sci_scif_sh4 = {
3610 .type = PORT_SCIF,
3611 .regtype = SCIx_SH4_SCIF_REGTYPE,
3612 .ops = &sci_port_ops,
3613 .uart_ops = &sci_uart_ops,
3614 .params = &sci_port_params[SCIx_SH4_SCIF_REGTYPE],
3615};
3616
3617static const struct sci_of_data of_sci_scifa = {
3618 .type = PORT_SCIFA,
3619 .regtype = SCIx_SCIFA_REGTYPE,
3620 .ops = &sci_port_ops,
3621 .uart_ops = &sci_uart_ops,
3622 .params = &sci_port_params[SCIx_SCIFA_REGTYPE],
3623};
3624
3625static const struct sci_of_data of_sci_scifb = {
3626 .type = PORT_SCIFB,
3627 .regtype = SCIx_SCIFB_REGTYPE,
3628 .ops = &sci_port_ops,
3629 .uart_ops = &sci_uart_ops,
3630 .params = &sci_port_params[SCIx_SCIFB_REGTYPE],
3631};
3632
3633static const struct sci_of_data of_sci_hscif = {
3634 .type = PORT_HSCIF,
3635 .regtype = SCIx_HSCIF_REGTYPE,
3636 .ops = &sci_port_ops,
3637 .uart_ops = &sci_uart_ops,
3638 .params = &sci_port_params[SCIx_HSCIF_REGTYPE],
3639};
3640
3641static const struct sci_of_data of_sci_sci = {
3642 .type = PORT_SCI,
3643 .regtype = SCIx_SCI_REGTYPE,
3644 .ops = &sci_port_ops,
3645 .uart_ops = &sci_uart_ops,
3646 .params = &sci_port_params[SCIx_SCI_REGTYPE],
3647};
3648
3649static const struct of_device_id of_sci_match[] __maybe_unused = {
3650 /* SoC-specific types */
3651 {
3652 .compatible = "renesas,scif-r7s72100",
3653 .data = &of_sci_scif_sh2,
3654 },
3655 {
3656 .compatible = "renesas,scif-r7s9210",
3657 .data = &of_sci_scif_rz_scifa,
3658 },
3659 {
3660 .compatible = "renesas,scif-r9a07g044",
3661 .data = &of_sci_scif_rz_scifa,
3662 },
3663 {
3664 .compatible = "renesas,scif-r9a09g057",
3665 .data = &of_sci_scif_rzv2h,
3666 },
3667#ifdef CONFIG_SERIAL_RSCI
3668 {
3669 .compatible = "renesas,r9a08g046-rsci",
3670 .data = &of_rsci_rzg3l_data,
3671 },
3672 {
3673 .compatible = "renesas,r9a09g047-rsci",
3674 .data = &of_rsci_rzg3e_data,
3675 },
3676 {
3677 .compatible = "renesas,r9a09g077-rsci",
3678 .data = &of_rsci_rzt2h_data,
3679 },
3680#endif /* CONFIG_SERIAL_RSCI */
3681 /* Family-specific types */
3682 {
3683 .compatible = "renesas,rcar-gen1-scif",
3684 .data = &of_sci_rcar_scif,
3685 }, {
3686 .compatible = "renesas,rcar-gen2-scif",
3687 .data = &of_sci_rcar_scif,
3688 }, {
3689 .compatible = "renesas,rcar-gen3-scif",
3690 .data = &of_sci_rcar_scif
3691 }, {
3692 .compatible = "renesas,rcar-gen4-scif",
3693 .data = &of_sci_rcar_scif
3694 }, {
3695 .compatible = "renesas,rcar-gen5-scif",
3696 .data = &of_sci_rcar_scif
3697 },
3698 /* Generic types */
3699 {
3700 .compatible = "renesas,scif",
3701 .data = &of_sci_scif_sh4,
3702 }, {
3703 .compatible = "renesas,scifa",
3704 .data = &of_sci_scifa,
3705 }, {
3706 .compatible = "renesas,scifb",
3707 .data = &of_sci_scifb,
3708 }, {
3709 .compatible = "renesas,hscif",
3710 .data = &of_sci_hscif,
3711 }, {
3712 .compatible = "renesas,sci",
3713 .data = &of_sci_sci,
3714 }, {
3715 /* Terminator */
3716 },
3717};
3718MODULE_DEVICE_TABLE(of, of_sci_match);
3719
3720static void sci_reset_control_assert(void *data)
3721{
3722 reset_control_assert(data);
3723}
3724
3725static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
3726 unsigned int *dev_id)
3727{
3728 struct device_node *np = pdev->dev.of_node;
3729 struct reset_control *rstc;
3730 struct plat_sci_port *p;
3731 struct sci_port *sp;
3732 const struct sci_of_data *data;
3733 int id, ret;
3734
3735 if (!IS_ENABLED(CONFIG_OF) || !np)
3736 return ERR_PTR(-EINVAL);
3737
3738 data = of_device_get_match_data(&pdev->dev);
3739
3740 rstc = devm_reset_control_array_get_optional_exclusive(&pdev->dev);
3741 if (IS_ERR(rstc))
3742 return ERR_PTR(dev_err_probe(&pdev->dev, PTR_ERR(rstc),
3743 "failed to get reset ctrl\n"));
3744
3745 ret = reset_control_deassert(rstc);
3746 if (ret) {
3747 dev_err(&pdev->dev, "failed to deassert reset %d\n", ret);
3748 return ERR_PTR(ret);
3749 }
3750
3751 ret = devm_add_action_or_reset(&pdev->dev, sci_reset_control_assert, rstc);
3752 if (ret) {
3753 dev_err(&pdev->dev, "failed to register assert devm action, %d\n",
3754 ret);
3755 return ERR_PTR(ret);
3756 }
3757
3758 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
3759 if (!p)
3760 return ERR_PTR(-ENOMEM);
3761
3762 /* Get the line number from the aliases node. */
3763 id = of_alias_get_id(np, "serial");
3764 if (id < 0 && ~sci_ports_in_use)
3765 id = ffz(sci_ports_in_use);
3766 if (id < 0) {
3767 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
3768 return ERR_PTR(-EINVAL);
3769 }
3770 if (id >= ARRAY_SIZE(sci_ports)) {
3771 dev_err(&pdev->dev, "serial%d out of range\n", id);
3772 return ERR_PTR(-EINVAL);
3773 }
3774
3775 sp = &sci_ports[id];
3776 sp->rstc = rstc;
3777 *dev_id = id;
3778
3779 p->type = data->type;
3780 p->regtype = data->regtype;
3781
3782 sp->ops = data->ops;
3783 sp->port.ops = data->uart_ops;
3784 sp->params = data->params;
3785
3786 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts");
3787
3788 return p;
3789}
3790
3791static int sci_probe_single(struct platform_device *dev,
3792 unsigned int index,
3793 struct plat_sci_port *p,
3794 struct sci_port *sciport,
3795 struct resource *sci_res)
3796{
3797 int ret;
3798
3799 /* Sanity check */
3800 if (unlikely(index >= SCI_NPORTS)) {
3801 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
3802 index+1, SCI_NPORTS);
3803 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
3804 return -EINVAL;
3805 }
3806 BUILD_BUG_ON(SCI_NPORTS > sizeof(sci_ports_in_use) * 8);
3807 if (sci_ports_in_use & BIT(index))
3808 return -EBUSY;
3809
3810 mutex_lock(&sci_uart_registration_lock);
3811 if (!sci_uart_driver.state) {
3812 ret = uart_register_driver(&sci_uart_driver);
3813 if (ret) {
3814 mutex_unlock(&sci_uart_registration_lock);
3815 return ret;
3816 }
3817 }
3818 mutex_unlock(&sci_uart_registration_lock);
3819
3820 ret = sci_init_single(dev, sciport, index, p, false);
3821 if (ret)
3822 return ret;
3823
3824 sciport->port.dev = &dev->dev;
3825 ret = devm_pm_runtime_enable(&dev->dev);
3826 if (ret)
3827 return ret;
3828
3829 sciport->gpios = mctrl_gpio_init(&sciport->port, 0);
3830 if (IS_ERR(sciport->gpios))
3831 return PTR_ERR(sciport->gpios);
3832
3833 if (sciport->has_rtscts) {
3834 if (mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_CTS) ||
3835 mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_RTS)) {
3836 dev_err(&dev->dev, "Conflicting RTS/CTS config\n");
3837 return -EINVAL;
3838 }
3839 sciport->port.flags |= UPF_HARD_FLOW;
3840 }
3841
3842 if (sci_uart_earlycon && sci_ports[0].port.mapbase == sci_res->start) {
3843 /*
3844 * In case:
3845 * - this is the earlycon port (mapped on index 0 in sci_ports[]) and
3846 * - it now maps to an alias other than zero and
3847 * - the earlycon is still alive (e.g., "earlycon keep_bootcon" is
3848 * available in bootargs)
3849 *
3850 * we need to avoid disabling clocks and PM domains through the runtime
3851 * PM APIs called in __device_attach(). For this, increment the runtime
3852 * PM reference counter (the clocks and PM domains were already enabled
3853 * by the bootloader). Otherwise the earlycon may access the HW when it
3854 * has no clocks enabled leading to failures (infinite loop in
3855 * sci_poll_put_char()).
3856 */
3857 pm_runtime_get_noresume(&dev->dev);
3858
3859 /*
3860 * Skip cleanup the sci_port[0] in early_console_exit(), this
3861 * port is the same as the earlycon one.
3862 */
3863 sci_uart_earlycon_dev_probing = true;
3864 }
3865
3866 return uart_add_one_port(&sci_uart_driver, &sciport->port);
3867}
3868
3869static int sci_probe(struct platform_device *dev)
3870{
3871 struct plat_sci_port *p;
3872 struct resource *res;
3873 struct sci_port *sp;
3874 unsigned int dev_id;
3875 int ret;
3876
3877 /*
3878 * If we've come here via earlyprintk initialization, head off to
3879 * the special early probe. We don't have sufficient device state
3880 * to make it beyond this yet.
3881 */
3882#ifdef CONFIG_SUPERH
3883 if (is_sh_early_platform_device(dev))
3884 return sci_probe_earlyprintk(dev);
3885#endif
3886
3887 if (dev->dev.of_node) {
3888 p = sci_parse_dt(dev, &dev_id);
3889 if (IS_ERR(p))
3890 return PTR_ERR(p);
3891 sp = &sci_ports[dev_id];
3892 } else {
3893 p = dev->dev.platform_data;
3894 if (p == NULL) {
3895 dev_err(&dev->dev, "no platform data supplied\n");
3896 return -EINVAL;
3897 }
3898
3899 dev_id = dev->id;
3900 sp = &sci_ports[dev_id];
3901 sp->params = sci_probe_regmap(p, sp);
3902 if (!sp->params)
3903 return -ENODEV;
3904 }
3905
3906 sp->suspend_regs = devm_kzalloc(&dev->dev,
3907 sp->ops->suspend_regs_size(),
3908 GFP_KERNEL);
3909 if (!sp->suspend_regs)
3910 return -ENOMEM;
3911
3912 /*
3913 * In case:
3914 * - the probed port alias is zero (as the one used by earlycon), and
3915 * - the earlycon is still active (e.g., "earlycon keep_bootcon" in
3916 * bootargs)
3917 *
3918 * defer the probe of this serial. This is a debug scenario and the user
3919 * must be aware of it.
3920 *
3921 * Except when the probed port is the same as the earlycon port.
3922 */
3923
3924 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
3925 if (!res)
3926 return -ENODEV;
3927
3928 if (sci_uart_earlycon && sp == &sci_ports[0] && sp->port.mapbase != res->start)
3929 return dev_err_probe(&dev->dev, -EBUSY, "sci_port[0] is used by earlycon!\n");
3930
3931 platform_set_drvdata(dev, sp);
3932
3933 ret = sci_probe_single(dev, dev_id, p, sp, res);
3934 if (ret)
3935 return ret;
3936
3937 if (sp->port.fifosize > 1) {
3938 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_trigger);
3939 if (ret)
3940 return ret;
3941
3942 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_timeout);
3943 if (ret) {
3944 device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger);
3945 return ret;
3946 }
3947 }
3948
3949#ifdef CONFIG_SH_STANDARD_BIOS
3950 sh_bios_gdb_detach();
3951#endif
3952
3953 sci_ports_in_use |= BIT(dev_id);
3954 return 0;
3955}
3956
3957static int sci_suspend(struct device *dev)
3958{
3959 struct sci_port *sport = dev_get_drvdata(dev);
3960
3961 if (sport) {
3962 uart_suspend_port(&sci_uart_driver, &sport->port);
3963
3964 if (!console_suspend_enabled && uart_console(&sport->port)) {
3965 if (sport->ops->console_save)
3966 sport->ops->console_save(&sport->port);
3967 }
3968 else
3969 return reset_control_assert(sport->rstc);
3970 }
3971
3972 return 0;
3973}
3974
3975static int sci_resume(struct device *dev)
3976{
3977 struct sci_port *sport = dev_get_drvdata(dev);
3978
3979 if (sport) {
3980 if (!console_suspend_enabled && uart_console(&sport->port)) {
3981 if (sport->ops->console_restore)
3982 sport->ops->console_restore(&sport->port);
3983 } else {
3984 int ret = reset_control_deassert(sport->rstc);
3985
3986 if (ret)
3987 return ret;
3988 }
3989
3990 uart_resume_port(&sci_uart_driver, &sport->port);
3991 }
3992
3993 return 0;
3994}
3995
3996static DEFINE_SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
3997
3998static struct platform_driver sci_driver = {
3999 .probe = sci_probe,
4000 .remove = sci_remove,
4001 .driver = {
4002 .name = "sh-sci",
4003 .pm = pm_sleep_ptr(&sci_dev_pm_ops),
4004 .of_match_table = of_match_ptr(of_sci_match),
4005 },
4006};
4007
4008static int __init sci_init(void)
4009{
4010 pr_info("%s\n", banner);
4011
4012 return platform_driver_register(&sci_driver);
4013}
4014
4015static void __exit sci_exit(void)
4016{
4017 platform_driver_unregister(&sci_driver);
4018
4019 if (sci_uart_driver.state)
4020 uart_unregister_driver(&sci_uart_driver);
4021}
4022
4023#if defined(CONFIG_SUPERH) && defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
4024sh_early_platform_init_buffer("earlyprintk", &sci_driver,
4025 early_serial_buf, ARRAY_SIZE(early_serial_buf));
4026#endif
4027#ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
4028static struct plat_sci_port port_cfg;
4029
4030static int early_console_exit(struct console *co)
4031{
4032 struct sci_port *sci_port = &sci_ports[0];
4033
4034 /*
4035 * Clean the slot used by earlycon. A new SCI device might
4036 * map to this slot.
4037 */
4038 if (!sci_uart_earlycon_dev_probing) {
4039 memset(sci_port, 0, sizeof(*sci_port));
4040 sci_uart_earlycon = false;
4041 }
4042
4043 return 0;
4044}
4045
4046int __init scix_early_console_setup(struct earlycon_device *device,
4047 const struct sci_of_data *data)
4048{
4049 const struct sci_common_regs *regs;
4050
4051 if (!device->port.membase)
4052 return -ENODEV;
4053
4054 device->port.type = SCI_PUBLIC_PORT_ID(data->type);
4055
4056 sci_ports[0].port = device->port;
4057 sci_ports[0].type = data->type;
4058 sci_ports[0].regtype = data->regtype;
4059
4060 port_cfg.type = data->type;
4061 port_cfg.regtype = data->regtype;
4062
4063 sci_ports[0].cfg = &port_cfg;
4064 sci_ports[0].params = data->params;
4065 sci_ports[0].ops = data->ops;
4066 sci_ports[0].port.ops = data->uart_ops;
4067 sci_uart_earlycon = true;
4068 regs = sci_ports[0].params->common_regs;
4069
4070 port_cfg.scscr = sci_ports[0].ops->read_reg(&sci_ports[0].port, regs->control);
4071 sci_ports[0].ops->write_reg(&sci_ports[0].port,
4072 regs->control,
4073 sci_ports[0].params->param_bits->rxtx_enable | port_cfg.scscr);
4074
4075 device->con->write = serial_console_write;
4076 device->con->exit = early_console_exit;
4077
4078 return 0;
4079}
4080static int __init sci_early_console_setup(struct earlycon_device *device,
4081 const char *opt)
4082{
4083 return scix_early_console_setup(device, &of_sci_sci);
4084}
4085static int __init scif_early_console_setup(struct earlycon_device *device,
4086 const char *opt)
4087{
4088 return scix_early_console_setup(device, &of_sci_scif_sh4);
4089}
4090static int __init rzscifa_early_console_setup(struct earlycon_device *device,
4091 const char *opt)
4092{
4093 return scix_early_console_setup(device, &of_sci_scif_rz_scifa);
4094}
4095
4096static int __init rzv2hscif_early_console_setup(struct earlycon_device *device,
4097 const char *opt)
4098{
4099 return scix_early_console_setup(device, &of_sci_scif_rzv2h);
4100}
4101
4102static int __init scifa_early_console_setup(struct earlycon_device *device,
4103 const char *opt)
4104{
4105 return scix_early_console_setup(device, &of_sci_scifa);
4106}
4107static int __init scifb_early_console_setup(struct earlycon_device *device,
4108 const char *opt)
4109{
4110 return scix_early_console_setup(device, &of_sci_scifb);
4111}
4112static int __init hscif_early_console_setup(struct earlycon_device *device,
4113 const char *opt)
4114{
4115 return scix_early_console_setup(device, &of_sci_hscif);
4116}
4117
4118OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
4119OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
4120OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup);
4121OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a07g044", rzscifa_early_console_setup);
4122OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a09g057", rzv2hscif_early_console_setup);
4123OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
4124OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
4125OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
4126#endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
4127
4128module_init(sci_init);
4129module_exit(sci_exit);
4130
4131MODULE_LICENSE("GPL");
4132MODULE_ALIAS("platform:sh-sci");
4133MODULE_AUTHOR("Paul Mundt");
4134MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");