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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Cadence UART driver (found in Xilinx Zynq)
4 *
5 * Copyright (c) 2011 - 2014 Xilinx, Inc.
6 *
7 * This driver has originally been pushed by Xilinx using a Zynq-branding. This
8 * still shows in the naming of this file, the kconfig symbols and some symbols
9 * in the code.
10 */
11
12#include <linux/platform_device.h>
13#include <linux/serial.h>
14#include <linux/console.h>
15#include <linux/serial_core.h>
16#include <linux/slab.h>
17#include <linux/tty.h>
18#include <linux/tty_flip.h>
19#include <linux/clk.h>
20#include <linux/irq.h>
21#include <linux/io.h>
22#include <linux/of.h>
23#include <linux/module.h>
24#include <linux/pm_runtime.h>
25#include <linux/gpio/consumer.h>
26#include <linux/delay.h>
27#include <linux/reset.h>
28
29#define CDNS_UART_TTY_NAME "ttyPS"
30#define CDNS_UART_NAME "xuartps"
31#define CDNS_UART_MAJOR 0 /* use dynamic node allocation */
32#define CDNS_UART_MINOR 0 /* works best with devtmpfs */
33#define CDNS_UART_NR_PORTS 16
34#define CDNS_UART_FIFO_SIZE 64 /* FIFO size */
35#define TX_TIMEOUT 500000
36
37/* Rx Trigger level */
38static int rx_trigger_level = 56;
39module_param(rx_trigger_level, uint, 0444);
40MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes");
41
42/* Rx Timeout */
43static int rx_timeout = 10;
44module_param(rx_timeout, uint, 0444);
45MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
46
47/* Register offsets for the UART. */
48#define CDNS_UART_CR 0x00 /* Control Register */
49#define CDNS_UART_MR 0x04 /* Mode Register */
50#define CDNS_UART_IER 0x08 /* Interrupt Enable */
51#define CDNS_UART_IDR 0x0C /* Interrupt Disable */
52#define CDNS_UART_IMR 0x10 /* Interrupt Mask */
53#define CDNS_UART_ISR 0x14 /* Interrupt Status */
54#define CDNS_UART_BAUDGEN 0x18 /* Baud Rate Generator */
55#define CDNS_UART_RXTOUT 0x1C /* RX Timeout */
56#define CDNS_UART_RXWM 0x20 /* RX FIFO Trigger Level */
57#define CDNS_UART_MODEMCR 0x24 /* Modem Control */
58#define CDNS_UART_MODEMSR 0x28 /* Modem Status */
59#define CDNS_UART_SR 0x2C /* Channel Status */
60#define CDNS_UART_FIFO 0x30 /* FIFO */
61#define CDNS_UART_BAUDDIV 0x34 /* Baud Rate Divider */
62#define CDNS_UART_FLOWDEL 0x38 /* Flow Delay */
63#define CDNS_UART_IRRX_PWIDTH 0x3C /* IR Min Received Pulse Width */
64#define CDNS_UART_IRTX_PWIDTH 0x40 /* IR Transmitted pulse Width */
65#define CDNS_UART_TXWM 0x44 /* TX FIFO Trigger Level */
66#define CDNS_UART_RXBS 0x48 /* RX FIFO byte status register */
67
68/* Control Register Bit Definitions */
69#define CDNS_UART_CR_STOPBRK 0x00000100 /* Stop TX break */
70#define CDNS_UART_CR_STARTBRK 0x00000080 /* Set TX break */
71#define CDNS_UART_CR_TX_DIS 0x00000020 /* TX disabled. */
72#define CDNS_UART_CR_TX_EN 0x00000010 /* TX enabled */
73#define CDNS_UART_CR_RX_DIS 0x00000008 /* RX disabled. */
74#define CDNS_UART_CR_RX_EN 0x00000004 /* RX enabled */
75#define CDNS_UART_CR_TXRST 0x00000002 /* TX logic reset */
76#define CDNS_UART_CR_RXRST 0x00000001 /* RX logic reset */
77#define CDNS_UART_CR_RST_TO 0x00000040 /* Restart Timeout Counter */
78#define CDNS_UART_RXBS_PARITY 0x00000001 /* Parity error status */
79#define CDNS_UART_RXBS_FRAMING 0x00000002 /* Framing error status */
80#define CDNS_UART_RXBS_BRK 0x00000004 /* Overrun error status */
81
82/*
83 * Mode Register:
84 * The mode register (MR) defines the mode of transfer as well as the data
85 * format. If this register is modified during transmission or reception,
86 * data validity cannot be guaranteed.
87 */
88#define CDNS_UART_MR_CLKSEL 0x00000001 /* Pre-scalar selection */
89#define CDNS_UART_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */
90#define CDNS_UART_MR_CHMODE_NORM 0x00000000 /* Normal mode */
91#define CDNS_UART_MR_CHMODE_MASK 0x00000300 /* Mask for mode bits */
92
93#define CDNS_UART_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */
94#define CDNS_UART_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */
95
96#define CDNS_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */
97#define CDNS_UART_MR_PARITY_MARK 0x00000018 /* Mark parity mode */
98#define CDNS_UART_MR_PARITY_SPACE 0x00000010 /* Space parity mode */
99#define CDNS_UART_MR_PARITY_ODD 0x00000008 /* Odd parity mode */
100#define CDNS_UART_MR_PARITY_EVEN 0x00000000 /* Even parity mode */
101
102#define CDNS_UART_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */
103#define CDNS_UART_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */
104#define CDNS_UART_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */
105
106/*
107 * Interrupt Registers:
108 * Interrupt control logic uses the interrupt enable register (IER) and the
109 * interrupt disable register (IDR) to set the value of the bits in the
110 * interrupt mask register (IMR). The IMR determines whether to pass an
111 * interrupt to the interrupt status register (ISR).
112 * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an
113 * interrupt. IMR and ISR are read only, and IER and IDR are write only.
114 * Reading either IER or IDR returns 0x00.
115 * All four registers have the same bit definitions.
116 */
117#define CDNS_UART_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */
118#define CDNS_UART_IXR_PARITY 0x00000080 /* Parity error interrupt */
119#define CDNS_UART_IXR_FRAMING 0x00000040 /* Framing error interrupt */
120#define CDNS_UART_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */
121#define CDNS_UART_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */
122#define CDNS_UART_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */
123#define CDNS_UART_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */
124#define CDNS_UART_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */
125#define CDNS_UART_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */
126#define CDNS_UART_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */
127#define CDNS_UART_IXR_RXMASK 0x000021e7 /* Valid RX bit mask */
128
129 /*
130 * Do not enable parity error interrupt for the following
131 * reason: When parity error interrupt is enabled, each Rx
132 * parity error always results in 2 events. The first one
133 * being parity error interrupt and the second one with a
134 * proper Rx interrupt with the incoming data. Disabling
135 * parity error interrupt ensures better handling of parity
136 * error events. With this change, for a parity error case, we
137 * get a Rx interrupt with parity error set in ISR register
138 * and we still handle parity errors in the desired way.
139 */
140
141#define CDNS_UART_RX_IRQS (CDNS_UART_IXR_FRAMING | \
142 CDNS_UART_IXR_OVERRUN | \
143 CDNS_UART_IXR_RXTRIG | \
144 CDNS_UART_IXR_TOUT)
145
146/* Goes in read_status_mask for break detection as the HW doesn't do it*/
147#define CDNS_UART_IXR_BRK 0x00002000
148
149#define CDNS_UART_RXBS_SUPPORT BIT(1)
150/*
151 * Modem Control register:
152 * The read/write Modem Control register controls the interface with the modem
153 * or data set, or a peripheral device emulating a modem.
154 */
155#define CDNS_UART_MODEMCR_FCM 0x00000020 /* Automatic flow control mode */
156#define CDNS_UART_MODEMCR_RTS 0x00000002 /* Request to send output control */
157#define CDNS_UART_MODEMCR_DTR 0x00000001 /* Data Terminal Ready */
158
159/*
160 * Modem Status register:
161 * The read/write Modem Status register reports the interface with the modem
162 * or data set, or a peripheral device emulating a modem.
163 */
164#define CDNS_UART_MODEMSR_DCD BIT(7) /* Data Carrier Detect */
165#define CDNS_UART_MODEMSR_RI BIT(6) /* Ting Indicator */
166#define CDNS_UART_MODEMSR_DSR BIT(5) /* Data Set Ready */
167#define CDNS_UART_MODEMSR_CTS BIT(4) /* Clear To Send */
168
169/*
170 * Channel Status Register:
171 * The channel status register (CSR) is provided to enable the control logic
172 * to monitor the status of bits in the channel interrupt status register,
173 * even if these are masked out by the interrupt mask register.
174 */
175#define CDNS_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
176#define CDNS_UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */
177#define CDNS_UART_SR_TXFULL 0x00000010 /* TX FIFO full */
178#define CDNS_UART_SR_RXTRIG 0x00000001 /* Rx Trigger */
179#define CDNS_UART_SR_TACTIVE 0x00000800 /* TX state machine active */
180
181/* baud dividers min/max values */
182#define CDNS_UART_BDIV_MIN 4
183#define CDNS_UART_BDIV_MAX 255
184#define CDNS_UART_CD_MAX 65535
185#define UART_AUTOSUSPEND_TIMEOUT 3000
186
187/**
188 * struct cdns_uart - device data
189 * @port: Pointer to the UART port
190 * @uartclk: Reference clock
191 * @pclk: APB clock
192 * @baud: Current baud rate
193 * @clk_rate_change_nb: Notifier block for clock changes
194 * @quirks: Flags for RXBS support.
195 * @cts_override: Modem control state override
196 * @gpiod_rts: Pointer to the gpio descriptor
197 * @rs485_tx_started: RS485 tx state
198 * @tx_timer: Timer for tx
199 * @rstc: Pointer to the reset control
200 */
201struct cdns_uart {
202 struct uart_port *port;
203 struct clk *uartclk;
204 struct clk *pclk;
205 unsigned int baud;
206 struct notifier_block clk_rate_change_nb;
207 u32 quirks;
208 bool cts_override;
209 struct gpio_desc *gpiod_rts;
210 bool rs485_tx_started;
211 struct hrtimer tx_timer;
212 struct reset_control *rstc;
213};
214struct cdns_platform_data {
215 u32 quirks;
216};
217
218static struct serial_rs485 cdns_rs485_supported = {
219 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND |
220 SER_RS485_RTS_AFTER_SEND,
221 .delay_rts_before_send = 1,
222 .delay_rts_after_send = 1,
223};
224
225#define to_cdns_uart(_nb) container_of(_nb, struct cdns_uart, \
226 clk_rate_change_nb)
227
228/**
229 * cdns_uart_handle_rx - Handle the received bytes along with Rx errors.
230 * @dev_id: Id of the UART port
231 * @isrstatus: The interrupt status register value as read
232 * Return: None
233 */
234static void cdns_uart_handle_rx(void *dev_id, unsigned int isrstatus)
235{
236 struct uart_port *port = (struct uart_port *)dev_id;
237 struct cdns_uart *cdns_uart = port->private_data;
238 unsigned int data;
239 unsigned int rxbs_status = 0;
240 unsigned int status_mask;
241 unsigned int framerrprocessed = 0;
242 char status = TTY_NORMAL;
243 bool is_rxbs_support;
244
245 is_rxbs_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;
246
247 while ((readl(port->membase + CDNS_UART_SR) &
248 CDNS_UART_SR_RXEMPTY) != CDNS_UART_SR_RXEMPTY) {
249 if (is_rxbs_support)
250 rxbs_status = readl(port->membase + CDNS_UART_RXBS);
251 data = readl(port->membase + CDNS_UART_FIFO);
252 port->icount.rx++;
253 /*
254 * There is no hardware break detection in Zynq, so we interpret
255 * framing error with all-zeros data as a break sequence.
256 * Most of the time, there's another non-zero byte at the
257 * end of the sequence.
258 */
259 if (!is_rxbs_support && (isrstatus & CDNS_UART_IXR_FRAMING)) {
260 if (!data) {
261 port->read_status_mask |= CDNS_UART_IXR_BRK;
262 framerrprocessed = 1;
263 continue;
264 }
265 }
266 if (is_rxbs_support && (rxbs_status & CDNS_UART_RXBS_BRK)) {
267 port->icount.brk++;
268 status = TTY_BREAK;
269 if (uart_handle_break(port))
270 continue;
271 }
272
273 isrstatus &= port->read_status_mask;
274 isrstatus &= ~port->ignore_status_mask;
275 status_mask = port->read_status_mask;
276 status_mask &= ~port->ignore_status_mask;
277
278 if (data &&
279 (port->read_status_mask & CDNS_UART_IXR_BRK)) {
280 port->read_status_mask &= ~CDNS_UART_IXR_BRK;
281 port->icount.brk++;
282 if (uart_handle_break(port))
283 continue;
284 }
285
286 if (uart_prepare_sysrq_char(port, data))
287 continue;
288
289 if (is_rxbs_support) {
290 if ((rxbs_status & CDNS_UART_RXBS_PARITY)
291 && (status_mask & CDNS_UART_IXR_PARITY)) {
292 port->icount.parity++;
293 status = TTY_PARITY;
294 }
295 if ((rxbs_status & CDNS_UART_RXBS_FRAMING)
296 && (status_mask & CDNS_UART_IXR_PARITY)) {
297 port->icount.frame++;
298 status = TTY_FRAME;
299 }
300 } else {
301 if (isrstatus & CDNS_UART_IXR_PARITY) {
302 port->icount.parity++;
303 status = TTY_PARITY;
304 }
305 if ((isrstatus & CDNS_UART_IXR_FRAMING) &&
306 !framerrprocessed) {
307 port->icount.frame++;
308 status = TTY_FRAME;
309 }
310 }
311 if (isrstatus & CDNS_UART_IXR_OVERRUN) {
312 port->icount.overrun++;
313 tty_insert_flip_char(&port->state->port, 0,
314 TTY_OVERRUN);
315 }
316 tty_insert_flip_char(&port->state->port, data, status);
317 isrstatus = 0;
318 }
319
320 tty_flip_buffer_push(&port->state->port);
321}
322
323/**
324 * cdns_rts_gpio_enable - Configure RTS/GPIO to high/low
325 * @cdns_uart: Handle to the cdns_uart
326 * @enable: Value to be set to RTS/GPIO
327 */
328static void cdns_rts_gpio_enable(struct cdns_uart *cdns_uart, bool enable)
329{
330 u32 val;
331
332 if (cdns_uart->gpiod_rts) {
333 gpiod_set_value(cdns_uart->gpiod_rts, enable);
334 } else {
335 val = readl(cdns_uart->port->membase + CDNS_UART_MODEMCR);
336 if (enable)
337 val |= CDNS_UART_MODEMCR_RTS;
338 else
339 val &= ~CDNS_UART_MODEMCR_RTS;
340 writel(val, cdns_uart->port->membase + CDNS_UART_MODEMCR);
341 }
342}
343
344/**
345 * cdns_rs485_tx_setup - Tx setup specific to rs485
346 * @cdns_uart: Handle to the cdns_uart
347 */
348static void cdns_rs485_tx_setup(struct cdns_uart *cdns_uart)
349{
350 bool enable;
351
352 enable = cdns_uart->port->rs485.flags & SER_RS485_RTS_ON_SEND;
353 cdns_rts_gpio_enable(cdns_uart, enable);
354
355 cdns_uart->rs485_tx_started = true;
356}
357
358/**
359 * cdns_rs485_rx_setup - Rx setup specific to rs485
360 * @cdns_uart: Handle to the cdns_uart
361 */
362static void cdns_rs485_rx_setup(struct cdns_uart *cdns_uart)
363{
364 bool enable;
365
366 enable = cdns_uart->port->rs485.flags & SER_RS485_RTS_AFTER_SEND;
367 cdns_rts_gpio_enable(cdns_uart, enable);
368
369 cdns_uart->rs485_tx_started = false;
370}
371
372/**
373 * cdns_uart_tx_empty - Check whether TX is empty
374 * @port: Handle to the uart port structure
375 *
376 * Return: TIOCSER_TEMT on success, 0 otherwise
377 */
378static unsigned int cdns_uart_tx_empty(struct uart_port *port)
379{
380 unsigned int status;
381
382 status = readl(port->membase + CDNS_UART_SR);
383 status &= (CDNS_UART_SR_TXEMPTY | CDNS_UART_SR_TACTIVE);
384 return (status == CDNS_UART_SR_TXEMPTY) ? TIOCSER_TEMT : 0;
385}
386
387/**
388 * cdns_rs485_rx_callback - Timer rx callback handler for rs485.
389 * @t: Handle to the hrtimer structure
390 */
391static enum hrtimer_restart cdns_rs485_rx_callback(struct hrtimer *t)
392{
393 struct cdns_uart *cdns_uart = container_of(t, struct cdns_uart, tx_timer);
394
395 /*
396 * Default Rx should be setup, because Rx signaling path
397 * need to enable to receive data.
398 */
399 cdns_rs485_rx_setup(cdns_uart);
400
401 return HRTIMER_NORESTART;
402}
403
404/**
405 * cdns_calc_after_tx_delay - calculate delay required for after tx.
406 * @cdns_uart: Handle to the cdns_uart
407 */
408static u64 cdns_calc_after_tx_delay(struct cdns_uart *cdns_uart)
409{
410 /*
411 * Frame time + stop bit time + rs485.delay_rts_after_send
412 */
413 return cdns_uart->port->frame_time
414 + DIV_ROUND_UP(cdns_uart->port->frame_time, 7)
415 + (u64)cdns_uart->port->rs485.delay_rts_after_send * NSEC_PER_MSEC;
416}
417
418/**
419 * cdns_uart_handle_tx - Handle the bytes to be transmitted.
420 * @dev_id: Id of the UART port
421 * Return: None
422 */
423static void cdns_uart_handle_tx(void *dev_id)
424{
425 struct uart_port *port = (struct uart_port *)dev_id;
426 struct cdns_uart *cdns_uart = port->private_data;
427 struct tty_port *tport = &port->state->port;
428 unsigned int numbytes;
429 unsigned char ch;
430 ktime_t rts_delay;
431
432 if (kfifo_is_empty(&tport->xmit_fifo) || uart_tx_stopped(port)) {
433 /* Disable the TX Empty interrupt */
434 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IDR);
435 /* Set RTS line after delay */
436 if (cdns_uart->port->rs485.flags & SER_RS485_ENABLED) {
437 cdns_uart->tx_timer.function = &cdns_rs485_rx_callback;
438 rts_delay = ns_to_ktime(cdns_calc_after_tx_delay(cdns_uart));
439 hrtimer_start(&cdns_uart->tx_timer, rts_delay, HRTIMER_MODE_REL);
440 }
441 return;
442 }
443
444 numbytes = port->fifosize;
445 while (numbytes &&
446 !(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXFULL) &&
447 uart_fifo_get(port, &ch)) {
448 writel(ch, port->membase + CDNS_UART_FIFO);
449 numbytes--;
450 }
451
452 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
453 uart_write_wakeup(port);
454
455 /* Enable the TX Empty interrupt */
456 writel(CDNS_UART_IXR_TXEMPTY, cdns_uart->port->membase + CDNS_UART_IER);
457}
458
459/**
460 * cdns_uart_isr - Interrupt handler
461 * @irq: Irq number
462 * @dev_id: Id of the port
463 *
464 * Return: IRQHANDLED
465 */
466static irqreturn_t cdns_uart_isr(int irq, void *dev_id)
467{
468 struct uart_port *port = (struct uart_port *)dev_id;
469 unsigned int isrstatus;
470
471 uart_port_lock(port);
472
473 /* Read the interrupt status register to determine which
474 * interrupt(s) is/are active and clear them.
475 */
476 isrstatus = readl(port->membase + CDNS_UART_ISR);
477 writel(isrstatus, port->membase + CDNS_UART_ISR);
478
479 if (isrstatus & CDNS_UART_IXR_TXEMPTY) {
480 cdns_uart_handle_tx(dev_id);
481 isrstatus &= ~CDNS_UART_IXR_TXEMPTY;
482 }
483
484 isrstatus &= port->read_status_mask;
485 isrstatus &= ~port->ignore_status_mask;
486 /*
487 * Skip RX processing if RX is disabled as RXEMPTY will never be set
488 * as read bytes will not be removed from the FIFO.
489 */
490 if (isrstatus & CDNS_UART_IXR_RXMASK &&
491 !(readl(port->membase + CDNS_UART_CR) & CDNS_UART_CR_RX_DIS))
492 cdns_uart_handle_rx(dev_id, isrstatus);
493
494 uart_unlock_and_check_sysrq(port);
495 return IRQ_HANDLED;
496}
497
498/**
499 * cdns_uart_calc_baud_divs - Calculate baud rate divisors
500 * @clk: UART module input clock
501 * @baud: Desired baud rate
502 * @rbdiv: BDIV value (return value)
503 * @rcd: CD value (return value)
504 * @div8: Value for clk_sel bit in mod (return value)
505 * Return: baud rate, requested baud when possible, or actual baud when there
506 * was too much error, zero if no valid divisors are found.
507 *
508 * Formula to obtain baud rate is
509 * baud_tx/rx rate = clk/CD * (BDIV + 1)
510 * input_clk = (Uart User Defined Clock or Apb Clock)
511 * depends on UCLKEN in MR Reg
512 * clk = input_clk or input_clk/8;
513 * depends on CLKS in MR reg
514 * CD and BDIV depends on values in
515 * baud rate generate register
516 * baud rate clock divisor register
517 */
518static unsigned int cdns_uart_calc_baud_divs(unsigned int clk,
519 unsigned int baud, u32 *rbdiv, u32 *rcd, int *div8)
520{
521 u32 cd, bdiv;
522 unsigned int calc_baud;
523 unsigned int bestbaud = 0;
524 unsigned int bauderror;
525 unsigned int besterror = ~0;
526
527 if (baud < clk / ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX)) {
528 *div8 = 1;
529 clk /= 8;
530 } else {
531 *div8 = 0;
532 }
533
534 for (bdiv = CDNS_UART_BDIV_MIN; bdiv <= CDNS_UART_BDIV_MAX; bdiv++) {
535 cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1));
536 if (cd < 1 || cd > CDNS_UART_CD_MAX)
537 continue;
538
539 calc_baud = clk / (cd * (bdiv + 1));
540
541 if (baud > calc_baud)
542 bauderror = baud - calc_baud;
543 else
544 bauderror = calc_baud - baud;
545
546 if (besterror > bauderror) {
547 *rbdiv = bdiv;
548 *rcd = cd;
549 bestbaud = calc_baud;
550 besterror = bauderror;
551 }
552 }
553 /* use the values when percent error is acceptable */
554 if (((besterror * 100) / baud) < 3)
555 bestbaud = baud;
556
557 return bestbaud;
558}
559
560/**
561 * cdns_uart_set_baud_rate - Calculate and set the baud rate
562 * @port: Handle to the uart port structure
563 * @baud: Baud rate to set
564 * Return: baud rate, requested baud when possible, or actual baud when there
565 * was too much error, zero if no valid divisors are found.
566 */
567static unsigned int cdns_uart_set_baud_rate(struct uart_port *port,
568 unsigned int baud)
569{
570 unsigned int calc_baud;
571 u32 cd = 0, bdiv = 0;
572 u32 mreg;
573 int div8;
574 struct cdns_uart *cdns_uart = port->private_data;
575
576 calc_baud = cdns_uart_calc_baud_divs(port->uartclk, baud, &bdiv, &cd,
577 &div8);
578
579 /* Write new divisors to hardware */
580 mreg = readl(port->membase + CDNS_UART_MR);
581 if (div8)
582 mreg |= CDNS_UART_MR_CLKSEL;
583 else
584 mreg &= ~CDNS_UART_MR_CLKSEL;
585 writel(mreg, port->membase + CDNS_UART_MR);
586 writel(cd, port->membase + CDNS_UART_BAUDGEN);
587 writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
588 cdns_uart->baud = baud;
589
590 return calc_baud;
591}
592
593#ifdef CONFIG_COMMON_CLK
594/**
595 * cdns_uart_clk_notifier_cb - Clock notifier callback
596 * @nb: Notifier block
597 * @event: Notify event
598 * @data: Notifier data
599 * Return: NOTIFY_OK or NOTIFY_DONE on success, NOTIFY_BAD on error.
600 */
601static int cdns_uart_clk_notifier_cb(struct notifier_block *nb,
602 unsigned long event, void *data)
603{
604 u32 ctrl_reg;
605 struct uart_port *port;
606 int locked = 0;
607 struct clk_notifier_data *ndata = data;
608 struct cdns_uart *cdns_uart = to_cdns_uart(nb);
609 unsigned long flags;
610
611 port = cdns_uart->port;
612 if (port->suspended)
613 return NOTIFY_OK;
614
615 switch (event) {
616 case PRE_RATE_CHANGE:
617 {
618 u32 bdiv, cd;
619 int div8;
620
621 /*
622 * Find out if current baud-rate can be achieved with new clock
623 * frequency.
624 */
625 if (!cdns_uart_calc_baud_divs(ndata->new_rate, cdns_uart->baud,
626 &bdiv, &cd, &div8)) {
627 dev_warn(port->dev, "clock rate change rejected\n");
628 return NOTIFY_BAD;
629 }
630
631 uart_port_lock_irqsave(cdns_uart->port, &flags);
632
633 /* Disable the TX and RX to set baud rate */
634 ctrl_reg = readl(port->membase + CDNS_UART_CR);
635 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
636 writel(ctrl_reg, port->membase + CDNS_UART_CR);
637
638 uart_port_unlock_irqrestore(cdns_uart->port, flags);
639
640 return NOTIFY_OK;
641 }
642 case POST_RATE_CHANGE:
643 /*
644 * Set clk dividers to generate correct baud with new clock
645 * frequency.
646 */
647
648 uart_port_lock_irqsave(cdns_uart->port, &flags);
649
650 locked = 1;
651 port->uartclk = ndata->new_rate;
652
653 cdns_uart->baud = cdns_uart_set_baud_rate(cdns_uart->port,
654 cdns_uart->baud);
655 fallthrough;
656 case ABORT_RATE_CHANGE:
657 if (!locked)
658 uart_port_lock_irqsave(cdns_uart->port, &flags);
659
660 /* Set TX/RX Reset */
661 ctrl_reg = readl(port->membase + CDNS_UART_CR);
662 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
663 writel(ctrl_reg, port->membase + CDNS_UART_CR);
664
665 while (readl(port->membase + CDNS_UART_CR) &
666 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
667 cpu_relax();
668
669 /*
670 * Clear the RX disable and TX disable bits and then set the TX
671 * enable bit and RX enable bit to enable the transmitter and
672 * receiver.
673 */
674 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
675 ctrl_reg = readl(port->membase + CDNS_UART_CR);
676 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
677 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
678 writel(ctrl_reg, port->membase + CDNS_UART_CR);
679
680 uart_port_unlock_irqrestore(cdns_uart->port, flags);
681
682 return NOTIFY_OK;
683 default:
684 return NOTIFY_DONE;
685 }
686}
687#endif
688
689/**
690 * cdns_rs485_tx_callback - Timer tx callback handler for rs485.
691 * @t: Handle to the hrtimer structure
692 */
693static enum hrtimer_restart cdns_rs485_tx_callback(struct hrtimer *t)
694{
695 struct cdns_uart *cdns_uart = container_of(t, struct cdns_uart, tx_timer);
696
697 uart_port_lock(cdns_uart->port);
698 cdns_uart_handle_tx(cdns_uart->port);
699 uart_port_unlock(cdns_uart->port);
700
701 return HRTIMER_NORESTART;
702}
703
704/**
705 * cdns_uart_start_tx - Start transmitting bytes
706 * @port: Handle to the uart port structure
707 */
708static void cdns_uart_start_tx(struct uart_port *port)
709{
710 unsigned int status;
711 struct cdns_uart *cdns_uart = port->private_data;
712
713 if (uart_tx_stopped(port))
714 return;
715
716 /*
717 * Set the TX enable bit and clear the TX disable bit to enable the
718 * transmitter.
719 */
720 status = readl(port->membase + CDNS_UART_CR);
721 status &= ~CDNS_UART_CR_TX_DIS;
722 status |= CDNS_UART_CR_TX_EN;
723 writel(status, port->membase + CDNS_UART_CR);
724
725 if (kfifo_is_empty(&port->state->port.xmit_fifo))
726 return;
727
728 /* Clear the TX Empty interrupt */
729 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_ISR);
730
731 if (cdns_uart->port->rs485.flags & SER_RS485_ENABLED) {
732 if (!cdns_uart->rs485_tx_started) {
733 hrtimer_update_function(&cdns_uart->tx_timer, cdns_rs485_tx_callback);
734 cdns_rs485_tx_setup(cdns_uart);
735 return hrtimer_start(&cdns_uart->tx_timer,
736 ms_to_ktime(port->rs485.delay_rts_before_send),
737 HRTIMER_MODE_REL);
738 }
739 }
740 cdns_uart_handle_tx(port);
741}
742
743/**
744 * cdns_uart_stop_tx - Stop TX
745 * @port: Handle to the uart port structure
746 */
747static void cdns_uart_stop_tx(struct uart_port *port)
748{
749 unsigned int regval;
750 struct cdns_uart *cdns_uart = port->private_data;
751
752 if (cdns_uart->port->rs485.flags & SER_RS485_ENABLED)
753 cdns_rs485_rx_setup(cdns_uart);
754
755 regval = readl(port->membase + CDNS_UART_CR);
756 regval |= CDNS_UART_CR_TX_DIS;
757 /* Disable the transmitter */
758 writel(regval, port->membase + CDNS_UART_CR);
759}
760
761/**
762 * cdns_uart_stop_rx - Stop RX
763 * @port: Handle to the uart port structure
764 */
765static void cdns_uart_stop_rx(struct uart_port *port)
766{
767 unsigned int regval;
768
769 /* Disable RX IRQs */
770 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IDR);
771
772 /* Disable the receiver */
773 regval = readl(port->membase + CDNS_UART_CR);
774 regval |= CDNS_UART_CR_RX_DIS;
775 writel(regval, port->membase + CDNS_UART_CR);
776}
777
778/**
779 * cdns_uart_break_ctl - Based on the input ctl we have to start or stop
780 * transmitting char breaks
781 * @port: Handle to the uart port structure
782 * @ctl: Value based on which start or stop decision is taken
783 */
784static void cdns_uart_break_ctl(struct uart_port *port, int ctl)
785{
786 unsigned int status;
787 unsigned long flags;
788
789 uart_port_lock_irqsave(port, &flags);
790
791 status = readl(port->membase + CDNS_UART_CR);
792
793 if (ctl == -1)
794 writel(CDNS_UART_CR_STARTBRK | (~CDNS_UART_CR_STOPBRK & status),
795 port->membase + CDNS_UART_CR);
796 else {
797 if ((status & CDNS_UART_CR_STOPBRK) == 0)
798 writel(CDNS_UART_CR_STOPBRK | status,
799 port->membase + CDNS_UART_CR);
800 }
801 uart_port_unlock_irqrestore(port, flags);
802}
803
804/**
805 * cdns_uart_set_termios - termios operations, handling data length, parity,
806 * stop bits, flow control, baud rate
807 * @port: Handle to the uart port structure
808 * @termios: Handle to the input termios structure
809 * @old: Values of the previously saved termios structure
810 */
811static void cdns_uart_set_termios(struct uart_port *port,
812 struct ktermios *termios,
813 const struct ktermios *old)
814{
815 u32 cval = 0;
816 unsigned int baud, minbaud, maxbaud;
817 unsigned long flags;
818 unsigned int ctrl_reg, mode_reg;
819
820 uart_port_lock_irqsave(port, &flags);
821
822 /* Disable the TX and RX to set baud rate */
823 ctrl_reg = readl(port->membase + CDNS_UART_CR);
824 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
825 writel(ctrl_reg, port->membase + CDNS_UART_CR);
826
827 /*
828 * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk
829 * min and max baud should be calculated here based on port->uartclk.
830 * this way we get a valid baud and can safely call set_baud()
831 */
832 minbaud = port->uartclk /
833 ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX * 8);
834 maxbaud = port->uartclk / (CDNS_UART_BDIV_MIN + 1);
835 baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud);
836 baud = cdns_uart_set_baud_rate(port, baud);
837 if (tty_termios_baud_rate(termios))
838 tty_termios_encode_baud_rate(termios, baud, baud);
839
840 /* Update the per-port timeout. */
841 uart_update_timeout(port, termios->c_cflag, baud);
842
843 /* Set TX/RX Reset */
844 ctrl_reg = readl(port->membase + CDNS_UART_CR);
845 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
846 writel(ctrl_reg, port->membase + CDNS_UART_CR);
847
848 while (readl(port->membase + CDNS_UART_CR) &
849 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
850 cpu_relax();
851
852 /*
853 * Clear the RX disable and TX disable bits and then set the TX enable
854 * bit and RX enable bit to enable the transmitter and receiver.
855 */
856 ctrl_reg = readl(port->membase + CDNS_UART_CR);
857 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
858 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
859 writel(ctrl_reg, port->membase + CDNS_UART_CR);
860
861 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
862
863 port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG |
864 CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT;
865 port->ignore_status_mask = 0;
866
867 if (termios->c_iflag & INPCK)
868 port->read_status_mask |= CDNS_UART_IXR_PARITY |
869 CDNS_UART_IXR_FRAMING;
870
871 if (termios->c_iflag & IGNPAR)
872 port->ignore_status_mask |= CDNS_UART_IXR_PARITY |
873 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
874
875 /* ignore all characters if CREAD is not set */
876 if ((termios->c_cflag & CREAD) == 0)
877 port->ignore_status_mask |= CDNS_UART_IXR_RXTRIG |
878 CDNS_UART_IXR_TOUT | CDNS_UART_IXR_PARITY |
879 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
880
881 mode_reg = readl(port->membase + CDNS_UART_MR);
882
883 /* Handling Data Size */
884 switch (termios->c_cflag & CSIZE) {
885 case CS6:
886 cval |= CDNS_UART_MR_CHARLEN_6_BIT;
887 break;
888 case CS7:
889 cval |= CDNS_UART_MR_CHARLEN_7_BIT;
890 break;
891 default:
892 case CS8:
893 cval |= CDNS_UART_MR_CHARLEN_8_BIT;
894 termios->c_cflag &= ~CSIZE;
895 termios->c_cflag |= CS8;
896 break;
897 }
898
899 /* Handling Parity and Stop Bits length */
900 if (termios->c_cflag & CSTOPB)
901 cval |= CDNS_UART_MR_STOPMODE_2_BIT; /* 2 STOP bits */
902 else
903 cval |= CDNS_UART_MR_STOPMODE_1_BIT; /* 1 STOP bit */
904
905 if (termios->c_cflag & PARENB) {
906 /* Mark or Space parity */
907 if (termios->c_cflag & CMSPAR) {
908 if (termios->c_cflag & PARODD)
909 cval |= CDNS_UART_MR_PARITY_MARK;
910 else
911 cval |= CDNS_UART_MR_PARITY_SPACE;
912 } else {
913 if (termios->c_cflag & PARODD)
914 cval |= CDNS_UART_MR_PARITY_ODD;
915 else
916 cval |= CDNS_UART_MR_PARITY_EVEN;
917 }
918 } else {
919 cval |= CDNS_UART_MR_PARITY_NONE;
920 }
921 cval |= mode_reg & 1;
922 writel(cval, port->membase + CDNS_UART_MR);
923
924 cval = readl(port->membase + CDNS_UART_MODEMCR);
925 if (termios->c_cflag & CRTSCTS)
926 cval |= CDNS_UART_MODEMCR_FCM;
927 else
928 cval &= ~CDNS_UART_MODEMCR_FCM;
929 writel(cval, port->membase + CDNS_UART_MODEMCR);
930
931 uart_port_unlock_irqrestore(port, flags);
932}
933
934/**
935 * cdns_uart_startup - Called when an application opens a cdns_uart port
936 * @port: Handle to the uart port structure
937 *
938 * Return: 0 on success, negative errno otherwise
939 */
940static int cdns_uart_startup(struct uart_port *port)
941{
942 struct cdns_uart *cdns_uart = port->private_data;
943 bool is_brk_support;
944 int ret;
945 unsigned long flags;
946 unsigned int status = 0;
947
948 is_brk_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;
949
950 ret = reset_control_deassert(cdns_uart->rstc);
951 if (ret)
952 return ret;
953
954 uart_port_lock_irqsave(port, &flags);
955
956 /* Disable the TX and RX */
957 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
958 port->membase + CDNS_UART_CR);
959
960 /* Set the Control Register with TX/RX Enable, TX/RX Reset,
961 * no break chars.
962 */
963 writel(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST,
964 port->membase + CDNS_UART_CR);
965
966 while (readl(port->membase + CDNS_UART_CR) &
967 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
968 cpu_relax();
969
970 if (cdns_uart->port->rs485.flags & SER_RS485_ENABLED)
971 cdns_rs485_rx_setup(cdns_uart);
972
973 /*
974 * Clear the RX disable bit and then set the RX enable bit to enable
975 * the receiver.
976 */
977 status = readl(port->membase + CDNS_UART_CR);
978 status &= ~CDNS_UART_CR_RX_DIS;
979 status |= CDNS_UART_CR_RX_EN;
980 writel(status, port->membase + CDNS_UART_CR);
981
982 /* Set the Mode Register with normal mode,8 data bits,1 stop bit,
983 * no parity.
984 */
985 writel(CDNS_UART_MR_CHMODE_NORM | CDNS_UART_MR_STOPMODE_1_BIT
986 | CDNS_UART_MR_PARITY_NONE | CDNS_UART_MR_CHARLEN_8_BIT,
987 port->membase + CDNS_UART_MR);
988
989 /*
990 * Set the RX FIFO Trigger level to use most of the FIFO, but it
991 * can be tuned with a module parameter
992 */
993 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
994
995 /*
996 * Receive Timeout register is enabled but it
997 * can be tuned with a module parameter
998 */
999 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
1000
1001 /* Clear out any pending interrupts before enabling them */
1002 writel(readl(port->membase + CDNS_UART_ISR),
1003 port->membase + CDNS_UART_ISR);
1004
1005 uart_port_unlock_irqrestore(port, flags);
1006
1007 ret = request_irq(port->irq, cdns_uart_isr, 0, CDNS_UART_NAME, port);
1008 if (ret) {
1009 dev_err(port->dev, "request_irq '%d' failed with %d\n",
1010 port->irq, ret);
1011 return ret;
1012 }
1013
1014 /* Set the Interrupt Registers with desired interrupts */
1015 if (is_brk_support)
1016 writel(CDNS_UART_RX_IRQS | CDNS_UART_IXR_BRK,
1017 port->membase + CDNS_UART_IER);
1018 else
1019 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IER);
1020
1021 return 0;
1022}
1023
1024/**
1025 * cdns_uart_shutdown - Called when an application closes a cdns_uart port
1026 * @port: Handle to the uart port structure
1027 */
1028static void cdns_uart_shutdown(struct uart_port *port)
1029{
1030 int status;
1031 unsigned long flags;
1032 struct cdns_uart *cdns_uart = port->private_data;
1033
1034 if (cdns_uart->port->rs485.flags & SER_RS485_ENABLED)
1035 hrtimer_cancel(&cdns_uart->tx_timer);
1036
1037 uart_port_lock_irqsave(port, &flags);
1038
1039 /* Disable interrupts */
1040 status = readl(port->membase + CDNS_UART_IMR);
1041 writel(status, port->membase + CDNS_UART_IDR);
1042 writel(0xffffffff, port->membase + CDNS_UART_ISR);
1043
1044 /* Disable the TX and RX */
1045 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
1046 port->membase + CDNS_UART_CR);
1047
1048 uart_port_unlock_irqrestore(port, flags);
1049
1050 free_irq(port->irq, port);
1051}
1052
1053/**
1054 * cdns_uart_type - Set UART type to cdns_uart port
1055 * @port: Handle to the uart port structure
1056 *
1057 * Return: string on success, NULL otherwise
1058 */
1059static const char *cdns_uart_type(struct uart_port *port)
1060{
1061 return port->type == PORT_XUARTPS ? CDNS_UART_NAME : NULL;
1062}
1063
1064/**
1065 * cdns_uart_verify_port - Verify the port params
1066 * @port: Handle to the uart port structure
1067 * @ser: Handle to the structure whose members are compared
1068 *
1069 * Return: 0 on success, negative errno otherwise.
1070 */
1071static int cdns_uart_verify_port(struct uart_port *port,
1072 struct serial_struct *ser)
1073{
1074 if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS)
1075 return -EINVAL;
1076 if (port->irq != ser->irq)
1077 return -EINVAL;
1078 if (ser->io_type != UPIO_MEM)
1079 return -EINVAL;
1080 if (port->iobase != ser->port)
1081 return -EINVAL;
1082 if (ser->hub6 != 0)
1083 return -EINVAL;
1084 return 0;
1085}
1086
1087/**
1088 * cdns_uart_request_port - Claim the memory region attached to cdns_uart port,
1089 * called when the driver adds a cdns_uart port via
1090 * uart_add_one_port()
1091 * @port: Handle to the uart port structure
1092 *
1093 * Return: 0 on success, negative errno otherwise.
1094 */
1095static int cdns_uart_request_port(struct uart_port *port)
1096{
1097 if (!request_mem_region(port->mapbase, port->mapsize,
1098 CDNS_UART_NAME)) {
1099 return -ENOMEM;
1100 }
1101
1102 port->membase = ioremap(port->mapbase, port->mapsize);
1103 if (!port->membase) {
1104 dev_err(port->dev, "Unable to map registers\n");
1105 release_mem_region(port->mapbase, port->mapsize);
1106 return -ENOMEM;
1107 }
1108 return 0;
1109}
1110
1111/**
1112 * cdns_uart_release_port - Release UART port
1113 * @port: Handle to the uart port structure
1114 *
1115 * Release the memory region attached to a cdns_uart port. Called when the
1116 * driver removes a cdns_uart port via uart_remove_one_port().
1117 */
1118static void cdns_uart_release_port(struct uart_port *port)
1119{
1120 release_mem_region(port->mapbase, port->mapsize);
1121 iounmap(port->membase);
1122 port->membase = NULL;
1123}
1124
1125/**
1126 * cdns_uart_config_port - Configure UART port
1127 * @port: Handle to the uart port structure
1128 * @flags: If any
1129 */
1130static void cdns_uart_config_port(struct uart_port *port, int flags)
1131{
1132 if (flags & UART_CONFIG_TYPE && cdns_uart_request_port(port) == 0)
1133 port->type = PORT_XUARTPS;
1134}
1135
1136/**
1137 * cdns_uart_get_mctrl - Get the modem control state
1138 * @port: Handle to the uart port structure
1139 *
1140 * Return: the modem control state
1141 */
1142static unsigned int cdns_uart_get_mctrl(struct uart_port *port)
1143{
1144 u32 val;
1145 unsigned int mctrl = 0;
1146 struct cdns_uart *cdns_uart_data = port->private_data;
1147
1148 if (cdns_uart_data->cts_override)
1149 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
1150
1151 val = readl(port->membase + CDNS_UART_MODEMSR);
1152 if (val & CDNS_UART_MODEMSR_CTS)
1153 mctrl |= TIOCM_CTS;
1154 if (val & CDNS_UART_MODEMSR_DSR)
1155 mctrl |= TIOCM_DSR;
1156 if (val & CDNS_UART_MODEMSR_RI)
1157 mctrl |= TIOCM_RNG;
1158 if (val & CDNS_UART_MODEMSR_DCD)
1159 mctrl |= TIOCM_CAR;
1160
1161 return mctrl;
1162}
1163
1164static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1165{
1166 u32 val;
1167 u32 mode_reg;
1168 struct cdns_uart *cdns_uart_data = port->private_data;
1169
1170 if (cdns_uart_data->cts_override)
1171 return;
1172
1173 val = readl(port->membase + CDNS_UART_MODEMCR);
1174 mode_reg = readl(port->membase + CDNS_UART_MR);
1175
1176 val &= ~(CDNS_UART_MODEMCR_RTS | CDNS_UART_MODEMCR_DTR);
1177 mode_reg &= ~CDNS_UART_MR_CHMODE_MASK;
1178
1179 if (mctrl & TIOCM_RTS)
1180 val |= CDNS_UART_MODEMCR_RTS;
1181 if (cdns_uart_data->gpiod_rts)
1182 gpiod_set_value(cdns_uart_data->gpiod_rts, !(mctrl & TIOCM_RTS));
1183 if (mctrl & TIOCM_DTR)
1184 val |= CDNS_UART_MODEMCR_DTR;
1185 if (mctrl & TIOCM_LOOP)
1186 mode_reg |= CDNS_UART_MR_CHMODE_L_LOOP;
1187 else
1188 mode_reg |= CDNS_UART_MR_CHMODE_NORM;
1189
1190 writel(val, port->membase + CDNS_UART_MODEMCR);
1191 writel(mode_reg, port->membase + CDNS_UART_MR);
1192}
1193
1194#ifdef CONFIG_CONSOLE_POLL
1195static int cdns_uart_poll_get_char(struct uart_port *port)
1196{
1197 int c;
1198 unsigned long flags;
1199
1200 uart_port_lock_irqsave(port, &flags);
1201
1202 /* Check if FIFO is empty */
1203 if (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_RXEMPTY)
1204 c = NO_POLL_CHAR;
1205 else /* Read a character */
1206 c = (unsigned char) readl(port->membase + CDNS_UART_FIFO);
1207
1208 uart_port_unlock_irqrestore(port, flags);
1209
1210 return c;
1211}
1212
1213static void cdns_uart_poll_put_char(struct uart_port *port, unsigned char c)
1214{
1215 unsigned long flags;
1216
1217 uart_port_lock_irqsave(port, &flags);
1218
1219 /* Wait until FIFO is empty */
1220 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1221 cpu_relax();
1222
1223 /* Write a character */
1224 writel(c, port->membase + CDNS_UART_FIFO);
1225
1226 /* Wait until FIFO is empty */
1227 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1228 cpu_relax();
1229
1230 uart_port_unlock_irqrestore(port, flags);
1231}
1232#endif
1233
1234static void cdns_uart_pm(struct uart_port *port, unsigned int state,
1235 unsigned int oldstate)
1236{
1237 switch (state) {
1238 case UART_PM_STATE_OFF:
1239 pm_runtime_mark_last_busy(port->dev);
1240 pm_runtime_put_autosuspend(port->dev);
1241 break;
1242 default:
1243 pm_runtime_get_sync(port->dev);
1244 break;
1245 }
1246}
1247
1248static const struct uart_ops cdns_uart_ops = {
1249 .set_mctrl = cdns_uart_set_mctrl,
1250 .get_mctrl = cdns_uart_get_mctrl,
1251 .start_tx = cdns_uart_start_tx,
1252 .stop_tx = cdns_uart_stop_tx,
1253 .stop_rx = cdns_uart_stop_rx,
1254 .tx_empty = cdns_uart_tx_empty,
1255 .break_ctl = cdns_uart_break_ctl,
1256 .set_termios = cdns_uart_set_termios,
1257 .startup = cdns_uart_startup,
1258 .shutdown = cdns_uart_shutdown,
1259 .pm = cdns_uart_pm,
1260 .type = cdns_uart_type,
1261 .verify_port = cdns_uart_verify_port,
1262 .request_port = cdns_uart_request_port,
1263 .release_port = cdns_uart_release_port,
1264 .config_port = cdns_uart_config_port,
1265#ifdef CONFIG_CONSOLE_POLL
1266 .poll_get_char = cdns_uart_poll_get_char,
1267 .poll_put_char = cdns_uart_poll_put_char,
1268#endif
1269};
1270
1271static struct uart_driver cdns_uart_uart_driver;
1272
1273#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1274/**
1275 * cdns_uart_console_putchar - write the character to the FIFO buffer
1276 * @port: Handle to the uart port structure
1277 * @ch: Character to be written
1278 */
1279static void cdns_uart_console_putchar(struct uart_port *port, unsigned char ch)
1280{
1281 unsigned int ctrl_reg;
1282 unsigned long timeout;
1283
1284 timeout = jiffies + msecs_to_jiffies(1000);
1285 while (1) {
1286 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1287 if (!(ctrl_reg & CDNS_UART_CR_TX_DIS))
1288 break;
1289 if (time_after(jiffies, timeout)) {
1290 dev_warn(port->dev,
1291 "timeout waiting for Enable\n");
1292 return;
1293 }
1294 cpu_relax();
1295 }
1296
1297 timeout = jiffies + msecs_to_jiffies(1000);
1298 while (1) {
1299 ctrl_reg = readl(port->membase + CDNS_UART_SR);
1300
1301 if (!(ctrl_reg & CDNS_UART_SR_TXFULL))
1302 break;
1303 if (time_after(jiffies, timeout)) {
1304 dev_warn(port->dev,
1305 "timeout waiting for TX fifo\n");
1306 return;
1307 }
1308 cpu_relax();
1309 }
1310 writel(ch, port->membase + CDNS_UART_FIFO);
1311}
1312
1313static void cdns_early_write(struct console *con, const char *s,
1314 unsigned int n)
1315{
1316 struct earlycon_device *dev = con->data;
1317
1318 uart_console_write(&dev->port, s, n, cdns_uart_console_putchar);
1319}
1320
1321static int __init cdns_early_console_setup(struct earlycon_device *device,
1322 const char *opt)
1323{
1324 struct uart_port *port = &device->port;
1325
1326 if (!port->membase)
1327 return -ENODEV;
1328
1329 /* initialise control register */
1330 writel(CDNS_UART_CR_TX_EN|CDNS_UART_CR_TXRST|CDNS_UART_CR_RXRST,
1331 port->membase + CDNS_UART_CR);
1332
1333 /* only set baud if specified on command line - otherwise
1334 * assume it has been initialized by a boot loader.
1335 */
1336 if (port->uartclk && device->baud) {
1337 u32 cd = 0, bdiv = 0;
1338 u32 mr;
1339 int div8;
1340
1341 cdns_uart_calc_baud_divs(port->uartclk, device->baud,
1342 &bdiv, &cd, &div8);
1343 mr = CDNS_UART_MR_PARITY_NONE;
1344 if (div8)
1345 mr |= CDNS_UART_MR_CLKSEL;
1346
1347 writel(mr, port->membase + CDNS_UART_MR);
1348 writel(cd, port->membase + CDNS_UART_BAUDGEN);
1349 writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
1350 }
1351
1352 device->con->write = cdns_early_write;
1353
1354 return 0;
1355}
1356OF_EARLYCON_DECLARE(cdns, "xlnx,xuartps", cdns_early_console_setup);
1357OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p8", cdns_early_console_setup);
1358OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p12", cdns_early_console_setup);
1359OF_EARLYCON_DECLARE(cdns, "xlnx,zynqmp-uart", cdns_early_console_setup);
1360
1361
1362/* Static pointer to console port */
1363static struct uart_port *console_port;
1364
1365/**
1366 * cdns_uart_console_write - perform write operation
1367 * @co: Console handle
1368 * @s: Pointer to character array
1369 * @count: No of characters
1370 */
1371static void cdns_uart_console_write(struct console *co, const char *s,
1372 unsigned int count)
1373{
1374 struct uart_port *port = console_port;
1375 unsigned long flags;
1376 unsigned int imr, ctrl;
1377 int locked = 1;
1378
1379 if (oops_in_progress)
1380 locked = uart_port_trylock_irqsave(port, &flags);
1381 else
1382 uart_port_lock_irqsave(port, &flags);
1383
1384 /* save and disable interrupt */
1385 imr = readl(port->membase + CDNS_UART_IMR);
1386 writel(imr, port->membase + CDNS_UART_IDR);
1387
1388 /*
1389 * Make sure that the tx part is enabled. Set the TX enable bit and
1390 * clear the TX disable bit to enable the transmitter.
1391 */
1392 ctrl = readl(port->membase + CDNS_UART_CR);
1393 ctrl &= ~CDNS_UART_CR_TX_DIS;
1394 ctrl |= CDNS_UART_CR_TX_EN;
1395 writel(ctrl, port->membase + CDNS_UART_CR);
1396
1397 uart_console_write(port, s, count, cdns_uart_console_putchar);
1398 while (cdns_uart_tx_empty(port) != TIOCSER_TEMT)
1399 cpu_relax();
1400
1401 /* restore interrupt state */
1402 writel(imr, port->membase + CDNS_UART_IER);
1403
1404 if (locked)
1405 uart_port_unlock_irqrestore(port, flags);
1406}
1407
1408/**
1409 * cdns_uart_console_setup - Initialize the uart to default config
1410 * @co: Console handle
1411 * @options: Initial settings of uart
1412 *
1413 * Return: 0 on success, negative errno otherwise.
1414 */
1415static int cdns_uart_console_setup(struct console *co, char *options)
1416{
1417 struct uart_port *port = console_port;
1418
1419 int baud = 9600;
1420 int bits = 8;
1421 int parity = 'n';
1422 int flow = 'n';
1423 unsigned long time_out;
1424
1425 if (!port->membase) {
1426 pr_debug("console on " CDNS_UART_TTY_NAME "%i not present\n",
1427 co->index);
1428 return -ENODEV;
1429 }
1430
1431 if (options)
1432 uart_parse_options(options, &baud, &parity, &bits, &flow);
1433
1434 /* Wait for tx_empty before setting up the console */
1435 time_out = jiffies + usecs_to_jiffies(TX_TIMEOUT);
1436
1437 while (time_before(jiffies, time_out) &&
1438 cdns_uart_tx_empty(port) != TIOCSER_TEMT)
1439 cpu_relax();
1440
1441 return uart_set_options(port, co, baud, parity, bits, flow);
1442}
1443
1444static struct console cdns_uart_console = {
1445 .name = CDNS_UART_TTY_NAME,
1446 .write = cdns_uart_console_write,
1447 .device = uart_console_device,
1448 .setup = cdns_uart_console_setup,
1449 .flags = CON_PRINTBUFFER,
1450 .index = -1, /* Specified on the cmdline (e.g. console=ttyPS ) */
1451 .data = &cdns_uart_uart_driver,
1452};
1453#endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */
1454
1455#ifdef CONFIG_PM_SLEEP
1456/**
1457 * cdns_uart_suspend - suspend event
1458 * @device: Pointer to the device structure
1459 *
1460 * Return: 0
1461 */
1462static int cdns_uart_suspend(struct device *device)
1463{
1464 struct uart_port *port = dev_get_drvdata(device);
1465 int may_wake;
1466
1467 may_wake = device_may_wakeup(device);
1468
1469 if (console_suspend_enabled && uart_console(port) && may_wake) {
1470 unsigned long flags;
1471
1472 uart_port_lock_irqsave(port, &flags);
1473 /* Empty the receive FIFO 1st before making changes */
1474 while (!(readl(port->membase + CDNS_UART_SR) &
1475 CDNS_UART_SR_RXEMPTY))
1476 readl(port->membase + CDNS_UART_FIFO);
1477 /* set RX trigger level to 1 */
1478 writel(1, port->membase + CDNS_UART_RXWM);
1479 /* disable RX timeout interrups */
1480 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IDR);
1481 uart_port_unlock_irqrestore(port, flags);
1482 }
1483
1484 /*
1485 * Call the API provided in serial_core.c file which handles
1486 * the suspend.
1487 */
1488 return uart_suspend_port(&cdns_uart_uart_driver, port);
1489}
1490
1491/**
1492 * cdns_uart_resume - Resume after a previous suspend
1493 * @device: Pointer to the device structure
1494 *
1495 * Return: 0
1496 */
1497static int cdns_uart_resume(struct device *device)
1498{
1499 struct uart_port *port = dev_get_drvdata(device);
1500 struct cdns_uart *cdns_uart = port->private_data;
1501 unsigned long flags;
1502 u32 ctrl_reg;
1503 int may_wake;
1504 int ret;
1505
1506 may_wake = device_may_wakeup(device);
1507
1508 if (console_suspend_enabled && uart_console(port) && !may_wake) {
1509 ret = clk_enable(cdns_uart->pclk);
1510 if (ret)
1511 return ret;
1512
1513 ret = clk_enable(cdns_uart->uartclk);
1514 if (ret) {
1515 clk_disable(cdns_uart->pclk);
1516 return ret;
1517 }
1518
1519 uart_port_lock_irqsave(port, &flags);
1520
1521 /* Set TX/RX Reset */
1522 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1523 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
1524 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1525 while (readl(port->membase + CDNS_UART_CR) &
1526 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
1527 cpu_relax();
1528
1529 /* restore rx timeout value */
1530 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
1531 /* Enable Tx/Rx */
1532 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1533 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
1534 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
1535 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1536
1537 clk_disable(cdns_uart->uartclk);
1538 clk_disable(cdns_uart->pclk);
1539 uart_port_unlock_irqrestore(port, flags);
1540 } else {
1541 uart_port_lock_irqsave(port, &flags);
1542 /* restore original rx trigger level */
1543 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
1544 /* enable RX timeout interrupt */
1545 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IER);
1546 uart_port_unlock_irqrestore(port, flags);
1547 }
1548
1549 return uart_resume_port(&cdns_uart_uart_driver, port);
1550}
1551#endif /* ! CONFIG_PM_SLEEP */
1552static int __maybe_unused cdns_runtime_suspend(struct device *dev)
1553{
1554 struct uart_port *port = dev_get_drvdata(dev);
1555 struct cdns_uart *cdns_uart = port->private_data;
1556
1557 clk_disable(cdns_uart->uartclk);
1558 clk_disable(cdns_uart->pclk);
1559 return 0;
1560};
1561
1562static int __maybe_unused cdns_runtime_resume(struct device *dev)
1563{
1564 struct uart_port *port = dev_get_drvdata(dev);
1565 struct cdns_uart *cdns_uart = port->private_data;
1566 int ret;
1567
1568 ret = clk_enable(cdns_uart->pclk);
1569 if (ret)
1570 return ret;
1571
1572 ret = clk_enable(cdns_uart->uartclk);
1573 if (ret) {
1574 clk_disable(cdns_uart->pclk);
1575 return ret;
1576 }
1577 return 0;
1578};
1579
1580static const struct dev_pm_ops cdns_uart_dev_pm_ops = {
1581 SET_SYSTEM_SLEEP_PM_OPS(cdns_uart_suspend, cdns_uart_resume)
1582 SET_RUNTIME_PM_OPS(cdns_runtime_suspend,
1583 cdns_runtime_resume, NULL)
1584};
1585
1586static const struct cdns_platform_data zynqmp_uart_def = {
1587 .quirks = CDNS_UART_RXBS_SUPPORT, };
1588
1589/* Match table for of_platform binding */
1590static const struct of_device_id cdns_uart_of_match[] = {
1591 { .compatible = "xlnx,xuartps", },
1592 { .compatible = "cdns,uart-r1p8", },
1593 { .compatible = "cdns,uart-r1p12", .data = &zynqmp_uart_def },
1594 { .compatible = "xlnx,zynqmp-uart", .data = &zynqmp_uart_def },
1595 {}
1596};
1597MODULE_DEVICE_TABLE(of, cdns_uart_of_match);
1598
1599/* Temporary variable for storing number of instances */
1600static int instances;
1601
1602/**
1603 * cdns_rs485_config - Called when an application calls TIOCSRS485 ioctl.
1604 * @port: Pointer to the uart_port structure
1605 * @termios: Pointer to the ktermios structure
1606 * @rs485: Pointer to the serial_rs485 structure
1607 *
1608 * Return: 0
1609 */
1610static int cdns_rs485_config(struct uart_port *port, struct ktermios *termios,
1611 struct serial_rs485 *rs485)
1612{
1613 u32 val;
1614 struct cdns_uart *cdns_uart = port->private_data;
1615
1616 if (rs485->flags & SER_RS485_ENABLED) {
1617 dev_dbg(port->dev, "Setting UART to RS485\n");
1618 /* Make sure auto RTS is disabled */
1619 val = readl(port->membase + CDNS_UART_MODEMCR);
1620 val &= ~CDNS_UART_MODEMCR_FCM;
1621 writel(val, port->membase + CDNS_UART_MODEMCR);
1622
1623 /* Timer setup */
1624 hrtimer_setup(&cdns_uart->tx_timer, &cdns_rs485_tx_callback, CLOCK_MONOTONIC,
1625 HRTIMER_MODE_REL);
1626
1627 /* Disable transmitter and make Rx setup*/
1628 cdns_uart_stop_tx(port);
1629 } else {
1630 hrtimer_cancel(&cdns_uart->tx_timer);
1631 }
1632 return 0;
1633}
1634
1635/**
1636 * cdns_uart_probe - Platform driver probe
1637 * @pdev: Pointer to the platform device structure
1638 *
1639 * Return: 0 on success, negative errno otherwise
1640 */
1641static int cdns_uart_probe(struct platform_device *pdev)
1642{
1643 int rc, id, irq;
1644 struct uart_port *port;
1645 struct resource *res;
1646 struct cdns_uart *cdns_uart_data;
1647 const struct of_device_id *match;
1648
1649 cdns_uart_data = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_data),
1650 GFP_KERNEL);
1651 if (!cdns_uart_data)
1652 return -ENOMEM;
1653 port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
1654 if (!port)
1655 return -ENOMEM;
1656
1657 /* Look for a serialN alias */
1658 id = of_alias_get_id(pdev->dev.of_node, "serial");
1659 if (id < 0)
1660 id = 0;
1661
1662 if (id >= CDNS_UART_NR_PORTS) {
1663 dev_err(&pdev->dev, "Cannot get uart_port structure\n");
1664 return -ENODEV;
1665 }
1666
1667 if (!cdns_uart_uart_driver.state) {
1668 cdns_uart_uart_driver.owner = THIS_MODULE;
1669 cdns_uart_uart_driver.driver_name = CDNS_UART_NAME;
1670 cdns_uart_uart_driver.dev_name = CDNS_UART_TTY_NAME;
1671 cdns_uart_uart_driver.major = CDNS_UART_MAJOR;
1672 cdns_uart_uart_driver.minor = CDNS_UART_MINOR;
1673 cdns_uart_uart_driver.nr = CDNS_UART_NR_PORTS;
1674#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1675 cdns_uart_uart_driver.cons = &cdns_uart_console;
1676#endif
1677
1678 rc = uart_register_driver(&cdns_uart_uart_driver);
1679 if (rc < 0) {
1680 dev_err(&pdev->dev, "Failed to register driver\n");
1681 return rc;
1682 }
1683 }
1684
1685 match = of_match_node(cdns_uart_of_match, pdev->dev.of_node);
1686 if (match && match->data) {
1687 const struct cdns_platform_data *data = match->data;
1688
1689 cdns_uart_data->quirks = data->quirks;
1690 }
1691
1692 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "pclk");
1693 if (PTR_ERR(cdns_uart_data->pclk) == -EPROBE_DEFER) {
1694 rc = PTR_ERR(cdns_uart_data->pclk);
1695 goto err_out_unregister_driver;
1696 }
1697
1698 if (IS_ERR(cdns_uart_data->pclk)) {
1699 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "aper_clk");
1700 if (IS_ERR(cdns_uart_data->pclk)) {
1701 rc = PTR_ERR(cdns_uart_data->pclk);
1702 goto err_out_unregister_driver;
1703 }
1704 dev_err(&pdev->dev, "clock name 'aper_clk' is deprecated.\n");
1705 }
1706
1707 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "uart_clk");
1708 if (PTR_ERR(cdns_uart_data->uartclk) == -EPROBE_DEFER) {
1709 rc = PTR_ERR(cdns_uart_data->uartclk);
1710 goto err_out_unregister_driver;
1711 }
1712
1713 if (IS_ERR(cdns_uart_data->uartclk)) {
1714 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "ref_clk");
1715 if (IS_ERR(cdns_uart_data->uartclk)) {
1716 rc = PTR_ERR(cdns_uart_data->uartclk);
1717 goto err_out_unregister_driver;
1718 }
1719 dev_err(&pdev->dev, "clock name 'ref_clk' is deprecated.\n");
1720 }
1721
1722 cdns_uart_data->rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
1723 if (IS_ERR(cdns_uart_data->rstc)) {
1724 rc = PTR_ERR(cdns_uart_data->rstc);
1725 dev_err_probe(&pdev->dev, rc, "Cannot get UART reset\n");
1726 goto err_out_unregister_driver;
1727 }
1728
1729 rc = clk_prepare_enable(cdns_uart_data->pclk);
1730 if (rc) {
1731 dev_err(&pdev->dev, "Unable to enable pclk clock.\n");
1732 goto err_out_unregister_driver;
1733 }
1734 rc = clk_prepare_enable(cdns_uart_data->uartclk);
1735 if (rc) {
1736 dev_err(&pdev->dev, "Unable to enable device clock.\n");
1737 goto err_out_clk_dis_pclk;
1738 }
1739
1740 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1741 if (!res) {
1742 rc = -ENODEV;
1743 goto err_out_clk_disable;
1744 }
1745
1746 irq = platform_get_irq(pdev, 0);
1747 if (irq < 0) {
1748 rc = irq;
1749 goto err_out_clk_disable;
1750 }
1751
1752#ifdef CONFIG_COMMON_CLK
1753 cdns_uart_data->clk_rate_change_nb.notifier_call =
1754 cdns_uart_clk_notifier_cb;
1755 if (clk_notifier_register(cdns_uart_data->uartclk,
1756 &cdns_uart_data->clk_rate_change_nb))
1757 dev_warn(&pdev->dev, "Unable to register clock notifier.\n");
1758#endif
1759
1760 /* At this point, we've got an empty uart_port struct, initialize it */
1761 spin_lock_init(&port->lock);
1762 port->type = PORT_UNKNOWN;
1763 port->iotype = UPIO_MEM32;
1764 port->flags = UPF_BOOT_AUTOCONF;
1765 port->ops = &cdns_uart_ops;
1766 port->fifosize = CDNS_UART_FIFO_SIZE;
1767 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE);
1768 port->line = id;
1769
1770 /*
1771 * Register the port.
1772 * This function also registers this device with the tty layer
1773 * and triggers invocation of the config_port() entry point.
1774 */
1775 port->mapbase = res->start;
1776 port->mapsize = resource_size(res);
1777 port->irq = irq;
1778 port->dev = &pdev->dev;
1779 port->uartclk = clk_get_rate(cdns_uart_data->uartclk);
1780 port->private_data = cdns_uart_data;
1781 port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG |
1782 CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT;
1783 port->rs485_config = cdns_rs485_config;
1784 port->rs485_supported = cdns_rs485_supported;
1785 cdns_uart_data->port = port;
1786 platform_set_drvdata(pdev, port);
1787
1788 rc = uart_get_rs485_mode(port);
1789 if (rc)
1790 goto err_out_clk_notifier;
1791
1792 cdns_uart_data->gpiod_rts = devm_gpiod_get_optional(&pdev->dev, "rts",
1793 GPIOD_OUT_LOW);
1794 if (IS_ERR(cdns_uart_data->gpiod_rts)) {
1795 rc = PTR_ERR(cdns_uart_data->gpiod_rts);
1796 dev_err(port->dev, "xuartps: devm_gpiod_get_optional failed\n");
1797 goto err_out_clk_notifier;
1798 }
1799
1800 pm_runtime_use_autosuspend(&pdev->dev);
1801 pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT);
1802 pm_runtime_set_active(&pdev->dev);
1803 pm_runtime_enable(&pdev->dev);
1804 device_init_wakeup(port->dev, true);
1805
1806#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1807 /*
1808 * If console hasn't been found yet try to assign this port
1809 * because it is required to be assigned for console setup function.
1810 * If register_console() don't assign value, then console_port pointer
1811 * is cleanup.
1812 */
1813 if (!console_port) {
1814 cdns_uart_console.index = id;
1815 console_port = port;
1816 }
1817#endif
1818 if (cdns_uart_data->port->rs485.flags & SER_RS485_ENABLED)
1819 cdns_rs485_rx_setup(cdns_uart_data);
1820
1821 rc = uart_add_one_port(&cdns_uart_uart_driver, port);
1822 if (rc) {
1823 dev_err(&pdev->dev,
1824 "uart_add_one_port() failed; err=%i\n", rc);
1825 goto err_out_pm_disable;
1826 }
1827
1828#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1829 /* This is not port which is used for console that's why clean it up */
1830 if (console_port == port &&
1831 !console_is_registered(cdns_uart_uart_driver.cons)) {
1832 console_port = NULL;
1833 cdns_uart_console.index = -1;
1834 }
1835#endif
1836
1837 cdns_uart_data->cts_override = of_property_read_bool(pdev->dev.of_node,
1838 "cts-override");
1839
1840 instances++;
1841
1842 return 0;
1843
1844err_out_pm_disable:
1845 pm_runtime_disable(&pdev->dev);
1846 pm_runtime_set_suspended(&pdev->dev);
1847 pm_runtime_dont_use_autosuspend(&pdev->dev);
1848err_out_clk_notifier:
1849#ifdef CONFIG_COMMON_CLK
1850 clk_notifier_unregister(cdns_uart_data->uartclk,
1851 &cdns_uart_data->clk_rate_change_nb);
1852#endif
1853err_out_clk_disable:
1854 clk_disable_unprepare(cdns_uart_data->uartclk);
1855err_out_clk_dis_pclk:
1856 clk_disable_unprepare(cdns_uart_data->pclk);
1857err_out_unregister_driver:
1858 if (!instances)
1859 uart_unregister_driver(&cdns_uart_uart_driver);
1860 return rc;
1861}
1862
1863/**
1864 * cdns_uart_remove - called when the platform driver is unregistered
1865 * @pdev: Pointer to the platform device structure
1866 */
1867static void cdns_uart_remove(struct platform_device *pdev)
1868{
1869 struct uart_port *port = platform_get_drvdata(pdev);
1870 struct cdns_uart *cdns_uart_data = port->private_data;
1871
1872 /* Remove the cdns_uart port from the serial core */
1873#ifdef CONFIG_COMMON_CLK
1874 clk_notifier_unregister(cdns_uart_data->uartclk,
1875 &cdns_uart_data->clk_rate_change_nb);
1876#endif
1877 uart_remove_one_port(&cdns_uart_uart_driver, port);
1878 port->mapbase = 0;
1879 clk_disable_unprepare(cdns_uart_data->uartclk);
1880 clk_disable_unprepare(cdns_uart_data->pclk);
1881 pm_runtime_disable(&pdev->dev);
1882 pm_runtime_set_suspended(&pdev->dev);
1883 pm_runtime_dont_use_autosuspend(&pdev->dev);
1884 device_init_wakeup(&pdev->dev, false);
1885
1886#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1887 if (console_port == port)
1888 console_port = NULL;
1889#endif
1890 reset_control_assert(cdns_uart_data->rstc);
1891
1892 if (!--instances)
1893 uart_unregister_driver(&cdns_uart_uart_driver);
1894}
1895
1896static struct platform_driver cdns_uart_platform_driver = {
1897 .probe = cdns_uart_probe,
1898 .remove = cdns_uart_remove,
1899 .driver = {
1900 .name = CDNS_UART_NAME,
1901 .of_match_table = cdns_uart_of_match,
1902 .pm = &cdns_uart_dev_pm_ops,
1903 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_XILINX_PS_UART),
1904 },
1905};
1906
1907static int __init cdns_uart_init(void)
1908{
1909 /* Register the platform driver */
1910 return platform_driver_register(&cdns_uart_platform_driver);
1911}
1912
1913static void __exit cdns_uart_exit(void)
1914{
1915 /* Unregister the platform driver */
1916 platform_driver_unregister(&cdns_uart_platform_driver);
1917}
1918
1919arch_initcall(cdns_uart_init);
1920module_exit(cdns_uart_exit);
1921
1922MODULE_DESCRIPTION("Driver for Cadence UART");
1923MODULE_AUTHOR("Xilinx Inc.");
1924MODULE_LICENSE("GPL");