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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * core.c - ChipIdea USB IP core family device controller
4 *
5 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
6 * Copyright (C) 2020 NXP
7 *
8 * Author: David Lopo
9 * Peter Chen <[email protected]>
10 *
11 * Main Features:
12 * - Four transfers are supported, usbtest is passed
13 * - USB Certification for gadget: CH9 and Mass Storage are passed
14 * - Low power mode
15 * - USB wakeup
16 */
17#include <linux/delay.h>
18#include <linux/device.h>
19#include <linux/dma-mapping.h>
20#include <linux/extcon.h>
21#include <linux/phy/phy.h>
22#include <linux/platform_device.h>
23#include <linux/module.h>
24#include <linux/idr.h>
25#include <linux/interrupt.h>
26#include <linux/io.h>
27#include <linux/kernel.h>
28#include <linux/slab.h>
29#include <linux/pm_runtime.h>
30#include <linux/pm_domain.h>
31#include <linux/pinctrl/consumer.h>
32#include <linux/usb/ch9.h>
33#include <linux/usb/gadget.h>
34#include <linux/usb/otg.h>
35#include <linux/usb/chipidea.h>
36#include <linux/usb/of.h>
37#include <linux/of.h>
38#include <linux/regulator/consumer.h>
39#include <linux/usb/ehci_def.h>
40
41#include "ci.h"
42#include "udc.h"
43#include "bits.h"
44#include "host.h"
45#include "otg.h"
46#include "otg_fsm.h"
47
48/* Controller register map */
49static const u8 ci_regs_nolpm[] = {
50 [CAP_CAPLENGTH] = 0x00U,
51 [CAP_HCCPARAMS] = 0x08U,
52 [CAP_DCCPARAMS] = 0x24U,
53 [CAP_TESTMODE] = 0x38U,
54 [OP_USBCMD] = 0x00U,
55 [OP_USBSTS] = 0x04U,
56 [OP_USBINTR] = 0x08U,
57 [OP_FRINDEX] = 0x0CU,
58 [OP_DEVICEADDR] = 0x14U,
59 [OP_ENDPTLISTADDR] = 0x18U,
60 [OP_TTCTRL] = 0x1CU,
61 [OP_BURSTSIZE] = 0x20U,
62 [OP_ULPI_VIEWPORT] = 0x30U,
63 [OP_PORTSC] = 0x44U,
64 [OP_DEVLC] = 0x84U,
65 [OP_OTGSC] = 0x64U,
66 [OP_USBMODE] = 0x68U,
67 [OP_ENDPTSETUPSTAT] = 0x6CU,
68 [OP_ENDPTPRIME] = 0x70U,
69 [OP_ENDPTFLUSH] = 0x74U,
70 [OP_ENDPTSTAT] = 0x78U,
71 [OP_ENDPTCOMPLETE] = 0x7CU,
72 [OP_ENDPTCTRL] = 0x80U,
73};
74
75static const u8 ci_regs_lpm[] = {
76 [CAP_CAPLENGTH] = 0x00U,
77 [CAP_HCCPARAMS] = 0x08U,
78 [CAP_DCCPARAMS] = 0x24U,
79 [CAP_TESTMODE] = 0xFCU,
80 [OP_USBCMD] = 0x00U,
81 [OP_USBSTS] = 0x04U,
82 [OP_USBINTR] = 0x08U,
83 [OP_FRINDEX] = 0x0CU,
84 [OP_DEVICEADDR] = 0x14U,
85 [OP_ENDPTLISTADDR] = 0x18U,
86 [OP_TTCTRL] = 0x1CU,
87 [OP_BURSTSIZE] = 0x20U,
88 [OP_ULPI_VIEWPORT] = 0x30U,
89 [OP_PORTSC] = 0x44U,
90 [OP_DEVLC] = 0x84U,
91 [OP_OTGSC] = 0xC4U,
92 [OP_USBMODE] = 0xC8U,
93 [OP_ENDPTSETUPSTAT] = 0xD8U,
94 [OP_ENDPTPRIME] = 0xDCU,
95 [OP_ENDPTFLUSH] = 0xE0U,
96 [OP_ENDPTSTAT] = 0xE4U,
97 [OP_ENDPTCOMPLETE] = 0xE8U,
98 [OP_ENDPTCTRL] = 0xECU,
99};
100
101static void hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm)
102{
103 int i;
104
105 for (i = 0; i < OP_ENDPTCTRL; i++)
106 ci->hw_bank.regmap[i] =
107 (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) +
108 (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);
109
110 for (; i <= OP_LAST; i++)
111 ci->hw_bank.regmap[i] = ci->hw_bank.op +
112 4 * (i - OP_ENDPTCTRL) +
113 (is_lpm
114 ? ci_regs_lpm[OP_ENDPTCTRL]
115 : ci_regs_nolpm[OP_ENDPTCTRL]);
116
117}
118
119static enum ci_revision ci_get_revision(struct ci_hdrc *ci)
120{
121 int ver = hw_read_id_reg(ci, ID_ID, VERSION) >> __ffs(VERSION);
122 enum ci_revision rev = CI_REVISION_UNKNOWN;
123
124 if (ver == 0x2) {
125 rev = hw_read_id_reg(ci, ID_ID, REVISION)
126 >> __ffs(REVISION);
127 rev += CI_REVISION_20;
128 } else if (ver == 0x0) {
129 rev = CI_REVISION_1X;
130 }
131
132 return rev;
133}
134
135/**
136 * hw_read_intr_enable: returns interrupt enable register
137 *
138 * @ci: the controller
139 *
140 * This function returns register data
141 */
142u32 hw_read_intr_enable(struct ci_hdrc *ci)
143{
144 return hw_read(ci, OP_USBINTR, ~0);
145}
146
147/**
148 * hw_read_intr_status: returns interrupt status register
149 *
150 * @ci: the controller
151 *
152 * This function returns register data
153 */
154u32 hw_read_intr_status(struct ci_hdrc *ci)
155{
156 return hw_read(ci, OP_USBSTS, ~0);
157}
158
159/**
160 * hw_port_test_set: writes port test mode (execute without interruption)
161 * @ci: the controller
162 * @mode: new value
163 *
164 * This function returns an error code
165 */
166int hw_port_test_set(struct ci_hdrc *ci, u8 mode)
167{
168 const u8 TEST_MODE_MAX = 7;
169
170 if (mode > TEST_MODE_MAX)
171 return -EINVAL;
172
173 hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC));
174 return 0;
175}
176
177/**
178 * hw_port_test_get: reads port test mode value
179 *
180 * @ci: the controller
181 *
182 * This function returns port test mode value
183 */
184u8 hw_port_test_get(struct ci_hdrc *ci)
185{
186 return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC);
187}
188
189static void hw_wait_phy_stable(void)
190{
191 /*
192 * The phy needs some delay to output the stable status from low
193 * power mode. And for OTGSC, the status inputs are debounced
194 * using a 1 ms time constant, so, delay 2ms for controller to get
195 * the stable status, like vbus and id when the phy leaves low power.
196 */
197 usleep_range(2000, 2500);
198}
199
200/* The PHY enters/leaves low power mode */
201static void ci_hdrc_enter_lpm_common(struct ci_hdrc *ci, bool enable)
202{
203 enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC;
204 bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm)));
205
206 if (enable && !lpm)
207 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
208 PORTSC_PHCD(ci->hw_bank.lpm));
209 else if (!enable && lpm)
210 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
211 0);
212}
213
214static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable)
215{
216 return ci->platdata->enter_lpm(ci, enable);
217}
218
219static int hw_device_init(struct ci_hdrc *ci, void __iomem *base)
220{
221 u32 reg;
222
223 /* bank is a module variable */
224 ci->hw_bank.abs = base;
225
226 ci->hw_bank.cap = ci->hw_bank.abs;
227 ci->hw_bank.cap += ci->platdata->capoffset;
228 ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff);
229
230 hw_alloc_regmap(ci, false);
231 reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
232 __ffs(HCCPARAMS_LEN);
233 ci->hw_bank.lpm = reg;
234 if (reg)
235 hw_alloc_regmap(ci, !!reg);
236 ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs;
237 ci->hw_bank.size += OP_LAST;
238 ci->hw_bank.size /= sizeof(u32);
239
240 reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
241 __ffs(DCCPARAMS_DEN);
242 ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */
243
244 if (ci->hw_ep_max > ENDPT_MAX)
245 return -ENODEV;
246
247 ci_hdrc_enter_lpm(ci, false);
248
249 /* Disable all interrupts bits */
250 hw_write(ci, OP_USBINTR, 0xffffffff, 0);
251
252 /* Clear all interrupts status bits*/
253 hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff);
254
255 ci->rev = ci_get_revision(ci);
256
257 dev_dbg(ci->dev,
258 "revision: %d, lpm: %d; cap: %px op: %px\n",
259 ci->rev, ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);
260
261 /* setup lock mode ? */
262
263 /* ENDPTSETUPSTAT is '0' by default */
264
265 /* HCSPARAMS.bf.ppc SHOULD BE zero for device */
266
267 return 0;
268}
269
270void hw_phymode_configure(struct ci_hdrc *ci)
271{
272 u32 portsc, lpm, sts = 0;
273
274 switch (ci->platdata->phy_mode) {
275 case USBPHY_INTERFACE_MODE_UTMI:
276 portsc = PORTSC_PTS(PTS_UTMI);
277 lpm = DEVLC_PTS(PTS_UTMI);
278 break;
279 case USBPHY_INTERFACE_MODE_UTMIW:
280 portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW;
281 lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW;
282 break;
283 case USBPHY_INTERFACE_MODE_ULPI:
284 portsc = PORTSC_PTS(PTS_ULPI);
285 lpm = DEVLC_PTS(PTS_ULPI);
286 break;
287 case USBPHY_INTERFACE_MODE_SERIAL:
288 portsc = PORTSC_PTS(PTS_SERIAL);
289 lpm = DEVLC_PTS(PTS_SERIAL);
290 sts = 1;
291 break;
292 case USBPHY_INTERFACE_MODE_HSIC:
293 portsc = PORTSC_PTS(PTS_HSIC);
294 lpm = DEVLC_PTS(PTS_HSIC);
295 break;
296 default:
297 return;
298 }
299
300 if (ci->hw_bank.lpm) {
301 hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm);
302 if (sts)
303 hw_write(ci, OP_DEVLC, DEVLC_STS, DEVLC_STS);
304 } else {
305 hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc);
306 if (sts)
307 hw_write(ci, OP_PORTSC, PORTSC_STS, PORTSC_STS);
308 }
309}
310EXPORT_SYMBOL_GPL(hw_phymode_configure);
311
312/**
313 * _ci_usb_phy_init: initialize phy taking in account both phy and usb_phy
314 * interfaces
315 * @ci: the controller
316 *
317 * This function returns an error code if the phy failed to init
318 */
319static int _ci_usb_phy_init(struct ci_hdrc *ci)
320{
321 int ret;
322
323 if (ci->phy) {
324 ret = phy_init(ci->phy);
325 if (ret)
326 return ret;
327
328 ret = phy_power_on(ci->phy);
329 if (ret) {
330 phy_exit(ci->phy);
331 return ret;
332 }
333 } else {
334 ret = usb_phy_init(ci->usb_phy);
335 }
336
337 return ret;
338}
339
340/**
341 * ci_usb_phy_exit: deinitialize phy taking in account both phy and usb_phy
342 * interfaces
343 * @ci: the controller
344 */
345static void ci_usb_phy_exit(struct ci_hdrc *ci)
346{
347 if (ci->platdata->flags & CI_HDRC_OVERRIDE_PHY_CONTROL)
348 return;
349
350 if (ci->phy) {
351 phy_power_off(ci->phy);
352 phy_exit(ci->phy);
353 } else {
354 usb_phy_shutdown(ci->usb_phy);
355 }
356}
357
358/**
359 * ci_usb_phy_init: initialize phy according to different phy type
360 * @ci: the controller
361 *
362 * This function returns an error code if usb_phy_init has failed
363 */
364static int ci_usb_phy_init(struct ci_hdrc *ci)
365{
366 int ret;
367
368 if (ci->platdata->flags & CI_HDRC_OVERRIDE_PHY_CONTROL)
369 return 0;
370
371 switch (ci->platdata->phy_mode) {
372 case USBPHY_INTERFACE_MODE_UTMI:
373 case USBPHY_INTERFACE_MODE_UTMIW:
374 case USBPHY_INTERFACE_MODE_HSIC:
375 ret = _ci_usb_phy_init(ci);
376 if (!ret)
377 hw_wait_phy_stable();
378 else
379 return ret;
380 hw_phymode_configure(ci);
381 break;
382 case USBPHY_INTERFACE_MODE_ULPI:
383 case USBPHY_INTERFACE_MODE_SERIAL:
384 hw_phymode_configure(ci);
385 ret = _ci_usb_phy_init(ci);
386 if (ret)
387 return ret;
388 break;
389 default:
390 ret = _ci_usb_phy_init(ci);
391 if (!ret)
392 hw_wait_phy_stable();
393 }
394
395 return ret;
396}
397
398
399/**
400 * ci_platform_configure: do controller configure
401 * @ci: the controller
402 *
403 */
404void ci_platform_configure(struct ci_hdrc *ci)
405{
406 bool is_device_mode, is_host_mode;
407
408 is_device_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_DC;
409 is_host_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_HC;
410
411 if (is_device_mode) {
412 phy_set_mode(ci->phy, PHY_MODE_USB_DEVICE);
413
414 if (ci->platdata->flags & CI_HDRC_DISABLE_DEVICE_STREAMING)
415 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS,
416 USBMODE_CI_SDIS);
417 }
418
419 if (is_host_mode) {
420 phy_set_mode(ci->phy, PHY_MODE_USB_HOST);
421
422 if (ci->platdata->flags & CI_HDRC_DISABLE_HOST_STREAMING)
423 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS,
424 USBMODE_CI_SDIS);
425 }
426
427 if (ci->platdata->flags & CI_HDRC_FORCE_FULLSPEED) {
428 if (ci->hw_bank.lpm)
429 hw_write(ci, OP_DEVLC, DEVLC_PFSC, DEVLC_PFSC);
430 else
431 hw_write(ci, OP_PORTSC, PORTSC_PFSC, PORTSC_PFSC);
432 }
433
434 if (ci->platdata->flags & CI_HDRC_SET_NON_ZERO_TTHA)
435 hw_write(ci, OP_TTCTRL, TTCTRL_TTHA_MASK, TTCTRL_TTHA);
436
437 hw_write(ci, OP_USBCMD, 0xff0000, ci->platdata->itc_setting << 16);
438
439 if (ci->platdata->flags & CI_HDRC_OVERRIDE_AHB_BURST)
440 hw_write_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK,
441 ci->platdata->ahb_burst_config);
442
443 /* override burst size, take effect only when ahb_burst_config is 0 */
444 if (!hw_read_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK)) {
445 if (ci->platdata->flags & CI_HDRC_OVERRIDE_TX_BURST)
446 hw_write(ci, OP_BURSTSIZE, TX_BURST_MASK,
447 ci->platdata->tx_burst_size << __ffs(TX_BURST_MASK));
448
449 if (ci->platdata->flags & CI_HDRC_OVERRIDE_RX_BURST)
450 hw_write(ci, OP_BURSTSIZE, RX_BURST_MASK,
451 ci->platdata->rx_burst_size);
452 }
453}
454
455/**
456 * hw_controller_reset: do controller reset
457 * @ci: the controller
458 *
459 * This function returns an error code
460 */
461static int hw_controller_reset(struct ci_hdrc *ci)
462{
463 int count = 0;
464
465 hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST);
466 while (hw_read(ci, OP_USBCMD, USBCMD_RST)) {
467 udelay(10);
468 if (count++ > 1000)
469 return -ETIMEDOUT;
470 }
471
472 return 0;
473}
474
475/**
476 * hw_device_reset: resets chip (execute without interruption)
477 * @ci: the controller
478 *
479 * This function returns an error code
480 */
481int hw_device_reset(struct ci_hdrc *ci)
482{
483 int ret;
484
485 /* should flush & stop before reset */
486 hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
487 hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
488
489 ret = hw_controller_reset(ci);
490 if (ret) {
491 dev_err(ci->dev, "error resetting controller, ret=%d\n", ret);
492 return ret;
493 }
494
495 if (ci->platdata->notify_event) {
496 ret = ci->platdata->notify_event(ci,
497 CI_HDRC_CONTROLLER_RESET_EVENT);
498 if (ret)
499 return ret;
500 }
501
502 /* USBMODE should be configured step by step */
503 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
504 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_DC);
505 /* HW >= 2.3 */
506 hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);
507
508 if (hw_read(ci, OP_USBMODE, USBMODE_CM) != USBMODE_CM_DC) {
509 dev_err(ci->dev, "cannot enter in %s device mode\n",
510 ci_role(ci)->name);
511 dev_err(ci->dev, "lpm = %i\n", ci->hw_bank.lpm);
512 return -ENODEV;
513 }
514
515 ci_platform_configure(ci);
516
517 return 0;
518}
519
520static irqreturn_t ci_irq_handler(int irq, void *data)
521{
522 struct ci_hdrc *ci = data;
523 irqreturn_t ret = IRQ_NONE;
524 u32 otgsc = 0;
525
526 if (ci->in_lpm) {
527 /*
528 * If we already have a wakeup irq pending there,
529 * let's just return to wait resume finished firstly.
530 */
531 if (ci->wakeup_int)
532 return IRQ_HANDLED;
533
534 disable_irq_nosync(irq);
535 ci->wakeup_int = true;
536 pm_runtime_get(ci->dev);
537 return IRQ_HANDLED;
538 }
539
540 if (ci->is_otg) {
541 otgsc = hw_read_otgsc(ci, ~0);
542 if (ci_otg_is_fsm_mode(ci)) {
543 ret = ci_otg_fsm_irq(ci);
544 if (ret == IRQ_HANDLED)
545 return ret;
546 }
547
548 /*
549 * Handle id change interrupt, it indicates device/host function
550 * switch.
551 */
552 if ((otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) {
553 ci->id_event = true;
554 /* Clear ID change irq status */
555 hw_write_otgsc(ci, OTGSC_IDIS, OTGSC_IDIS);
556 }
557
558 /*
559 * Handle vbus change interrupt, it indicates device connection
560 * and disconnection events.
561 */
562 if ((otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) {
563 ci->b_sess_valid_event = true;
564 /* Clear BSV irq */
565 hw_write_otgsc(ci, OTGSC_BSVIS, OTGSC_BSVIS);
566 }
567
568 if (ci->id_event || ci->b_sess_valid_event) {
569 ci_otg_queue_work(ci);
570 return IRQ_HANDLED;
571 }
572 }
573
574 /* Handle device/host interrupt */
575 if (ci->role != CI_ROLE_END)
576 ret = ci_role(ci)->irq(ci);
577
578 return ret;
579}
580
581static void ci_irq(struct ci_hdrc *ci)
582{
583 unsigned long flags;
584
585 local_irq_save(flags);
586 ci_irq_handler(ci->irq, ci);
587 local_irq_restore(flags);
588}
589
590static int ci_cable_notifier(struct notifier_block *nb, unsigned long event,
591 void *ptr)
592{
593 struct ci_hdrc_cable *cbl = container_of(nb, struct ci_hdrc_cable, nb);
594 struct ci_hdrc *ci = cbl->ci;
595
596 cbl->connected = event;
597 cbl->changed = true;
598
599 ci_irq(ci);
600 return NOTIFY_DONE;
601}
602
603static enum usb_role ci_usb_role_switch_get(struct usb_role_switch *sw)
604{
605 struct ci_hdrc *ci = usb_role_switch_get_drvdata(sw);
606 enum usb_role role;
607 unsigned long flags;
608
609 spin_lock_irqsave(&ci->lock, flags);
610 role = ci_role_to_usb_role(ci);
611 spin_unlock_irqrestore(&ci->lock, flags);
612
613 return role;
614}
615
616static int ci_usb_role_switch_set(struct usb_role_switch *sw,
617 enum usb_role role)
618{
619 struct ci_hdrc *ci = usb_role_switch_get_drvdata(sw);
620 struct ci_hdrc_cable *cable;
621
622 cable = &ci->platdata->id_extcon;
623 cable->changed = true;
624 cable->connected = (role == USB_ROLE_HOST);
625
626 cable = &ci->platdata->vbus_extcon;
627 cable->changed = true;
628 cable->connected = (role == USB_ROLE_DEVICE);
629
630 ci_irq(ci);
631 return 0;
632}
633
634static enum ci_role ci_get_role(struct ci_hdrc *ci)
635{
636 enum ci_role role;
637
638 if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
639 if (ci->is_otg) {
640 role = ci_otg_role(ci);
641 hw_write_otgsc(ci, OTGSC_IDIE, OTGSC_IDIE);
642 } else {
643 /*
644 * If the controller is not OTG capable, but support
645 * role switch, the defalt role is gadget, and the
646 * user can switch it through debugfs.
647 */
648 role = CI_ROLE_GADGET;
649 }
650 } else {
651 role = ci->roles[CI_ROLE_HOST] ? CI_ROLE_HOST
652 : CI_ROLE_GADGET;
653 }
654
655 return role;
656}
657
658static int ci_get_platdata(struct device *dev,
659 struct ci_hdrc_platform_data *platdata)
660{
661 struct extcon_dev *ext_vbus, *ext_id;
662 struct ci_hdrc_cable *cable;
663 int ret;
664
665 if (!platdata->phy_mode)
666 platdata->phy_mode = of_usb_get_phy_mode(dev->of_node);
667
668 if (!platdata->dr_mode)
669 platdata->dr_mode = usb_get_dr_mode(dev);
670
671 if (platdata->dr_mode == USB_DR_MODE_UNKNOWN)
672 platdata->dr_mode = USB_DR_MODE_OTG;
673
674 if (platdata->dr_mode != USB_DR_MODE_PERIPHERAL) {
675 /* Get the vbus regulator */
676 platdata->reg_vbus = devm_regulator_get_optional(dev, "vbus");
677 if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) {
678 return -EPROBE_DEFER;
679 } else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) {
680 /* no vbus regulator is needed */
681 platdata->reg_vbus = NULL;
682 } else if (IS_ERR(platdata->reg_vbus)) {
683 dev_err(dev, "Getting regulator error: %ld\n",
684 PTR_ERR(platdata->reg_vbus));
685 return PTR_ERR(platdata->reg_vbus);
686 }
687 /* Get TPL support */
688 if (!platdata->tpl_support)
689 platdata->tpl_support =
690 of_usb_host_tpl_support(dev->of_node);
691 }
692
693 if (platdata->dr_mode == USB_DR_MODE_OTG) {
694 /* We can support HNP and SRP of OTG 2.0 */
695 platdata->ci_otg_caps.otg_rev = 0x0200;
696 platdata->ci_otg_caps.hnp_support = true;
697 platdata->ci_otg_caps.srp_support = true;
698
699 /* Update otg capabilities by DT properties */
700 ret = of_usb_update_otg_caps(dev->of_node,
701 &platdata->ci_otg_caps);
702 if (ret)
703 return ret;
704 }
705
706 if (usb_get_maximum_speed(dev) == USB_SPEED_FULL)
707 platdata->flags |= CI_HDRC_FORCE_FULLSPEED;
708
709 of_property_read_u32(dev->of_node, "phy-clkgate-delay-us",
710 &platdata->phy_clkgate_delay_us);
711
712 platdata->itc_setting = 1;
713
714 of_property_read_u32(dev->of_node, "itc-setting",
715 &platdata->itc_setting);
716
717 ret = of_property_read_u32(dev->of_node, "ahb-burst-config",
718 &platdata->ahb_burst_config);
719 if (!ret) {
720 platdata->flags |= CI_HDRC_OVERRIDE_AHB_BURST;
721 } else if (ret != -EINVAL) {
722 dev_err(dev, "failed to get ahb-burst-config\n");
723 return ret;
724 }
725
726 ret = of_property_read_u32(dev->of_node, "tx-burst-size-dword",
727 &platdata->tx_burst_size);
728 if (!ret) {
729 platdata->flags |= CI_HDRC_OVERRIDE_TX_BURST;
730 } else if (ret != -EINVAL) {
731 dev_err(dev, "failed to get tx-burst-size-dword\n");
732 return ret;
733 }
734
735 ret = of_property_read_u32(dev->of_node, "rx-burst-size-dword",
736 &platdata->rx_burst_size);
737 if (!ret) {
738 platdata->flags |= CI_HDRC_OVERRIDE_RX_BURST;
739 } else if (ret != -EINVAL) {
740 dev_err(dev, "failed to get rx-burst-size-dword\n");
741 return ret;
742 }
743
744 if (of_property_read_bool(dev->of_node, "non-zero-ttctrl-ttha"))
745 platdata->flags |= CI_HDRC_SET_NON_ZERO_TTHA;
746
747 ext_id = ERR_PTR(-ENODEV);
748 ext_vbus = ERR_PTR(-ENODEV);
749 if (of_property_present(dev->of_node, "extcon")) {
750 /* Each one of them is not mandatory */
751 ext_vbus = extcon_get_edev_by_phandle(dev, 0);
752 if (IS_ERR(ext_vbus) && PTR_ERR(ext_vbus) != -ENODEV)
753 return PTR_ERR(ext_vbus);
754
755 ext_id = extcon_get_edev_by_phandle(dev, 1);
756 if (IS_ERR(ext_id) && PTR_ERR(ext_id) != -ENODEV)
757 return PTR_ERR(ext_id);
758 }
759
760 cable = &platdata->vbus_extcon;
761 cable->nb.notifier_call = ci_cable_notifier;
762 cable->edev = ext_vbus;
763
764 if (!IS_ERR(ext_vbus)) {
765 ret = extcon_get_state(cable->edev, EXTCON_USB);
766 if (ret)
767 cable->connected = true;
768 else
769 cable->connected = false;
770 }
771
772 cable = &platdata->id_extcon;
773 cable->nb.notifier_call = ci_cable_notifier;
774 cable->edev = ext_id;
775
776 if (!IS_ERR(ext_id)) {
777 ret = extcon_get_state(cable->edev, EXTCON_USB_HOST);
778 if (ret)
779 cable->connected = true;
780 else
781 cable->connected = false;
782 }
783
784 platdata->pctl = devm_pinctrl_get(dev);
785 if (!IS_ERR(platdata->pctl)) {
786 struct pinctrl_state *p;
787
788 p = pinctrl_lookup_state(platdata->pctl, "default");
789 if (!IS_ERR(p))
790 platdata->pins_default = p;
791
792 p = pinctrl_lookup_state(platdata->pctl, "host");
793 if (!IS_ERR(p))
794 platdata->pins_host = p;
795
796 p = pinctrl_lookup_state(platdata->pctl, "device");
797 if (!IS_ERR(p))
798 platdata->pins_device = p;
799 }
800
801 if (!platdata->enter_lpm)
802 platdata->enter_lpm = ci_hdrc_enter_lpm_common;
803
804 return 0;
805}
806
807static int ci_extcon_register(struct ci_hdrc *ci)
808{
809 struct ci_hdrc_cable *id, *vbus;
810 int ret;
811
812 id = &ci->platdata->id_extcon;
813 id->ci = ci;
814 if (!IS_ERR_OR_NULL(id->edev)) {
815 ret = devm_extcon_register_notifier(ci->dev, id->edev,
816 EXTCON_USB_HOST, &id->nb);
817 if (ret < 0) {
818 dev_err(ci->dev, "register ID failed\n");
819 return ret;
820 }
821 }
822
823 vbus = &ci->platdata->vbus_extcon;
824 vbus->ci = ci;
825 if (!IS_ERR_OR_NULL(vbus->edev)) {
826 ret = devm_extcon_register_notifier(ci->dev, vbus->edev,
827 EXTCON_USB, &vbus->nb);
828 if (ret < 0) {
829 dev_err(ci->dev, "register VBUS failed\n");
830 return ret;
831 }
832 }
833
834 return 0;
835}
836
837static void ci_power_lost_work(struct work_struct *work)
838{
839 struct ci_hdrc *ci = container_of(work, struct ci_hdrc, power_lost_work);
840 enum ci_role role;
841
842 disable_irq_nosync(ci->irq);
843 pm_runtime_get_sync(ci->dev);
844 if (!ci_otg_is_fsm_mode(ci)) {
845 role = ci_get_role(ci);
846
847 if (ci->role != role) {
848 ci_handle_id_switch(ci);
849 } else if (role == CI_ROLE_GADGET) {
850 if (ci->is_otg && hw_read_otgsc(ci, OTGSC_BSV))
851 usb_gadget_vbus_connect(&ci->gadget);
852 }
853 }
854 pm_runtime_put_sync(ci->dev);
855 enable_irq(ci->irq);
856}
857
858static DEFINE_IDA(ci_ida);
859
860struct platform_device *ci_hdrc_add_device(struct device *dev,
861 struct resource *res, int nres,
862 struct ci_hdrc_platform_data *platdata)
863{
864 struct platform_device *pdev;
865 int id, ret;
866
867 ret = ci_get_platdata(dev, platdata);
868 if (ret)
869 return ERR_PTR(ret);
870
871 id = ida_alloc(&ci_ida, GFP_KERNEL);
872 if (id < 0)
873 return ERR_PTR(id);
874
875 pdev = platform_device_alloc("ci_hdrc", id);
876 if (!pdev) {
877 ret = -ENOMEM;
878 goto put_id;
879 }
880
881 pdev->dev.parent = dev;
882 platform_device_set_of_node_from_dev(pdev, dev);
883
884 ret = platform_device_add_resources(pdev, res, nres);
885 if (ret)
886 goto err;
887
888 ret = platform_device_add_data(pdev, platdata, sizeof(*platdata));
889 if (ret)
890 goto err;
891
892 ret = platform_device_add(pdev);
893 if (ret)
894 goto err;
895
896 dev_pm_domain_detach(&pdev->dev, false);
897
898 return pdev;
899
900err:
901 platform_device_put(pdev);
902put_id:
903 ida_free(&ci_ida, id);
904 return ERR_PTR(ret);
905}
906EXPORT_SYMBOL_GPL(ci_hdrc_add_device);
907
908void ci_hdrc_remove_device(struct platform_device *pdev)
909{
910 int id = pdev->id;
911 platform_device_unregister(pdev);
912 ida_free(&ci_ida, id);
913}
914EXPORT_SYMBOL_GPL(ci_hdrc_remove_device);
915
916/**
917 * ci_hdrc_query_available_role: get runtime available operation mode
918 *
919 * The glue layer can get current operation mode (host/peripheral/otg)
920 * This function should be called after ci core device has created.
921 *
922 * @pdev: the platform device of ci core.
923 *
924 * Return runtime usb_dr_mode.
925 */
926enum usb_dr_mode ci_hdrc_query_available_role(struct platform_device *pdev)
927{
928 struct ci_hdrc *ci = platform_get_drvdata(pdev);
929
930 if (!ci)
931 return USB_DR_MODE_UNKNOWN;
932 if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET])
933 return USB_DR_MODE_OTG;
934 else if (ci->roles[CI_ROLE_HOST])
935 return USB_DR_MODE_HOST;
936 else if (ci->roles[CI_ROLE_GADGET])
937 return USB_DR_MODE_PERIPHERAL;
938 else
939 return USB_DR_MODE_UNKNOWN;
940}
941EXPORT_SYMBOL_GPL(ci_hdrc_query_available_role);
942
943static inline void ci_role_destroy(struct ci_hdrc *ci)
944{
945 ci_hdrc_gadget_destroy(ci);
946 ci_hdrc_host_destroy(ci);
947 if (ci->is_otg && ci->roles[CI_ROLE_GADGET])
948 ci_hdrc_otg_destroy(ci);
949}
950
951static void ci_get_otg_capable(struct ci_hdrc *ci)
952{
953 if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG)
954 ci->is_otg = false;
955 else
956 ci->is_otg = (hw_read(ci, CAP_DCCPARAMS,
957 DCCPARAMS_DC | DCCPARAMS_HC)
958 == (DCCPARAMS_DC | DCCPARAMS_HC));
959 if (ci->is_otg) {
960 dev_dbg(ci->dev, "It is OTG capable controller\n");
961 /* Disable and clear all OTG irq */
962 hw_write_otgsc(ci, OTGSC_INT_EN_BITS | OTGSC_INT_STATUS_BITS,
963 OTGSC_INT_STATUS_BITS);
964 }
965}
966
967static ssize_t role_show(struct device *dev, struct device_attribute *attr,
968 char *buf)
969{
970 struct ci_hdrc *ci = dev_get_drvdata(dev);
971
972 if (ci->role != CI_ROLE_END)
973 return sprintf(buf, "%s\n", ci_role(ci)->name);
974
975 return 0;
976}
977
978static ssize_t role_store(struct device *dev,
979 struct device_attribute *attr, const char *buf, size_t n)
980{
981 struct ci_hdrc *ci = dev_get_drvdata(dev);
982 enum ci_role role;
983 int ret;
984
985 if (!(ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET])) {
986 dev_warn(dev, "Current configuration is not dual-role, quit\n");
987 return -EPERM;
988 }
989
990 for (role = CI_ROLE_HOST; role < CI_ROLE_END; role++)
991 if (!strncmp(buf, ci->roles[role]->name,
992 strlen(ci->roles[role]->name)))
993 break;
994
995 if (role == CI_ROLE_END)
996 return -EINVAL;
997
998 mutex_lock(&ci->mutex);
999
1000 if (role == ci->role) {
1001 mutex_unlock(&ci->mutex);
1002 return n;
1003 }
1004
1005 pm_runtime_get_sync(dev);
1006 disable_irq(ci->irq);
1007 ci_role_stop(ci);
1008 ret = ci_role_start(ci, role);
1009 if (!ret && ci->role == CI_ROLE_GADGET)
1010 ci_handle_vbus_change(ci);
1011 enable_irq(ci->irq);
1012 pm_runtime_put_sync(dev);
1013 mutex_unlock(&ci->mutex);
1014
1015 return (ret == 0) ? n : ret;
1016}
1017static DEVICE_ATTR_RW(role);
1018
1019static struct attribute *ci_attrs[] = {
1020 &dev_attr_role.attr,
1021 NULL,
1022};
1023ATTRIBUTE_GROUPS(ci);
1024
1025static int ci_hdrc_probe(struct platform_device *pdev)
1026{
1027 struct usb_role_switch_desc ci_role_switch = {};
1028 struct device *dev = &pdev->dev;
1029 struct ci_hdrc *ci;
1030 struct resource *res;
1031 void __iomem *base;
1032 int ret;
1033 enum usb_dr_mode dr_mode;
1034
1035 if (!dev_get_platdata(dev)) {
1036 dev_err(dev, "platform data missing\n");
1037 return -ENODEV;
1038 }
1039
1040 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1041 if (IS_ERR(base))
1042 return PTR_ERR(base);
1043
1044 ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL);
1045 if (!ci)
1046 return -ENOMEM;
1047
1048 spin_lock_init(&ci->lock);
1049 mutex_init(&ci->mutex);
1050 INIT_WORK(&ci->power_lost_work, ci_power_lost_work);
1051
1052 ci->dev = dev;
1053 ci->platdata = dev_get_platdata(dev);
1054 ci->imx28_write_fix = !!(ci->platdata->flags &
1055 CI_HDRC_IMX28_WRITE_FIX);
1056 ci->supports_runtime_pm = !!(ci->platdata->flags &
1057 CI_HDRC_SUPPORTS_RUNTIME_PM);
1058 ci->has_portsc_pec_bug = !!(ci->platdata->flags &
1059 CI_HDRC_HAS_PORTSC_PEC_MISSED);
1060 ci->has_short_pkt_limit = !!(ci->platdata->flags &
1061 CI_HDRC_HAS_SHORT_PKT_LIMIT);
1062 platform_set_drvdata(pdev, ci);
1063
1064 ret = hw_device_init(ci, base);
1065 if (ret < 0) {
1066 dev_err(dev, "can't initialize hardware\n");
1067 return -ENODEV;
1068 }
1069
1070 ret = ci_ulpi_init(ci);
1071 if (ret)
1072 return ret;
1073
1074 if (ci->platdata->phy) {
1075 ci->phy = ci->platdata->phy;
1076 } else if (ci->platdata->usb_phy) {
1077 ci->usb_phy = ci->platdata->usb_phy;
1078 } else {
1079 /* Look for a generic PHY first */
1080 ci->phy = devm_phy_get(dev->parent, "usb-phy");
1081
1082 if (PTR_ERR(ci->phy) == -EPROBE_DEFER) {
1083 ret = -EPROBE_DEFER;
1084 goto ulpi_exit;
1085 } else if (IS_ERR(ci->phy)) {
1086 ci->phy = NULL;
1087 }
1088
1089 /* Look for a legacy USB PHY from device-tree next */
1090 if (!ci->phy) {
1091 ci->usb_phy = devm_usb_get_phy_by_phandle(dev->parent,
1092 "phys", 0);
1093
1094 if (PTR_ERR(ci->usb_phy) == -EPROBE_DEFER) {
1095 ret = -EPROBE_DEFER;
1096 goto ulpi_exit;
1097 } else if (IS_ERR(ci->usb_phy)) {
1098 ci->usb_phy = NULL;
1099 }
1100 }
1101
1102 /* Look for any registered legacy USB PHY as last resort */
1103 if (!ci->phy && !ci->usb_phy) {
1104 ci->usb_phy = devm_usb_get_phy(dev->parent,
1105 USB_PHY_TYPE_USB2);
1106
1107 if (PTR_ERR(ci->usb_phy) == -EPROBE_DEFER) {
1108 ret = -EPROBE_DEFER;
1109 goto ulpi_exit;
1110 } else if (IS_ERR(ci->usb_phy)) {
1111 ci->usb_phy = NULL;
1112 }
1113 }
1114
1115 /* No USB PHY was found in the end */
1116 if (!ci->phy && !ci->usb_phy) {
1117 ret = -ENXIO;
1118 goto ulpi_exit;
1119 }
1120 }
1121
1122 ret = ci_usb_phy_init(ci);
1123 if (ret) {
1124 dev_err(dev, "unable to init phy: %d\n", ret);
1125 goto ulpi_exit;
1126 }
1127
1128 ci->hw_bank.phys = res->start;
1129
1130 ci->irq = platform_get_irq(pdev, 0);
1131 if (ci->irq < 0) {
1132 ret = ci->irq;
1133 goto deinit_phy;
1134 }
1135
1136 ci_get_otg_capable(ci);
1137
1138 dr_mode = ci->platdata->dr_mode;
1139 /* initialize role(s) before the interrupt is requested */
1140 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) {
1141 ret = ci_hdrc_host_init(ci);
1142 if (ret) {
1143 if (ret == -ENXIO)
1144 dev_info(dev, "doesn't support host\n");
1145 else
1146 goto deinit_phy;
1147 }
1148 }
1149
1150 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) {
1151 ret = ci_hdrc_gadget_init(ci);
1152 if (ret) {
1153 if (ret == -ENXIO)
1154 dev_info(dev, "doesn't support gadget\n");
1155 else
1156 goto deinit_host;
1157 }
1158 }
1159
1160 if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) {
1161 dev_err(dev, "no supported roles\n");
1162 ret = -ENODEV;
1163 goto deinit_gadget;
1164 }
1165
1166 if (ci->is_otg && ci->roles[CI_ROLE_GADGET]) {
1167 ret = ci_hdrc_otg_init(ci);
1168 if (ret) {
1169 dev_err(dev, "init otg fails, ret = %d\n", ret);
1170 goto deinit_gadget;
1171 }
1172 }
1173
1174 if (device_property_read_bool(dev, "usb-role-switch")) {
1175 ci_role_switch.set = ci_usb_role_switch_set;
1176 ci_role_switch.get = ci_usb_role_switch_get;
1177 ci_role_switch.allow_userspace_control = true;
1178 ci_role_switch.fwnode = dev_fwnode(dev);
1179 ci_role_switch.driver_data = ci;
1180 ci->role_switch = usb_role_switch_register(dev,
1181 &ci_role_switch);
1182 if (IS_ERR(ci->role_switch)) {
1183 ret = PTR_ERR(ci->role_switch);
1184 goto deinit_otg;
1185 }
1186 }
1187
1188 ci->role = ci_get_role(ci);
1189 if (!ci_otg_is_fsm_mode(ci)) {
1190 ret = ci_role_start(ci, ci->role);
1191 if (ret) {
1192 dev_err(dev, "can't start %s role\n",
1193 ci_role(ci)->name);
1194 goto stop;
1195 }
1196
1197 /* only update vbus status for peripheral */
1198 if (ci->role == CI_ROLE_GADGET)
1199 ci_handle_vbus_change(ci);
1200 }
1201
1202 ret = devm_request_irq(dev, ci->irq, ci_irq_handler, IRQF_SHARED,
1203 ci->platdata->name, ci);
1204 if (ret)
1205 goto stop;
1206
1207 ret = ci_extcon_register(ci);
1208 if (ret)
1209 goto stop;
1210
1211 if (ci->supports_runtime_pm) {
1212 pm_runtime_set_active(&pdev->dev);
1213 pm_runtime_enable(&pdev->dev);
1214 pm_runtime_set_autosuspend_delay(&pdev->dev, 2000);
1215 pm_runtime_mark_last_busy(ci->dev);
1216 pm_runtime_use_autosuspend(&pdev->dev);
1217 }
1218
1219 if (ci_otg_is_fsm_mode(ci))
1220 ci_hdrc_otg_fsm_start(ci);
1221
1222 device_set_wakeup_capable(&pdev->dev, true);
1223 dbg_create_files(ci);
1224
1225 return 0;
1226
1227stop:
1228 if (ci->role_switch)
1229 usb_role_switch_unregister(ci->role_switch);
1230deinit_otg:
1231 if (ci->is_otg && ci->roles[CI_ROLE_GADGET])
1232 ci_hdrc_otg_destroy(ci);
1233deinit_gadget:
1234 ci_hdrc_gadget_destroy(ci);
1235deinit_host:
1236 ci_hdrc_host_destroy(ci);
1237deinit_phy:
1238 ci_usb_phy_exit(ci);
1239ulpi_exit:
1240 ci_ulpi_exit(ci);
1241
1242 return ret;
1243}
1244
1245static void ci_hdrc_remove(struct platform_device *pdev)
1246{
1247 struct ci_hdrc *ci = platform_get_drvdata(pdev);
1248
1249 if (ci->role_switch)
1250 usb_role_switch_unregister(ci->role_switch);
1251
1252 if (ci->supports_runtime_pm) {
1253 pm_runtime_dont_use_autosuspend(&pdev->dev);
1254 pm_runtime_get_sync(&pdev->dev);
1255 pm_runtime_disable(&pdev->dev);
1256 pm_runtime_put_noidle(&pdev->dev);
1257 }
1258
1259 dbg_remove_files(ci);
1260 ci_role_destroy(ci);
1261 ci_hdrc_enter_lpm(ci, true);
1262 ci_usb_phy_exit(ci);
1263 ci_ulpi_exit(ci);
1264}
1265
1266#ifdef CONFIG_PM
1267/* Prepare wakeup by SRP before suspend */
1268static void ci_otg_fsm_suspend_for_srp(struct ci_hdrc *ci)
1269{
1270 if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) &&
1271 !hw_read_otgsc(ci, OTGSC_ID)) {
1272 hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_PP,
1273 PORTSC_PP);
1274 hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_WKCN,
1275 PORTSC_WKCN);
1276 }
1277}
1278
1279/* Handle SRP when wakeup by data pulse */
1280static void ci_otg_fsm_wakeup_by_srp(struct ci_hdrc *ci)
1281{
1282 if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) &&
1283 (ci->fsm.a_bus_drop == 1) && (ci->fsm.a_bus_req == 0)) {
1284 if (!hw_read_otgsc(ci, OTGSC_ID)) {
1285 ci->fsm.a_srp_det = 1;
1286 ci->fsm.a_bus_drop = 0;
1287 } else {
1288 ci->fsm.id = 1;
1289 }
1290 ci_otg_queue_work(ci);
1291 }
1292}
1293
1294static void ci_controller_suspend(struct ci_hdrc *ci)
1295{
1296 disable_irq(ci->irq);
1297 ci_hdrc_enter_lpm(ci, true);
1298 if (ci->platdata->phy_clkgate_delay_us)
1299 usleep_range(ci->platdata->phy_clkgate_delay_us,
1300 ci->platdata->phy_clkgate_delay_us + 50);
1301 usb_phy_set_suspend(ci->usb_phy, 1);
1302 ci->in_lpm = true;
1303 enable_irq(ci->irq);
1304}
1305
1306/*
1307 * Handle the wakeup interrupt triggered by extcon connector
1308 * We need to call ci_irq again for extcon since the first
1309 * interrupt (wakeup int) only let the controller be out of
1310 * low power mode, but not handle any interrupts.
1311 */
1312static void ci_extcon_wakeup_int(struct ci_hdrc *ci)
1313{
1314 struct ci_hdrc_cable *cable_id, *cable_vbus;
1315 u32 otgsc = hw_read_otgsc(ci, ~0);
1316
1317 cable_id = &ci->platdata->id_extcon;
1318 cable_vbus = &ci->platdata->vbus_extcon;
1319
1320 if ((!IS_ERR(cable_id->edev) || ci->role_switch)
1321 && ci->is_otg &&
1322 (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS))
1323 ci_irq(ci);
1324
1325 if ((!IS_ERR(cable_vbus->edev) || ci->role_switch)
1326 && ci->is_otg &&
1327 (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS))
1328 ci_irq(ci);
1329}
1330
1331static int ci_controller_resume(struct device *dev)
1332{
1333 struct ci_hdrc *ci = dev_get_drvdata(dev);
1334 int ret;
1335
1336 dev_dbg(dev, "at %s\n", __func__);
1337
1338 if (!ci->in_lpm) {
1339 WARN_ON(1);
1340 return 0;
1341 }
1342
1343 ci_hdrc_enter_lpm(ci, false);
1344
1345 ret = ci_ulpi_resume(ci);
1346 if (ret)
1347 return ret;
1348
1349 if (ci->usb_phy) {
1350 usb_phy_set_suspend(ci->usb_phy, 0);
1351 usb_phy_set_wakeup(ci->usb_phy, false);
1352 hw_wait_phy_stable();
1353 }
1354
1355 ci->in_lpm = false;
1356 if (ci->wakeup_int) {
1357 ci->wakeup_int = false;
1358 pm_runtime_put_autosuspend(ci->dev);
1359 enable_irq(ci->irq);
1360 if (ci_otg_is_fsm_mode(ci))
1361 ci_otg_fsm_wakeup_by_srp(ci);
1362 ci_extcon_wakeup_int(ci);
1363 }
1364
1365 return 0;
1366}
1367
1368#ifdef CONFIG_PM_SLEEP
1369static int ci_suspend(struct device *dev)
1370{
1371 struct ci_hdrc *ci = dev_get_drvdata(dev);
1372
1373 if (ci->wq)
1374 flush_workqueue(ci->wq);
1375 /*
1376 * Controller needs to be active during suspend, otherwise the core
1377 * may run resume when the parent is at suspend if other driver's
1378 * suspend fails, it occurs before parent's suspend has not started,
1379 * but the core suspend has finished.
1380 */
1381 if (ci->in_lpm)
1382 pm_runtime_resume(dev);
1383
1384 if (ci->in_lpm) {
1385 WARN_ON(1);
1386 return 0;
1387 }
1388
1389 /* Extra routine per role before system suspend */
1390 if (ci->role != CI_ROLE_END && ci_role(ci)->suspend)
1391 ci_role(ci)->suspend(ci);
1392
1393 if (device_may_wakeup(dev)) {
1394 if (ci_otg_is_fsm_mode(ci))
1395 ci_otg_fsm_suspend_for_srp(ci);
1396
1397 usb_phy_set_wakeup(ci->usb_phy, true);
1398 enable_irq_wake(ci->irq);
1399 }
1400
1401 ci_controller_suspend(ci);
1402
1403 return 0;
1404}
1405
1406static int ci_resume(struct device *dev)
1407{
1408 struct ci_hdrc *ci = dev_get_drvdata(dev);
1409 bool power_lost;
1410 int ret;
1411
1412 /* Since ASYNCLISTADDR (host mode) and ENDPTLISTADDR (device
1413 * mode) share the same register address. We can check if
1414 * controller resume from power lost based on this address
1415 * due to this register will be reset after power lost.
1416 */
1417 power_lost = !hw_read(ci, OP_ENDPTLISTADDR, ~0);
1418
1419 if (device_may_wakeup(dev))
1420 disable_irq_wake(ci->irq);
1421
1422 ret = ci_controller_resume(dev);
1423 if (ret)
1424 return ret;
1425
1426 if (power_lost) {
1427 /* shutdown and re-init for phy */
1428 ci_usb_phy_exit(ci);
1429 ci_usb_phy_init(ci);
1430 }
1431
1432 /* Extra routine per role after system resume */
1433 if (ci->role != CI_ROLE_END && ci_role(ci)->resume)
1434 ci_role(ci)->resume(ci, power_lost);
1435
1436 if (power_lost)
1437 queue_work(system_freezable_wq, &ci->power_lost_work);
1438
1439 if (ci->supports_runtime_pm) {
1440 pm_runtime_disable(dev);
1441 pm_runtime_set_active(dev);
1442 pm_runtime_enable(dev);
1443 }
1444
1445 return ret;
1446}
1447#endif /* CONFIG_PM_SLEEP */
1448
1449static int ci_runtime_suspend(struct device *dev)
1450{
1451 struct ci_hdrc *ci = dev_get_drvdata(dev);
1452
1453 dev_dbg(dev, "at %s\n", __func__);
1454
1455 if (ci->in_lpm) {
1456 WARN_ON(1);
1457 return 0;
1458 }
1459
1460 if (ci_otg_is_fsm_mode(ci))
1461 ci_otg_fsm_suspend_for_srp(ci);
1462
1463 usb_phy_set_wakeup(ci->usb_phy, true);
1464 ci_controller_suspend(ci);
1465
1466 return 0;
1467}
1468
1469static int ci_runtime_resume(struct device *dev)
1470{
1471 return ci_controller_resume(dev);
1472}
1473
1474#endif /* CONFIG_PM */
1475static const struct dev_pm_ops ci_pm_ops = {
1476 SET_SYSTEM_SLEEP_PM_OPS(ci_suspend, ci_resume)
1477 SET_RUNTIME_PM_OPS(ci_runtime_suspend, ci_runtime_resume, NULL)
1478};
1479
1480static struct platform_driver ci_hdrc_driver = {
1481 .probe = ci_hdrc_probe,
1482 .remove = ci_hdrc_remove,
1483 .driver = {
1484 .name = "ci_hdrc",
1485 .pm = &ci_pm_ops,
1486 .dev_groups = ci_groups,
1487 },
1488};
1489
1490static int __init ci_hdrc_platform_register(void)
1491{
1492 ci_hdrc_host_driver_init();
1493 return platform_driver_register(&ci_hdrc_driver);
1494}
1495module_init(ci_hdrc_platform_register);
1496
1497static void __exit ci_hdrc_platform_unregister(void)
1498{
1499 platform_driver_unregister(&ci_hdrc_driver);
1500}
1501module_exit(ci_hdrc_platform_unregister);
1502
1503MODULE_ALIAS("platform:ci_hdrc");
1504MODULE_LICENSE("GPL v2");
1505MODULE_AUTHOR("David Lopo <[email protected]>");
1506MODULE_DESCRIPTION("ChipIdea HDRC Driver");