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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * core.c - DesignWare USB3 DRD Controller Core file
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
6 *
7 * Authors: Felipe Balbi <[email protected]>,
8 * Sebastian Andrzej Siewior <[email protected]>
9 */
10
11#include <linux/clk.h>
12#include <linux/version.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/slab.h>
16#include <linux/spinlock.h>
17#include <linux/platform_device.h>
18#include <linux/pm_runtime.h>
19#include <linux/interrupt.h>
20#include <linux/ioport.h>
21#include <linux/io.h>
22#include <linux/list.h>
23#include <linux/delay.h>
24#include <linux/dma-mapping.h>
25#include <linux/of.h>
26#include <linux/of_graph.h>
27#include <linux/acpi.h>
28#include <linux/pci.h>
29#include <linux/pinctrl/consumer.h>
30#include <linux/pinctrl/devinfo.h>
31#include <linux/reset.h>
32#include <linux/bitfield.h>
33
34#include <linux/usb/ch9.h>
35#include <linux/usb/gadget.h>
36#include <linux/usb/of.h>
37#include <linux/usb/otg.h>
38
39#include "core.h"
40#include "gadget.h"
41#include "glue.h"
42#include "io.h"
43
44#include "debug.h"
45#include "../host/xhci-ext-caps.h"
46
47#define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */
48
49/**
50 * dwc3_get_dr_mode - Validates and sets dr_mode
51 * @dwc: pointer to our context structure
52 */
53static int dwc3_get_dr_mode(struct dwc3 *dwc)
54{
55 enum usb_dr_mode mode;
56 struct device *dev = dwc->dev;
57 unsigned int hw_mode;
58
59 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
60 dwc->dr_mode = USB_DR_MODE_OTG;
61
62 mode = dwc->dr_mode;
63 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
64
65 switch (hw_mode) {
66 case DWC3_GHWPARAMS0_MODE_GADGET:
67 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
68 dev_err(dev,
69 "Controller does not support host mode.\n");
70 return -EINVAL;
71 }
72 mode = USB_DR_MODE_PERIPHERAL;
73 break;
74 case DWC3_GHWPARAMS0_MODE_HOST:
75 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
76 dev_err(dev,
77 "Controller does not support device mode.\n");
78 return -EINVAL;
79 }
80 mode = USB_DR_MODE_HOST;
81 break;
82 default:
83 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
84 mode = USB_DR_MODE_HOST;
85 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
86 mode = USB_DR_MODE_PERIPHERAL;
87
88 /*
89 * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG
90 * mode. If the controller supports DRD but the dr_mode is not
91 * specified or set to OTG, then set the mode to peripheral.
92 */
93 if (mode == USB_DR_MODE_OTG && !dwc->edev &&
94 (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) ||
95 !device_property_read_bool(dwc->dev, "usb-role-switch")) &&
96 !DWC3_VER_IS_PRIOR(DWC3, 330A))
97 mode = USB_DR_MODE_PERIPHERAL;
98 }
99
100 if (mode != dwc->dr_mode) {
101 dev_warn(dev,
102 "Configuration mismatch. dr_mode forced to %s\n",
103 mode == USB_DR_MODE_HOST ? "host" : "gadget");
104
105 dwc->dr_mode = mode;
106 }
107
108 return 0;
109}
110
111void dwc3_enable_susphy(struct dwc3 *dwc, bool enable)
112{
113 u32 reg;
114 int i;
115
116 for (i = 0; i < dwc->num_usb3_ports; i++) {
117 reg = dwc3_readl(dwc, DWC3_GUSB3PIPECTL(i));
118 if (enable && !dwc->dis_u3_susphy_quirk)
119 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
120 else
121 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
122
123 dwc3_writel(dwc, DWC3_GUSB3PIPECTL(i), reg);
124 }
125
126 for (i = 0; i < dwc->num_usb2_ports; i++) {
127 reg = dwc3_readl(dwc, DWC3_GUSB2PHYCFG(i));
128 if (enable && !dwc->dis_u2_susphy_quirk)
129 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
130 else
131 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
132
133 dwc3_writel(dwc, DWC3_GUSB2PHYCFG(i), reg);
134 }
135}
136EXPORT_SYMBOL_GPL(dwc3_enable_susphy);
137
138void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode, bool ignore_susphy)
139{
140 unsigned int hw_mode;
141 u32 reg;
142
143 reg = dwc3_readl(dwc, DWC3_GCTL);
144
145 /*
146 * For DRD controllers, GUSB3PIPECTL.SUSPENDENABLE and
147 * GUSB2PHYCFG.SUSPHY should be cleared during mode switching,
148 * and they can be set after core initialization.
149 */
150 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
151 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD && !ignore_susphy) {
152 if (DWC3_GCTL_PRTCAP(reg) != mode)
153 dwc3_enable_susphy(dwc, false);
154 }
155
156 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
157 reg |= DWC3_GCTL_PRTCAPDIR(mode);
158 dwc3_writel(dwc, DWC3_GCTL, reg);
159
160 dwc->current_dr_role = mode;
161 trace_dwc3_set_prtcap(dwc, mode);
162}
163EXPORT_SYMBOL_GPL(dwc3_set_prtcap);
164
165static void __dwc3_set_mode(struct work_struct *work)
166{
167 struct dwc3 *dwc = work_to_dwc(work);
168 unsigned long flags;
169 int ret;
170 u32 reg;
171 u32 desired_dr_role;
172 int i;
173
174 mutex_lock(&dwc->mutex);
175 spin_lock_irqsave(&dwc->lock, flags);
176 desired_dr_role = dwc->desired_dr_role;
177 spin_unlock_irqrestore(&dwc->lock, flags);
178
179 pm_runtime_get_sync(dwc->dev);
180
181 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG)
182 dwc3_otg_update(dwc, 0);
183
184 if (!desired_dr_role)
185 goto out;
186
187 if (desired_dr_role == dwc->current_dr_role)
188 goto out;
189
190 if (desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev)
191 goto out;
192
193 switch (dwc->current_dr_role) {
194 case DWC3_GCTL_PRTCAP_HOST:
195 dwc3_host_exit(dwc);
196 break;
197 case DWC3_GCTL_PRTCAP_DEVICE:
198 dwc3_gadget_exit(dwc);
199 dwc3_event_buffers_cleanup(dwc);
200 break;
201 case DWC3_GCTL_PRTCAP_OTG:
202 dwc3_otg_exit(dwc);
203 spin_lock_irqsave(&dwc->lock, flags);
204 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE;
205 spin_unlock_irqrestore(&dwc->lock, flags);
206 dwc3_otg_update(dwc, 1);
207 break;
208 default:
209 break;
210 }
211
212 /*
213 * When current_dr_role is not set, there's no role switching.
214 * Only perform GCTL.CoreSoftReset when there's DRD role switching.
215 */
216 if (dwc->current_dr_role && ((DWC3_IP_IS(DWC3) ||
217 DWC3_VER_IS_PRIOR(DWC31, 190A)) &&
218 desired_dr_role != DWC3_GCTL_PRTCAP_OTG)) {
219 reg = dwc3_readl(dwc, DWC3_GCTL);
220 reg |= DWC3_GCTL_CORESOFTRESET;
221 dwc3_writel(dwc, DWC3_GCTL, reg);
222
223 /*
224 * Wait for internal clocks to synchronized. DWC_usb31 and
225 * DWC_usb32 may need at least 50ms (less for DWC_usb3). To
226 * keep it consistent across different IPs, let's wait up to
227 * 100ms before clearing GCTL.CORESOFTRESET.
228 */
229 msleep(100);
230
231 reg = dwc3_readl(dwc, DWC3_GCTL);
232 reg &= ~DWC3_GCTL_CORESOFTRESET;
233 dwc3_writel(dwc, DWC3_GCTL, reg);
234 }
235
236 spin_lock_irqsave(&dwc->lock, flags);
237
238 dwc3_set_prtcap(dwc, desired_dr_role, false);
239
240 spin_unlock_irqrestore(&dwc->lock, flags);
241
242 switch (desired_dr_role) {
243 case DWC3_GCTL_PRTCAP_HOST:
244 ret = dwc3_host_init(dwc);
245 if (ret) {
246 dev_err(dwc->dev, "failed to initialize host\n");
247 } else {
248 if (dwc->usb2_phy)
249 otg_set_vbus(dwc->usb2_phy->otg, true);
250
251 for (i = 0; i < dwc->num_usb2_ports; i++)
252 phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST);
253 for (i = 0; i < dwc->num_usb3_ports; i++)
254 phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST);
255
256 if (dwc->dis_split_quirk) {
257 reg = dwc3_readl(dwc, DWC3_GUCTL3);
258 reg |= DWC3_GUCTL3_SPLITDISABLE;
259 dwc3_writel(dwc, DWC3_GUCTL3, reg);
260 }
261 }
262 break;
263 case DWC3_GCTL_PRTCAP_DEVICE:
264 dwc3_core_soft_reset(dwc);
265
266 dwc3_event_buffers_setup(dwc);
267
268 if (dwc->usb2_phy)
269 otg_set_vbus(dwc->usb2_phy->otg, false);
270 phy_set_mode(dwc->usb2_generic_phy[0], PHY_MODE_USB_DEVICE);
271 phy_set_mode(dwc->usb3_generic_phy[0], PHY_MODE_USB_DEVICE);
272
273 ret = dwc3_gadget_init(dwc);
274 if (ret)
275 dev_err(dwc->dev, "failed to initialize peripheral\n");
276 break;
277 case DWC3_GCTL_PRTCAP_OTG:
278 dwc3_otg_init(dwc);
279 dwc3_otg_update(dwc, 0);
280 break;
281 default:
282 break;
283 }
284
285out:
286 pm_runtime_put_autosuspend(dwc->dev);
287 mutex_unlock(&dwc->mutex);
288}
289
290void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
291{
292 unsigned long flags;
293
294 if (dwc->dr_mode != USB_DR_MODE_OTG)
295 return;
296
297 spin_lock_irqsave(&dwc->lock, flags);
298 dwc->desired_dr_role = mode;
299 spin_unlock_irqrestore(&dwc->lock, flags);
300
301 queue_work(system_freezable_wq, &dwc->drd_work);
302}
303
304u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
305{
306 struct dwc3 *dwc = dep->dwc;
307 u32 reg;
308
309 dwc3_writel(dwc, DWC3_GDBGFIFOSPACE,
310 DWC3_GDBGFIFOSPACE_NUM(dep->number) |
311 DWC3_GDBGFIFOSPACE_TYPE(type));
312
313 reg = dwc3_readl(dwc, DWC3_GDBGFIFOSPACE);
314
315 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
316}
317
318/**
319 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
320 * @dwc: pointer to our context structure
321 */
322int dwc3_core_soft_reset(struct dwc3 *dwc)
323{
324 u32 reg;
325 int retries = 1000;
326
327 /*
328 * We're resetting only the device side because, if we're in host mode,
329 * XHCI driver will reset the host block. If dwc3 was configured for
330 * host-only mode, then we can return early.
331 */
332 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
333 return 0;
334
335 reg = dwc3_readl(dwc, DWC3_DCTL);
336 reg |= DWC3_DCTL_CSFTRST;
337 reg &= ~DWC3_DCTL_RUN_STOP;
338 dwc3_gadget_dctl_write_safe(dwc, reg);
339
340 /*
341 * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit
342 * is cleared only after all the clocks are synchronized. This can
343 * take a little more than 50ms. Set the polling rate at 20ms
344 * for 10 times instead.
345 */
346 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
347 retries = 10;
348
349 do {
350 reg = dwc3_readl(dwc, DWC3_DCTL);
351 if (!(reg & DWC3_DCTL_CSFTRST))
352 goto done;
353
354 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
355 msleep(20);
356 else
357 udelay(1);
358 } while (--retries);
359
360 dev_warn(dwc->dev, "DWC3 controller soft reset failed.\n");
361 return -ETIMEDOUT;
362
363done:
364 /*
365 * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit
366 * is cleared, we must wait at least 50ms before accessing the PHY
367 * domain (synchronization delay).
368 */
369 if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A))
370 msleep(50);
371
372 return 0;
373}
374
375/*
376 * dwc3_frame_length_adjustment - Adjusts frame length if required
377 * @dwc3: Pointer to our controller context structure
378 */
379static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
380{
381 u32 reg;
382 u32 dft;
383
384 if (DWC3_VER_IS_PRIOR(DWC3, 250A))
385 return;
386
387 if (dwc->fladj == 0)
388 return;
389
390 reg = dwc3_readl(dwc, DWC3_GFLADJ);
391 dft = reg & DWC3_GFLADJ_30MHZ_MASK;
392 if (dft != dwc->fladj) {
393 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
394 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
395 dwc3_writel(dwc, DWC3_GFLADJ, reg);
396 }
397}
398
399/**
400 * dwc3_ref_clk_period - Reference clock period configuration
401 * Default reference clock period depends on hardware
402 * configuration. For systems with reference clock that differs
403 * from the default, this will set clock period in DWC3_GUCTL
404 * register.
405 * @dwc: Pointer to our controller context structure
406 */
407static void dwc3_ref_clk_period(struct dwc3 *dwc)
408{
409 unsigned long period;
410 unsigned long fladj;
411 unsigned long decr;
412 unsigned long rate;
413 u32 reg;
414
415 if (dwc->ref_clk) {
416 rate = clk_get_rate(dwc->ref_clk);
417 if (!rate)
418 return;
419 period = NSEC_PER_SEC / rate;
420 } else if (dwc->ref_clk_per) {
421 period = dwc->ref_clk_per;
422 rate = NSEC_PER_SEC / period;
423 } else {
424 return;
425 }
426
427 reg = dwc3_readl(dwc, DWC3_GUCTL);
428 FIELD_MODIFY(DWC3_GUCTL_REFCLKPER_MASK, &reg, period);
429 dwc3_writel(dwc, DWC3_GUCTL, reg);
430
431 if (DWC3_VER_IS_PRIOR(DWC3, 250A))
432 return;
433
434 /*
435 * The calculation below is
436 *
437 * 125000 * (NSEC_PER_SEC / (rate * period) - 1)
438 *
439 * but rearranged for fixed-point arithmetic. The division must be
440 * 64-bit because 125000 * NSEC_PER_SEC doesn't fit in 32 bits (and
441 * neither does rate * period).
442 *
443 * Note that rate * period ~= NSEC_PER_SECOND, minus the number of
444 * nanoseconds of error caused by the truncation which happened during
445 * the division when calculating rate or period (whichever one was
446 * derived from the other). We first calculate the relative error, then
447 * scale it to units of 8 ppm.
448 */
449 fladj = div64_u64(125000ULL * NSEC_PER_SEC, (u64)rate * period);
450 fladj -= 125000;
451
452 /*
453 * The documented 240MHz constant is scaled by 2 to get PLS1 as well.
454 */
455 decr = 480000000 / rate;
456
457 reg = dwc3_readl(dwc, DWC3_GFLADJ);
458 FIELD_MODIFY(DWC3_GFLADJ_REFCLK_FLADJ_MASK, &reg, fladj);
459 FIELD_MODIFY(DWC3_GFLADJ_240MHZDECR, &reg, decr >> 1);
460 FIELD_MODIFY(DWC3_GFLADJ_240MHZDECR_PLS1, &reg, decr & 1);
461
462 if (dwc->gfladj_refclk_lpm_sel)
463 reg |= DWC3_GFLADJ_REFCLK_LPM_SEL;
464
465 dwc3_writel(dwc, DWC3_GFLADJ, reg);
466}
467
468/**
469 * dwc3_free_one_event_buffer - Frees one event buffer
470 * @dwc: Pointer to our controller context structure
471 * @evt: Pointer to event buffer to be freed
472 */
473static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
474 struct dwc3_event_buffer *evt)
475{
476 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
477}
478
479/**
480 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
481 * @dwc: Pointer to our controller context structure
482 * @length: size of the event buffer
483 *
484 * Returns a pointer to the allocated event buffer structure on success
485 * otherwise ERR_PTR(errno).
486 */
487static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
488 unsigned int length)
489{
490 struct dwc3_event_buffer *evt;
491
492 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
493 if (!evt)
494 return ERR_PTR(-ENOMEM);
495
496 evt->dwc = dwc;
497 evt->length = length;
498 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
499 if (!evt->cache)
500 return ERR_PTR(-ENOMEM);
501
502 evt->buf = dma_alloc_coherent(dwc->sysdev, length,
503 &evt->dma, GFP_KERNEL);
504 if (!evt->buf)
505 return ERR_PTR(-ENOMEM);
506
507 return evt;
508}
509
510/**
511 * dwc3_free_event_buffers - frees all allocated event buffers
512 * @dwc: Pointer to our controller context structure
513 */
514static void dwc3_free_event_buffers(struct dwc3 *dwc)
515{
516 struct dwc3_event_buffer *evt;
517
518 evt = dwc->ev_buf;
519 if (evt)
520 dwc3_free_one_event_buffer(dwc, evt);
521}
522
523/**
524 * dwc3_alloc_event_buffers - Allocate one event buffer of size @length
525 * @dwc: pointer to our controller context structure
526 * @length: size of event buffer
527 *
528 * Returns 0 on success otherwise negative errno. In the error case, dwc
529 * may contain some buffers allocated but not all which were requested.
530 */
531static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned int length)
532{
533 struct dwc3_event_buffer *evt;
534 unsigned int hw_mode;
535
536 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
537 if (hw_mode == DWC3_GHWPARAMS0_MODE_HOST) {
538 dwc->ev_buf = NULL;
539 return 0;
540 }
541
542 evt = dwc3_alloc_one_event_buffer(dwc, length);
543 if (IS_ERR(evt)) {
544 dev_err(dwc->dev, "can't allocate event buffer\n");
545 return PTR_ERR(evt);
546 }
547 dwc->ev_buf = evt;
548
549 return 0;
550}
551
552/**
553 * dwc3_event_buffers_setup - setup our allocated event buffers
554 * @dwc: pointer to our controller context structure
555 *
556 * Returns 0 on success otherwise negative errno.
557 */
558int dwc3_event_buffers_setup(struct dwc3 *dwc)
559{
560 struct dwc3_event_buffer *evt;
561 u32 reg;
562
563 if (!dwc->ev_buf)
564 return 0;
565
566 evt = dwc->ev_buf;
567 evt->lpos = 0;
568 dwc3_writel(dwc, DWC3_GEVNTADRLO(0),
569 lower_32_bits(evt->dma));
570 dwc3_writel(dwc, DWC3_GEVNTADRHI(0),
571 upper_32_bits(evt->dma));
572 dwc3_writel(dwc, DWC3_GEVNTSIZ(0),
573 DWC3_GEVNTSIZ_SIZE(evt->length));
574
575 /* Clear any stale event */
576 reg = dwc3_readl(dwc, DWC3_GEVNTCOUNT(0));
577 dwc3_writel(dwc, DWC3_GEVNTCOUNT(0), reg);
578 return 0;
579}
580
581void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
582{
583 struct dwc3_event_buffer *evt;
584 u32 reg;
585
586 if (!dwc->ev_buf)
587 return;
588 /*
589 * Exynos platforms may not be able to access event buffer if the
590 * controller failed to halt on dwc3_core_exit().
591 */
592 reg = dwc3_readl(dwc, DWC3_DSTS);
593 if (!(reg & DWC3_DSTS_DEVCTRLHLT))
594 return;
595
596 evt = dwc->ev_buf;
597
598 evt->lpos = 0;
599
600 dwc3_writel(dwc, DWC3_GEVNTADRLO(0), 0);
601 dwc3_writel(dwc, DWC3_GEVNTADRHI(0), 0);
602 dwc3_writel(dwc, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
603 | DWC3_GEVNTSIZ_SIZE(0));
604
605 /* Clear any stale event */
606 reg = dwc3_readl(dwc, DWC3_GEVNTCOUNT(0));
607 dwc3_writel(dwc, DWC3_GEVNTCOUNT(0), reg);
608}
609
610static void dwc3_core_num_eps(struct dwc3 *dwc)
611{
612 struct dwc3_hwparams *parms = &dwc->hwparams;
613
614 dwc->num_eps = DWC3_NUM_EPS(parms);
615}
616
617static void dwc3_cache_hwparams(struct dwc3 *dwc)
618{
619 struct dwc3_hwparams *parms = &dwc->hwparams;
620
621 parms->hwparams0 = dwc3_readl(dwc, DWC3_GHWPARAMS0);
622 parms->hwparams1 = dwc3_readl(dwc, DWC3_GHWPARAMS1);
623 parms->hwparams2 = dwc3_readl(dwc, DWC3_GHWPARAMS2);
624 parms->hwparams3 = dwc3_readl(dwc, DWC3_GHWPARAMS3);
625 parms->hwparams4 = dwc3_readl(dwc, DWC3_GHWPARAMS4);
626 parms->hwparams5 = dwc3_readl(dwc, DWC3_GHWPARAMS5);
627 parms->hwparams6 = dwc3_readl(dwc, DWC3_GHWPARAMS6);
628 parms->hwparams7 = dwc3_readl(dwc, DWC3_GHWPARAMS7);
629 parms->hwparams8 = dwc3_readl(dwc, DWC3_GHWPARAMS8);
630
631 if (DWC3_IP_IS(DWC32))
632 parms->hwparams9 = dwc3_readl(dwc, DWC3_GHWPARAMS9);
633}
634
635static void dwc3_config_soc_bus(struct dwc3 *dwc)
636{
637 if (dwc->gsbuscfg0_reqinfo != DWC3_GSBUSCFG0_REQINFO_UNSPECIFIED) {
638 u32 reg;
639
640 reg = dwc3_readl(dwc, DWC3_GSBUSCFG0);
641 reg &= ~DWC3_GSBUSCFG0_REQINFO(~0);
642 reg |= DWC3_GSBUSCFG0_REQINFO(dwc->gsbuscfg0_reqinfo);
643 dwc3_writel(dwc, DWC3_GSBUSCFG0, reg);
644 }
645}
646
647static int dwc3_core_ulpi_init(struct dwc3 *dwc)
648{
649 int intf;
650 int ret = 0;
651
652 intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
653
654 if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
655 (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
656 dwc->hsphy_interface &&
657 !strncmp(dwc->hsphy_interface, "ulpi", 4)))
658 ret = dwc3_ulpi_init(dwc);
659
660 return ret;
661}
662
663static int dwc3_ss_phy_setup(struct dwc3 *dwc, int index)
664{
665 u32 reg;
666
667 reg = dwc3_readl(dwc, DWC3_GUSB3PIPECTL(index));
668
669 /*
670 * Make sure UX_EXIT_PX is cleared as that causes issues with some
671 * PHYs. Also, this bit is not supposed to be used in normal operation.
672 */
673 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
674
675 /* Ensure the GUSB3PIPECTL.SUSPENDENABLE is cleared prior to phy init. */
676 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
677
678 if (dwc->u2ss_inp3_quirk)
679 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
680
681 if (dwc->dis_rxdet_inp3_quirk)
682 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
683
684 if (dwc->req_p1p2p3_quirk)
685 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
686
687 if (dwc->del_p1p2p3_quirk)
688 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
689
690 if (dwc->del_phy_power_chg_quirk)
691 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
692
693 if (dwc->lfps_filter_quirk)
694 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
695
696 if (dwc->rx_detect_poll_quirk)
697 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
698
699 if (dwc->tx_de_emphasis_quirk)
700 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
701
702 if (dwc->dis_del_phy_power_chg_quirk)
703 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
704
705 dwc3_writel(dwc, DWC3_GUSB3PIPECTL(index), reg);
706
707 return 0;
708}
709
710static int dwc3_hs_phy_setup(struct dwc3 *dwc, int index)
711{
712 u32 reg;
713
714 reg = dwc3_readl(dwc, DWC3_GUSB2PHYCFG(index));
715
716 /* Select the HS PHY interface */
717 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
718 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
719 if (dwc->hsphy_interface &&
720 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
721 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
722 break;
723 } else if (dwc->hsphy_interface &&
724 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
725 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
726 dwc3_writel(dwc, DWC3_GUSB2PHYCFG(index), reg);
727 } else {
728 /* Relying on default value. */
729 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
730 break;
731 }
732 fallthrough;
733 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
734 default:
735 break;
736 }
737
738 switch (dwc->hsphy_mode) {
739 case USBPHY_INTERFACE_MODE_UTMI:
740 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
741 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
742 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
743 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
744 break;
745 case USBPHY_INTERFACE_MODE_UTMIW:
746 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
747 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
748 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
749 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
750 break;
751 default:
752 break;
753 }
754
755 /* Ensure the GUSB2PHYCFG.SUSPHY is cleared prior to phy init. */
756 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
757
758 if (dwc->dis_enblslpm_quirk)
759 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
760 else
761 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM;
762
763 if (dwc->dis_u2_freeclk_exists_quirk || dwc->gfladj_refclk_lpm_sel)
764 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
765
766 /*
767 * Some ULPI USB PHY does not support internal VBUS supply, to drive
768 * the CPEN pin requires the configuration of the ULPI DRVVBUSEXTERNAL
769 * bit of OTG_CTRL register. Controller configures the USB2 PHY
770 * ULPIEXTVBUSDRV bit[17] of the GUSB2PHYCFG register to drive vBus
771 * with an external supply.
772 */
773 if (dwc->ulpi_ext_vbus_drv)
774 reg |= DWC3_GUSB2PHYCFG_ULPIEXTVBUSDRV;
775
776 dwc3_writel(dwc, DWC3_GUSB2PHYCFG(index), reg);
777
778 return 0;
779}
780
781static void dwc3_ulpi_setup(struct dwc3 *dwc)
782{
783 int index;
784 u32 reg;
785
786 /* Don't do anything if there is no ULPI PHY */
787 if (!dwc->ulpi)
788 return;
789
790 if (dwc->enable_usb2_transceiver_delay) {
791 for (index = 0; index < dwc->num_usb2_ports; index++) {
792 reg = dwc3_readl(dwc, DWC3_GUSB2PHYCFG(index));
793 reg |= DWC3_GUSB2PHYCFG_XCVRDLY;
794 dwc3_writel(dwc, DWC3_GUSB2PHYCFG(index), reg);
795 }
796 }
797}
798
799/**
800 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
801 * @dwc: Pointer to our controller context structure
802 *
803 * Returns 0 on success. The USB PHY interfaces are configured but not
804 * initialized. The PHY interfaces and the PHYs get initialized together with
805 * the core in dwc3_core_init.
806 */
807static int dwc3_phy_setup(struct dwc3 *dwc)
808{
809 int i;
810 int ret;
811
812 for (i = 0; i < dwc->num_usb3_ports; i++) {
813 ret = dwc3_ss_phy_setup(dwc, i);
814 if (ret)
815 return ret;
816 }
817
818 for (i = 0; i < dwc->num_usb2_ports; i++) {
819 ret = dwc3_hs_phy_setup(dwc, i);
820 if (ret)
821 return ret;
822 }
823
824 return 0;
825}
826
827static int dwc3_phy_init(struct dwc3 *dwc)
828{
829 int ret;
830 int i;
831 int j;
832
833 usb_phy_init(dwc->usb2_phy);
834 usb_phy_init(dwc->usb3_phy);
835
836 for (i = 0; i < dwc->num_usb2_ports; i++) {
837 ret = phy_init(dwc->usb2_generic_phy[i]);
838 if (ret < 0)
839 goto err_exit_usb2_phy;
840 }
841
842 for (j = 0; j < dwc->num_usb3_ports; j++) {
843 ret = phy_init(dwc->usb3_generic_phy[j]);
844 if (ret < 0)
845 goto err_exit_usb3_phy;
846 }
847
848 /*
849 * Above DWC_usb3.0 1.94a, it is recommended to set
850 * DWC3_GUSB3PIPECTL_SUSPHY and DWC3_GUSB2PHYCFG_SUSPHY to '0' during
851 * coreConsultant configuration. So default value will be '0' when the
852 * core is reset. Application needs to set it to '1' after the core
853 * initialization is completed.
854 *
855 * Certain phy requires to be in P0 power state during initialization.
856 * Make sure GUSB3PIPECTL.SUSPENDENABLE and GUSB2PHYCFG.SUSPHY are clear
857 * prior to phy init to maintain in the P0 state.
858 *
859 * After phy initialization, some phy operations can only be executed
860 * while in lower P states. Ensure GUSB3PIPECTL.SUSPENDENABLE and
861 * GUSB2PHYCFG.SUSPHY are set soon after initialization to avoid
862 * blocking phy ops.
863 */
864 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A))
865 dwc3_enable_susphy(dwc, true);
866
867 return 0;
868
869err_exit_usb3_phy:
870 while (--j >= 0)
871 phy_exit(dwc->usb3_generic_phy[j]);
872
873err_exit_usb2_phy:
874 while (--i >= 0)
875 phy_exit(dwc->usb2_generic_phy[i]);
876
877 usb_phy_shutdown(dwc->usb3_phy);
878 usb_phy_shutdown(dwc->usb2_phy);
879
880 return ret;
881}
882
883static void dwc3_phy_exit(struct dwc3 *dwc)
884{
885 int i;
886
887 for (i = 0; i < dwc->num_usb3_ports; i++)
888 phy_exit(dwc->usb3_generic_phy[i]);
889
890 for (i = 0; i < dwc->num_usb2_ports; i++)
891 phy_exit(dwc->usb2_generic_phy[i]);
892
893 usb_phy_shutdown(dwc->usb3_phy);
894 usb_phy_shutdown(dwc->usb2_phy);
895}
896
897static int dwc3_phy_power_on(struct dwc3 *dwc)
898{
899 int ret;
900 int i;
901 int j;
902
903 usb_phy_set_suspend(dwc->usb2_phy, 0);
904 usb_phy_set_suspend(dwc->usb3_phy, 0);
905
906 for (i = 0; i < dwc->num_usb2_ports; i++) {
907 ret = phy_power_on(dwc->usb2_generic_phy[i]);
908 if (ret < 0)
909 goto err_power_off_usb2_phy;
910 }
911
912 for (j = 0; j < dwc->num_usb3_ports; j++) {
913 ret = phy_power_on(dwc->usb3_generic_phy[j]);
914 if (ret < 0)
915 goto err_power_off_usb3_phy;
916 }
917
918 return 0;
919
920err_power_off_usb3_phy:
921 while (--j >= 0)
922 phy_power_off(dwc->usb3_generic_phy[j]);
923
924err_power_off_usb2_phy:
925 while (--i >= 0)
926 phy_power_off(dwc->usb2_generic_phy[i]);
927
928 usb_phy_set_suspend(dwc->usb3_phy, 1);
929 usb_phy_set_suspend(dwc->usb2_phy, 1);
930
931 return ret;
932}
933
934static void dwc3_phy_power_off(struct dwc3 *dwc)
935{
936 int i;
937
938 for (i = 0; i < dwc->num_usb3_ports; i++)
939 phy_power_off(dwc->usb3_generic_phy[i]);
940
941 for (i = 0; i < dwc->num_usb2_ports; i++)
942 phy_power_off(dwc->usb2_generic_phy[i]);
943
944 usb_phy_set_suspend(dwc->usb3_phy, 1);
945 usb_phy_set_suspend(dwc->usb2_phy, 1);
946}
947
948static int dwc3_clk_enable(struct dwc3 *dwc)
949{
950 int ret;
951
952 ret = clk_prepare_enable(dwc->bus_clk);
953 if (ret)
954 return ret;
955
956 ret = clk_prepare_enable(dwc->ref_clk);
957 if (ret)
958 goto disable_bus_clk;
959
960 ret = clk_prepare_enable(dwc->susp_clk);
961 if (ret)
962 goto disable_ref_clk;
963
964 ret = clk_prepare_enable(dwc->utmi_clk);
965 if (ret)
966 goto disable_susp_clk;
967
968 ret = clk_prepare_enable(dwc->pipe_clk);
969 if (ret)
970 goto disable_utmi_clk;
971
972 return 0;
973
974disable_utmi_clk:
975 clk_disable_unprepare(dwc->utmi_clk);
976disable_susp_clk:
977 clk_disable_unprepare(dwc->susp_clk);
978disable_ref_clk:
979 clk_disable_unprepare(dwc->ref_clk);
980disable_bus_clk:
981 clk_disable_unprepare(dwc->bus_clk);
982 return ret;
983}
984
985static void dwc3_clk_disable(struct dwc3 *dwc)
986{
987 clk_disable_unprepare(dwc->pipe_clk);
988 clk_disable_unprepare(dwc->utmi_clk);
989 clk_disable_unprepare(dwc->susp_clk);
990 clk_disable_unprepare(dwc->ref_clk);
991 clk_disable_unprepare(dwc->bus_clk);
992}
993
994void dwc3_core_exit(struct dwc3 *dwc)
995{
996 dwc3_event_buffers_cleanup(dwc);
997 dwc3_phy_power_off(dwc);
998 dwc3_phy_exit(dwc);
999 dwc3_clk_disable(dwc);
1000 reset_control_assert(dwc->reset);
1001}
1002EXPORT_SYMBOL_GPL(dwc3_core_exit);
1003
1004static bool dwc3_core_is_valid(struct dwc3 *dwc)
1005{
1006 u32 reg;
1007
1008 reg = dwc3_readl(dwc, DWC3_GSNPSID);
1009 dwc->ip = DWC3_GSNPS_ID(reg);
1010 if (dwc->ip == DWC4_IP)
1011 dwc->ip = DWC32_IP;
1012
1013 /* This should read as U3 followed by revision number */
1014 if (DWC3_IP_IS(DWC3)) {
1015 dwc->revision = reg;
1016 } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) {
1017 dwc->revision = dwc3_readl(dwc, DWC3_VER_NUMBER);
1018 dwc->version_type = dwc3_readl(dwc, DWC3_VER_TYPE);
1019 } else {
1020 return false;
1021 }
1022
1023 return true;
1024}
1025
1026static void dwc3_core_setup_global_control(struct dwc3 *dwc)
1027{
1028 unsigned int power_opt;
1029 unsigned int hw_mode;
1030 u32 reg;
1031
1032 reg = dwc3_readl(dwc, DWC3_GCTL);
1033 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
1034 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
1035 power_opt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
1036
1037 switch (power_opt) {
1038 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
1039 /**
1040 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
1041 * issue which would cause xHCI compliance tests to fail.
1042 *
1043 * Because of that we cannot enable clock gating on such
1044 * configurations.
1045 *
1046 * Refers to:
1047 *
1048 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
1049 * SOF/ITP Mode Used
1050 */
1051 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
1052 dwc->dr_mode == USB_DR_MODE_OTG) &&
1053 DWC3_VER_IS_WITHIN(DWC3, 210A, 250A))
1054 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
1055 else
1056 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
1057 break;
1058 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
1059 /*
1060 * REVISIT Enabling this bit so that host-mode hibernation
1061 * will work. Device-mode hibernation is not yet implemented.
1062 */
1063 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
1064 break;
1065 default:
1066 /* nothing */
1067 break;
1068 }
1069
1070 /*
1071 * This is a workaround for STAR#4846132, which only affects
1072 * DWC_usb31 version2.00a operating in host mode.
1073 *
1074 * There is a problem in DWC_usb31 version 2.00a operating
1075 * in host mode that would cause a CSR read timeout When CSR
1076 * read coincides with RAM Clock Gating Entry. By disable
1077 * Clock Gating, sacrificing power consumption for normal
1078 * operation.
1079 */
1080 if (power_opt != DWC3_GHWPARAMS1_EN_PWROPT_NO &&
1081 hw_mode != DWC3_GHWPARAMS0_MODE_GADGET && DWC3_VER_IS(DWC31, 200A))
1082 reg |= DWC3_GCTL_DSBLCLKGTNG;
1083
1084 /* check if current dwc3 is on simulation board */
1085 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
1086 dev_info(dwc->dev, "Running with FPGA optimizations\n");
1087 dwc->is_fpga = true;
1088 }
1089
1090 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
1091 "disable_scramble cannot be used on non-FPGA builds\n");
1092
1093 if (dwc->disable_scramble_quirk && dwc->is_fpga)
1094 reg |= DWC3_GCTL_DISSCRAMBLE;
1095 else
1096 reg &= ~DWC3_GCTL_DISSCRAMBLE;
1097
1098 if (dwc->u2exit_lfps_quirk)
1099 reg |= DWC3_GCTL_U2EXIT_LFPS;
1100
1101 /*
1102 * WORKAROUND: DWC3 revisions <1.90a have a bug
1103 * where the device can fail to connect at SuperSpeed
1104 * and falls back to high-speed mode which causes
1105 * the device to enter a Connect/Disconnect loop
1106 */
1107 if (DWC3_VER_IS_PRIOR(DWC3, 190A))
1108 reg |= DWC3_GCTL_U2RSTECN;
1109
1110 dwc3_writel(dwc, DWC3_GCTL, reg);
1111}
1112
1113static int dwc3_core_get_phy(struct dwc3 *dwc);
1114static int dwc3_core_ulpi_init(struct dwc3 *dwc);
1115
1116/* set global incr burst type configuration registers */
1117static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
1118{
1119 struct device *dev = dwc->dev;
1120 /* incrx_mode : for INCR burst type. */
1121 bool incrx_mode;
1122 /* incrx_size : for size of INCRX burst. */
1123 u32 incrx_size;
1124 u32 *vals;
1125 u32 cfg;
1126 int ntype;
1127 int ret;
1128 int i;
1129
1130 cfg = dwc3_readl(dwc, DWC3_GSBUSCFG0);
1131
1132 /*
1133 * Handle property "snps,incr-burst-type-adjustment".
1134 * Get the number of value from this property:
1135 * result <= 0, means this property is not supported.
1136 * result = 1, means INCRx burst mode supported.
1137 * result > 1, means undefined length burst mode supported.
1138 */
1139 ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment");
1140 if (ntype <= 0)
1141 return;
1142
1143 vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
1144 if (!vals)
1145 return;
1146
1147 /* Get INCR burst type, and parse it */
1148 ret = device_property_read_u32_array(dev,
1149 "snps,incr-burst-type-adjustment", vals, ntype);
1150 if (ret) {
1151 kfree(vals);
1152 dev_err(dev, "Error to get property\n");
1153 return;
1154 }
1155
1156 incrx_size = *vals;
1157
1158 if (ntype > 1) {
1159 /* INCRX (undefined length) burst mode */
1160 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
1161 for (i = 1; i < ntype; i++) {
1162 if (vals[i] > incrx_size)
1163 incrx_size = vals[i];
1164 }
1165 } else {
1166 /* INCRX burst mode */
1167 incrx_mode = INCRX_BURST_MODE;
1168 }
1169
1170 kfree(vals);
1171
1172 /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
1173 cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
1174 if (incrx_mode)
1175 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
1176 switch (incrx_size) {
1177 case 256:
1178 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
1179 break;
1180 case 128:
1181 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
1182 break;
1183 case 64:
1184 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
1185 break;
1186 case 32:
1187 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
1188 break;
1189 case 16:
1190 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
1191 break;
1192 case 8:
1193 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
1194 break;
1195 case 4:
1196 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
1197 break;
1198 case 1:
1199 break;
1200 default:
1201 dev_err(dev, "Invalid property\n");
1202 break;
1203 }
1204
1205 dwc3_writel(dwc, DWC3_GSBUSCFG0, cfg);
1206}
1207
1208static void dwc3_set_power_down_clk_scale(struct dwc3 *dwc)
1209{
1210 u32 scale;
1211 u32 reg;
1212
1213 if (!dwc->susp_clk)
1214 return;
1215
1216 /*
1217 * The power down scale field specifies how many suspend_clk
1218 * periods fit into a 16KHz clock period. When performing
1219 * the division, round up the remainder.
1220 *
1221 * The power down scale value is calculated using the fastest
1222 * frequency of the suspend_clk. If it isn't fixed (but within
1223 * the accuracy requirement), the driver may not know the max
1224 * rate of the suspend_clk, so only update the power down scale
1225 * if the default is less than the calculated value from
1226 * clk_get_rate() or if the default is questionably high
1227 * (3x or more) to be within the requirement.
1228 */
1229 scale = DIV_ROUND_UP(clk_get_rate(dwc->susp_clk), 16000);
1230 reg = dwc3_readl(dwc, DWC3_GCTL);
1231 if ((reg & DWC3_GCTL_PWRDNSCALE_MASK) < DWC3_GCTL_PWRDNSCALE(scale) ||
1232 (reg & DWC3_GCTL_PWRDNSCALE_MASK) > DWC3_GCTL_PWRDNSCALE(scale*3)) {
1233 reg &= ~(DWC3_GCTL_PWRDNSCALE_MASK);
1234 reg |= DWC3_GCTL_PWRDNSCALE(scale);
1235 dwc3_writel(dwc, DWC3_GCTL, reg);
1236 }
1237}
1238
1239static void dwc3_config_threshold(struct dwc3 *dwc)
1240{
1241 u32 reg;
1242 u8 rx_thr_num;
1243 u8 rx_maxburst;
1244 u8 tx_thr_num;
1245 u8 tx_maxburst;
1246
1247 /*
1248 * Must config both number of packets and max burst settings to enable
1249 * RX and/or TX threshold.
1250 */
1251 if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) {
1252 rx_thr_num = dwc->rx_thr_num_pkt_prd;
1253 rx_maxburst = dwc->rx_max_burst_prd;
1254 tx_thr_num = dwc->tx_thr_num_pkt_prd;
1255 tx_maxburst = dwc->tx_max_burst_prd;
1256
1257 if (rx_thr_num && rx_maxburst) {
1258 reg = dwc3_readl(dwc, DWC3_GRXTHRCFG);
1259 reg |= DWC31_RXTHRNUMPKTSEL_PRD;
1260
1261 reg &= ~DWC31_RXTHRNUMPKT_PRD(~0);
1262 reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num);
1263
1264 reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0);
1265 reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst);
1266
1267 dwc3_writel(dwc, DWC3_GRXTHRCFG, reg);
1268 }
1269
1270 if (tx_thr_num && tx_maxburst) {
1271 reg = dwc3_readl(dwc, DWC3_GTXTHRCFG);
1272 reg |= DWC31_TXTHRNUMPKTSEL_PRD;
1273
1274 reg &= ~DWC31_TXTHRNUMPKT_PRD(~0);
1275 reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num);
1276
1277 reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0);
1278 reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst);
1279
1280 dwc3_writel(dwc, DWC3_GTXTHRCFG, reg);
1281 }
1282 }
1283
1284 rx_thr_num = dwc->rx_thr_num_pkt;
1285 rx_maxburst = dwc->rx_max_burst;
1286 tx_thr_num = dwc->tx_thr_num_pkt;
1287 tx_maxburst = dwc->tx_max_burst;
1288
1289 if (DWC3_IP_IS(DWC3)) {
1290 if (rx_thr_num && rx_maxburst) {
1291 reg = dwc3_readl(dwc, DWC3_GRXTHRCFG);
1292 reg |= DWC3_GRXTHRCFG_PKTCNTSEL;
1293
1294 reg &= ~DWC3_GRXTHRCFG_RXPKTCNT(~0);
1295 reg |= DWC3_GRXTHRCFG_RXPKTCNT(rx_thr_num);
1296
1297 reg &= ~DWC3_GRXTHRCFG_MAXRXBURSTSIZE(~0);
1298 reg |= DWC3_GRXTHRCFG_MAXRXBURSTSIZE(rx_maxburst);
1299
1300 dwc3_writel(dwc, DWC3_GRXTHRCFG, reg);
1301 }
1302
1303 if (tx_thr_num && tx_maxburst) {
1304 reg = dwc3_readl(dwc, DWC3_GTXTHRCFG);
1305 reg |= DWC3_GTXTHRCFG_PKTCNTSEL;
1306
1307 reg &= ~DWC3_GTXTHRCFG_TXPKTCNT(~0);
1308 reg |= DWC3_GTXTHRCFG_TXPKTCNT(tx_thr_num);
1309
1310 reg &= ~DWC3_GTXTHRCFG_MAXTXBURSTSIZE(~0);
1311 reg |= DWC3_GTXTHRCFG_MAXTXBURSTSIZE(tx_maxburst);
1312
1313 dwc3_writel(dwc, DWC3_GTXTHRCFG, reg);
1314 }
1315 } else {
1316 if (rx_thr_num && rx_maxburst) {
1317 reg = dwc3_readl(dwc, DWC3_GRXTHRCFG);
1318 reg |= DWC31_GRXTHRCFG_PKTCNTSEL;
1319
1320 reg &= ~DWC31_GRXTHRCFG_RXPKTCNT(~0);
1321 reg |= DWC31_GRXTHRCFG_RXPKTCNT(rx_thr_num);
1322
1323 reg &= ~DWC31_GRXTHRCFG_MAXRXBURSTSIZE(~0);
1324 reg |= DWC31_GRXTHRCFG_MAXRXBURSTSIZE(rx_maxburst);
1325
1326 dwc3_writel(dwc, DWC3_GRXTHRCFG, reg);
1327 }
1328
1329 if (tx_thr_num && tx_maxburst) {
1330 reg = dwc3_readl(dwc, DWC3_GTXTHRCFG);
1331 reg |= DWC31_GTXTHRCFG_PKTCNTSEL;
1332
1333 reg &= ~DWC31_GTXTHRCFG_TXPKTCNT(~0);
1334 reg |= DWC31_GTXTHRCFG_TXPKTCNT(tx_thr_num);
1335
1336 reg &= ~DWC31_GTXTHRCFG_MAXTXBURSTSIZE(~0);
1337 reg |= DWC31_GTXTHRCFG_MAXTXBURSTSIZE(tx_maxburst);
1338
1339 dwc3_writel(dwc, DWC3_GTXTHRCFG, reg);
1340 }
1341 }
1342}
1343
1344/**
1345 * dwc3_core_init - Low-level initialization of DWC3 Core
1346 * @dwc: Pointer to our controller context structure
1347 *
1348 * Returns 0 on success otherwise negative errno.
1349 */
1350int dwc3_core_init(struct dwc3 *dwc)
1351{
1352 unsigned int hw_mode;
1353 u32 reg;
1354 int ret;
1355
1356 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
1357
1358 ret = dwc3_phy_setup(dwc);
1359 if (ret)
1360 return ret;
1361
1362 if (!dwc->ulpi_ready) {
1363 ret = dwc3_core_ulpi_init(dwc);
1364 if (ret) {
1365 if (ret == -ETIMEDOUT) {
1366 dwc3_core_soft_reset(dwc);
1367 ret = -EPROBE_DEFER;
1368 }
1369 return ret;
1370 }
1371 dwc->ulpi_ready = true;
1372 }
1373
1374 dwc3_ulpi_setup(dwc);
1375
1376 if (!dwc->phys_ready) {
1377 ret = dwc3_core_get_phy(dwc);
1378 if (ret)
1379 goto err_exit_ulpi;
1380 dwc->phys_ready = true;
1381 }
1382
1383 ret = dwc3_phy_init(dwc);
1384 if (ret)
1385 goto err_exit_ulpi;
1386
1387 ret = dwc3_core_soft_reset(dwc);
1388 if (ret)
1389 goto err_exit_phy;
1390
1391 /*
1392 * Write Linux Version Code to our GUID register so it's easy to figure
1393 * out which kernel version a bug was found.
1394 */
1395 dwc3_writel(dwc, DWC3_GUID, LINUX_VERSION_CODE);
1396
1397 dwc3_core_setup_global_control(dwc);
1398 dwc3_core_num_eps(dwc);
1399
1400 /* Set power down scale of suspend_clk */
1401 dwc3_set_power_down_clk_scale(dwc);
1402
1403 /* Adjust Frame Length */
1404 dwc3_frame_length_adjustment(dwc);
1405
1406 /* Adjust Reference Clock Period */
1407 dwc3_ref_clk_period(dwc);
1408
1409 dwc3_set_incr_burst_type(dwc);
1410
1411 dwc3_config_soc_bus(dwc);
1412
1413 ret = dwc3_phy_power_on(dwc);
1414 if (ret)
1415 goto err_exit_phy;
1416
1417 ret = dwc3_event_buffers_setup(dwc);
1418 if (ret) {
1419 dev_err(dwc->dev, "failed to setup event buffers\n");
1420 goto err_power_off_phy;
1421 }
1422
1423 /*
1424 * ENDXFER polling is available on version 3.10a and later of
1425 * the DWC_usb3 controller. It is NOT available in the
1426 * DWC_usb31 controller.
1427 */
1428 if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) {
1429 reg = dwc3_readl(dwc, DWC3_GUCTL2);
1430 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
1431 dwc3_writel(dwc, DWC3_GUCTL2, reg);
1432 }
1433
1434 /*
1435 * STAR 9001285599: This issue affects DWC_usb3 version 3.20a
1436 * only. If the PM TIMER ECM is enabled through GUCTL2[19], the
1437 * link compliance test (TD7.21) may fail. If the ECN is not
1438 * enabled (GUCTL2[19] = 0), the controller will use the old timer
1439 * value (5us), which is still acceptable for the link compliance
1440 * test. Therefore, do not enable PM TIMER ECM in 3.20a by
1441 * setting GUCTL2[19] by default; instead, use GUCTL2[19] = 0.
1442 */
1443 if (DWC3_VER_IS(DWC3, 320A)) {
1444 reg = dwc3_readl(dwc, DWC3_GUCTL2);
1445 reg &= ~DWC3_GUCTL2_LC_TIMER;
1446 dwc3_writel(dwc, DWC3_GUCTL2, reg);
1447 }
1448
1449 /*
1450 * When configured in HOST mode, after issuing U3/L2 exit controller
1451 * fails to send proper CRC checksum in CRC5 field. Because of this
1452 * behaviour Transaction Error is generated, resulting in reset and
1453 * re-enumeration of usb device attached. All the termsel, xcvrsel,
1454 * opmode becomes 0 during end of resume. Enabling bit 10 of GUCTL1
1455 * will correct this problem. This option is to support certain
1456 * legacy ULPI PHYs.
1457 */
1458 if (dwc->resume_hs_terminations) {
1459 reg = dwc3_readl(dwc, DWC3_GUCTL1);
1460 reg |= DWC3_GUCTL1_RESUME_OPMODE_HS_HOST;
1461 dwc3_writel(dwc, DWC3_GUCTL1, reg);
1462 }
1463
1464 if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) {
1465 reg = dwc3_readl(dwc, DWC3_GUCTL1);
1466
1467 /*
1468 * Enable hardware control of sending remote wakeup
1469 * in HS when the device is in the L1 state.
1470 */
1471 if (!DWC3_VER_IS_PRIOR(DWC3, 290A))
1472 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
1473
1474 /*
1475 * Decouple USB 2.0 L1 & L2 events which will allow for
1476 * gadget driver to only receive U3/L2 suspend & wakeup
1477 * events and prevent the more frequent L1 LPM transitions
1478 * from interrupting the driver.
1479 */
1480 if (!DWC3_VER_IS_PRIOR(DWC3, 300A))
1481 reg |= DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT;
1482
1483 if (dwc->dis_tx_ipgap_linecheck_quirk)
1484 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
1485
1486 if (dwc->parkmode_disable_ss_quirk)
1487 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
1488
1489 if (dwc->parkmode_disable_hs_quirk)
1490 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_HS;
1491
1492 if (DWC3_VER_IS_WITHIN(DWC3, 290A, ANY)) {
1493 if (dwc->maximum_speed == USB_SPEED_FULL ||
1494 dwc->maximum_speed == USB_SPEED_HIGH)
1495 reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK;
1496 else
1497 reg &= ~DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK;
1498 }
1499
1500 dwc3_writel(dwc, DWC3_GUCTL1, reg);
1501 }
1502
1503 dwc3_config_threshold(dwc);
1504
1505 if (hw_mode != DWC3_GHWPARAMS0_MODE_GADGET &&
1506 (DWC3_IP_IS(DWC31)) &&
1507 dwc->maximum_speed == USB_SPEED_SUPER) {
1508 int i;
1509
1510 for (i = 0; i < dwc->num_usb3_ports; i++) {
1511 reg = dwc3_readl(dwc, DWC3_LLUCTL(i));
1512 reg |= DWC3_LLUCTL_FORCE_GEN1;
1513 dwc3_writel(dwc, DWC3_LLUCTL(i), reg);
1514 }
1515 }
1516
1517 /*
1518 * STAR 9001346572: This issue affects DWC_usb31 versions 1.80a and
1519 * prior. When an active endpoint not currently cached in the host
1520 * controller is chosen to be cached to the same index as an endpoint
1521 * receiving NAKs, the endpoint receiving NAKs enters continuous
1522 * retry mode. This prevents it from being evicted from the host
1523 * controller cache, blocking the new endpoint from being cached and
1524 * serviced.
1525 *
1526 * To resolve this, for controller versions 1.70a and 1.80a, set the
1527 * GUCTL3 bit[16] (USB2.0 Internal Retry Disable) to 1. This bit
1528 * disables the USB2.0 internal retry feature. The GUCTL3[16] register
1529 * function is available only from version 1.70a.
1530 */
1531 if (DWC3_VER_IS_WITHIN(DWC31, 170A, 180A)) {
1532 reg = dwc3_readl(dwc, DWC3_GUCTL3);
1533 reg |= DWC3_GUCTL3_USB20_RETRY_DISABLE;
1534 dwc3_writel(dwc, DWC3_GUCTL3, reg);
1535 }
1536
1537 return 0;
1538
1539err_power_off_phy:
1540 dwc3_phy_power_off(dwc);
1541err_exit_phy:
1542 dwc3_phy_exit(dwc);
1543err_exit_ulpi:
1544 dwc3_ulpi_exit(dwc);
1545
1546 return ret;
1547}
1548EXPORT_SYMBOL_GPL(dwc3_core_init);
1549
1550static int dwc3_core_get_phy(struct dwc3 *dwc)
1551{
1552 struct device *dev = dwc->dev;
1553 struct device_node *node = dev->of_node;
1554 char phy_name[9];
1555 int ret;
1556 u8 i;
1557
1558 if (node) {
1559 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
1560 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
1561 } else {
1562 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
1563 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
1564 }
1565
1566 if (IS_ERR(dwc->usb2_phy)) {
1567 ret = PTR_ERR(dwc->usb2_phy);
1568 if (ret == -ENXIO || ret == -ENODEV)
1569 dwc->usb2_phy = NULL;
1570 else
1571 return dev_err_probe(dev, ret, "no usb2 phy configured\n");
1572 }
1573
1574 if (IS_ERR(dwc->usb3_phy)) {
1575 ret = PTR_ERR(dwc->usb3_phy);
1576 if (ret == -ENXIO || ret == -ENODEV)
1577 dwc->usb3_phy = NULL;
1578 else
1579 return dev_err_probe(dev, ret, "no usb3 phy configured\n");
1580 }
1581
1582 for (i = 0; i < dwc->num_usb2_ports; i++) {
1583 if (dwc->num_usb2_ports == 1)
1584 snprintf(phy_name, sizeof(phy_name), "usb2-phy");
1585 else
1586 snprintf(phy_name, sizeof(phy_name), "usb2-%u", i);
1587
1588 dwc->usb2_generic_phy[i] = devm_phy_get(dev, phy_name);
1589 if (IS_ERR(dwc->usb2_generic_phy[i])) {
1590 ret = PTR_ERR(dwc->usb2_generic_phy[i]);
1591 if (ret == -ENOSYS || ret == -ENODEV)
1592 dwc->usb2_generic_phy[i] = NULL;
1593 else
1594 return dev_err_probe(dev, ret, "failed to lookup phy %s\n",
1595 phy_name);
1596 }
1597 }
1598
1599 for (i = 0; i < dwc->num_usb3_ports; i++) {
1600 if (dwc->num_usb3_ports == 1)
1601 snprintf(phy_name, sizeof(phy_name), "usb3-phy");
1602 else
1603 snprintf(phy_name, sizeof(phy_name), "usb3-%u", i);
1604
1605 dwc->usb3_generic_phy[i] = devm_phy_get(dev, phy_name);
1606 if (IS_ERR(dwc->usb3_generic_phy[i])) {
1607 ret = PTR_ERR(dwc->usb3_generic_phy[i]);
1608 if (ret == -ENOSYS || ret == -ENODEV)
1609 dwc->usb3_generic_phy[i] = NULL;
1610 else
1611 return dev_err_probe(dev, ret, "failed to lookup phy %s\n",
1612 phy_name);
1613 }
1614 }
1615
1616 return 0;
1617}
1618
1619static int dwc3_core_init_mode(struct dwc3 *dwc)
1620{
1621 struct device *dev = dwc->dev;
1622 int ret;
1623 int i;
1624
1625 switch (dwc->dr_mode) {
1626 case USB_DR_MODE_PERIPHERAL:
1627 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE, false);
1628
1629 if (dwc->usb2_phy)
1630 otg_set_vbus(dwc->usb2_phy->otg, false);
1631 phy_set_mode(dwc->usb2_generic_phy[0], PHY_MODE_USB_DEVICE);
1632 phy_set_mode(dwc->usb3_generic_phy[0], PHY_MODE_USB_DEVICE);
1633
1634 ret = dwc3_gadget_init(dwc);
1635 if (ret)
1636 return dev_err_probe(dev, ret, "failed to initialize gadget\n");
1637 break;
1638 case USB_DR_MODE_HOST:
1639 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST, false);
1640
1641 if (dwc->usb2_phy)
1642 otg_set_vbus(dwc->usb2_phy->otg, true);
1643 for (i = 0; i < dwc->num_usb2_ports; i++)
1644 phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST);
1645 for (i = 0; i < dwc->num_usb3_ports; i++)
1646 phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST);
1647
1648 ret = dwc3_host_init(dwc);
1649 if (ret)
1650 return dev_err_probe(dev, ret, "failed to initialize host\n");
1651 break;
1652 case USB_DR_MODE_OTG:
1653 INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
1654 ret = dwc3_drd_init(dwc);
1655 if (ret)
1656 return dev_err_probe(dev, ret, "failed to initialize dual-role\n");
1657 break;
1658 default:
1659 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
1660 return -EINVAL;
1661 }
1662
1663 return 0;
1664}
1665
1666static void dwc3_core_exit_mode(struct dwc3 *dwc)
1667{
1668 switch (dwc->dr_mode) {
1669 case USB_DR_MODE_PERIPHERAL:
1670 dwc3_gadget_exit(dwc);
1671 break;
1672 case USB_DR_MODE_HOST:
1673 dwc3_host_exit(dwc);
1674 break;
1675 case USB_DR_MODE_OTG:
1676 dwc3_drd_exit(dwc);
1677 break;
1678 default:
1679 /* do nothing */
1680 break;
1681 }
1682
1683 /* de-assert DRVVBUS for HOST and OTG mode */
1684 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE, true);
1685}
1686
1687static void dwc3_get_software_properties(struct dwc3 *dwc,
1688 const struct dwc3_properties *properties)
1689{
1690 struct device *tmpdev;
1691 u16 gsbuscfg0_reqinfo;
1692 int ret;
1693
1694 if (properties->needs_full_reinit)
1695 dwc->needs_full_reinit = true;
1696
1697 dwc->gsbuscfg0_reqinfo = DWC3_GSBUSCFG0_REQINFO_UNSPECIFIED;
1698
1699 if (properties->gsbuscfg0_reqinfo !=
1700 DWC3_GSBUSCFG0_REQINFO_UNSPECIFIED) {
1701 dwc->gsbuscfg0_reqinfo = properties->gsbuscfg0_reqinfo;
1702 return;
1703 }
1704
1705 /*
1706 * Iterate over all parent nodes for finding swnode properties
1707 * and non-DT (non-ABI) properties.
1708 */
1709 for (tmpdev = dwc->dev; tmpdev; tmpdev = tmpdev->parent) {
1710 ret = device_property_read_u16(tmpdev,
1711 "snps,gsbuscfg0-reqinfo",
1712 &gsbuscfg0_reqinfo);
1713 if (!ret)
1714 dwc->gsbuscfg0_reqinfo = gsbuscfg0_reqinfo;
1715 }
1716}
1717
1718static void dwc3_get_properties(struct dwc3 *dwc)
1719{
1720 struct device *dev = dwc->dev;
1721 u8 lpm_nyet_threshold;
1722 u8 tx_de_emphasis;
1723 u8 hird_threshold;
1724 u8 rx_thr_num_pkt = 0;
1725 u8 rx_max_burst = 0;
1726 u8 tx_thr_num_pkt = 0;
1727 u8 tx_max_burst = 0;
1728 u8 rx_thr_num_pkt_prd = 0;
1729 u8 rx_max_burst_prd = 0;
1730 u8 tx_thr_num_pkt_prd = 0;
1731 u8 tx_max_burst_prd = 0;
1732 u8 tx_fifo_resize_max_num;
1733 u16 num_hc_interrupters;
1734
1735 /* default to highest possible threshold */
1736 lpm_nyet_threshold = 0xf;
1737
1738 /* default to -3.5dB de-emphasis */
1739 tx_de_emphasis = 1;
1740
1741 /*
1742 * default to assert utmi_sleep_n and use maximum allowed HIRD
1743 * threshold value of 0b1100
1744 */
1745 hird_threshold = 12;
1746
1747 /*
1748 * default to a TXFIFO size large enough to fit 6 max packets. This
1749 * allows for systems with larger bus latencies to have some headroom
1750 * for endpoints that have a large bMaxBurst value.
1751 */
1752 tx_fifo_resize_max_num = 6;
1753
1754 /* default to a single XHCI interrupter */
1755 num_hc_interrupters = 1;
1756
1757 dwc->maximum_speed = usb_get_maximum_speed(dev);
1758 dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev);
1759 dwc->dr_mode = usb_get_dr_mode(dev);
1760 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
1761
1762 dwc->sysdev_is_parent = device_property_read_bool(dev,
1763 "linux,sysdev_is_parent");
1764 if (dwc->sysdev_is_parent)
1765 dwc->sysdev = dwc->dev->parent;
1766 else
1767 dwc->sysdev = dwc->dev;
1768
1769 dwc->sys_wakeup = device_may_wakeup(dwc->sysdev);
1770
1771 dwc->has_lpm_erratum = device_property_read_bool(dev,
1772 "snps,has-lpm-erratum");
1773 device_property_read_u8(dev, "snps,lpm-nyet-threshold",
1774 &lpm_nyet_threshold);
1775 dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
1776 "snps,is-utmi-l1-suspend");
1777 device_property_read_u8(dev, "snps,hird-threshold",
1778 &hird_threshold);
1779 dwc->dis_start_transfer_quirk = device_property_read_bool(dev,
1780 "snps,dis-start-transfer-quirk");
1781 dwc->usb3_lpm_capable = device_property_read_bool(dev,
1782 "snps,usb3_lpm_capable");
1783 dwc->usb2_lpm_disable = device_property_read_bool(dev,
1784 "snps,usb2-lpm-disable");
1785 dwc->usb2_gadget_lpm_disable = device_property_read_bool(dev,
1786 "snps,usb2-gadget-lpm-disable");
1787 device_property_read_u8(dev, "snps,rx-thr-num-pkt",
1788 &rx_thr_num_pkt);
1789 device_property_read_u8(dev, "snps,rx-max-burst",
1790 &rx_max_burst);
1791 device_property_read_u8(dev, "snps,tx-thr-num-pkt",
1792 &tx_thr_num_pkt);
1793 device_property_read_u8(dev, "snps,tx-max-burst",
1794 &tx_max_burst);
1795 device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd",
1796 &rx_thr_num_pkt_prd);
1797 device_property_read_u8(dev, "snps,rx-max-burst-prd",
1798 &rx_max_burst_prd);
1799 device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd",
1800 &tx_thr_num_pkt_prd);
1801 device_property_read_u8(dev, "snps,tx-max-burst-prd",
1802 &tx_max_burst_prd);
1803 device_property_read_u16(dev, "num-hc-interrupters",
1804 &num_hc_interrupters);
1805 /* DWC3 core allowed to have a max of 8 interrupters */
1806 if (num_hc_interrupters > 8)
1807 num_hc_interrupters = 8;
1808
1809 dwc->do_fifo_resize = device_property_read_bool(dev,
1810 "tx-fifo-resize");
1811 if (dwc->do_fifo_resize)
1812 device_property_read_u8(dev, "tx-fifo-max-num",
1813 &tx_fifo_resize_max_num);
1814
1815 dwc->disable_scramble_quirk = device_property_read_bool(dev,
1816 "snps,disable_scramble_quirk");
1817 dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
1818 "snps,u2exit_lfps_quirk");
1819 dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
1820 "snps,u2ss_inp3_quirk");
1821 dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
1822 "snps,req_p1p2p3_quirk");
1823 dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
1824 "snps,del_p1p2p3_quirk");
1825 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
1826 "snps,del_phy_power_chg_quirk");
1827 dwc->lfps_filter_quirk = device_property_read_bool(dev,
1828 "snps,lfps_filter_quirk");
1829 dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
1830 "snps,rx_detect_poll_quirk");
1831 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
1832 "snps,dis_u3_susphy_quirk");
1833 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
1834 "snps,dis_u2_susphy_quirk");
1835 dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1836 "snps,dis_enblslpm_quirk");
1837 dwc->dis_u1_entry_quirk = device_property_read_bool(dev,
1838 "snps,dis-u1-entry-quirk");
1839 dwc->dis_u2_entry_quirk = device_property_read_bool(dev,
1840 "snps,dis-u2-entry-quirk");
1841 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1842 "snps,dis_rxdet_inp3_quirk");
1843 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1844 "snps,dis-u2-freeclk-exists-quirk");
1845 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1846 "snps,dis-del-phy-power-chg-quirk");
1847 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1848 "snps,dis-tx-ipgap-linecheck-quirk");
1849 dwc->resume_hs_terminations = device_property_read_bool(dev,
1850 "snps,resume-hs-terminations");
1851 dwc->ulpi_ext_vbus_drv = device_property_read_bool(dev,
1852 "snps,ulpi-ext-vbus-drv");
1853 dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev,
1854 "snps,parkmode-disable-ss-quirk");
1855 dwc->parkmode_disable_hs_quirk = device_property_read_bool(dev,
1856 "snps,parkmode-disable-hs-quirk");
1857 dwc->gfladj_refclk_lpm_sel = device_property_read_bool(dev,
1858 "snps,gfladj-refclk-lpm-sel-quirk");
1859
1860 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
1861 "snps,tx_de_emphasis_quirk");
1862 device_property_read_u8(dev, "snps,tx_de_emphasis",
1863 &tx_de_emphasis);
1864 device_property_read_string(dev, "snps,hsphy_interface",
1865 &dwc->hsphy_interface);
1866 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
1867 &dwc->fladj);
1868 device_property_read_u32(dev, "snps,ref-clock-period-ns",
1869 &dwc->ref_clk_per);
1870
1871 dwc->dis_metastability_quirk = device_property_read_bool(dev,
1872 "snps,dis_metastability_quirk");
1873
1874 dwc->dis_split_quirk = device_property_read_bool(dev,
1875 "snps,dis-split-quirk");
1876
1877 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1878 dwc->tx_de_emphasis = tx_de_emphasis;
1879
1880 dwc->hird_threshold = hird_threshold;
1881
1882 dwc->rx_thr_num_pkt = rx_thr_num_pkt;
1883 dwc->rx_max_burst = rx_max_burst;
1884
1885 dwc->tx_thr_num_pkt = tx_thr_num_pkt;
1886 dwc->tx_max_burst = tx_max_burst;
1887
1888 dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
1889 dwc->rx_max_burst_prd = rx_max_burst_prd;
1890
1891 dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
1892 dwc->tx_max_burst_prd = tx_max_burst_prd;
1893
1894 dwc->tx_fifo_resize_max_num = tx_fifo_resize_max_num;
1895
1896 dwc->num_hc_interrupters = num_hc_interrupters;
1897}
1898
1899/* check whether the core supports IMOD */
1900bool dwc3_has_imod(struct dwc3 *dwc)
1901{
1902 return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) ||
1903 DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) ||
1904 DWC3_IP_IS(DWC32);
1905}
1906
1907static void dwc3_check_params(struct dwc3 *dwc)
1908{
1909 struct device *dev = dwc->dev;
1910 unsigned int hwparam_gen =
1911 DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3);
1912
1913 /*
1914 * Enable IMOD for all supporting controllers.
1915 *
1916 * Particularly, DWC_usb3 v3.00a must enable this feature for
1917 * the following reason:
1918 *
1919 * Workaround for STAR 9000961433 which affects only version
1920 * 3.00a of the DWC_usb3 core. This prevents the controller
1921 * interrupt from being masked while handling events. IMOD
1922 * allows us to work around this issue. Enable it for the
1923 * affected version.
1924 */
1925 if (dwc3_has_imod((dwc)))
1926 dwc->imod_interval = 1;
1927
1928 /* Check the maximum_speed parameter */
1929 switch (dwc->maximum_speed) {
1930 case USB_SPEED_FULL:
1931 case USB_SPEED_HIGH:
1932 break;
1933 case USB_SPEED_SUPER:
1934 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS)
1935 dev_warn(dev, "UDC doesn't support Gen 1\n");
1936 break;
1937 case USB_SPEED_SUPER_PLUS:
1938 if ((DWC3_IP_IS(DWC32) &&
1939 hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) ||
1940 (!DWC3_IP_IS(DWC32) &&
1941 hwparam_gen != DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1942 dev_warn(dev, "UDC doesn't support SSP\n");
1943 break;
1944 default:
1945 dev_err(dev, "invalid maximum_speed parameter %d\n",
1946 dwc->maximum_speed);
1947 fallthrough;
1948 case USB_SPEED_UNKNOWN:
1949 switch (hwparam_gen) {
1950 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
1951 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1952 break;
1953 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1954 if (DWC3_IP_IS(DWC32))
1955 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1956 else
1957 dwc->maximum_speed = USB_SPEED_SUPER;
1958 break;
1959 case DWC3_GHWPARAMS3_SSPHY_IFC_DIS:
1960 dwc->maximum_speed = USB_SPEED_HIGH;
1961 break;
1962 default:
1963 dwc->maximum_speed = USB_SPEED_SUPER;
1964 break;
1965 }
1966 break;
1967 }
1968
1969 /*
1970 * Currently the controller does not have visibility into the HW
1971 * parameter to determine the maximum number of lanes the HW supports.
1972 * If the number of lanes is not specified in the device property, then
1973 * set the default to support dual-lane for DWC_usb32 and single-lane
1974 * for DWC_usb31 for super-speed-plus.
1975 */
1976 if (dwc->maximum_speed == USB_SPEED_SUPER_PLUS) {
1977 switch (dwc->max_ssp_rate) {
1978 case USB_SSP_GEN_2x1:
1979 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_GEN1)
1980 dev_warn(dev, "UDC only supports Gen 1\n");
1981 break;
1982 case USB_SSP_GEN_1x2:
1983 case USB_SSP_GEN_2x2:
1984 if (DWC3_IP_IS(DWC31))
1985 dev_warn(dev, "UDC only supports single lane\n");
1986 break;
1987 case USB_SSP_GEN_UNKNOWN:
1988 default:
1989 switch (hwparam_gen) {
1990 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
1991 if (DWC3_IP_IS(DWC32))
1992 dwc->max_ssp_rate = USB_SSP_GEN_2x2;
1993 else
1994 dwc->max_ssp_rate = USB_SSP_GEN_2x1;
1995 break;
1996 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1997 if (DWC3_IP_IS(DWC32))
1998 dwc->max_ssp_rate = USB_SSP_GEN_1x2;
1999 break;
2000 }
2001 break;
2002 }
2003 }
2004}
2005
2006static struct extcon_dev *dwc3_get_extcon(struct dwc3 *dwc)
2007{
2008 struct device *dev = dwc->dev;
2009 struct device_node *np_phy;
2010 struct extcon_dev *edev = NULL;
2011 const char *name;
2012
2013 if (device_property_present(dev, "extcon"))
2014 return extcon_get_edev_by_phandle(dev, 0);
2015
2016 /*
2017 * Device tree platforms should get extcon via phandle.
2018 * On ACPI platforms, we get the name from a device property.
2019 * This device property is for kernel internal use only and
2020 * is expected to be set by the glue code.
2021 */
2022 if (device_property_read_string(dev, "linux,extcon-name", &name) == 0)
2023 return extcon_get_extcon_dev(name);
2024
2025 /*
2026 * Check explicitly if "usb-role-switch" is used since
2027 * extcon_find_edev_by_node() can not be used to check the absence of
2028 * an extcon device. In the absence of an device it will always return
2029 * EPROBE_DEFER.
2030 */
2031 if (IS_ENABLED(CONFIG_USB_ROLE_SWITCH) &&
2032 device_property_read_bool(dev, "usb-role-switch"))
2033 return NULL;
2034
2035 /*
2036 * Try to get an extcon device from the USB PHY controller's "port"
2037 * node. Check if it has the "port" node first, to avoid printing the
2038 * error message from underlying code, as it's a valid case: extcon
2039 * device (and "port" node) may be missing in case of "usb-role-switch"
2040 * or OTG mode.
2041 */
2042 np_phy = of_parse_phandle(dev->of_node, "phys", 0);
2043 if (of_graph_is_present(np_phy)) {
2044 struct device_node *np_conn;
2045
2046 np_conn = of_graph_get_remote_node(np_phy, -1, -1);
2047 if (np_conn)
2048 edev = extcon_find_edev_by_node(np_conn);
2049 of_node_put(np_conn);
2050 }
2051 of_node_put(np_phy);
2052
2053 return edev;
2054}
2055
2056static int dwc3_get_clocks(struct dwc3 *dwc)
2057{
2058 struct device *dev = dwc->dev;
2059
2060 if (!dev->of_node)
2061 return 0;
2062
2063 /*
2064 * Clocks are optional, but new DT platforms should support all clocks
2065 * as required by the DT-binding.
2066 * Some devices have different clock names in legacy device trees,
2067 * check for them to retain backwards compatibility.
2068 */
2069 dwc->bus_clk = devm_clk_get_optional(dev, "bus_early");
2070 if (IS_ERR(dwc->bus_clk)) {
2071 return dev_err_probe(dev, PTR_ERR(dwc->bus_clk),
2072 "could not get bus clock\n");
2073 }
2074
2075 if (dwc->bus_clk == NULL) {
2076 dwc->bus_clk = devm_clk_get_optional(dev, "bus_clk");
2077 if (IS_ERR(dwc->bus_clk)) {
2078 return dev_err_probe(dev, PTR_ERR(dwc->bus_clk),
2079 "could not get bus clock\n");
2080 }
2081 }
2082
2083 dwc->ref_clk = devm_clk_get_optional(dev, "ref");
2084 if (IS_ERR(dwc->ref_clk)) {
2085 return dev_err_probe(dev, PTR_ERR(dwc->ref_clk),
2086 "could not get ref clock\n");
2087 }
2088
2089 if (dwc->ref_clk == NULL) {
2090 dwc->ref_clk = devm_clk_get_optional(dev, "ref_clk");
2091 if (IS_ERR(dwc->ref_clk)) {
2092 return dev_err_probe(dev, PTR_ERR(dwc->ref_clk),
2093 "could not get ref clock\n");
2094 }
2095 }
2096
2097 dwc->susp_clk = devm_clk_get_optional(dev, "suspend");
2098 if (IS_ERR(dwc->susp_clk)) {
2099 return dev_err_probe(dev, PTR_ERR(dwc->susp_clk),
2100 "could not get suspend clock\n");
2101 }
2102
2103 if (dwc->susp_clk == NULL) {
2104 dwc->susp_clk = devm_clk_get_optional(dev, "suspend_clk");
2105 if (IS_ERR(dwc->susp_clk)) {
2106 return dev_err_probe(dev, PTR_ERR(dwc->susp_clk),
2107 "could not get suspend clock\n");
2108 }
2109 }
2110
2111 /* specific to Rockchip RK3588 */
2112 dwc->utmi_clk = devm_clk_get_optional(dev, "utmi");
2113 if (IS_ERR(dwc->utmi_clk)) {
2114 return dev_err_probe(dev, PTR_ERR(dwc->utmi_clk),
2115 "could not get utmi clock\n");
2116 }
2117
2118 /* specific to Rockchip RK3588 */
2119 dwc->pipe_clk = devm_clk_get_optional(dev, "pipe");
2120 if (IS_ERR(dwc->pipe_clk)) {
2121 return dev_err_probe(dev, PTR_ERR(dwc->pipe_clk),
2122 "could not get pipe clock\n");
2123 }
2124
2125 return 0;
2126}
2127
2128static int dwc3_get_num_ports(struct dwc3 *dwc)
2129{
2130 void __iomem *base;
2131 u8 major_revision;
2132 u32 offset;
2133 u32 val;
2134
2135 /*
2136 * Remap xHCI address space to access XHCI ext cap regs since it is
2137 * needed to get information on number of ports present.
2138 */
2139 base = ioremap(dwc->xhci_resources[0].start,
2140 resource_size(&dwc->xhci_resources[0]));
2141 if (!base)
2142 return -ENOMEM;
2143
2144 offset = 0;
2145 do {
2146 offset = xhci_find_next_ext_cap(base, offset,
2147 XHCI_EXT_CAPS_PROTOCOL);
2148 if (!offset)
2149 break;
2150
2151 val = readl(base + offset);
2152 major_revision = XHCI_EXT_PORT_MAJOR(val);
2153
2154 val = readl(base + offset + 0x08);
2155 if (major_revision == 0x03) {
2156 dwc->num_usb3_ports += XHCI_EXT_PORT_COUNT(val);
2157 } else if (major_revision <= 0x02) {
2158 dwc->num_usb2_ports += XHCI_EXT_PORT_COUNT(val);
2159 } else {
2160 dev_warn(dwc->dev, "unrecognized port major revision %d\n",
2161 major_revision);
2162 }
2163 } while (1);
2164
2165 dev_dbg(dwc->dev, "hs-ports: %u ss-ports: %u\n",
2166 dwc->num_usb2_ports, dwc->num_usb3_ports);
2167
2168 iounmap(base);
2169
2170 if (dwc->num_usb2_ports > DWC3_USB2_MAX_PORTS ||
2171 dwc->num_usb3_ports > DWC3_USB3_MAX_PORTS)
2172 return -EINVAL;
2173
2174 return 0;
2175}
2176
2177static void dwc3_vbus_draw_work(struct work_struct *work)
2178{
2179 struct dwc3 *dwc = container_of(work, struct dwc3, vbus_draw_work);
2180 union power_supply_propval val = {0};
2181 int ret;
2182
2183 val.intval = 1000 * (dwc->current_limit);
2184 ret = power_supply_set_property(dwc->usb_psy, POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT, &val);
2185
2186 if (ret < 0)
2187 dev_dbg(dwc->dev, "Error (%d) setting vbus draw (%d mA)\n",
2188 ret, dwc->current_limit);
2189}
2190
2191static int dwc3_psy_notifier(struct notifier_block *nb,
2192 unsigned long event, void *data)
2193{
2194 struct dwc3 *dwc = container_of(nb, struct dwc3, psy_nb);
2195 struct power_supply *psy = data;
2196 unsigned long flags;
2197
2198 if (dwc->usb_psy)
2199 return NOTIFY_DONE;
2200
2201 if (strcmp(psy->desc->name, dwc->usb_psy_name) != 0)
2202 return NOTIFY_DONE;
2203
2204 /* Explicitly get the reference for this psy */
2205 psy = power_supply_get_by_name(dwc->usb_psy_name);
2206 if (!psy)
2207 return NOTIFY_DONE;
2208
2209 spin_lock_irqsave(&dwc->lock, flags);
2210 /*
2211 * The USB power_supply may already be set. This can happen if notifier
2212 * callbacks for the USB power_supply race, or if a previous notifier
2213 * callback has already successfully fetched and associated the instance.
2214 * In such cases, release the newly acquired reference and ignore
2215 * subsequent notifications until the notifier is unregistered.
2216 */
2217 if (dwc->usb_psy) {
2218 spin_unlock_irqrestore(&dwc->lock, flags);
2219 power_supply_put(psy);
2220 return NOTIFY_DONE;
2221 }
2222
2223 dwc->usb_psy = psy;
2224 if (dwc->current_limit != DWC3_CURRENT_UNSPECIFIED)
2225 schedule_work(&dwc->vbus_draw_work);
2226 spin_unlock_irqrestore(&dwc->lock, flags);
2227
2228 return NOTIFY_OK;
2229}
2230
2231static void dwc3_get_usb_power_supply(struct dwc3 *dwc)
2232{
2233 struct power_supply *psy;
2234 unsigned long flags;
2235 int ret;
2236
2237 ret = device_property_read_string(dwc->dev, "usb-psy-name", &dwc->usb_psy_name);
2238 if (ret < 0)
2239 return;
2240
2241 INIT_WORK(&dwc->vbus_draw_work, dwc3_vbus_draw_work);
2242
2243 dwc->current_limit = DWC3_CURRENT_UNSPECIFIED;
2244 dwc->psy_nb.notifier_call = dwc3_psy_notifier;
2245 ret = power_supply_reg_notifier(&dwc->psy_nb);
2246 if (ret) {
2247 dev_err(dwc->dev, "Failed to register power supply notifier: %d\n", ret);
2248 dwc->psy_nb.notifier_call = NULL;
2249 return;
2250 }
2251
2252 psy = power_supply_get_by_name(dwc->usb_psy_name);
2253 if (!psy)
2254 return;
2255
2256 /* Unregister the notifier now that we have the power supply */
2257 power_supply_unreg_notifier(&dwc->psy_nb);
2258 dwc->psy_nb.notifier_call = NULL;
2259
2260 spin_lock_irqsave(&dwc->lock, flags);
2261 /*
2262 * It is possible that the notifier callback ran before we reached here
2263 * and successfully fetched the power supply. In that case we need to
2264 * release the above reference.
2265 */
2266 if (dwc->usb_psy) {
2267 spin_unlock_irqrestore(&dwc->lock, flags);
2268 power_supply_put(psy);
2269 return;
2270 }
2271
2272 dwc->usb_psy = psy;
2273 spin_unlock_irqrestore(&dwc->lock, flags);
2274}
2275
2276int dwc3_core_probe(const struct dwc3_probe_data *data)
2277{
2278 struct dwc3 *dwc = data->dwc;
2279 struct device *dev = dwc->dev;
2280 struct resource dwc_res;
2281 unsigned int hw_mode;
2282 void __iomem *regs;
2283 struct resource *res = data->res;
2284 int ret;
2285
2286 dwc->xhci_resources[0].start = res->start;
2287 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
2288 DWC3_XHCI_REGS_END;
2289 dwc->xhci_resources[0].flags = res->flags;
2290 dwc->xhci_resources[0].name = res->name;
2291
2292 /*
2293 * Request memory region but exclude xHCI regs,
2294 * since it will be requested by the xhci-plat driver.
2295 */
2296 dwc_res = *res;
2297 dwc_res.start += DWC3_GLOBALS_REGS_START;
2298
2299 if (dev->of_node) {
2300 struct device_node *parent = of_get_parent(dev->of_node);
2301
2302 if (of_device_is_compatible(parent, "realtek,rtd-dwc3")) {
2303 dwc_res.start -= DWC3_GLOBALS_REGS_START;
2304 dwc_res.start += DWC3_RTK_RTD_GLOBALS_REGS_START;
2305 }
2306
2307 of_node_put(parent);
2308 }
2309
2310 regs = devm_ioremap_resource(dev, &dwc_res);
2311 if (IS_ERR(regs))
2312 return PTR_ERR(regs);
2313
2314 dwc->regs = regs;
2315 dwc->regs_size = resource_size(&dwc_res);
2316
2317 dwc3_get_properties(dwc);
2318
2319 dwc3_get_software_properties(dwc, &data->properties);
2320
2321 spin_lock_init(&dwc->lock);
2322
2323 dwc3_get_usb_power_supply(dwc);
2324
2325 if (!data->ignore_clocks_and_resets) {
2326 dwc->reset = devm_reset_control_array_get_optional_shared(dev);
2327 if (IS_ERR(dwc->reset)) {
2328 ret = PTR_ERR(dwc->reset);
2329 goto err_put_psy;
2330 }
2331
2332 ret = dwc3_get_clocks(dwc);
2333 if (ret)
2334 goto err_put_psy;
2335 }
2336
2337 ret = reset_control_deassert(dwc->reset);
2338 if (ret)
2339 goto err_put_psy;
2340
2341 ret = dwc3_clk_enable(dwc);
2342 if (ret)
2343 goto err_assert_reset;
2344
2345 if (!dwc3_core_is_valid(dwc)) {
2346 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
2347 ret = -ENODEV;
2348 goto err_disable_clks;
2349 }
2350
2351 dev_set_drvdata(dev, dwc);
2352 dwc3_cache_hwparams(dwc);
2353
2354 if (!dev_is_pci(dwc->sysdev) &&
2355 DWC3_GHWPARAMS0_AWIDTH(dwc->hwparams.hwparams0) == 64) {
2356 ret = dma_set_mask_and_coherent(dwc->sysdev, DMA_BIT_MASK(64));
2357 if (ret)
2358 goto err_disable_clks;
2359 }
2360
2361 /*
2362 * Currently only DWC3 controllers that are host-only capable
2363 * can have more than one port.
2364 */
2365 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
2366 if (hw_mode == DWC3_GHWPARAMS0_MODE_HOST) {
2367 ret = dwc3_get_num_ports(dwc);
2368 if (ret)
2369 goto err_disable_clks;
2370 } else {
2371 dwc->num_usb2_ports = 1;
2372 dwc->num_usb3_ports = 1;
2373 }
2374
2375 mutex_init(&dwc->mutex);
2376
2377 pm_runtime_get_noresume(dev);
2378 pm_runtime_set_active(dev);
2379 pm_runtime_use_autosuspend(dev);
2380 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
2381 pm_runtime_enable(dev);
2382
2383 pm_runtime_forbid(dev);
2384
2385 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
2386 if (ret) {
2387 dev_err(dwc->dev, "failed to allocate event buffers\n");
2388 ret = -ENOMEM;
2389 goto err_allow_rpm;
2390 }
2391
2392 dwc->edev = dwc3_get_extcon(dwc);
2393 if (IS_ERR(dwc->edev)) {
2394 ret = dev_err_probe(dwc->dev, PTR_ERR(dwc->edev), "failed to get extcon\n");
2395 goto err_free_event_buffers;
2396 }
2397
2398 ret = dwc3_get_dr_mode(dwc);
2399 if (ret)
2400 goto err_free_event_buffers;
2401
2402 ret = dwc3_core_init(dwc);
2403 if (ret) {
2404 dev_err_probe(dev, ret, "failed to initialize core\n");
2405 goto err_free_event_buffers;
2406 }
2407
2408 dwc3_check_params(dwc);
2409 dwc3_debugfs_init(dwc);
2410
2411 if (!data->skip_core_init_mode) {
2412 ret = dwc3_core_init_mode(dwc);
2413 if (ret)
2414 goto err_exit_debugfs;
2415 }
2416
2417 pm_runtime_put(dev);
2418
2419 dma_set_max_seg_size(dev, UINT_MAX);
2420
2421 return 0;
2422
2423err_exit_debugfs:
2424 dwc3_debugfs_exit(dwc);
2425 dwc3_event_buffers_cleanup(dwc);
2426 dwc3_phy_power_off(dwc);
2427 dwc3_phy_exit(dwc);
2428 dwc3_ulpi_exit(dwc);
2429err_free_event_buffers:
2430 dwc3_free_event_buffers(dwc);
2431err_allow_rpm:
2432 pm_runtime_allow(dev);
2433 pm_runtime_disable(dev);
2434 pm_runtime_dont_use_autosuspend(dev);
2435 pm_runtime_set_suspended(dev);
2436 pm_runtime_put_noidle(dev);
2437err_disable_clks:
2438 dwc3_clk_disable(dwc);
2439err_assert_reset:
2440 reset_control_assert(dwc->reset);
2441err_put_psy:
2442 if (dwc->psy_nb.notifier_call)
2443 power_supply_unreg_notifier(&dwc->psy_nb);
2444 if (dwc->usb_psy)
2445 power_supply_put(dwc->usb_psy);
2446
2447 return ret;
2448}
2449EXPORT_SYMBOL_GPL(dwc3_core_probe);
2450
2451static int dwc3_probe(struct platform_device *pdev)
2452{
2453 struct dwc3_probe_data probe_data = {};
2454 struct resource *res;
2455 struct dwc3 *dwc;
2456
2457 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2458 if (!res) {
2459 dev_err(&pdev->dev, "missing memory resource\n");
2460 return -ENODEV;
2461 }
2462
2463 dwc = devm_kzalloc(&pdev->dev, sizeof(*dwc), GFP_KERNEL);
2464 if (!dwc)
2465 return -ENOMEM;
2466
2467 dwc->dev = &pdev->dev;
2468 dwc->glue_ops = NULL;
2469
2470 probe_data.dwc = dwc;
2471 probe_data.res = res;
2472 probe_data.properties = DWC3_DEFAULT_PROPERTIES;
2473
2474 return dwc3_core_probe(&probe_data);
2475}
2476
2477void dwc3_core_remove(struct dwc3 *dwc)
2478{
2479 pm_runtime_get_sync(dwc->dev);
2480
2481 dwc3_core_exit_mode(dwc);
2482 dwc3_debugfs_exit(dwc);
2483
2484 dwc3_core_exit(dwc);
2485 dwc3_ulpi_exit(dwc);
2486
2487 pm_runtime_allow(dwc->dev);
2488 pm_runtime_disable(dwc->dev);
2489 pm_runtime_dont_use_autosuspend(dwc->dev);
2490 pm_runtime_put_noidle(dwc->dev);
2491 /*
2492 * HACK: Clear the driver data, which is currently accessed by parent
2493 * glue drivers, before allowing the parent to suspend.
2494 */
2495 dev_set_drvdata(dwc->dev, NULL);
2496 pm_runtime_set_suspended(dwc->dev);
2497
2498 dwc3_free_event_buffers(dwc);
2499
2500 if (dwc->psy_nb.notifier_call)
2501 power_supply_unreg_notifier(&dwc->psy_nb);
2502
2503 if (dwc->usb_psy) {
2504 cancel_work_sync(&dwc->vbus_draw_work);
2505 power_supply_put(dwc->usb_psy);
2506 }
2507}
2508EXPORT_SYMBOL_GPL(dwc3_core_remove);
2509
2510static void dwc3_remove(struct platform_device *pdev)
2511{
2512 dwc3_core_remove(platform_get_drvdata(pdev));
2513}
2514
2515#ifdef CONFIG_PM
2516static int dwc3_core_init_for_resume(struct dwc3 *dwc)
2517{
2518 int ret;
2519
2520 ret = reset_control_deassert(dwc->reset);
2521 if (ret)
2522 return ret;
2523
2524 ret = dwc3_clk_enable(dwc);
2525 if (ret)
2526 goto assert_reset;
2527
2528 ret = dwc3_core_init(dwc);
2529 if (ret)
2530 goto disable_clks;
2531
2532 return 0;
2533
2534disable_clks:
2535 dwc3_clk_disable(dwc);
2536assert_reset:
2537 reset_control_assert(dwc->reset);
2538
2539 return ret;
2540}
2541
2542static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
2543{
2544 u32 reg;
2545 int i;
2546 int ret;
2547
2548 if (!pm_runtime_suspended(dwc->dev) && !PMSG_IS_AUTO(msg)) {
2549 dwc->susphy_state = (dwc3_readl(dwc, DWC3_GUSB2PHYCFG(0)) &
2550 DWC3_GUSB2PHYCFG_SUSPHY) ||
2551 (dwc3_readl(dwc, DWC3_GUSB3PIPECTL(0)) &
2552 DWC3_GUSB3PIPECTL_SUSPHY);
2553 /*
2554 * TI AM62 platform requires SUSPHY to be
2555 * enabled for system suspend to work.
2556 */
2557 if (!dwc->susphy_state)
2558 dwc3_enable_susphy(dwc, true);
2559 }
2560
2561 switch (dwc->current_dr_role) {
2562 case DWC3_GCTL_PRTCAP_DEVICE:
2563 if (pm_runtime_suspended(dwc->dev))
2564 break;
2565 ret = dwc3_gadget_suspend(dwc);
2566 if (ret)
2567 return ret;
2568 synchronize_irq(dwc->irq_gadget);
2569 dwc3_core_exit(dwc);
2570 break;
2571 case DWC3_GCTL_PRTCAP_HOST:
2572 if (!PMSG_IS_AUTO(msg) &&
2573 (!device_may_wakeup(dwc->dev) || dwc->needs_full_reinit)) {
2574 dwc3_core_exit(dwc);
2575 break;
2576 }
2577
2578 /* Let controller to suspend HSPHY before PHY driver suspends */
2579 if (dwc->dis_u2_susphy_quirk ||
2580 dwc->dis_enblslpm_quirk) {
2581 for (i = 0; i < dwc->num_usb2_ports; i++) {
2582 reg = dwc3_readl(dwc, DWC3_GUSB2PHYCFG(i));
2583 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM |
2584 DWC3_GUSB2PHYCFG_SUSPHY;
2585 dwc3_writel(dwc, DWC3_GUSB2PHYCFG(i), reg);
2586 }
2587
2588 /* Give some time for USB2 PHY to suspend */
2589 usleep_range(5000, 6000);
2590 }
2591
2592 for (i = 0; i < dwc->num_usb2_ports; i++)
2593 phy_pm_runtime_put_sync(dwc->usb2_generic_phy[i]);
2594 for (i = 0; i < dwc->num_usb3_ports; i++)
2595 phy_pm_runtime_put_sync(dwc->usb3_generic_phy[i]);
2596 break;
2597 case DWC3_GCTL_PRTCAP_OTG:
2598 /* do nothing during runtime_suspend */
2599 if (PMSG_IS_AUTO(msg))
2600 break;
2601
2602 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
2603 ret = dwc3_gadget_suspend(dwc);
2604 if (ret)
2605 return ret;
2606 synchronize_irq(dwc->irq_gadget);
2607 }
2608
2609 dwc3_otg_exit(dwc);
2610 dwc3_core_exit(dwc);
2611 break;
2612 default:
2613 /* do nothing */
2614 break;
2615 }
2616
2617 return 0;
2618}
2619
2620static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
2621{
2622 int ret;
2623 u32 reg;
2624 int i;
2625
2626 switch (dwc->current_dr_role) {
2627 case DWC3_GCTL_PRTCAP_DEVICE:
2628 ret = dwc3_core_init_for_resume(dwc);
2629 if (ret)
2630 return ret;
2631
2632 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE, true);
2633 dwc3_gadget_resume(dwc);
2634 break;
2635 case DWC3_GCTL_PRTCAP_HOST:
2636 if (!PMSG_IS_AUTO(msg) &&
2637 (!device_may_wakeup(dwc->dev) || dwc->needs_full_reinit)) {
2638 ret = dwc3_core_init_for_resume(dwc);
2639 if (ret)
2640 return ret;
2641 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST, true);
2642 break;
2643 }
2644 /* Restore GUSB2PHYCFG bits that were modified in suspend */
2645 for (i = 0; i < dwc->num_usb2_ports; i++) {
2646 reg = dwc3_readl(dwc, DWC3_GUSB2PHYCFG(i));
2647 if (dwc->dis_u2_susphy_quirk)
2648 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
2649
2650 if (dwc->dis_enblslpm_quirk)
2651 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
2652
2653 dwc3_writel(dwc, DWC3_GUSB2PHYCFG(i), reg);
2654 }
2655
2656 for (i = 0; i < dwc->num_usb2_ports; i++)
2657 phy_pm_runtime_get_sync(dwc->usb2_generic_phy[i]);
2658 for (i = 0; i < dwc->num_usb3_ports; i++)
2659 phy_pm_runtime_get_sync(dwc->usb3_generic_phy[i]);
2660 break;
2661 case DWC3_GCTL_PRTCAP_OTG:
2662 /* nothing to do on runtime_resume */
2663 if (PMSG_IS_AUTO(msg))
2664 break;
2665
2666 ret = dwc3_core_init_for_resume(dwc);
2667 if (ret)
2668 return ret;
2669
2670 dwc3_set_prtcap(dwc, dwc->current_dr_role, true);
2671
2672 dwc3_otg_init(dwc);
2673 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) {
2674 dwc3_otg_host_init(dwc);
2675 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
2676 dwc3_gadget_resume(dwc);
2677 }
2678
2679 break;
2680 default:
2681 /* do nothing */
2682 break;
2683 }
2684
2685 if (!PMSG_IS_AUTO(msg)) {
2686 /* restore SUSPHY state to that before system suspend. */
2687 dwc3_enable_susphy(dwc, dwc->susphy_state);
2688 }
2689
2690 return 0;
2691}
2692
2693static int dwc3_runtime_checks(struct dwc3 *dwc)
2694{
2695 switch (dwc->current_dr_role) {
2696 case DWC3_GCTL_PRTCAP_DEVICE:
2697 if (dwc->connected)
2698 return -EBUSY;
2699 break;
2700 case DWC3_GCTL_PRTCAP_HOST:
2701 default:
2702 /* do nothing */
2703 break;
2704 }
2705
2706 return 0;
2707}
2708
2709int dwc3_runtime_suspend(struct dwc3 *dwc)
2710{
2711 int ret;
2712
2713 if (dwc3_runtime_checks(dwc))
2714 return -EBUSY;
2715
2716 ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
2717 if (ret)
2718 return ret;
2719
2720 return 0;
2721}
2722EXPORT_SYMBOL_GPL(dwc3_runtime_suspend);
2723
2724int dwc3_runtime_resume(struct dwc3 *dwc)
2725{
2726 struct device *dev = dwc->dev;
2727 int ret;
2728
2729 ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
2730 if (ret)
2731 return ret;
2732
2733 switch (dwc->current_dr_role) {
2734 case DWC3_GCTL_PRTCAP_DEVICE:
2735 if (dwc->pending_events) {
2736 pm_runtime_put(dev);
2737 dwc->pending_events = false;
2738 enable_irq(dwc->irq_gadget);
2739 }
2740 break;
2741 case DWC3_GCTL_PRTCAP_HOST:
2742 default:
2743 /* do nothing */
2744 break;
2745 }
2746
2747 pm_runtime_mark_last_busy(dev);
2748
2749 return 0;
2750}
2751EXPORT_SYMBOL_GPL(dwc3_runtime_resume);
2752
2753int dwc3_runtime_idle(struct dwc3 *dwc)
2754{
2755 struct device *dev = dwc->dev;
2756
2757 switch (dwc->current_dr_role) {
2758 case DWC3_GCTL_PRTCAP_DEVICE:
2759 if (dwc3_runtime_checks(dwc))
2760 return -EBUSY;
2761 break;
2762 case DWC3_GCTL_PRTCAP_HOST:
2763 default:
2764 /* do nothing */
2765 break;
2766 }
2767
2768 pm_runtime_autosuspend(dev);
2769
2770 return 0;
2771}
2772EXPORT_SYMBOL_GPL(dwc3_runtime_idle);
2773
2774static int dwc3_plat_runtime_suspend(struct device *dev)
2775{
2776 return dwc3_runtime_suspend(dev_get_drvdata(dev));
2777}
2778
2779static int dwc3_plat_runtime_resume(struct device *dev)
2780{
2781 return dwc3_runtime_resume(dev_get_drvdata(dev));
2782}
2783
2784static int dwc3_plat_runtime_idle(struct device *dev)
2785{
2786 return dwc3_runtime_idle(dev_get_drvdata(dev));
2787}
2788#endif /* CONFIG_PM */
2789
2790#ifdef CONFIG_PM_SLEEP
2791int dwc3_pm_suspend(struct dwc3 *dwc)
2792{
2793 struct device *dev = dwc->dev;
2794 int ret;
2795
2796 ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
2797 if (ret)
2798 return ret;
2799
2800 pinctrl_pm_select_sleep_state(dev);
2801
2802 return 0;
2803}
2804EXPORT_SYMBOL_GPL(dwc3_pm_suspend);
2805
2806int dwc3_pm_resume(struct dwc3 *dwc)
2807{
2808 struct device *dev = dwc->dev;
2809 int ret = 0;
2810
2811 pinctrl_pm_select_default_state(dev);
2812
2813 pm_runtime_disable(dev);
2814 ret = pm_runtime_set_active(dev);
2815 if (ret)
2816 goto out;
2817
2818 ret = dwc3_resume_common(dwc, PMSG_RESUME);
2819 if (ret)
2820 pm_runtime_set_suspended(dev);
2821
2822out:
2823 pm_runtime_enable(dev);
2824
2825 return ret;
2826}
2827EXPORT_SYMBOL_GPL(dwc3_pm_resume);
2828
2829void dwc3_pm_complete(struct dwc3 *dwc)
2830{
2831 u32 reg;
2832
2833 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST &&
2834 dwc->dis_split_quirk) {
2835 reg = dwc3_readl(dwc, DWC3_GUCTL3);
2836 reg |= DWC3_GUCTL3_SPLITDISABLE;
2837 dwc3_writel(dwc, DWC3_GUCTL3, reg);
2838 }
2839}
2840EXPORT_SYMBOL_GPL(dwc3_pm_complete);
2841
2842int dwc3_pm_prepare(struct dwc3 *dwc)
2843{
2844 struct device *dev = dwc->dev;
2845
2846 /*
2847 * Indicate to the PM core that it may safely leave the device in
2848 * runtime suspend if runtime-suspended already in device mode.
2849 */
2850 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_DEVICE &&
2851 pm_runtime_suspended(dev) &&
2852 !dev_pinctrl(dev))
2853 return 1;
2854
2855 return 0;
2856}
2857EXPORT_SYMBOL_GPL(dwc3_pm_prepare);
2858
2859static int dwc3_plat_suspend(struct device *dev)
2860{
2861 return dwc3_pm_suspend(dev_get_drvdata(dev));
2862}
2863
2864static int dwc3_plat_resume(struct device *dev)
2865{
2866 return dwc3_pm_resume(dev_get_drvdata(dev));
2867}
2868
2869static void dwc3_plat_complete(struct device *dev)
2870{
2871 dwc3_pm_complete(dev_get_drvdata(dev));
2872}
2873
2874static int dwc3_plat_prepare(struct device *dev)
2875{
2876 return dwc3_pm_prepare(dev_get_drvdata(dev));
2877}
2878#else
2879#define dwc3_plat_complete NULL
2880#define dwc3_plat_prepare NULL
2881#endif /* CONFIG_PM_SLEEP */
2882
2883static const struct dev_pm_ops dwc3_dev_pm_ops = {
2884 SET_SYSTEM_SLEEP_PM_OPS(dwc3_plat_suspend, dwc3_plat_resume)
2885 .complete = dwc3_plat_complete,
2886 .prepare = dwc3_plat_prepare,
2887 /*
2888 * Runtime suspend halts the controller on disconnection. It relies on
2889 * platforms with custom connection notification to start the controller
2890 * again.
2891 */
2892 SET_RUNTIME_PM_OPS(dwc3_plat_runtime_suspend, dwc3_plat_runtime_resume,
2893 dwc3_plat_runtime_idle)
2894};
2895
2896#ifdef CONFIG_OF
2897static const struct of_device_id of_dwc3_match[] = {
2898 {
2899 .compatible = "snps,dwc3"
2900 },
2901 {
2902 .compatible = "synopsys,dwc3"
2903 },
2904 { },
2905};
2906MODULE_DEVICE_TABLE(of, of_dwc3_match);
2907#endif
2908
2909#ifdef CONFIG_ACPI
2910
2911#define ACPI_ID_INTEL_BSW "808622B7"
2912
2913static const struct acpi_device_id dwc3_acpi_match[] = {
2914 { ACPI_ID_INTEL_BSW, 0 },
2915 { },
2916};
2917MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
2918#endif
2919
2920static struct platform_driver dwc3_driver = {
2921 .probe = dwc3_probe,
2922 .remove = dwc3_remove,
2923 .driver = {
2924 .name = "dwc3",
2925 .of_match_table = of_match_ptr(of_dwc3_match),
2926 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
2927 .pm = &dwc3_dev_pm_ops,
2928 },
2929};
2930
2931module_platform_driver(dwc3_driver);
2932
2933MODULE_ALIAS("platform:dwc3");
2934MODULE_AUTHOR("Felipe Balbi <[email protected]>");
2935MODULE_LICENSE("GPL v2");
2936MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");