projects/linux·blob master · refs

1218 lines · 32.0 KiB

1/*
2 * linux/drivers/video/arkfb.c -- Frame buffer device driver for ARK 2000PV
3 * with ICS 5342 dac (it is easy to add support for different dacs).
4 *
5 * Copyright (c) 2007 Ondrej Zajicek <[email protected]>
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file COPYING in the main directory of this archive for
9 * more details.
10 *
11 * Code is based on s3fb
12 */
13
14#include <linux/aperture.h>
15#include <linux/module.h>
16#include <linux/kernel.h>
17#include <linux/errno.h>
18#include <linux/string.h>
19#include <linux/mm.h>
20#include <linux/tty.h>
21#include <linux/slab.h>
22#include <linux/delay.h>
23#include <linux/fb.h>
24#include <linux/svga.h>
25#include <linux/init.h>
26#include <linux/pci.h>
27#include <linux/console.h> /* Why should fb driver call console functions? because console_lock() */
28#include <video/vga.h>
29
30struct arkfb_info {
31 int mclk_freq;
32 int wc_cookie;
33
34 struct dac_info *dac;
35 struct vgastate state;
36 struct mutex open_lock;
37 unsigned int ref_count;
38 u32 pseudo_palette[16];
39};
40
41
42/* ------------------------------------------------------------------------- */
43
44
45static const struct svga_fb_format arkfb_formats[] = {
46 { 0, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0,
47 FB_TYPE_TEXT, FB_AUX_TEXT_SVGA_STEP4, FB_VISUAL_PSEUDOCOLOR, 8, 8},
48 { 4, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0,
49 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 8, 16},
50 { 4, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 1,
51 FB_TYPE_INTERLEAVED_PLANES, 1, FB_VISUAL_PSEUDOCOLOR, 8, 16},
52 { 8, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0,
53 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 8, 8},
54 {16, {10, 5, 0}, {5, 5, 0}, {0, 5, 0}, {0, 0, 0}, 0,
55 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 4, 4},
56 {16, {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0}, 0,
57 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 4, 4},
58 {24, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0,
59 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 8, 8},
60 {32, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0,
61 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 2},
62 SVGA_FORMAT_END
63};
64
65
66/* CRT timing register sets */
67
68static const struct vga_regset ark_h_total_regs[] = {{0x00, 0, 7}, {0x41, 7, 7}, VGA_REGSET_END};
69static const struct vga_regset ark_h_display_regs[] = {{0x01, 0, 7}, {0x41, 6, 6}, VGA_REGSET_END};
70static const struct vga_regset ark_h_blank_start_regs[] = {{0x02, 0, 7}, {0x41, 5, 5}, VGA_REGSET_END};
71static const struct vga_regset ark_h_blank_end_regs[] = {{0x03, 0, 4}, {0x05, 7, 7 }, VGA_REGSET_END};
72static const struct vga_regset ark_h_sync_start_regs[] = {{0x04, 0, 7}, {0x41, 4, 4}, VGA_REGSET_END};
73static const struct vga_regset ark_h_sync_end_regs[] = {{0x05, 0, 4}, VGA_REGSET_END};
74
75static const struct vga_regset ark_v_total_regs[] = {{0x06, 0, 7}, {0x07, 0, 0}, {0x07, 5, 5}, {0x40, 7, 7}, VGA_REGSET_END};
76static const struct vga_regset ark_v_display_regs[] = {{0x12, 0, 7}, {0x07, 1, 1}, {0x07, 6, 6}, {0x40, 6, 6}, VGA_REGSET_END};
77static const struct vga_regset ark_v_blank_start_regs[] = {{0x15, 0, 7}, {0x07, 3, 3}, {0x09, 5, 5}, {0x40, 5, 5}, VGA_REGSET_END};
78// const struct vga_regset ark_v_blank_end_regs[] = {{0x16, 0, 6}, VGA_REGSET_END};
79static const struct vga_regset ark_v_blank_end_regs[] = {{0x16, 0, 7}, VGA_REGSET_END};
80static const struct vga_regset ark_v_sync_start_regs[] = {{0x10, 0, 7}, {0x07, 2, 2}, {0x07, 7, 7}, {0x40, 4, 4}, VGA_REGSET_END};
81static const struct vga_regset ark_v_sync_end_regs[] = {{0x11, 0, 3}, VGA_REGSET_END};
82
83static const struct vga_regset ark_line_compare_regs[] = {{0x18, 0, 7}, {0x07, 4, 4}, {0x09, 6, 6}, VGA_REGSET_END};
84static const struct vga_regset ark_start_address_regs[] = {{0x0d, 0, 7}, {0x0c, 0, 7}, {0x40, 0, 2}, VGA_REGSET_END};
85static const struct vga_regset ark_offset_regs[] = {{0x13, 0, 7}, {0x41, 3, 3}, VGA_REGSET_END};
86
87static const struct svga_timing_regs ark_timing_regs = {
88 ark_h_total_regs, ark_h_display_regs, ark_h_blank_start_regs,
89 ark_h_blank_end_regs, ark_h_sync_start_regs, ark_h_sync_end_regs,
90 ark_v_total_regs, ark_v_display_regs, ark_v_blank_start_regs,
91 ark_v_blank_end_regs, ark_v_sync_start_regs, ark_v_sync_end_regs,
92};
93
94
95/* ------------------------------------------------------------------------- */
96
97
98/* Module parameters */
99
100static char *mode_option = "640x480-8@60";
101
102MODULE_AUTHOR("(c) 2007 Ondrej Zajicek <[email protected]>");
103MODULE_LICENSE("GPL");
104MODULE_DESCRIPTION("fbdev driver for ARK 2000PV");
105
106module_param(mode_option, charp, 0444);
107MODULE_PARM_DESC(mode_option, "Default video mode ('640x480-8@60', etc)");
108module_param_named(mode, mode_option, charp, 0444);
109MODULE_PARM_DESC(mode, "Default video mode ('640x480-8@60', etc) (deprecated)");
110
111static int threshold = 4;
112
113module_param(threshold, int, 0644);
114MODULE_PARM_DESC(threshold, "FIFO threshold");
115
116
117/* ------------------------------------------------------------------------- */
118
119
120static void arkfb_settile(struct fb_info *info, struct fb_tilemap *map)
121{
122 const u8 *font = map->data;
123 u8 __iomem *fb = (u8 __iomem *)info->screen_base;
124 int i, c;
125
126 if ((map->width != 8) || (map->height != 16) ||
127 (map->depth != 1) || (map->length != 256)) {
128 fb_err(info, "unsupported font parameters: width %d, height %d, depth %d, length %d\n",
129 map->width, map->height, map->depth, map->length);
130 return;
131 }
132
133 fb += 2;
134 for (c = 0; c < map->length; c++) {
135 for (i = 0; i < map->height; i++) {
136 fb_writeb(font[i], &fb[i * 4]);
137 fb_writeb(font[i], &fb[i * 4 + (128 * 8)]);
138 }
139 fb += 128;
140
141 if ((c % 8) == 7)
142 fb += 128*8;
143
144 font += map->height;
145 }
146}
147
148static void arkfb_tilecursor(struct fb_info *info, struct fb_tilecursor *cursor)
149{
150 struct arkfb_info *par = info->par;
151
152 svga_tilecursor(par->state.vgabase, info, cursor);
153}
154
155static struct fb_tile_ops arkfb_tile_ops = {
156 .fb_settile = arkfb_settile,
157 .fb_tilecopy = svga_tilecopy,
158 .fb_tilefill = svga_tilefill,
159 .fb_tileblit = svga_tileblit,
160 .fb_tilecursor = arkfb_tilecursor,
161 .fb_get_tilemax = svga_get_tilemax,
162};
163
164
165/* ------------------------------------------------------------------------- */
166
167
168/* image data is MSB-first, fb structure is MSB-first too */
169static inline u32 expand_color(u32 c)
170{
171 return ((c & 1) | ((c & 2) << 7) | ((c & 4) << 14) | ((c & 8) << 21)) * 0xFF;
172}
173
174/* arkfb_iplan_imageblit silently assumes that almost everything is 8-pixel aligned */
175static void arkfb_iplan_imageblit(struct fb_info *info, const struct fb_image *image)
176{
177 u32 fg = expand_color(image->fg_color);
178 u32 bg = expand_color(image->bg_color);
179 const u8 *src1, *src;
180 u8 __iomem *dst1;
181 u32 __iomem *dst;
182 u32 val;
183 int x, y;
184
185 src1 = image->data;
186 dst1 = info->screen_base + (image->dy * info->fix.line_length)
187 + ((image->dx / 8) * 4);
188
189 for (y = 0; y < image->height; y++) {
190 src = src1;
191 dst = (u32 __iomem *) dst1;
192 for (x = 0; x < image->width; x += 8) {
193 val = *(src++) * 0x01010101;
194 val = (val & fg) | (~val & bg);
195 fb_writel(val, dst++);
196 }
197 src1 += image->width / 8;
198 dst1 += info->fix.line_length;
199 }
200
201}
202
203/* arkfb_iplan_fillrect silently assumes that almost everything is 8-pixel aligned */
204static void arkfb_iplan_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
205{
206 u32 fg = expand_color(rect->color);
207 u8 __iomem *dst1;
208 u32 __iomem *dst;
209 int x, y;
210
211 dst1 = info->screen_base + (rect->dy * info->fix.line_length)
212 + ((rect->dx / 8) * 4);
213
214 for (y = 0; y < rect->height; y++) {
215 dst = (u32 __iomem *) dst1;
216 for (x = 0; x < rect->width; x += 8) {
217 fb_writel(fg, dst++);
218 }
219 dst1 += info->fix.line_length;
220 }
221
222}
223
224
225/* image data is MSB-first, fb structure is high-nibble-in-low-byte-first */
226static inline u32 expand_pixel(u32 c)
227{
228 return (((c & 1) << 24) | ((c & 2) << 27) | ((c & 4) << 14) | ((c & 8) << 17) |
229 ((c & 16) << 4) | ((c & 32) << 7) | ((c & 64) >> 6) | ((c & 128) >> 3)) * 0xF;
230}
231
232/* arkfb_cfb4_imageblit silently assumes that almost everything is 8-pixel aligned */
233static void arkfb_cfb4_imageblit(struct fb_info *info, const struct fb_image *image)
234{
235 u32 fg = image->fg_color * 0x11111111;
236 u32 bg = image->bg_color * 0x11111111;
237 const u8 *src1, *src;
238 u8 __iomem *dst1;
239 u32 __iomem *dst;
240 u32 val;
241 int x, y;
242
243 src1 = image->data;
244 dst1 = info->screen_base + (image->dy * info->fix.line_length)
245 + ((image->dx / 8) * 4);
246
247 for (y = 0; y < image->height; y++) {
248 src = src1;
249 dst = (u32 __iomem *) dst1;
250 for (x = 0; x < image->width; x += 8) {
251 val = expand_pixel(*(src++));
252 val = (val & fg) | (~val & bg);
253 fb_writel(val, dst++);
254 }
255 src1 += image->width / 8;
256 dst1 += info->fix.line_length;
257 }
258
259}
260
261static void arkfb_imageblit(struct fb_info *info, const struct fb_image *image)
262{
263 if ((info->var.bits_per_pixel == 4) && (image->depth == 1)
264 && ((image->width % 8) == 0) && ((image->dx % 8) == 0)) {
265 if (info->fix.type == FB_TYPE_INTERLEAVED_PLANES)
266 arkfb_iplan_imageblit(info, image);
267 else
268 arkfb_cfb4_imageblit(info, image);
269 } else
270 cfb_imageblit(info, image);
271}
272
273static void arkfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
274{
275 if ((info->var.bits_per_pixel == 4)
276 && ((rect->width % 8) == 0) && ((rect->dx % 8) == 0)
277 && (info->fix.type == FB_TYPE_INTERLEAVED_PLANES))
278 arkfb_iplan_fillrect(info, rect);
279 else
280 cfb_fillrect(info, rect);
281}
282
283
284/* ------------------------------------------------------------------------- */
285
286
287enum
288{
289 DAC_PSEUDO8_8,
290 DAC_RGB1555_8,
291 DAC_RGB0565_8,
292 DAC_RGB0888_8,
293 DAC_RGB8888_8,
294 DAC_PSEUDO8_16,
295 DAC_RGB1555_16,
296 DAC_RGB0565_16,
297 DAC_RGB0888_16,
298 DAC_RGB8888_16,
299 DAC_MAX
300};
301
302struct dac_ops {
303 int (*dac_get_mode)(struct dac_info *info);
304 int (*dac_set_mode)(struct dac_info *info, int mode);
305 int (*dac_get_freq)(struct dac_info *info, int channel);
306 int (*dac_set_freq)(struct dac_info *info, int channel, u32 freq);
307 void (*dac_release)(struct dac_info *info);
308};
309
310typedef void (*dac_read_regs_t)(void *data, u8 *code, int count);
311typedef void (*dac_write_regs_t)(void *data, u8 *code, int count);
312
313struct dac_info
314{
315 struct dac_ops *dacops;
316 dac_read_regs_t dac_read_regs;
317 dac_write_regs_t dac_write_regs;
318 void *data;
319};
320
321static inline void dac_read_regs(struct dac_info *info, u8 *code, int count)
322{
323 info->dac_read_regs(info->data, code, count);
324}
325
326static inline void dac_write_reg(struct dac_info *info, u8 reg, u8 val)
327{
328 u8 code[2] = {reg, val};
329 info->dac_write_regs(info->data, code, 1);
330}
331
332static inline void dac_write_regs(struct dac_info *info, u8 *code, int count)
333{
334 info->dac_write_regs(info->data, code, count);
335}
336
337static inline int dac_set_mode(struct dac_info *info, int mode)
338{
339 return info->dacops->dac_set_mode(info, mode);
340}
341
342static inline int dac_set_freq(struct dac_info *info, int channel, u32 freq)
343{
344 return info->dacops->dac_set_freq(info, channel, freq);
345}
346
347static inline void dac_release(struct dac_info *info)
348{
349 info->dacops->dac_release(info);
350}
351
352
353/* ------------------------------------------------------------------------- */
354
355
356/* ICS5342 DAC */
357
358struct ics5342_info
359{
360 struct dac_info dac;
361 u8 mode;
362};
363
364#define DAC_PAR(info) ((struct ics5342_info *) info)
365
366/* LSB is set to distinguish unused slots */
367static const u8 ics5342_mode_table[DAC_MAX] = {
368 [DAC_PSEUDO8_8] = 0x01, [DAC_RGB1555_8] = 0x21, [DAC_RGB0565_8] = 0x61,
369 [DAC_RGB0888_8] = 0x41, [DAC_PSEUDO8_16] = 0x11, [DAC_RGB1555_16] = 0x31,
370 [DAC_RGB0565_16] = 0x51, [DAC_RGB0888_16] = 0x91, [DAC_RGB8888_16] = 0x71
371};
372
373static int ics5342_set_mode(struct dac_info *info, int mode)
374{
375 u8 code;
376
377 if (mode >= DAC_MAX)
378 return -EINVAL;
379
380 code = ics5342_mode_table[mode];
381
382 if (! code)
383 return -EINVAL;
384
385 dac_write_reg(info, 6, code & 0xF0);
386 DAC_PAR(info)->mode = mode;
387
388 return 0;
389}
390
391static const struct svga_pll ics5342_pll = {3, 129, 3, 33, 0, 3,
392 60000, 250000, 14318};
393
394/* pd4 - allow only posdivider 4 (r=2) */
395static const struct svga_pll ics5342_pll_pd4 = {3, 129, 3, 33, 2, 2,
396 60000, 335000, 14318};
397
398/* 270 MHz should be upper bound for VCO clock according to specs,
399 but that is too restrictive in pd4 case */
400
401static int ics5342_set_freq(struct dac_info *info, int channel, u32 freq)
402{
403 u16 m, n, r;
404
405 /* only postdivider 4 (r=2) is valid in mode DAC_PSEUDO8_16 */
406 int rv = svga_compute_pll((DAC_PAR(info)->mode == DAC_PSEUDO8_16)
407 ? &ics5342_pll_pd4 : &ics5342_pll,
408 freq, &m, &n, &r, 0);
409
410 if (rv < 0) {
411 return -EINVAL;
412 } else {
413 u8 code[6] = {4, 3, 5, m-2, 5, (n-2) | (r << 5)};
414 dac_write_regs(info, code, 3);
415 return 0;
416 }
417}
418
419static void ics5342_release(struct dac_info *info)
420{
421 ics5342_set_mode(info, DAC_PSEUDO8_8);
422 kfree(info);
423}
424
425static struct dac_ops ics5342_ops = {
426 .dac_set_mode = ics5342_set_mode,
427 .dac_set_freq = ics5342_set_freq,
428 .dac_release = ics5342_release
429};
430
431
432static struct dac_info * ics5342_init(dac_read_regs_t drr, dac_write_regs_t dwr, void *data)
433{
434 struct ics5342_info *ics_info = kzalloc_obj(struct ics5342_info);
435 struct dac_info *info = &ics_info->dac;
436
437 if (!ics_info)
438 return NULL;
439
440 info->dacops = &ics5342_ops;
441 info->dac_read_regs = drr;
442 info->dac_write_regs = dwr;
443 info->data = data;
444 DAC_PAR(info)->mode = DAC_PSEUDO8_8; /* estimation */
445 return info;
446}
447
448
449/* ------------------------------------------------------------------------- */
450
451
452static unsigned short dac_regs[4] = {0x3c8, 0x3c9, 0x3c6, 0x3c7};
453
454static void ark_dac_read_regs(void *data, u8 *code, int count)
455{
456 struct fb_info *info = data;
457 struct arkfb_info *par;
458 u8 regval;
459
460 par = info->par;
461 regval = vga_rseq(par->state.vgabase, 0x1C);
462 while (count != 0)
463 {
464 vga_wseq(par->state.vgabase, 0x1C, regval | (code[0] & 4 ? 0x80 : 0));
465 code[1] = vga_r(par->state.vgabase, dac_regs[code[0] & 3]);
466 count--;
467 code += 2;
468 }
469
470 vga_wseq(par->state.vgabase, 0x1C, regval);
471}
472
473static void ark_dac_write_regs(void *data, u8 *code, int count)
474{
475 struct fb_info *info = data;
476 struct arkfb_info *par;
477 u8 regval;
478
479 par = info->par;
480 regval = vga_rseq(par->state.vgabase, 0x1C);
481 while (count != 0)
482 {
483 vga_wseq(par->state.vgabase, 0x1C, regval | (code[0] & 4 ? 0x80 : 0));
484 vga_w(par->state.vgabase, dac_regs[code[0] & 3], code[1]);
485 count--;
486 code += 2;
487 }
488
489 vga_wseq(par->state.vgabase, 0x1C, regval);
490}
491
492
493static void ark_set_pixclock(struct fb_info *info, u32 pixclock)
494{
495 struct arkfb_info *par = info->par;
496 u8 regval;
497
498 int rv = dac_set_freq(par->dac, 0, 1000000000 / pixclock);
499 if (rv < 0) {
500 fb_err(info, "cannot set requested pixclock, keeping old value\n");
501 return;
502 }
503
504 /* Set VGA misc register */
505 regval = vga_r(par->state.vgabase, VGA_MIS_R);
506 vga_w(par->state.vgabase, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD);
507}
508
509
510/* Open framebuffer */
511
512static int arkfb_open(struct fb_info *info, int user)
513{
514 struct arkfb_info *par = info->par;
515
516 mutex_lock(&(par->open_lock));
517 if (par->ref_count == 0) {
518 void __iomem *vgabase = par->state.vgabase;
519
520 memset(&(par->state), 0, sizeof(struct vgastate));
521 par->state.vgabase = vgabase;
522 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS | VGA_SAVE_CMAP;
523 par->state.num_crtc = 0x60;
524 par->state.num_seq = 0x30;
525 save_vga(&(par->state));
526 }
527
528 par->ref_count++;
529 mutex_unlock(&(par->open_lock));
530
531 return 0;
532}
533
534/* Close framebuffer */
535
536static int arkfb_release(struct fb_info *info, int user)
537{
538 struct arkfb_info *par = info->par;
539
540 mutex_lock(&(par->open_lock));
541 if (par->ref_count == 0) {
542 mutex_unlock(&(par->open_lock));
543 return -EINVAL;
544 }
545
546 if (par->ref_count == 1) {
547 restore_vga(&(par->state));
548 dac_set_mode(par->dac, DAC_PSEUDO8_8);
549 }
550
551 par->ref_count--;
552 mutex_unlock(&(par->open_lock));
553
554 return 0;
555}
556
557/* Validate passed in var */
558
559static int arkfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
560{
561 int rv, mem, step;
562
563 if (!var->pixclock)
564 return -EINVAL;
565
566 /* Find appropriate format */
567 rv = svga_match_format (arkfb_formats, var, NULL);
568 if (rv < 0)
569 {
570 fb_err(info, "unsupported mode requested\n");
571 return rv;
572 }
573
574 /* Do not allow to have real resoulution larger than virtual */
575 if (var->xres > var->xres_virtual)
576 var->xres_virtual = var->xres;
577
578 if (var->yres > var->yres_virtual)
579 var->yres_virtual = var->yres;
580
581 /* Round up xres_virtual to have proper alignment of lines */
582 step = arkfb_formats[rv].xresstep - 1;
583 var->xres_virtual = (var->xres_virtual+step) & ~step;
584
585
586 /* Check whether have enough memory */
587 mem = ((var->bits_per_pixel * var->xres_virtual) >> 3) * var->yres_virtual;
588 if (mem > info->screen_size)
589 {
590 fb_err(info, "not enough framebuffer memory (%d kB requested, %d kB available)\n",
591 mem >> 10, (unsigned int) (info->screen_size >> 10));
592 return -EINVAL;
593 }
594
595 rv = svga_check_timings (&ark_timing_regs, var, info->node);
596 if (rv < 0)
597 {
598 fb_err(info, "invalid timings requested\n");
599 return rv;
600 }
601
602 /* Interlaced mode is broken */
603 if (var->vmode & FB_VMODE_INTERLACED)
604 return -EINVAL;
605
606 return 0;
607}
608
609/* Set video mode from par */
610
611static int arkfb_set_par(struct fb_info *info)
612{
613 struct arkfb_info *par = info->par;
614 u32 value, mode, hmul, hdiv, offset_value, screen_size;
615 u32 bpp = info->var.bits_per_pixel;
616 u8 regval;
617
618 if (bpp != 0) {
619 info->fix.ypanstep = 1;
620 info->fix.line_length = (info->var.xres_virtual * bpp) / 8;
621
622 info->flags &= ~FBINFO_MISC_TILEBLITTING;
623 info->tileops = NULL;
624
625 /* in 4bpp supports 8p wide tiles only, any tiles otherwise */
626 if (bpp == 4) {
627 bitmap_zero(info->pixmap.blit_x, FB_MAX_BLIT_WIDTH);
628 set_bit(8 - 1, info->pixmap.blit_x);
629 } else {
630 bitmap_fill(info->pixmap.blit_x, FB_MAX_BLIT_WIDTH);
631 }
632 bitmap_fill(info->pixmap.blit_y, FB_MAX_BLIT_HEIGHT);
633
634 offset_value = (info->var.xres_virtual * bpp) / 64;
635 screen_size = info->var.yres_virtual * info->fix.line_length;
636 } else {
637 info->fix.ypanstep = 16;
638 info->fix.line_length = 0;
639
640 info->flags |= FBINFO_MISC_TILEBLITTING;
641 info->tileops = &arkfb_tile_ops;
642
643 /* supports 8x16 tiles only */
644 bitmap_zero(info->pixmap.blit_x, FB_MAX_BLIT_WIDTH);
645 set_bit(8 - 1, info->pixmap.blit_x);
646 bitmap_zero(info->pixmap.blit_y, FB_MAX_BLIT_HEIGHT);
647 set_bit(16 - 1, info->pixmap.blit_y);
648
649 offset_value = info->var.xres_virtual / 16;
650 screen_size = (info->var.xres_virtual * info->var.yres_virtual) / 64;
651 }
652
653 info->var.xoffset = 0;
654 info->var.yoffset = 0;
655 info->var.activate = FB_ACTIVATE_NOW;
656
657 /* Unlock registers */
658 svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x80);
659
660 /* Blank screen and turn off sync */
661 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
662 svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80);
663
664 /* Set default values */
665 svga_set_default_gfx_regs(par->state.vgabase);
666 svga_set_default_atc_regs(par->state.vgabase);
667 svga_set_default_seq_regs(par->state.vgabase);
668 svga_set_default_crt_regs(par->state.vgabase);
669 svga_wcrt_multi(par->state.vgabase, ark_line_compare_regs, 0xFFFFFFFF);
670 svga_wcrt_multi(par->state.vgabase, ark_start_address_regs, 0);
671
672 /* ARK specific initialization */
673 svga_wseq_mask(par->state.vgabase, 0x10, 0x1F, 0x1F); /* enable linear framebuffer and full memory access */
674 svga_wseq_mask(par->state.vgabase, 0x12, 0x03, 0x03); /* 4 MB linear framebuffer size */
675
676 vga_wseq(par->state.vgabase, 0x13, info->fix.smem_start >> 16);
677 vga_wseq(par->state.vgabase, 0x14, info->fix.smem_start >> 24);
678 vga_wseq(par->state.vgabase, 0x15, 0);
679 vga_wseq(par->state.vgabase, 0x16, 0);
680
681 /* Set the FIFO threshold register */
682 /* It is fascinating way to store 5-bit value in 8-bit register */
683 regval = 0x10 | ((threshold & 0x0E) >> 1) | (threshold & 0x01) << 7 | (threshold & 0x10) << 1;
684 vga_wseq(par->state.vgabase, 0x18, regval);
685
686 /* Set the offset register */
687 fb_dbg(info, "offset register : %d\n", offset_value);
688 svga_wcrt_multi(par->state.vgabase, ark_offset_regs, offset_value);
689
690 /* fix for hi-res textmode */
691 svga_wcrt_mask(par->state.vgabase, 0x40, 0x08, 0x08);
692
693 if (info->var.vmode & FB_VMODE_DOUBLE)
694 svga_wcrt_mask(par->state.vgabase, 0x09, 0x80, 0x80);
695 else
696 svga_wcrt_mask(par->state.vgabase, 0x09, 0x00, 0x80);
697
698 if (info->var.vmode & FB_VMODE_INTERLACED)
699 svga_wcrt_mask(par->state.vgabase, 0x44, 0x04, 0x04);
700 else
701 svga_wcrt_mask(par->state.vgabase, 0x44, 0x00, 0x04);
702
703 hmul = 1;
704 hdiv = 1;
705 mode = svga_match_format(arkfb_formats, &(info->var), &(info->fix));
706
707 /* Set mode-specific register values */
708 switch (mode) {
709 case 0:
710 fb_dbg(info, "text mode\n");
711 svga_set_textmode_vga_regs(par->state.vgabase);
712
713 vga_wseq(par->state.vgabase, 0x11, 0x10); /* basic VGA mode */
714 svga_wcrt_mask(par->state.vgabase, 0x46, 0x00, 0x04); /* 8bit pixel path */
715 dac_set_mode(par->dac, DAC_PSEUDO8_8);
716
717 break;
718 case 1:
719 fb_dbg(info, "4 bit pseudocolor\n");
720 vga_wgfx(par->state.vgabase, VGA_GFX_MODE, 0x40);
721
722 vga_wseq(par->state.vgabase, 0x11, 0x10); /* basic VGA mode */
723 svga_wcrt_mask(par->state.vgabase, 0x46, 0x00, 0x04); /* 8bit pixel path */
724 dac_set_mode(par->dac, DAC_PSEUDO8_8);
725 break;
726 case 2:
727 fb_dbg(info, "4 bit pseudocolor, planar\n");
728
729 vga_wseq(par->state.vgabase, 0x11, 0x10); /* basic VGA mode */
730 svga_wcrt_mask(par->state.vgabase, 0x46, 0x00, 0x04); /* 8bit pixel path */
731 dac_set_mode(par->dac, DAC_PSEUDO8_8);
732 break;
733 case 3:
734 fb_dbg(info, "8 bit pseudocolor\n");
735
736 vga_wseq(par->state.vgabase, 0x11, 0x16); /* 8bpp accel mode */
737
738 if (info->var.pixclock > 20000) {
739 fb_dbg(info, "not using multiplex\n");
740 svga_wcrt_mask(par->state.vgabase, 0x46, 0x00, 0x04); /* 8bit pixel path */
741 dac_set_mode(par->dac, DAC_PSEUDO8_8);
742 } else {
743 fb_dbg(info, "using multiplex\n");
744 svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */
745 dac_set_mode(par->dac, DAC_PSEUDO8_16);
746 hdiv = 2;
747 }
748 break;
749 case 4:
750 fb_dbg(info, "5/5/5 truecolor\n");
751
752 vga_wseq(par->state.vgabase, 0x11, 0x1A); /* 16bpp accel mode */
753 svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */
754 dac_set_mode(par->dac, DAC_RGB1555_16);
755 break;
756 case 5:
757 fb_dbg(info, "5/6/5 truecolor\n");
758
759 vga_wseq(par->state.vgabase, 0x11, 0x1A); /* 16bpp accel mode */
760 svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */
761 dac_set_mode(par->dac, DAC_RGB0565_16);
762 break;
763 case 6:
764 fb_dbg(info, "8/8/8 truecolor\n");
765
766 vga_wseq(par->state.vgabase, 0x11, 0x16); /* 8bpp accel mode ??? */
767 svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */
768 dac_set_mode(par->dac, DAC_RGB0888_16);
769 hmul = 3;
770 hdiv = 2;
771 break;
772 case 7:
773 fb_dbg(info, "8/8/8/8 truecolor\n");
774
775 vga_wseq(par->state.vgabase, 0x11, 0x1E); /* 32bpp accel mode */
776 svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */
777 dac_set_mode(par->dac, DAC_RGB8888_16);
778 hmul = 2;
779 break;
780 default:
781 fb_err(info, "unsupported mode - bug\n");
782 return -EINVAL;
783 }
784
785 value = (hdiv * info->var.pixclock) / hmul;
786 if (!value) {
787 fb_dbg(info, "invalid pixclock\n");
788 value = 1;
789 }
790 ark_set_pixclock(info, value);
791 svga_set_timings(par->state.vgabase, &ark_timing_regs, &(info->var), hmul, hdiv,
792 (info->var.vmode & FB_VMODE_DOUBLE) ? 2 : 1,
793 (info->var.vmode & FB_VMODE_INTERLACED) ? 2 : 1,
794 hmul, info->node);
795
796 /* Set interlaced mode start/end register */
797 value = info->var.xres + info->var.left_margin + info->var.right_margin + info->var.hsync_len;
798 value = ((value * hmul / hdiv) / 8) - 5;
799 vga_wcrt(par->state.vgabase, 0x42, (value + 1) / 2);
800
801 if (screen_size > info->screen_size)
802 screen_size = info->screen_size;
803 memset_io(info->screen_base, 0x00, screen_size);
804 /* Device and screen back on */
805 svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80);
806 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
807
808 return 0;
809}
810
811/* Set a colour register */
812
813static int arkfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
814 u_int transp, struct fb_info *fb)
815{
816 switch (fb->var.bits_per_pixel) {
817 case 0:
818 case 4:
819 if (regno >= 16)
820 return -EINVAL;
821
822 if ((fb->var.bits_per_pixel == 4) &&
823 (fb->var.nonstd == 0)) {
824 outb(0xF0, VGA_PEL_MSK);
825 outb(regno*16, VGA_PEL_IW);
826 } else {
827 outb(0x0F, VGA_PEL_MSK);
828 outb(regno, VGA_PEL_IW);
829 }
830 outb(red >> 10, VGA_PEL_D);
831 outb(green >> 10, VGA_PEL_D);
832 outb(blue >> 10, VGA_PEL_D);
833 break;
834 case 8:
835 if (regno >= 256)
836 return -EINVAL;
837
838 outb(0xFF, VGA_PEL_MSK);
839 outb(regno, VGA_PEL_IW);
840 outb(red >> 10, VGA_PEL_D);
841 outb(green >> 10, VGA_PEL_D);
842 outb(blue >> 10, VGA_PEL_D);
843 break;
844 case 16:
845 if (regno >= 16)
846 return 0;
847
848 if (fb->var.green.length == 5)
849 ((u32*)fb->pseudo_palette)[regno] = ((red & 0xF800) >> 1) |
850 ((green & 0xF800) >> 6) | ((blue & 0xF800) >> 11);
851 else if (fb->var.green.length == 6)
852 ((u32*)fb->pseudo_palette)[regno] = (red & 0xF800) |
853 ((green & 0xFC00) >> 5) | ((blue & 0xF800) >> 11);
854 else
855 return -EINVAL;
856 break;
857 case 24:
858 case 32:
859 if (regno >= 16)
860 return 0;
861
862 ((u32*)fb->pseudo_palette)[regno] = ((red & 0xFF00) << 8) |
863 (green & 0xFF00) | ((blue & 0xFF00) >> 8);
864 break;
865 default:
866 return -EINVAL;
867 }
868
869 return 0;
870}
871
872/* Set the display blanking state */
873
874static int arkfb_blank(int blank_mode, struct fb_info *info)
875{
876 struct arkfb_info *par = info->par;
877
878 switch (blank_mode) {
879 case FB_BLANK_UNBLANK:
880 fb_dbg(info, "unblank\n");
881 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
882 svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80);
883 break;
884 case FB_BLANK_NORMAL:
885 fb_dbg(info, "blank\n");
886 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
887 svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80);
888 break;
889 case FB_BLANK_POWERDOWN:
890 case FB_BLANK_HSYNC_SUSPEND:
891 case FB_BLANK_VSYNC_SUSPEND:
892 fb_dbg(info, "sync down\n");
893 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
894 svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80);
895 break;
896 }
897 return 0;
898}
899
900
901/* Pan the display */
902
903static int arkfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
904{
905 struct arkfb_info *par = info->par;
906 unsigned int offset;
907
908 /* Calculate the offset */
909 if (info->var.bits_per_pixel == 0) {
910 offset = (var->yoffset / 16) * (info->var.xres_virtual / 2)
911 + (var->xoffset / 2);
912 offset = offset >> 2;
913 } else {
914 offset = (var->yoffset * info->fix.line_length) +
915 (var->xoffset * info->var.bits_per_pixel / 8);
916 offset = offset >> ((info->var.bits_per_pixel == 4) ? 2 : 3);
917 }
918
919 /* Set the offset */
920 svga_wcrt_multi(par->state.vgabase, ark_start_address_regs, offset);
921
922 return 0;
923}
924
925
926/* ------------------------------------------------------------------------- */
927
928
929/* Frame buffer operations */
930
931static const struct fb_ops arkfb_ops = {
932 .owner = THIS_MODULE,
933 .fb_open = arkfb_open,
934 .fb_release = arkfb_release,
935 __FB_DEFAULT_IOMEM_OPS_RDWR,
936 .fb_check_var = arkfb_check_var,
937 .fb_set_par = arkfb_set_par,
938 .fb_setcolreg = arkfb_setcolreg,
939 .fb_blank = arkfb_blank,
940 .fb_pan_display = arkfb_pan_display,
941 .fb_fillrect = arkfb_fillrect,
942 .fb_copyarea = cfb_copyarea,
943 .fb_imageblit = arkfb_imageblit,
944 __FB_DEFAULT_IOMEM_OPS_MMAP,
945 .fb_get_caps = svga_get_caps,
946};
947
948
949/* ------------------------------------------------------------------------- */
950
951
952/* PCI probe */
953static int ark_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
954{
955 struct pci_bus_region bus_reg;
956 struct resource vga_res;
957 struct fb_info *info;
958 struct arkfb_info *par;
959 int rc;
960 u8 regval;
961
962 rc = aperture_remove_conflicting_pci_devices(dev, "arkfb");
963 if (rc < 0)
964 return rc;
965
966 /* Ignore secondary VGA device because there is no VGA arbitration */
967 if (! svga_primary_device(dev)) {
968 dev_info(&(dev->dev), "ignoring secondary device\n");
969 return -ENODEV;
970 }
971
972 /* Allocate and fill driver data structure */
973 info = framebuffer_alloc(sizeof(struct arkfb_info), &(dev->dev));
974 if (!info)
975 return -ENOMEM;
976
977 par = info->par;
978 mutex_init(&par->open_lock);
979
980 info->flags = FBINFO_PARTIAL_PAN_OK | FBINFO_HWACCEL_YPAN;
981 info->fbops = &arkfb_ops;
982
983 /* Prepare PCI device */
984 rc = pci_enable_device(dev);
985 if (rc < 0) {
986 dev_err(info->device, "cannot enable PCI device\n");
987 goto err_enable_device;
988 }
989
990 rc = pci_request_regions(dev, "arkfb");
991 if (rc < 0) {
992 dev_err(info->device, "cannot reserve framebuffer region\n");
993 goto err_request_regions;
994 }
995
996 par->dac = ics5342_init(ark_dac_read_regs, ark_dac_write_regs, info);
997 if (! par->dac) {
998 rc = -ENOMEM;
999 dev_err(info->device, "RAMDAC initialization failed\n");
1000 goto err_dac;
1001 }
1002
1003 info->fix.smem_start = pci_resource_start(dev, 0);
1004 info->fix.smem_len = pci_resource_len(dev, 0);
1005
1006 /* Map physical IO memory address into kernel space */
1007 info->screen_base = pci_iomap_wc(dev, 0, 0);
1008 if (! info->screen_base) {
1009 rc = -ENOMEM;
1010 dev_err(info->device, "iomap for framebuffer failed\n");
1011 goto err_iomap;
1012 }
1013
1014 bus_reg.start = 0;
1015 bus_reg.end = 64 * 1024;
1016
1017 vga_res.flags = IORESOURCE_IO;
1018
1019 pcibios_bus_to_resource(dev->bus, &vga_res, &bus_reg);
1020
1021 par->state.vgabase = (void __iomem *) (unsigned long) vga_res.start;
1022
1023 /* FIXME get memsize */
1024 regval = vga_rseq(par->state.vgabase, 0x10);
1025 info->screen_size = (1 << (regval >> 6)) << 20;
1026 info->fix.smem_len = info->screen_size;
1027
1028 strcpy(info->fix.id, "ARK 2000PV");
1029 info->fix.mmio_start = 0;
1030 info->fix.mmio_len = 0;
1031 info->fix.type = FB_TYPE_PACKED_PIXELS;
1032 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
1033 info->fix.ypanstep = 0;
1034 info->fix.accel = FB_ACCEL_NONE;
1035 info->pseudo_palette = (void*) (par->pseudo_palette);
1036
1037 /* Prepare startup mode */
1038 rc = fb_find_mode(&(info->var), info, mode_option, NULL, 0, NULL, 8);
1039 if (! ((rc == 1) || (rc == 2))) {
1040 rc = -EINVAL;
1041 dev_err(info->device, "mode %s not found\n", mode_option);
1042 goto err_find_mode;
1043 }
1044
1045 rc = fb_alloc_cmap(&info->cmap, 256, 0);
1046 if (rc < 0) {
1047 dev_err(info->device, "cannot allocate colormap\n");
1048 goto err_alloc_cmap;
1049 }
1050
1051 rc = register_framebuffer(info);
1052 if (rc < 0) {
1053 dev_err(info->device, "cannot register framebuffer\n");
1054 goto err_reg_fb;
1055 }
1056
1057 fb_info(info, "%s on %s, %d MB RAM\n",
1058 info->fix.id, pci_name(dev), info->fix.smem_len >> 20);
1059
1060 /* Record a reference to the driver data */
1061 pci_set_drvdata(dev, info);
1062 par->wc_cookie = arch_phys_wc_add(info->fix.smem_start,
1063 info->fix.smem_len);
1064 return 0;
1065
1066 /* Error handling */
1067err_reg_fb:
1068 fb_dealloc_cmap(&info->cmap);
1069err_alloc_cmap:
1070err_find_mode:
1071 pci_iounmap(dev, info->screen_base);
1072err_iomap:
1073 dac_release(par->dac);
1074err_dac:
1075 pci_release_regions(dev);
1076err_request_regions:
1077/* pci_disable_device(dev); */
1078err_enable_device:
1079 framebuffer_release(info);
1080 return rc;
1081}
1082
1083/* PCI remove */
1084
1085static void ark_pci_remove(struct pci_dev *dev)
1086{
1087 struct fb_info *info = pci_get_drvdata(dev);
1088
1089 if (info) {
1090 struct arkfb_info *par = info->par;
1091 arch_phys_wc_del(par->wc_cookie);
1092 dac_release(par->dac);
1093 unregister_framebuffer(info);
1094 fb_dealloc_cmap(&info->cmap);
1095
1096 pci_iounmap(dev, info->screen_base);
1097 pci_release_regions(dev);
1098/* pci_disable_device(dev); */
1099
1100 framebuffer_release(info);
1101 }
1102}
1103
1104
1105/* PCI suspend */
1106
1107static int __maybe_unused ark_pci_suspend(struct device *dev)
1108{
1109 struct fb_info *info = dev_get_drvdata(dev);
1110 struct arkfb_info *par = info->par;
1111
1112 dev_info(info->device, "suspend\n");
1113
1114 console_lock();
1115 mutex_lock(&(par->open_lock));
1116
1117 if (par->ref_count == 0) {
1118 mutex_unlock(&(par->open_lock));
1119 console_unlock();
1120 return 0;
1121 }
1122
1123 fb_set_suspend(info, 1);
1124
1125 mutex_unlock(&(par->open_lock));
1126 console_unlock();
1127
1128 return 0;
1129}
1130
1131
1132/* PCI resume */
1133
1134static int __maybe_unused ark_pci_resume(struct device *dev)
1135{
1136 struct fb_info *info = dev_get_drvdata(dev);
1137 struct arkfb_info *par = info->par;
1138
1139 dev_info(info->device, "resume\n");
1140
1141 console_lock();
1142 mutex_lock(&(par->open_lock));
1143
1144 if (par->ref_count == 0)
1145 goto fail;
1146
1147 arkfb_set_par(info);
1148 fb_set_suspend(info, 0);
1149
1150fail:
1151 mutex_unlock(&(par->open_lock));
1152 console_unlock();
1153 return 0;
1154}
1155
1156static const struct dev_pm_ops ark_pci_pm_ops = {
1157#ifdef CONFIG_PM_SLEEP
1158 .suspend = ark_pci_suspend,
1159 .resume = ark_pci_resume,
1160 .freeze = NULL,
1161 .thaw = ark_pci_resume,
1162 .poweroff = ark_pci_suspend,
1163 .restore = ark_pci_resume,
1164#endif
1165};
1166
1167/* List of boards that we are trying to support */
1168
1169static const struct pci_device_id ark_devices[] = {
1170 { PCI_DEVICE(0xEDD8, 0xA099) },
1171 { }
1172};
1173
1174
1175MODULE_DEVICE_TABLE(pci, ark_devices);
1176
1177static struct pci_driver arkfb_pci_driver = {
1178 .name = "arkfb",
1179 .id_table = ark_devices,
1180 .probe = ark_pci_probe,
1181 .remove = ark_pci_remove,
1182 .driver.pm = &ark_pci_pm_ops,
1183};
1184
1185/* Cleanup */
1186
1187static void __exit arkfb_cleanup(void)
1188{
1189 pr_debug("arkfb: cleaning up\n");
1190 pci_unregister_driver(&arkfb_pci_driver);
1191}
1192
1193/* Driver Initialisation */
1194
1195static int __init arkfb_init(void)
1196{
1197
1198#ifndef MODULE
1199 char *option = NULL;
1200#endif
1201
1202 if (fb_modesetting_disabled("arkfb"))
1203 return -ENODEV;
1204
1205#ifndef MODULE
1206 if (fb_get_options("arkfb", &option))
1207 return -ENODEV;
1208
1209 if (option && *option)
1210 mode_option = option;
1211#endif
1212
1213 pr_debug("arkfb: initializing\n");
1214 return pci_register_driver(&arkfb_pci_driver);
1215}
1216
1217module_init(arkfb_init);
1218module_exit(arkfb_cleanup);