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1/*
2 * linux/drivers/video/nvidia/nvidia.c - nVidia fb driver
3 *
4 * Copyright 2004 Antonino Daplas <[email protected]>
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive
8 * for more details.
9 *
10 */
11
12#include <linux/aperture.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/errno.h>
16#include <linux/string.h>
17#include <linux/mm.h>
18#include <linux/slab.h>
19#include <linux/delay.h>
20#include <linux/fb.h>
21#include <linux/init.h>
22#include <linux/pci.h>
23#include <linux/console.h>
24#include <linux/backlight.h>
25#include <linux/string_choices.h>
26#ifdef CONFIG_BOOTX_TEXT
27#include <asm/btext.h>
28#endif
29
30#include "nv_local.h"
31#include "nv_type.h"
32#include "nv_proto.h"
33#include "nv_dma.h"
34
35#ifdef CONFIG_FB_NVIDIA_DEBUG
36#define NVTRACE printk
37#else
38#define NVTRACE if (0) printk
39#endif
40
41#define NVTRACE_ENTER(...) NVTRACE("%s START\n", __func__)
42#define NVTRACE_LEAVE(...) NVTRACE("%s END\n", __func__)
43
44#ifdef CONFIG_FB_NVIDIA_DEBUG
45#define assert(expr) \
46 if (!(expr)) { \
47 printk( "Assertion failed! %s,%s,%s,line=%d\n",\
48 #expr,__FILE__,__func__,__LINE__); \
49 BUG(); \
50 }
51#else
52#define assert(expr)
53#endif
54
55#define PFX "nvidiafb: "
56
57/* HW cursor parameters */
58#define MAX_CURS 32
59
60static const struct pci_device_id nvidiafb_pci_tbl[] = {
61 {
62 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
63 .class = PCI_BASE_CLASS_DISPLAY << 16,
64 .class_mask = 0xff0000
65 },
66 { }
67};
68MODULE_DEVICE_TABLE(pci, nvidiafb_pci_tbl);
69
70/* command line data, set in nvidiafb_setup() */
71static int flatpanel = -1; /* Autodetect later */
72static int fpdither = -1;
73static int forceCRTC = -1;
74static int hwcur = 0;
75static int noaccel = 0;
76static int noscale = 0;
77static int paneltweak = 0;
78static int vram = 0;
79static int bpp = 8;
80static int reverse_i2c;
81static bool nomtrr = false;
82static int backlight = IS_BUILTIN(CONFIG_PMAC_BACKLIGHT);
83
84static char *mode_option = NULL;
85
86static struct fb_fix_screeninfo nvidiafb_fix = {
87 .type = FB_TYPE_PACKED_PIXELS,
88 .xpanstep = 8,
89 .ypanstep = 1,
90};
91
92static struct fb_var_screeninfo nvidiafb_default_var = {
93 .xres = 640,
94 .yres = 480,
95 .xres_virtual = 640,
96 .yres_virtual = 480,
97 .bits_per_pixel = 8,
98 .red = {0, 8, 0},
99 .green = {0, 8, 0},
100 .blue = {0, 8, 0},
101 .transp = {0, 0, 0},
102 .activate = FB_ACTIVATE_NOW,
103 .height = -1,
104 .width = -1,
105 .pixclock = 39721,
106 .left_margin = 40,
107 .right_margin = 24,
108 .upper_margin = 32,
109 .lower_margin = 11,
110 .hsync_len = 96,
111 .vsync_len = 2,
112 .vmode = FB_VMODE_NONINTERLACED
113};
114
115static void nvidiafb_load_cursor_image(struct nvidia_par *par, u8 * data8,
116 u16 bg, u16 fg, u32 w, u32 h)
117{
118 u32 *data = (u32 *) data8;
119 int i, j, k = 0;
120 u32 b, tmp;
121
122 w = (w + 1) & ~1;
123
124 for (i = 0; i < h; i++) {
125 b = *data++;
126 reverse_order(&b);
127
128 for (j = 0; j < w / 2; j++) {
129 tmp = 0;
130#if defined (__BIG_ENDIAN)
131 tmp = (b & (1 << 31)) ? fg << 16 : bg << 16;
132 b <<= 1;
133 tmp |= (b & (1 << 31)) ? fg : bg;
134 b <<= 1;
135#else
136 tmp = (b & 1) ? fg : bg;
137 b >>= 1;
138 tmp |= (b & 1) ? fg << 16 : bg << 16;
139 b >>= 1;
140#endif
141 NV_WR32(&par->CURSOR[k++], 0, tmp);
142 }
143 k += (MAX_CURS - w) / 2;
144 }
145}
146
147static void nvidia_write_clut(struct nvidia_par *par,
148 u8 regnum, u8 red, u8 green, u8 blue)
149{
150 NVWriteDacMask(par, 0xff);
151 NVWriteDacWriteAddr(par, regnum);
152 NVWriteDacData(par, red);
153 NVWriteDacData(par, green);
154 NVWriteDacData(par, blue);
155}
156
157static void nvidia_read_clut(struct nvidia_par *par,
158 u8 regnum, u8 * red, u8 * green, u8 * blue)
159{
160 NVWriteDacMask(par, 0xff);
161 NVWriteDacReadAddr(par, regnum);
162 *red = NVReadDacData(par);
163 *green = NVReadDacData(par);
164 *blue = NVReadDacData(par);
165}
166
167static int nvidia_panel_tweak(struct nvidia_par *par,
168 struct _riva_hw_state *state)
169{
170 int tweak = 0;
171
172 if (par->paneltweak) {
173 tweak = par->paneltweak;
174 } else {
175 /* Begin flat panel hacks.
176 * This is unfortunate, but some chips need this register
177 * tweaked or else you get artifacts where adjacent pixels are
178 * swapped. There are no hard rules for what to set here so all
179 * we can do is experiment and apply hacks.
180 */
181 if (((par->Chipset & 0xffff) == 0x0328) && (state->bpp == 32)) {
182 /* At least one NV34 laptop needs this workaround. */
183 tweak = -1;
184 }
185
186 if ((par->Chipset & 0xfff0) == 0x0310)
187 tweak = 1;
188 /* end flat panel hacks */
189 }
190
191 return tweak;
192}
193
194static void nvidia_screen_off(struct nvidia_par *par, int on)
195{
196 unsigned char tmp;
197
198 if (on) {
199 /*
200 * Turn off screen and disable sequencer.
201 */
202 tmp = NVReadSeq(par, 0x01);
203
204 NVWriteSeq(par, 0x00, 0x01); /* Synchronous Reset */
205 NVWriteSeq(par, 0x01, tmp | 0x20); /* disable the display */
206 } else {
207 /*
208 * Reenable sequencer, then turn on screen.
209 */
210
211 tmp = NVReadSeq(par, 0x01);
212
213 NVWriteSeq(par, 0x01, tmp & ~0x20); /* reenable display */
214 NVWriteSeq(par, 0x00, 0x03); /* End Reset */
215 }
216}
217
218static void nvidia_save_vga(struct nvidia_par *par,
219 struct _riva_hw_state *state)
220{
221 int i;
222
223 NVTRACE_ENTER();
224 NVLockUnlock(par, 0);
225
226 NVUnloadStateExt(par, state);
227
228 state->misc_output = NVReadMiscOut(par);
229
230 for (i = 0; i < NUM_CRT_REGS; i++)
231 state->crtc[i] = NVReadCrtc(par, i);
232
233 for (i = 0; i < NUM_ATC_REGS; i++)
234 state->attr[i] = NVReadAttr(par, i);
235
236 for (i = 0; i < NUM_GRC_REGS; i++)
237 state->gra[i] = NVReadGr(par, i);
238
239 for (i = 0; i < NUM_SEQ_REGS; i++)
240 state->seq[i] = NVReadSeq(par, i);
241 NVTRACE_LEAVE();
242}
243
244#undef DUMP_REG
245
246static void nvidia_write_regs(struct nvidia_par *par,
247 struct _riva_hw_state *state)
248{
249 int i;
250
251 NVTRACE_ENTER();
252
253 NVLoadStateExt(par, state);
254
255 NVWriteMiscOut(par, state->misc_output);
256
257 for (i = 1; i < NUM_SEQ_REGS; i++) {
258#ifdef DUMP_REG
259 printk(" SEQ[%02x] = %08x\n", i, state->seq[i]);
260#endif
261 NVWriteSeq(par, i, state->seq[i]);
262 }
263
264 /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 of CRTC[17] */
265 NVWriteCrtc(par, 0x11, state->crtc[0x11] & ~0x80);
266
267 for (i = 0; i < NUM_CRT_REGS; i++) {
268 switch (i) {
269 case 0x19:
270 case 0x20 ... 0x40:
271 break;
272 default:
273#ifdef DUMP_REG
274 printk("CRTC[%02x] = %08x\n", i, state->crtc[i]);
275#endif
276 NVWriteCrtc(par, i, state->crtc[i]);
277 }
278 }
279
280 for (i = 0; i < NUM_GRC_REGS; i++) {
281#ifdef DUMP_REG
282 printk(" GRA[%02x] = %08x\n", i, state->gra[i]);
283#endif
284 NVWriteGr(par, i, state->gra[i]);
285 }
286
287 for (i = 0; i < NUM_ATC_REGS; i++) {
288#ifdef DUMP_REG
289 printk("ATTR[%02x] = %08x\n", i, state->attr[i]);
290#endif
291 NVWriteAttr(par, i, state->attr[i]);
292 }
293
294 NVTRACE_LEAVE();
295}
296
297static int nvidia_calc_regs(struct fb_info *info)
298{
299 struct nvidia_par *par = info->par;
300 struct _riva_hw_state *state = &par->ModeReg;
301 int i, depth = fb_get_color_depth(&info->var, &info->fix);
302 int h_display = info->var.xres / 8 - 1;
303 int h_start = (info->var.xres + info->var.right_margin) / 8 - 1;
304 int h_end = (info->var.xres + info->var.right_margin +
305 info->var.hsync_len) / 8 - 1;
306 int h_total = (info->var.xres + info->var.right_margin +
307 info->var.hsync_len + info->var.left_margin) / 8 - 5;
308 int h_blank_s = h_display;
309 int h_blank_e = h_total + 4;
310 int v_display = info->var.yres - 1;
311 int v_start = info->var.yres + info->var.lower_margin - 1;
312 int v_end = (info->var.yres + info->var.lower_margin +
313 info->var.vsync_len) - 1;
314 int v_total = (info->var.yres + info->var.lower_margin +
315 info->var.vsync_len + info->var.upper_margin) - 2;
316 int v_blank_s = v_display;
317 int v_blank_e = v_total + 1;
318
319 /*
320 * Set all CRTC values.
321 */
322
323 if (info->var.vmode & FB_VMODE_INTERLACED)
324 v_total |= 1;
325
326 if (par->FlatPanel == 1) {
327 v_start = v_total - 3;
328 v_end = v_total - 2;
329 v_blank_s = v_start;
330 h_start = h_total - 5;
331 h_end = h_total - 2;
332 h_blank_e = h_total + 4;
333 }
334
335 state->crtc[0x0] = Set8Bits(h_total);
336 state->crtc[0x1] = Set8Bits(h_display);
337 state->crtc[0x2] = Set8Bits(h_blank_s);
338 state->crtc[0x3] = SetBitField(h_blank_e, 4: 0, 4:0)
339 | SetBit(7);
340 state->crtc[0x4] = Set8Bits(h_start);
341 state->crtc[0x5] = SetBitField(h_blank_e, 5: 5, 7:7)
342 | SetBitField(h_end, 4: 0, 4:0);
343 state->crtc[0x6] = SetBitField(v_total, 7: 0, 7:0);
344 state->crtc[0x7] = SetBitField(v_total, 8: 8, 0:0)
345 | SetBitField(v_display, 8: 8, 1:1)
346 | SetBitField(v_start, 8: 8, 2:2)
347 | SetBitField(v_blank_s, 8: 8, 3:3)
348 | SetBit(4)
349 | SetBitField(v_total, 9: 9, 5:5)
350 | SetBitField(v_display, 9: 9, 6:6)
351 | SetBitField(v_start, 9: 9, 7:7);
352 state->crtc[0x9] = SetBitField(v_blank_s, 9: 9, 5:5)
353 | SetBit(6)
354 | ((info->var.vmode & FB_VMODE_DOUBLE) ? 0x80 : 0x00);
355 state->crtc[0x10] = Set8Bits(v_start);
356 state->crtc[0x11] = SetBitField(v_end, 3: 0, 3:0) | SetBit(5);
357 state->crtc[0x12] = Set8Bits(v_display);
358 state->crtc[0x13] = ((info->var.xres_virtual / 8) *
359 (info->var.bits_per_pixel / 8));
360 state->crtc[0x15] = Set8Bits(v_blank_s);
361 state->crtc[0x16] = Set8Bits(v_blank_e);
362
363 state->attr[0x10] = 0x01;
364
365 if (par->Television)
366 state->attr[0x11] = 0x00;
367
368 state->screen = SetBitField(h_blank_e, 6: 6, 4:4)
369 | SetBitField(v_blank_s, 10: 10, 3:3)
370 | SetBitField(v_start, 10: 10, 2:2)
371 | SetBitField(v_display, 10: 10, 1:1)
372 | SetBitField(v_total, 10: 10, 0:0);
373
374 state->horiz = SetBitField(h_total, 8: 8, 0:0)
375 | SetBitField(h_display, 8: 8, 1:1)
376 | SetBitField(h_blank_s, 8: 8, 2:2)
377 | SetBitField(h_start, 8: 8, 3:3);
378
379 state->extra = SetBitField(v_total, 11: 11, 0:0)
380 | SetBitField(v_display, 11: 11, 2:2)
381 | SetBitField(v_start, 11: 11, 4:4)
382 | SetBitField(v_blank_s, 11: 11, 6:6);
383
384 if (info->var.vmode & FB_VMODE_INTERLACED) {
385 h_total = (h_total >> 1) & ~1;
386 state->interlace = Set8Bits(h_total);
387 state->horiz |= SetBitField(h_total, 8: 8, 4:4);
388 } else {
389 state->interlace = 0xff; /* interlace off */
390 }
391
392 /*
393 * Calculate the extended registers.
394 */
395
396 if (depth < 24)
397 i = depth;
398 else
399 i = 32;
400
401 if (par->Architecture >= NV_ARCH_10)
402 par->CURSOR = (volatile u32 __iomem *)(info->screen_base +
403 par->CursorStart);
404
405 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
406 state->misc_output &= ~0x40;
407 else
408 state->misc_output |= 0x40;
409 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
410 state->misc_output &= ~0x80;
411 else
412 state->misc_output |= 0x80;
413
414 NVCalcStateExt(par, state, i, info->var.xres_virtual,
415 info->var.xres, info->var.yres_virtual,
416 1000000000 / info->var.pixclock, info->var.vmode);
417
418 state->scale = NV_RD32(par->PRAMDAC, 0x00000848) & 0xfff000ff;
419 if (par->FlatPanel == 1) {
420 state->pixel |= (1 << 7);
421
422 if (!par->fpScaler || (par->fpWidth <= info->var.xres)
423 || (par->fpHeight <= info->var.yres)) {
424 state->scale |= (1 << 8);
425 }
426
427 if (!par->crtcSync_read) {
428 state->crtcSync = NV_RD32(par->PRAMDAC, 0x0828);
429 par->crtcSync_read = 1;
430 }
431
432 par->PanelTweak = nvidia_panel_tweak(par, state);
433 }
434
435 state->vpll = state->pll;
436 state->vpll2 = state->pll;
437 state->vpllB = state->pllB;
438 state->vpll2B = state->pllB;
439
440 VGA_WR08(par->PCIO, 0x03D4, 0x1C);
441 state->fifo = VGA_RD08(par->PCIO, 0x03D5) & ~(1<<5);
442
443 if (par->CRTCnumber) {
444 state->head = NV_RD32(par->PCRTC0, 0x00000860) & ~0x00001000;
445 state->head2 = NV_RD32(par->PCRTC0, 0x00002860) | 0x00001000;
446 state->crtcOwner = 3;
447 state->pllsel |= 0x20000800;
448 state->vpll = NV_RD32(par->PRAMDAC0, 0x00000508);
449 if (par->twoStagePLL)
450 state->vpllB = NV_RD32(par->PRAMDAC0, 0x00000578);
451 } else if (par->twoHeads) {
452 state->head = NV_RD32(par->PCRTC0, 0x00000860) | 0x00001000;
453 state->head2 = NV_RD32(par->PCRTC0, 0x00002860) & ~0x00001000;
454 state->crtcOwner = 0;
455 state->vpll2 = NV_RD32(par->PRAMDAC0, 0x0520);
456 if (par->twoStagePLL)
457 state->vpll2B = NV_RD32(par->PRAMDAC0, 0x057C);
458 }
459
460 state->cursorConfig = 0x00000100;
461
462 if (info->var.vmode & FB_VMODE_DOUBLE)
463 state->cursorConfig |= (1 << 4);
464
465 if (par->alphaCursor) {
466 if ((par->Chipset & 0x0ff0) != 0x0110)
467 state->cursorConfig |= 0x04011000;
468 else
469 state->cursorConfig |= 0x14011000;
470 state->general |= (1 << 29);
471 } else
472 state->cursorConfig |= 0x02000000;
473
474 if (par->twoHeads) {
475 if ((par->Chipset & 0x0ff0) == 0x0110) {
476 state->dither = NV_RD32(par->PRAMDAC, 0x0528) &
477 ~0x00010000;
478 if (par->FPDither)
479 state->dither |= 0x00010000;
480 } else {
481 state->dither = NV_RD32(par->PRAMDAC, 0x083C) & ~1;
482 if (par->FPDither)
483 state->dither |= 1;
484 }
485 }
486
487 state->timingH = 0;
488 state->timingV = 0;
489 state->displayV = info->var.xres;
490
491 return 0;
492}
493
494static void nvidia_init_vga(struct fb_info *info)
495{
496 struct nvidia_par *par = info->par;
497 struct _riva_hw_state *state = &par->ModeReg;
498 int i;
499
500 for (i = 0; i < 0x10; i++)
501 state->attr[i] = i;
502 state->attr[0x10] = 0x41;
503 state->attr[0x11] = 0xff;
504 state->attr[0x12] = 0x0f;
505 state->attr[0x13] = 0x00;
506 state->attr[0x14] = 0x00;
507
508 memset(state->crtc, 0x00, NUM_CRT_REGS);
509 state->crtc[0x0a] = 0x20;
510 state->crtc[0x17] = 0xe3;
511 state->crtc[0x18] = 0xff;
512 state->crtc[0x28] = 0x40;
513
514 memset(state->gra, 0x00, NUM_GRC_REGS);
515 state->gra[0x05] = 0x40;
516 state->gra[0x06] = 0x05;
517 state->gra[0x07] = 0x0f;
518 state->gra[0x08] = 0xff;
519
520 state->seq[0x00] = 0x03;
521 state->seq[0x01] = 0x01;
522 state->seq[0x02] = 0x0f;
523 state->seq[0x03] = 0x00;
524 state->seq[0x04] = 0x0e;
525
526 state->misc_output = 0xeb;
527}
528
529static int nvidiafb_cursor(struct fb_info *info, struct fb_cursor *cursor)
530{
531 struct nvidia_par *par = info->par;
532 u8 data[MAX_CURS * MAX_CURS / 8];
533 int i, set = cursor->set;
534 u16 fg, bg;
535
536 if (cursor->image.width > MAX_CURS || cursor->image.height > MAX_CURS)
537 return -ENXIO;
538
539 NVShowHideCursor(par, 0);
540
541 if (par->cursor_reset) {
542 set = FB_CUR_SETALL;
543 par->cursor_reset = 0;
544 }
545
546 if (set & FB_CUR_SETSIZE)
547 memset_io(par->CURSOR, 0, MAX_CURS * MAX_CURS * 2);
548
549 if (set & FB_CUR_SETPOS) {
550 u32 xx, yy, temp;
551
552 yy = cursor->image.dy - info->var.yoffset;
553 xx = cursor->image.dx - info->var.xoffset;
554 temp = xx & 0xFFFF;
555 temp |= yy << 16;
556
557 NV_WR32(par->PRAMDAC, 0x0000300, temp);
558 }
559
560 if (set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) {
561 u32 bg_idx = cursor->image.bg_color;
562 u32 fg_idx = cursor->image.fg_color;
563 u32 s_pitch = (cursor->image.width + 7) >> 3;
564 u32 d_pitch = MAX_CURS / 8;
565 u8 *dat = (u8 *) cursor->image.data;
566 u8 *msk = (u8 *) cursor->mask;
567 u8 *src;
568
569 src = kmalloc_array(s_pitch, cursor->image.height, GFP_ATOMIC);
570
571 if (src) {
572 switch (cursor->rop) {
573 case ROP_XOR:
574 for (i = 0; i < s_pitch * cursor->image.height; i++)
575 src[i] = dat[i] ^ msk[i];
576 break;
577 case ROP_COPY:
578 default:
579 for (i = 0; i < s_pitch * cursor->image.height; i++)
580 src[i] = dat[i] & msk[i];
581 break;
582 }
583
584 fb_pad_aligned_buffer(data, d_pitch, src, s_pitch,
585 cursor->image.height);
586
587 bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) |
588 ((info->cmap.green[bg_idx] & 0xf8) << 2) |
589 ((info->cmap.blue[bg_idx] & 0xf8) >> 3) | 1 << 15;
590
591 fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) |
592 ((info->cmap.green[fg_idx] & 0xf8) << 2) |
593 ((info->cmap.blue[fg_idx] & 0xf8) >> 3) | 1 << 15;
594
595 NVLockUnlock(par, 0);
596
597 nvidiafb_load_cursor_image(par, data, bg, fg,
598 cursor->image.width,
599 cursor->image.height);
600 kfree(src);
601 }
602 }
603
604 if (cursor->enable)
605 NVShowHideCursor(par, 1);
606
607 return 0;
608}
609
610static struct fb_ops nvidia_fb_ops;
611
612static int nvidiafb_set_par(struct fb_info *info)
613{
614 struct nvidia_par *par = info->par;
615
616 NVTRACE_ENTER();
617
618 NVLockUnlock(par, 1);
619 if (!par->FlatPanel || !par->twoHeads)
620 par->FPDither = 0;
621
622 if (par->FPDither < 0) {
623 if ((par->Chipset & 0x0ff0) == 0x0110)
624 par->FPDither = !!(NV_RD32(par->PRAMDAC, 0x0528)
625 & 0x00010000);
626 else
627 par->FPDither = !!(NV_RD32(par->PRAMDAC, 0x083C) & 1);
628 printk(KERN_INFO PFX "Flat panel dithering %s\n",
629 str_enabled_disabled(par->FPDither));
630 }
631
632 info->fix.visual = (info->var.bits_per_pixel == 8) ?
633 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
634
635 nvidia_init_vga(info);
636 nvidia_calc_regs(info);
637
638 NVLockUnlock(par, 0);
639 if (par->twoHeads) {
640 VGA_WR08(par->PCIO, 0x03D4, 0x44);
641 VGA_WR08(par->PCIO, 0x03D5, par->ModeReg.crtcOwner);
642 NVLockUnlock(par, 0);
643 }
644
645 nvidia_screen_off(par, 1);
646
647 nvidia_write_regs(par, &par->ModeReg);
648 NVSetStartAddress(par, 0);
649
650#if defined (__BIG_ENDIAN)
651 /* turn on LFB swapping */
652 {
653 unsigned char tmp;
654
655 VGA_WR08(par->PCIO, 0x3d4, 0x46);
656 tmp = VGA_RD08(par->PCIO, 0x3d5);
657 tmp |= (1 << 7);
658 VGA_WR08(par->PCIO, 0x3d5, tmp);
659 }
660#endif
661
662 info->fix.line_length = (info->var.xres_virtual *
663 info->var.bits_per_pixel) >> 3;
664 if (info->var.accel_flags) {
665 nvidia_fb_ops.fb_imageblit = nvidiafb_imageblit;
666 nvidia_fb_ops.fb_fillrect = nvidiafb_fillrect;
667 nvidia_fb_ops.fb_copyarea = nvidiafb_copyarea;
668 nvidia_fb_ops.fb_sync = nvidiafb_sync;
669 info->pixmap.scan_align = 4;
670 info->flags &= ~FBINFO_HWACCEL_DISABLED;
671 info->flags |= FBINFO_READS_FAST;
672 NVResetGraphics(info);
673 } else {
674 nvidia_fb_ops.fb_imageblit = cfb_imageblit;
675 nvidia_fb_ops.fb_fillrect = cfb_fillrect;
676 nvidia_fb_ops.fb_copyarea = cfb_copyarea;
677 nvidia_fb_ops.fb_sync = NULL;
678 info->pixmap.scan_align = 1;
679 info->flags |= FBINFO_HWACCEL_DISABLED;
680 info->flags &= ~FBINFO_READS_FAST;
681 }
682
683 par->cursor_reset = 1;
684
685 nvidia_screen_off(par, 0);
686
687#ifdef CONFIG_BOOTX_TEXT
688 /* Update debug text engine */
689 btext_update_display(info->fix.smem_start,
690 info->var.xres, info->var.yres,
691 info->var.bits_per_pixel, info->fix.line_length);
692#endif
693
694 NVLockUnlock(par, 0);
695 NVTRACE_LEAVE();
696 return 0;
697}
698
699static int nvidiafb_setcolreg(unsigned regno, unsigned red, unsigned green,
700 unsigned blue, unsigned transp,
701 struct fb_info *info)
702{
703 struct nvidia_par *par = info->par;
704 int i;
705
706 NVTRACE_ENTER();
707 if (regno >= (1 << info->var.green.length))
708 return -EINVAL;
709
710 if (info->var.grayscale) {
711 /* gray = 0.30*R + 0.59*G + 0.11*B */
712 red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
713 }
714
715 if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
716 ((u32 *) info->pseudo_palette)[regno] =
717 (regno << info->var.red.offset) |
718 (regno << info->var.green.offset) |
719 (regno << info->var.blue.offset);
720 }
721
722 switch (info->var.bits_per_pixel) {
723 case 8:
724 /* "transparent" stuff is completely ignored. */
725 nvidia_write_clut(par, regno, red >> 8, green >> 8, blue >> 8);
726 break;
727 case 16:
728 if (info->var.green.length == 5) {
729 for (i = 0; i < 8; i++) {
730 nvidia_write_clut(par, regno * 8 + i, red >> 8,
731 green >> 8, blue >> 8);
732 }
733 } else {
734 u8 r, g, b;
735
736 if (regno < 32) {
737 for (i = 0; i < 8; i++) {
738 nvidia_write_clut(par, regno * 8 + i,
739 red >> 8, green >> 8,
740 blue >> 8);
741 }
742 }
743
744 nvidia_read_clut(par, regno * 4, &r, &g, &b);
745
746 for (i = 0; i < 4; i++)
747 nvidia_write_clut(par, regno * 4 + i, r,
748 green >> 8, b);
749 }
750 break;
751 case 32:
752 nvidia_write_clut(par, regno, red >> 8, green >> 8, blue >> 8);
753 break;
754 default:
755 /* do nothing */
756 break;
757 }
758
759 NVTRACE_LEAVE();
760 return 0;
761}
762
763static int nvidiafb_check_var(struct fb_var_screeninfo *var,
764 struct fb_info *info)
765{
766 struct nvidia_par *par = info->par;
767 int memlen, vramlen, mode_valid = 0;
768 int pitch, err = 0;
769
770 NVTRACE_ENTER();
771 if (!var->pixclock)
772 return -EINVAL;
773
774 var->transp.offset = 0;
775 var->transp.length = 0;
776
777 var->xres &= ~7;
778
779 if (var->bits_per_pixel <= 8)
780 var->bits_per_pixel = 8;
781 else if (var->bits_per_pixel <= 16)
782 var->bits_per_pixel = 16;
783 else
784 var->bits_per_pixel = 32;
785
786 switch (var->bits_per_pixel) {
787 case 8:
788 var->red.offset = 0;
789 var->red.length = 8;
790 var->green.offset = 0;
791 var->green.length = 8;
792 var->blue.offset = 0;
793 var->blue.length = 8;
794 var->transp.offset = 0;
795 var->transp.length = 0;
796 break;
797 case 16:
798 var->green.length = (var->green.length < 6) ? 5 : 6;
799 var->red.length = 5;
800 var->blue.length = 5;
801 var->transp.length = 6 - var->green.length;
802 var->blue.offset = 0;
803 var->green.offset = 5;
804 var->red.offset = 5 + var->green.length;
805 var->transp.offset = (5 + var->red.offset) & 15;
806 break;
807 case 32: /* RGBA 8888 */
808 var->red.offset = 16;
809 var->red.length = 8;
810 var->green.offset = 8;
811 var->green.length = 8;
812 var->blue.offset = 0;
813 var->blue.length = 8;
814 var->transp.length = 8;
815 var->transp.offset = 24;
816 break;
817 }
818
819 var->red.msb_right = 0;
820 var->green.msb_right = 0;
821 var->blue.msb_right = 0;
822 var->transp.msb_right = 0;
823
824 if (!info->monspecs.hfmax || !info->monspecs.vfmax ||
825 !info->monspecs.dclkmax || !fb_validate_mode(var, info))
826 mode_valid = 1;
827
828 /* calculate modeline if supported by monitor */
829 if (!mode_valid && info->monspecs.gtf) {
830 if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info))
831 mode_valid = 1;
832 }
833
834 if (!mode_valid) {
835 const struct fb_videomode *mode;
836
837 mode = fb_find_best_mode(var, &info->modelist);
838 if (mode) {
839 fb_videomode_to_var(var, mode);
840 mode_valid = 1;
841 }
842 }
843
844 if (!mode_valid && info->monspecs.modedb_len)
845 return -EINVAL;
846
847 /*
848 * If we're on a flat panel, check if the mode is outside of the
849 * panel dimensions. If so, cap it and try for the next best mode
850 * before bailing out.
851 */
852 if (par->fpWidth && par->fpHeight && (par->fpWidth < var->xres ||
853 par->fpHeight < var->yres)) {
854 const struct fb_videomode *mode;
855
856 var->xres = par->fpWidth;
857 var->yres = par->fpHeight;
858
859 mode = fb_find_best_mode(var, &info->modelist);
860 if (!mode) {
861 printk(KERN_ERR PFX "mode out of range of flat "
862 "panel dimensions\n");
863 return -EINVAL;
864 }
865
866 fb_videomode_to_var(var, mode);
867 }
868
869 if (var->yres_virtual < var->yres)
870 var->yres_virtual = var->yres;
871
872 if (var->xres_virtual < var->xres)
873 var->xres_virtual = var->xres;
874
875 var->xres_virtual = (var->xres_virtual + 63) & ~63;
876
877 vramlen = info->screen_size;
878 pitch = ((var->xres_virtual * var->bits_per_pixel) + 7) / 8;
879 memlen = pitch * var->yres_virtual;
880
881 if (memlen > vramlen) {
882 var->yres_virtual = vramlen / pitch;
883
884 if (var->yres_virtual < var->yres) {
885 var->yres_virtual = var->yres;
886 var->xres_virtual = vramlen / var->yres_virtual;
887 var->xres_virtual /= var->bits_per_pixel / 8;
888 var->xres_virtual &= ~63;
889 pitch = (var->xres_virtual *
890 var->bits_per_pixel + 7) / 8;
891 memlen = pitch * var->yres;
892
893 if (var->xres_virtual < var->xres) {
894 printk("nvidiafb: required video memory, "
895 "%d bytes, for %dx%d-%d (virtual) "
896 "is out of range\n",
897 memlen, var->xres_virtual,
898 var->yres_virtual, var->bits_per_pixel);
899 err = -ENOMEM;
900 }
901 }
902 }
903
904 if (var->accel_flags) {
905 if (var->yres_virtual > 0x7fff)
906 var->yres_virtual = 0x7fff;
907 if (var->xres_virtual > 0x7fff)
908 var->xres_virtual = 0x7fff;
909 }
910
911 var->xres_virtual &= ~63;
912
913 NVTRACE_LEAVE();
914
915 return err;
916}
917
918static int nvidiafb_pan_display(struct fb_var_screeninfo *var,
919 struct fb_info *info)
920{
921 struct nvidia_par *par = info->par;
922 u32 total;
923
924 total = var->yoffset * info->fix.line_length + var->xoffset;
925
926 NVSetStartAddress(par, total);
927
928 return 0;
929}
930
931static int nvidiafb_blank(int blank, struct fb_info *info)
932{
933 struct nvidia_par *par = info->par;
934 unsigned char tmp, vesa;
935
936 tmp = NVReadSeq(par, 0x01) & ~0x20; /* screen on/off */
937 vesa = NVReadCrtc(par, 0x1a) & ~0xc0; /* sync on/off */
938
939 NVTRACE_ENTER();
940
941 if (blank)
942 tmp |= 0x20;
943
944 switch (blank) {
945 case FB_BLANK_UNBLANK:
946 case FB_BLANK_NORMAL:
947 break;
948 case FB_BLANK_VSYNC_SUSPEND:
949 vesa |= 0x80;
950 break;
951 case FB_BLANK_HSYNC_SUSPEND:
952 vesa |= 0x40;
953 break;
954 case FB_BLANK_POWERDOWN:
955 vesa |= 0xc0;
956 break;
957 }
958
959 NVWriteSeq(par, 0x01, tmp);
960 NVWriteCrtc(par, 0x1a, vesa);
961
962 NVTRACE_LEAVE();
963
964 return 0;
965}
966
967/*
968 * Because the VGA registers are not mapped linearly in its MMIO space,
969 * restrict VGA register saving and restore to x86 only, where legacy VGA IO
970 * access is legal. Consequently, we must also check if the device is the
971 * primary display.
972 */
973#ifdef CONFIG_X86
974static void save_vga_x86(struct nvidia_par *par)
975{
976 struct resource *res= &par->pci_dev->resource[PCI_ROM_RESOURCE];
977
978 if (res && res->flags & IORESOURCE_ROM_SHADOW) {
979 memset(&par->vgastate, 0, sizeof(par->vgastate));
980 par->vgastate.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS |
981 VGA_SAVE_CMAP;
982 save_vga(&par->vgastate);
983 }
984}
985
986static void restore_vga_x86(struct nvidia_par *par)
987{
988 struct resource *res= &par->pci_dev->resource[PCI_ROM_RESOURCE];
989
990 if (res && res->flags & IORESOURCE_ROM_SHADOW)
991 restore_vga(&par->vgastate);
992}
993#else
994#define save_vga_x86(x) do {} while (0)
995#define restore_vga_x86(x) do {} while (0)
996#endif /* X86 */
997
998static int nvidiafb_open(struct fb_info *info, int user)
999{
1000 struct nvidia_par *par = info->par;
1001
1002 if (!par->open_count) {
1003 save_vga_x86(par);
1004 nvidia_save_vga(par, &par->initial_state);
1005 }
1006
1007 par->open_count++;
1008 return 0;
1009}
1010
1011static int nvidiafb_release(struct fb_info *info, int user)
1012{
1013 struct nvidia_par *par = info->par;
1014 int err = 0;
1015
1016 if (!par->open_count) {
1017 err = -EINVAL;
1018 goto done;
1019 }
1020
1021 if (par->open_count == 1) {
1022 nvidia_write_regs(par, &par->initial_state);
1023 restore_vga_x86(par);
1024 }
1025
1026 par->open_count--;
1027done:
1028 return err;
1029}
1030
1031static struct fb_ops nvidia_fb_ops = {
1032 .owner = THIS_MODULE,
1033 .fb_open = nvidiafb_open,
1034 .fb_release = nvidiafb_release,
1035 __FB_DEFAULT_IOMEM_OPS_RDWR,
1036 .fb_check_var = nvidiafb_check_var,
1037 .fb_set_par = nvidiafb_set_par,
1038 .fb_setcolreg = nvidiafb_setcolreg,
1039 .fb_pan_display = nvidiafb_pan_display,
1040 .fb_blank = nvidiafb_blank,
1041 .fb_fillrect = nvidiafb_fillrect,
1042 .fb_copyarea = nvidiafb_copyarea,
1043 .fb_imageblit = nvidiafb_imageblit,
1044 .fb_cursor = nvidiafb_cursor,
1045 .fb_sync = nvidiafb_sync,
1046 __FB_DEFAULT_IOMEM_OPS_MMAP,
1047};
1048
1049static int nvidiafb_suspend_late(struct device *dev, pm_message_t mesg)
1050{
1051 struct fb_info *info = dev_get_drvdata(dev);
1052 struct nvidia_par *par = info->par;
1053
1054 if (mesg.event == PM_EVENT_PRETHAW)
1055 mesg.event = PM_EVENT_FREEZE;
1056 console_lock();
1057 par->pm_state = mesg.event;
1058
1059 if (mesg.event & PM_EVENT_SLEEP) {
1060 fb_set_suspend(info, 1);
1061 nvidiafb_blank(FB_BLANK_POWERDOWN, info);
1062 nvidia_write_regs(par, &par->SavedReg);
1063 }
1064 dev->power.power_state = mesg;
1065
1066 console_unlock();
1067 return 0;
1068}
1069
1070static int __maybe_unused nvidiafb_suspend(struct device *dev)
1071{
1072 return nvidiafb_suspend_late(dev, PMSG_SUSPEND);
1073}
1074
1075static int __maybe_unused nvidiafb_hibernate(struct device *dev)
1076{
1077 return nvidiafb_suspend_late(dev, PMSG_HIBERNATE);
1078}
1079
1080static int __maybe_unused nvidiafb_freeze(struct device *dev)
1081{
1082 return nvidiafb_suspend_late(dev, PMSG_FREEZE);
1083}
1084
1085static int __maybe_unused nvidiafb_resume(struct device *dev)
1086{
1087 struct fb_info *info = dev_get_drvdata(dev);
1088 struct nvidia_par *par = info->par;
1089
1090 console_lock();
1091
1092 par->pm_state = PM_EVENT_ON;
1093 nvidiafb_set_par(info);
1094 fb_set_suspend (info, 0);
1095 nvidiafb_blank(FB_BLANK_UNBLANK, info);
1096
1097 console_unlock();
1098 return 0;
1099}
1100
1101static const struct dev_pm_ops nvidiafb_pm_ops = {
1102#ifdef CONFIG_PM_SLEEP
1103 .suspend = nvidiafb_suspend,
1104 .resume = nvidiafb_resume,
1105 .freeze = nvidiafb_freeze,
1106 .thaw = nvidiafb_resume,
1107 .poweroff = nvidiafb_hibernate,
1108 .restore = nvidiafb_resume,
1109#endif /* CONFIG_PM_SLEEP */
1110};
1111
1112static int nvidia_set_fbinfo(struct fb_info *info)
1113{
1114 struct fb_monspecs *specs = &info->monspecs;
1115 struct fb_videomode modedb;
1116 struct nvidia_par *par = info->par;
1117 int lpitch;
1118
1119 NVTRACE_ENTER();
1120 info->flags =
1121 FBINFO_HWACCEL_IMAGEBLIT
1122 | FBINFO_HWACCEL_FILLRECT
1123 | FBINFO_HWACCEL_COPYAREA
1124 | FBINFO_HWACCEL_YPAN;
1125
1126 fb_videomode_to_modelist(info->monspecs.modedb,
1127 info->monspecs.modedb_len, &info->modelist);
1128 fb_var_to_videomode(&modedb, &nvidiafb_default_var);
1129
1130 switch (bpp) {
1131 case 0 ... 8:
1132 bpp = 8;
1133 break;
1134 case 9 ... 16:
1135 bpp = 16;
1136 break;
1137 default:
1138 bpp = 32;
1139 break;
1140 }
1141
1142 if (specs->modedb != NULL) {
1143 const struct fb_videomode *mode;
1144
1145 mode = fb_find_best_display(specs, &info->modelist);
1146 fb_videomode_to_var(&nvidiafb_default_var, mode);
1147 nvidiafb_default_var.bits_per_pixel = bpp;
1148 } else if (par->fpWidth && par->fpHeight) {
1149 char buf[16];
1150
1151 memset(buf, 0, 16);
1152 snprintf(buf, 15, "%dx%dMR", par->fpWidth, par->fpHeight);
1153 fb_find_mode(&nvidiafb_default_var, info, buf, specs->modedb,
1154 specs->modedb_len, &modedb, bpp);
1155 }
1156
1157 if (mode_option)
1158 fb_find_mode(&nvidiafb_default_var, info, mode_option,
1159 specs->modedb, specs->modedb_len, &modedb, bpp);
1160
1161 info->var = nvidiafb_default_var;
1162 info->fix.visual = (info->var.bits_per_pixel == 8) ?
1163 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1164 info->pseudo_palette = par->pseudo_palette;
1165 fb_alloc_cmap(&info->cmap, 256, 0);
1166 fb_destroy_modedb(info->monspecs.modedb);
1167 info->monspecs.modedb = NULL;
1168
1169 /* maximize virtual vertical length */
1170 lpitch = info->var.xres_virtual *
1171 ((info->var.bits_per_pixel + 7) >> 3);
1172 info->var.yres_virtual = info->screen_size / lpitch;
1173
1174 info->pixmap.scan_align = 4;
1175 info->pixmap.buf_align = 4;
1176 info->pixmap.access_align = 32;
1177 info->pixmap.size = 8 * 1024;
1178 info->pixmap.flags = FB_PIXMAP_SYSTEM;
1179
1180 if (!hwcur)
1181 nvidia_fb_ops.fb_cursor = NULL;
1182
1183 info->var.accel_flags = (!noaccel);
1184
1185 switch (par->Architecture) {
1186 case NV_ARCH_04:
1187 info->fix.accel = FB_ACCEL_NV4;
1188 break;
1189 case NV_ARCH_10:
1190 info->fix.accel = FB_ACCEL_NV_10;
1191 break;
1192 case NV_ARCH_20:
1193 info->fix.accel = FB_ACCEL_NV_20;
1194 break;
1195 case NV_ARCH_30:
1196 info->fix.accel = FB_ACCEL_NV_30;
1197 break;
1198 case NV_ARCH_40:
1199 info->fix.accel = FB_ACCEL_NV_40;
1200 break;
1201 }
1202
1203 NVTRACE_LEAVE();
1204
1205 return nvidiafb_check_var(&info->var, info);
1206}
1207
1208static u32 nvidia_get_chipset(struct pci_dev *pci_dev,
1209 volatile u32 __iomem *REGS)
1210{
1211 u32 id = (pci_dev->vendor << 16) | pci_dev->device;
1212
1213 printk(KERN_INFO PFX "Device ID: %x \n", id);
1214
1215 if ((id & 0xfff0) == 0x00f0 ||
1216 (id & 0xfff0) == 0x02e0) {
1217 /* pci-e */
1218 id = NV_RD32(REGS, 0x1800);
1219
1220 if ((id & 0x0000ffff) == 0x000010DE)
1221 id = 0x10DE0000 | (id >> 16);
1222 else if ((id & 0xffff0000) == 0xDE100000) /* wrong endian */
1223 id = 0x10DE0000 | ((id << 8) & 0x0000ff00) |
1224 ((id >> 8) & 0x000000ff);
1225 printk(KERN_INFO PFX "Subsystem ID: %x \n", id);
1226 }
1227
1228 return id;
1229}
1230
1231static u32 nvidia_get_arch(u32 Chipset)
1232{
1233 u32 arch = 0;
1234
1235 switch (Chipset & 0x0ff0) {
1236 case 0x0100: /* GeForce 256 */
1237 case 0x0110: /* GeForce2 MX */
1238 case 0x0150: /* GeForce2 */
1239 case 0x0170: /* GeForce4 MX */
1240 case 0x0180: /* GeForce4 MX (8x AGP) */
1241 case 0x01A0: /* nForce */
1242 case 0x01F0: /* nForce2 */
1243 arch = NV_ARCH_10;
1244 break;
1245 case 0x0200: /* GeForce3 */
1246 case 0x0250: /* GeForce4 Ti */
1247 case 0x0280: /* GeForce4 Ti (8x AGP) */
1248 arch = NV_ARCH_20;
1249 break;
1250 case 0x0300: /* GeForceFX 5800 */
1251 case 0x0310: /* GeForceFX 5600 */
1252 case 0x0320: /* GeForceFX 5200 */
1253 case 0x0330: /* GeForceFX 5900 */
1254 case 0x0340: /* GeForceFX 5700 */
1255 arch = NV_ARCH_30;
1256 break;
1257 case 0x0040: /* GeForce 6800 */
1258 case 0x00C0: /* GeForce 6800 */
1259 case 0x0120: /* GeForce 6800 */
1260 case 0x0140: /* GeForce 6600 */
1261 case 0x0160: /* GeForce 6200 */
1262 case 0x01D0: /* GeForce 7200, 7300, 7400 */
1263 case 0x0090: /* GeForce 7800 */
1264 case 0x0210: /* GeForce 6800 */
1265 case 0x0220: /* GeForce 6200 */
1266 case 0x0240: /* GeForce 6100 */
1267 case 0x0290: /* GeForce 7900 */
1268 case 0x0390: /* GeForce 7600 */
1269 case 0x03D0:
1270 arch = NV_ARCH_40;
1271 break;
1272 case 0x0020: /* TNT, TNT2 */
1273 arch = NV_ARCH_04;
1274 break;
1275 default: /* unknown architecture */
1276 break;
1277 }
1278
1279 return arch;
1280}
1281
1282static int nvidiafb_probe(struct pci_dev *pd, const struct pci_device_id *ent)
1283{
1284 struct nvidia_par *par;
1285 struct fb_info *info;
1286 unsigned short cmd;
1287 int ret;
1288 volatile u32 __iomem *REGS;
1289 int Chipset;
1290 u32 Architecture;
1291
1292 NVTRACE_ENTER();
1293 assert(pd != NULL);
1294
1295 if (pcim_enable_device(pd)) {
1296 printk(KERN_ERR PFX "cannot enable PCI device\n");
1297 return -ENODEV;
1298 }
1299
1300 /* enable IO and mem if not already done */
1301 pci_read_config_word(pd, PCI_COMMAND, &cmd);
1302 cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
1303 pci_write_config_word(pd, PCI_COMMAND, cmd);
1304
1305 nvidiafb_fix.mmio_start = pci_resource_start(pd, 0);
1306 nvidiafb_fix.mmio_len = pci_resource_len(pd, 0);
1307
1308 REGS = devm_ioremap(&pd->dev, nvidiafb_fix.mmio_start, nvidiafb_fix.mmio_len);
1309 if (!REGS) {
1310 printk(KERN_ERR PFX "cannot ioremap MMIO base\n");
1311 return -ENODEV;
1312 }
1313
1314 Chipset = nvidia_get_chipset(pd, REGS);
1315 Architecture = nvidia_get_arch(Chipset);
1316 if (Architecture == 0) {
1317 printk(KERN_ERR PFX "unknown NV_ARCH\n");
1318 goto err_out;
1319 }
1320
1321 ret = aperture_remove_conflicting_pci_devices(pd, "nvidiafb");
1322 if (ret)
1323 goto err_out;
1324
1325 info = framebuffer_alloc(sizeof(struct nvidia_par), &pd->dev);
1326 if (!info)
1327 goto err_out;
1328
1329 par = info->par;
1330 par->pci_dev = pd;
1331 info->pixmap.addr = kzalloc(8 * 1024, GFP_KERNEL);
1332
1333 if (info->pixmap.addr == NULL)
1334 goto err_out_kfree;
1335
1336 if (pcim_request_all_regions(pd, "nvidiafb")) {
1337 printk(KERN_ERR PFX "cannot request PCI regions\n");
1338 goto err_out_enable;
1339 }
1340
1341 par->FlatPanel = flatpanel;
1342 if (flatpanel == 1)
1343 printk(KERN_INFO PFX "flatpanel support enabled\n");
1344 par->FPDither = fpdither;
1345
1346 par->CRTCnumber = forceCRTC;
1347 par->FpScale = (!noscale);
1348 par->paneltweak = paneltweak;
1349 par->reverse_i2c = reverse_i2c;
1350
1351 nvidiafb_fix.smem_start = pci_resource_start(pd, 1);
1352
1353 par->REGS = REGS;
1354
1355 par->Chipset = Chipset;
1356 par->Architecture = Architecture;
1357
1358 sprintf(nvidiafb_fix.id, "NV%x", (pd->device & 0x0ff0) >> 4);
1359
1360 if (NVCommonSetup(info))
1361 goto err_out_enable;
1362
1363 par->FbAddress = nvidiafb_fix.smem_start;
1364 par->FbMapSize = par->RamAmountKBytes * 1024;
1365 if (vram && vram * 1024 * 1024 < par->FbMapSize)
1366 par->FbMapSize = vram * 1024 * 1024;
1367
1368 /* Limit amount of vram to 64 MB */
1369 if (par->FbMapSize > 64 * 1024 * 1024)
1370 par->FbMapSize = 64 * 1024 * 1024;
1371
1372 if(par->Architecture >= NV_ARCH_40)
1373 par->FbUsableSize = par->FbMapSize - (560 * 1024);
1374 else
1375 par->FbUsableSize = par->FbMapSize - (128 * 1024);
1376 par->ScratchBufferSize = (par->Architecture < NV_ARCH_10) ? 8 * 1024 :
1377 16 * 1024;
1378 par->ScratchBufferStart = par->FbUsableSize - par->ScratchBufferSize;
1379 par->CursorStart = par->FbUsableSize + (32 * 1024);
1380
1381 info->screen_base = devm_ioremap_wc(&pd->dev, nvidiafb_fix.smem_start,
1382 par->FbMapSize);
1383 info->screen_size = par->FbUsableSize;
1384 nvidiafb_fix.smem_len = par->RamAmountKBytes * 1024;
1385
1386 if (!info->screen_base) {
1387 printk(KERN_ERR PFX "cannot ioremap FB base\n");
1388 goto err_out_free_base1;
1389 }
1390
1391 par->FbStart = info->screen_base;
1392
1393 if (!nomtrr)
1394 par->wc_cookie = arch_phys_wc_add(nvidiafb_fix.smem_start,
1395 par->RamAmountKBytes * 1024);
1396
1397 info->fbops = &nvidia_fb_ops;
1398 info->fix = nvidiafb_fix;
1399
1400 if (nvidia_set_fbinfo(info) < 0) {
1401 printk(KERN_ERR PFX "error setting initial video mode\n");
1402 goto err_out_iounmap_fb;
1403 }
1404
1405 nvidia_save_vga(par, &par->SavedReg);
1406
1407 pci_set_drvdata(pd, info);
1408
1409 if (register_framebuffer(info) < 0) {
1410 printk(KERN_ERR PFX "error registering nVidia framebuffer\n");
1411 goto err_out_iounmap_fb;
1412 }
1413
1414 if (backlight)
1415 nvidia_bl_init(par);
1416
1417 printk(KERN_INFO PFX
1418 "PCI nVidia %s framebuffer (%dMB @ 0x%lX)\n",
1419 info->fix.id,
1420 par->FbMapSize / (1024 * 1024), info->fix.smem_start);
1421
1422 NVTRACE_LEAVE();
1423 return 0;
1424
1425err_out_iounmap_fb:
1426 fb_destroy_modelist(&info->modelist);
1427err_out_free_base1:
1428 fb_destroy_modedb(info->monspecs.modedb);
1429 nvidia_delete_i2c_busses(par);
1430err_out_enable:
1431 kfree(info->pixmap.addr);
1432err_out_kfree:
1433 framebuffer_release(info);
1434err_out:
1435 return -ENODEV;
1436}
1437
1438static void nvidiafb_remove(struct pci_dev *pd)
1439{
1440 struct fb_info *info = pci_get_drvdata(pd);
1441 struct nvidia_par *par = info->par;
1442
1443 NVTRACE_ENTER();
1444
1445 nvidia_bl_exit(par);
1446 unregister_framebuffer(info);
1447
1448 arch_phys_wc_del(par->wc_cookie);
1449 fb_destroy_modedb(info->monspecs.modedb);
1450 nvidia_delete_i2c_busses(par);
1451 kfree(info->pixmap.addr);
1452 framebuffer_release(info);
1453 NVTRACE_LEAVE();
1454}
1455
1456/* ------------------------------------------------------------------------- *
1457 *
1458 * initialization
1459 *
1460 * ------------------------------------------------------------------------- */
1461
1462#ifndef MODULE
1463static int nvidiafb_setup(char *options)
1464{
1465 char *this_opt;
1466
1467 NVTRACE_ENTER();
1468 if (!options || !*options)
1469 return 0;
1470
1471 while ((this_opt = strsep(&options, ",")) != NULL) {
1472 if (!strncmp(this_opt, "forceCRTC", 9)) {
1473 char *p;
1474
1475 p = this_opt + 9;
1476 if (!*p || !*(++p))
1477 continue;
1478 forceCRTC = *p - '0';
1479 if (forceCRTC < 0 || forceCRTC > 1)
1480 forceCRTC = -1;
1481 } else if (!strncmp(this_opt, "flatpanel", 9)) {
1482 flatpanel = 1;
1483 } else if (!strncmp(this_opt, "hwcur", 5)) {
1484 hwcur = 1;
1485 } else if (!strncmp(this_opt, "noaccel", 7)) {
1486 noaccel = 1;
1487 } else if (!strncmp(this_opt, "noscale", 7)) {
1488 noscale = 1;
1489 } else if (!strncmp(this_opt, "reverse_i2c", 11)) {
1490 reverse_i2c = 1;
1491 } else if (!strncmp(this_opt, "paneltweak:", 11)) {
1492 paneltweak = simple_strtoul(this_opt+11, NULL, 0);
1493 } else if (!strncmp(this_opt, "vram:", 5)) {
1494 vram = simple_strtoul(this_opt+5, NULL, 0);
1495 } else if (!strncmp(this_opt, "backlight:", 10)) {
1496 backlight = simple_strtoul(this_opt+10, NULL, 0);
1497 } else if (!strncmp(this_opt, "nomtrr", 6)) {
1498 nomtrr = true;
1499 } else if (!strncmp(this_opt, "fpdither:", 9)) {
1500 fpdither = simple_strtol(this_opt+9, NULL, 0);
1501 } else if (!strncmp(this_opt, "bpp:", 4)) {
1502 bpp = simple_strtoul(this_opt+4, NULL, 0);
1503 } else
1504 mode_option = this_opt;
1505 }
1506 NVTRACE_LEAVE();
1507 return 0;
1508}
1509#endif /* !MODULE */
1510
1511static struct pci_driver nvidiafb_driver = {
1512 .name = "nvidiafb",
1513 .id_table = nvidiafb_pci_tbl,
1514 .probe = nvidiafb_probe,
1515 .driver.pm = &nvidiafb_pm_ops,
1516 .remove = nvidiafb_remove,
1517};
1518
1519/* ------------------------------------------------------------------------- *
1520 *
1521 * modularization
1522 *
1523 * ------------------------------------------------------------------------- */
1524
1525static int nvidiafb_init(void)
1526{
1527#ifndef MODULE
1528 char *option = NULL;
1529#endif
1530
1531 if (fb_modesetting_disabled("nvidiafb"))
1532 return -ENODEV;
1533
1534#ifndef MODULE
1535 if (fb_get_options("nvidiafb", &option))
1536 return -ENODEV;
1537 nvidiafb_setup(option);
1538#endif
1539 return pci_register_driver(&nvidiafb_driver);
1540}
1541
1542module_init(nvidiafb_init);
1543
1544static void __exit nvidiafb_exit(void)
1545{
1546 pci_unregister_driver(&nvidiafb_driver);
1547}
1548
1549module_exit(nvidiafb_exit);
1550
1551module_param(flatpanel, int, 0);
1552MODULE_PARM_DESC(flatpanel,
1553 "Enables experimental flat panel support for some chipsets. "
1554 "(0=disabled, 1=enabled, -1=autodetect) (default=-1)");
1555module_param(fpdither, int, 0);
1556MODULE_PARM_DESC(fpdither,
1557 "Enables dithering of flat panel for 6 bits panels. "
1558 "(0=disabled, 1=enabled, -1=autodetect) (default=-1)");
1559module_param(hwcur, int, 0);
1560MODULE_PARM_DESC(hwcur,
1561 "Enables hardware cursor implementation. (0 or 1=enabled) "
1562 "(default=0)");
1563module_param(noaccel, int, 0);
1564MODULE_PARM_DESC(noaccel,
1565 "Disables hardware acceleration. (0 or 1=disable) "
1566 "(default=0)");
1567module_param(noscale, int, 0);
1568MODULE_PARM_DESC(noscale,
1569 "Disables screen scaling. (0 or 1=disable) "
1570 "(default=0, do scaling)");
1571module_param(paneltweak, int, 0);
1572MODULE_PARM_DESC(paneltweak,
1573 "Tweak display settings for flatpanels. "
1574 "(default=0, no tweaks)");
1575module_param(forceCRTC, int, 0);
1576MODULE_PARM_DESC(forceCRTC,
1577 "Forces usage of a particular CRTC in case autodetection "
1578 "fails. (0 or 1) (default=autodetect)");
1579module_param(vram, int, 0);
1580MODULE_PARM_DESC(vram,
1581 "amount of framebuffer memory to remap in MiB"
1582 "(default=0 - remap entire memory)");
1583module_param(mode_option, charp, 0);
1584MODULE_PARM_DESC(mode_option, "Specify initial video mode");
1585module_param(bpp, int, 0);
1586MODULE_PARM_DESC(bpp, "pixel width in bits"
1587 "(default=8)");
1588module_param(reverse_i2c, int, 0);
1589MODULE_PARM_DESC(reverse_i2c, "reverse port assignment of the i2c bus");
1590module_param(nomtrr, bool, false);
1591MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) "
1592 "(default=0)");
1593
1594MODULE_AUTHOR("Antonino Daplas");
1595MODULE_DESCRIPTION("Framebuffer driver for nVidia graphics chipset");
1596MODULE_LICENSE("GPL");